Instructions and logic for performing floating-point and integer operations for machine learning

Abstract

One embodiment provides a machine learning hardware accelerator including a computing unit having adders and multipliers shared between an integer data path and a floating-point data path, and high-order bits of input operands to the multipliers are to be gated during floating-point operations.

Description

[0001] Cross-reference

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 491,699, filed Apr. 28, 2017, which is hereby incorporated by reference herein in its entirety. Technical Field

[0003] Embodiments generally relate to data processing, and more particularly, to data processing via a general purpose graphics processing unit. Background Art

[0004] Current parallel graphics data processing involves developing systems and methods for performing specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed function computing units to process graphics data; however, recently, portions of the graphics processors have been made programmable, enabling such processors to support a wide variety of operations for processing vertex and fragment data.

[0005] To further increase performance, graphics processors typically implement processing techniques such as pipelined operations that attempt to parallel process as much graphics data as possible across different portions of the graphics pipeline. Parallel graphics processors with a single instruction multiple thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to synchronously execute program instructions together as often as possible to increase processing efficiency. A general overview of software and hardware for a SIMT architecture can be found in Shane Cook's CUDA Programming, Chapter 3, pages 37-51 (2013) and / or Nicholas Wilt's CUDA Handbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2 through 3.1.2 (June 2013). Brief Description of the Drawings

[0006] A more particular description of the invention can be had by reference to the embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the drawings illustrate only typical embodiments of the invention and are therefore not to be considered limiting of its scope.

[0007] Figure 1 is a block diagram showing a computer system configured to implement one or more aspects of the embodiments described herein.

[0008] Figures 2A - 2D shows a parallel processor component in accordance with an embodiment.

[0009] Figures 3A - 3BIs a block diagram of a graphics multi - processor according to an embodiment.

[0010] Figures 4A - 4F Shows an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi - core processors.

[0011] Figure 5 Shows a graphics processing pipeline according to an embodiment.

[0012] Figure 6 Shows a machine learning software stack according to an embodiment.

[0013] Figure 7 Shows a highly parallel general - purpose graphics processing unit according to an embodiment.

[0014] Figure 8 Shows a multi - GPU computing system according to an embodiment.

[0015] Figures 9A - 9B Shows the layers of a exemplary deep neural network.

[0016] Figure 10 Shows a exemplary recurrent neural network.

[0017] Figure 11 Shows the training and deployment of a deep neural network.

[0018] Figure 12 Is a block diagram showing distributed learning.

[0019] Figure 13 Shows an exemplary inference system - on - a - chip (SOC) suitable for performing inference using a trained model.

[0020] Figure 14 Is a block diagram of a multi - processor unit according to an embodiment.

[0021] Figures 15A - 15B Shows the design of a logic unit for performing integer and floating - point fused multiply - add operations according to an embodiment.

[0022] Figure 16 Shows a fused multiply - add logic unit with a merged floating - point and integer data path according to an embodiment.

[0023] Figures 17A - 17B Shows a logic unit including merged computing circuits to perform floating - point and integer fused multiply - accumulate operations according to an embodiment.

[0024] Figure 18A - 18B shows a data processing system and associated computing and logic units for performing accelerated training and inference operations for machine learning.

[0025] Figure 19Shows details of an activation instruction module according to an embodiment.

[0026] Figure 20 Shows a random quantization unit according to an embodiment.

[0027] Figure 21 Shows an FPU encoding and configuration module according to an embodiment.

[0028] Figure 22 Shows the logic for processing instructions using a dynamically configurable computing unit according to an embodiment.

[0029] Figures 23A - 23B Is a flowchart showing the logic for performing sparse computing operations within a GPGPU provided by the embodiments described herein.

[0030] Figure 24 Is a block diagram of a processing system according to an embodiment.

[0031] Figure 25 Is a block diagram of a processor according to an embodiment.

[0032] Figure 26 Block diagram of a graphics processor according to an embodiment.

[0033] Figure 27 Is a block diagram of a graphics processing engine of a graphics processor according to some embodiments.

[0034] Figure 28 Is a block diagram of a graphics processor provided by additional embodiments.

[0035] Figure 29 Shows thread execution logic including an array of processing elements employed in some embodiments.

[0036] Figure 30 Is a block diagram showing a graphics processor instruction format according to some embodiments. ]>

[0037] Figure 31 Is a block diagram of a graphics processor according to another embodiment.

[0038] Figures 32A - 32B Shows a graphics processor command format and command sequence according to some embodiments.

[0039] Figure 33 Shows a exemplary graphics software architecture for a data processing system according to some embodiments.

[0040] Figure 34 Is a block diagram showing a development system for an IP core according to an embodiment.

[0041] Figure 35It is a block diagram showing a exemplary system-on-chip integrated circuit according to an embodiment.

[0042] Figure 36 It is a block diagram showing an additional graphics processor according to an embodiment.

[0043] Figure 37 It is a block diagram showing an additional exemplary graphics processor of a system-on-chip integrated circuit according to an embodiment. Detailed Description

[0044] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU can be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0045] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of ordinary skill in the art that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the embodiments of the present invention.

[0046] System Overview

[0047] Figure 1FIG. 0 is a block diagram of a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104 that communicate via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that may enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 may enable a display controller to provide output to one or more display devices 110A, which may be included within the one or more processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0048] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 that are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 may be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or may be a vendor-specific communication interface or communication fabric. In one embodiment, the one or more parallel processors 112 form a parallel or vector processing system in a computing cluster that includes a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that may output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable a direct connection to one or more display devices 110B.

[0049] Within the I / O subsystem 111, the system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components that can be integrated into the platform, such as the network adapter 118 and / or the wireless network adapter 119, and various other devices that can be added via one or more plug-in devices 120. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0050] The computing system 100 can include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which can also be connected to the I / O hub 107. Any suitable protocol can be used, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or protocol, such as NV-Link high-speed interconnect or an interconnect protocol known in the art, to implement the communication paths that interconnect the various components Figure 1 in.

[0051] In one embodiment, the one or more parallel processors 112 are combined with circuitry optimized for graphics and video processing, which includes, for example, video output circuitry, and constitute a Graphics Processing Unit (GPU). In another embodiment, the one or more parallel processors 112 are combined with circuitry optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 can be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, the memory hub 105, the processor(s) 102, and the I / O hub 107 can be integrated into a System-on-Chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a System-in-Package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 can be integrated into a Multi-Chip Module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0052] It will be appreciated that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connection topology can be modified as desired, which includes the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, the system memory 104 is connected directly to the processors 102 rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processors 102. In other alternative topologies, the parallel processors 112 are connected to the I / O hub 107 or directly to one of the one or more processors 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 can be integrated into a single chip. Some embodiments can include two or more sets of processors 102 attached via multiple sockets, which can be coupled to two or more instances of the parallel processors 112.

[0053] Some of the specific components shown herein are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripheral devices can be supported, or some components can be eliminated. Additionally, some architectures may use different terms for components similar to those shown Figure 1 herein. For example, in some architectures, the memory hub 105 may be referred to as the north bridge, while the I / O hub 107 may be referred to as the south bridge.

[0054] Figure 2A A parallel processor 200 is shown in accordance with an embodiment. The various components of the parallel processor 200 can be implemented using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In accordance with an embodiment, the shown parallel processor 200 is Figure 1 a variant of the one or more parallel processors 112 shown herein.

[0055] In one embodiment, parallel processor 200 includes parallel processing unit 202. The parallel processing unit includes I / O unit 204, and the I / O unit 204 enables communication with other devices including other instances of parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface such as memory hub 105. The connection between memory hub 105 and I / O unit 204 forms communication link 113. Within parallel processing unit 202, the I / O unit 204 is connected to host interface 206 and memory crossbar 216, where the host interface 206 receives commands related to performing processing operations, and the memory crossbar 216 receives commands related to performing memory operations.

[0056] When host interface 206 receives a command buffer via I / O unit 204, the host interface 206 may direct the work operations for executing those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, and the scheduler 210 is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in an active state before distributing tasks to the processing clusters of processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both a coarse-grained and fine-grained level, enabling context switching and rapid preemption of threads executing on processing array 212. In one embodiment, host software may check the workload for scheduling on processing array 212 via one of a plurality of graphics processing doorbells. Subsequently, the workload may be automatically distributed across processing array 212 by scheduler 210 logic within the scheduler microcontroller.

[0057] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B to cluster 214N). Each of the clusters 214A - 214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to the clusters 214A - 214N of the processing cluster array 212, and the algorithms may vary according to the workload generated for each type of program or computation. Scheduling may be handled dynamically by the scheduler 210, or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the processing cluster array 212. In one embodiment, different clusters 214A - 214N of the processing cluster array 212 may be allocated to process different types of programs or to perform different types of computations.

[0058] The processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks, which include filtering of video and / or audio data, performing modeling operations including physical operations, and performing data transformation.

[0059] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, tessellation logic, and other vertex processing logic. Additionally, the processing cluster array 212 may be configured to execute graphics processing-related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transfer data from the system memory via the I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) during processing and then written back to the system memory.

[0060] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable graphics processing operations to be distributed to multiple clusters 214A - 214N of processing cluster array 212. In some embodiments, portions of processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of clusters 214A - 214N may be stored in a buffer to allow the intermediate data to be transferred between clusters 214A - 214N for further processing.

[0061] During operation, processing cluster array 212 may receive processing tasks to be executed via scheduler 210, which receives commands defining the processing tasks from front end 208. For graphics processing operations, the processing tasks may include data to be processed and indices of status parameters and commands defining how the data is to be processed (e.g., what program is to be executed), such as surface (patch) data, primitive data, vertex data, and / or pixel data. Scheduler 210 may be configured to obtain the index corresponding to the task or may receive the index from front end 208. Front end 208 may be configured to ensure that processing cluster array 212 is configured in a valid state before the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.) is initiated.

[0062] Each of one or more instances of the parallel processing unit 202 can be coupled to the parallel processor memory 222. The parallel processor memory 222 can be accessed via a memory crossbar 216, which can receive memory requests from the array of processing clusters 212 as well as the I / O unit 204. The memory crossbar 216 can access the parallel processor memory 222 via a memory interface 218. The memory interface 218 can include a plurality of partition units (e.g., partition unit 220A, partition unit 220B to partition unit 220N), each of which can be coupled to a portion (e.g., a memory unit) of the parallel processor memory 222. In one implementation, the number of partition units 220A - 220N is configured to be equal to the number of memory units, such that the first partition unit 220A has a corresponding first memory unit 224A, the second partition unit 220B has a corresponding memory unit 224B, and the Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A - 220N may not be equal to the number of memory devices.

[0063] In various embodiments, the memory units 224A - 224N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A - 224N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of the memory units 224A - 224N can vary and can be selected from one of a variety of conventional designs. Rendering targets such as frame buffers or texture maps can be stored across the memory units 224A - 224N, allowing the partition units 220A - 220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 222. In some embodiments, a local instance of the parallel processor memory 222 can be excluded to support a unified memory design that utilizes system memory along with a local cache memory.

[0064] In one embodiment, any one of clusters 214A - 214N of processing cluster array 212 can process any data to be written into memory cells 224A - 224N within parallel processor memory 222. Memory crossbar 216 can be configured to transfer the output of each cluster 214A - 214N to any partition unit 220A - 220N or another cluster 214A - 214N, which can perform additional processing operations on the output. Each cluster 214A - 214N can communicate with memory interface 218 through memory crossbar 216 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has connections to memory interface 218 for communicating with I / O unit 204, and connections to local instances of parallel processor memory 222, such that processing units within different processing clusters 214A - 214N can communicate with system memory or other memories that are non - local to parallel processing unit 202. In one embodiment, memory crossbar 216 can use virtual channels to separate the traffic flow between clusters 214A - 214N and partition units 220A - 220N.

[0065] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 can be included. For example, multiple instances of parallel processing unit 202 can be provided on a single plug - in card, or multiple plug - in cards can be interconnected. Even if different instances of parallel processing unit 202 have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences, the different instances can be configured to interoperate. For example and in one embodiment, some instances of parallel processing unit 202 can include floating - point units with higher precision relative to other instances. Systems incorporating one or more instances of parallel processing unit 202 or parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0066] Figure 2B is a block diagram of partition unit 220 according to an embodiment. In one embodiment, partition unit 220 is Figure 2AAn example of one of the partition units 220A - 220N. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. The L2 cache 221 outputs read misses and urgent writeback requests to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory cells in the parallel processor memory, such as the memory cells 224A - 224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0067] In a graphics application, the ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. The ROP 226 then outputs the processed graphics data, which is stored in the graphics memory. In some embodiments, the ROP 226 includes compression logic to compress the depth or color data written to the memory and decompress the depth or color data read from the memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by the ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on the depth and color data on a per-tile basis.

[0068] In some embodiments, the ROP 226 is included within each processing cluster (e.g., clusters 214A - 214N of FIG. 2) instead of within the partition unit 220. In such embodiments, read and write requests for pixel data, rather than pixel fragment data, are transmitted through the memory crossbar 216. The processed graphics data can be displayed on a display device (such as Figure 1 one of the one or more display devices 110), routed for further processing by the (multiple) processors 102, or routed for further processing by Figure 2A one of the processing entities within the parallel processor 200.

[0069] Figure 2CIt is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A - 214N of FIG. 2. The processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In some embodiments, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters. Different from the SIMD execution regime in which all processing engines typically execute the same instructions, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0070] The operation of the processing cluster 214 can be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is a demonstrative example of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and a data crossbar 240 can be used to distribute the processed data to one of a number of possible destinations including other shader units. The pipeline manager 232 can facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed via the data crossbar 240.

[0071] Each graphics multiprocessor 234 within the processing cluster 214 can include a set of identical functional execution logic (e.g., arithmetic logic units, load - store units, etc.). The functional execution logic can be configured in a pipelined manner where new instructions can be issued before the completion of previous instructions. The functional execution logic supports a variety of operations including integer and floating - point arithmetic, comparison operations, boolean operations, shifts, and the calculation of various algebraic functions. In one embodiment, the same functional unit hardware can be utilized to perform different operations, and any combination of functional units may exist.

[0072] Instructions transmitted to processing cluster 214 constitute threads. A set of threads executed across a collection of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycles in which the thread group is processed. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be executed in consecutive clock cycles. In one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 234.

[0073] In one embodiment, graphics multiprocessor 234 includes an internal cache for performing load and store operations. In one embodiment, graphics multiprocessor 234 can forego the internal cache and instead use a cache within processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 is also capable of accessing an L2 cache within a partitioning unit (e.g., partitioning units 220A - 220N of FIG. 2) that is shared among all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data that can be stored in L1 cache 308.

[0074] Each processing cluster 214 can include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 can reside within memory interface 218 of FIG. 2. MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to the physical addresses of tiles and optionally to cache line indices. MMU 245 can include a translation lookaside buffer (TLB) or cache, which can reside within graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to allow for efficient request interleaving between partitioning units. Cache line indices can be used to determine whether a request to a cache line is a hit or a miss.

[0075] In graphics and computing applications, processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. As needed, texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234 and fetched from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs processed tasks to data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 216. The preROP 242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to ROP units, which may be collocated with partitioning units (e.g., partitioning units 220A - 220N of FIG. 2) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0076] It will be appreciated that the core architectures described herein are illustrative and variations and modifications are possible. Any number of processing units, such as graphics multiprocessors 234, texture units 236, preROP 242, etc., may be included within processing cluster 214. Further, although only one processing cluster 214 is shown, the parallel processing units as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0077] Figure 2D A graphics multiprocessor 234 is shown in accordance with one embodiment. In such embodiments, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0078] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched for execution by the instruction unit 254. The instruction unit 254 may dispatch instructions as thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions may access any address space in the local, shared, or global address space by specifying an address within the unified address space. The address mapping unit 256 may be used to translate an address in the unified address space into a different memory address accessible by the load / store unit 266.

[0079] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for the operands of the data paths connected to the functional units (e.g., GPGPU core 262, load / store unit 266) of the graphics multiprocessor 324. In one embodiment, the register file 258 is partitioned among each of the functional units such that each functional unit is assigned a dedicated portion of the register file 258. In one embodiment, the register file 258 is partitioned among different warps being executed by the graphics multiprocessor 324.

[0080] The GPGPU cores 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of the graphics multiprocessor 324. According to embodiments, the GPGPU cores 262 may be similar in architecture or may be different in architecture. For example and in one embodiment, a first portion of the GPGPU cores 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU cores includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units for performing specific functions such as copy rectangle or pixel blend operations. In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0081] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core may be generated by a shader compiler at compile time or may be automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logical unit.

[0082] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 324 to the register file 258 and the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 may operate at the same frequency as the GPGPU core 262, so data transfer between the GPGPU core 262 and the register file 258 has a very low latency. The shared memory 270 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 234. For example, the cache memory 272 may be used as a data cache to cache texture data transferred between the functional units and the texture unit 236. The shared memory 270 may also be used as a cached managed program. In addition to the automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 may also programmatically store data in the shared memory.

[0083] Figures 3A - 3B An additional graphics multiprocessor according to an embodiment is shown. The shown graphics multiprocessors 325, 350 are Figure 2C variants of the graphics multiprocessor 234. The shown graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of simultaneously executing a large number of execution threads.

[0084] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 includes Figure 2DMultiple additional instances of execution resource units related to the graphics multiprocessor 234. For example, the graphics multiprocessor 325 can include multiple instances of instruction units 332A - 332B, register files 334A - 334B, and (multiple) texture units 344A - 344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A - 336B, GPGPU cores 337A - 337B, GPGPU cores 338A - 338B) and multiple sets of load / store units 340A - 340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache 342, and a shared memory 346.

[0085] The various components can communicate via the interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbars to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, the interconnect structure 327 is a separate high - speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the GPGPU cores 336A - 336B, 337A - 337B, and 3378A - 338B can each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0086] Figure 3B Shows a graphics multiprocessor 350 according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A - 356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load - store units, as Figure 2D and Figure 3A shown. The execution resources 356A - 356D can work in concert with (multiple) texture units 360A - 360D for texture operations while sharing an instruction cache 354 and a shared memory 362. In one embodiment, the execution resources 356A - 356D can share the instruction cache 354 and the shared memory 362 as well as multiple instances of texture and / or data caches 358A - 358B. The various components can communicate via an interconnect structure 352 similar to the Figure 3A interconnect structure 327.

[0087] Those skilled in the art will understand that Figure 1 、 2AThe architectures described in 2D and 3A-3B are illustrative rather than restrictive with respect to the scope of embodiments of the present invention. Thus, the techniques described herein may be implemented on any suitably configured processing unit, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as the parallel processing unit 202 of FIG. 2), and one or more graphics processors or specialized processing units, without departing from the scope of the embodiments described herein.

[0088] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic for efficiently processing these commands / instructions.

[0089] Techniques for GPU - to - Host Processor Interconnect

[0090] Figure 4A A exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440-443 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher, depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the present invention are not limited to any particular communication protocol or throughput.

[0091] Additionally, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as those used for the high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via a high-speed link 433, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively,Figure 4A All communication between the various system components shown can be accomplished using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the present invention are not limited to any particular type of interconnect technology.

[0092] In one embodiment, each multi-core processor 405 - 406 is communicatively coupled to a processor memory 401 - 402 via a memory interconnect 430 - 431 respectively, and each GPU 410 - 413 is communicatively coupled to a GPU memory 420 - 423 via a GPU memory interconnect 450 - 453 respectively. The memory interconnects 430 - 431 and 450 - 453 can utilize the same or different memory access technologies. By way of example and not limitation, the processor memories 401 - 402 and the GPU memories 420 - 423 can be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memories such as 3D XPoint or Nano-RAM. In one embodiment, a portion of the memory can be volatile memory and another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0093] As described below, although the various processors 405 - 406 and GPUs 410 - 413 can be physically coupled to specific memories 401 - 402, 420 - 423 respectively, a unified memory architecture can be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among all the various physical memories. For example, each of the processor memories 401 - 402 can include a 64GB system memory address space, and each of the GPU memories 420 - 423 can include a 32GB system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0094] Figure 4B Additional details of the interconnect between a multi-core processor 407 and a graphics acceleration module 446 in accordance with one embodiment are shown. The graphics acceleration module 446 can include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 can be integrated on the same package or chip as the processor 407.

[0095] The illustrated processor 407 includes a plurality of cores 460A - 460D, each having a translation lookaside buffer 461A - 461D and one or more caches 462A - 462D. The cores may include various other components for executing instructions and processing data (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.), which are not shown to avoid obscuring the basic principles of the present invention. The caches 462A - 462D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by a set of cores 460A - 460D. For example, one embodiment of processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 caches and the L3 cache is shared by two adjacent cores. The processor 407 and the graphics accelerator integration module 446 are connected to the system memory 441, which may include processor memories 401 - 402.

[0096] Consistency is maintained for the data and instructions stored in the various caches 462A - 462D, 456, and the system memory 441 through inter - core communication via the coherence bus 464. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles of the present invention.

[0097] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the cores. Specifically, the interface 435 provides connectivity to the proxy circuit 425 via a high - speed link 440 (e.g., PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the high - speed link 440.

[0098] In one implementation, the accelerator integrated circuit 436 represents multiple graphics processing engines 431, 432, N of the graphics acceleration module 446, providing cache management, memory access, context management, and interrupt management services. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, N may be separate GPUs integrated on a common package, line card, or chip.

[0099] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, the data stored in the cache 438 and the graphics memories 433-434, N is kept consistent with the core caches 462A-462D, 456, and the system memory 411. As mentioned, this may be done via the proxy circuit 425, which participates in the cache coherence mechanism on behalf of the cache 438 and the memories 433-434, N (e.g., sending updates related to cache line modifications / accesses on the processor caches 462A-462D, 456 to the cache 438 and receiving updates from the cache 438).

[0100] A set of registers 445 stores context data for the threads executed by the graphics processing engines 431-432, N, and the context management circuit 448 manages the thread contexts. For example, the context management circuit 448 may perform save and restore operations to save and restore the contexts of various threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 448 may store the current register values into a specified area in memory (e.g., identified by a context pointer). It may then restore the register values when returning to that context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0101] In one implementation, the MMU 439 converts virtual / valid addresses from the graphics processing engine 431 into real / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator modules 446 may be dedicated to a single application executing on the processor 407 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, in which the resources of the graphics processing engines 431-432, N are shared among multiple applications or virtual machines (VMs). The resources may be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0102] Accordingly, the accelerator integrated circuit acts as a bridge to the system of the graphics accelerator modules 446 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 436 may provide virtualization facilities for the host processor to manage the virtualization of the graphics processing engine, interrupts, and memory management.

[0103] Because the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N such that they appear as independent units to the system.

[0104] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store the instructions and data being processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories such as 3D XPoint or Nano-Ram.

[0105] In one embodiment, to reduce data traffic on the high-speed link 440, a biasing technique is used to ensure that the data stored in the graphics memories 433-434, M is the data that will be most frequently used by the graphics processing engines 431-432, N and is preferably not used (or at least not frequently used) by the cores 460A-460D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not the graphics processing engines 431-432, N) within the caches 462A-462D, 456 of the cores and the system memory 411.

[0106] Figure 4C Another embodiment is shown in which the accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via the interface 437 and the interface 435 (again, which can utilize any form of bus or interface protocol) over the high-speed link 440. The accelerator integrated circuit 436 can perform the same operations as those described with respect to Figure 4B but may perform the operations with higher throughput considering its proximity to the coherence bus 462 and the caches 462A-462D, 426.

[0107] One embodiment supports different programming models, which include a dedicated process programming model (without virtualization of the graphics acceleration module) and a shared programming model (with virtualization). The shared programming model can include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

[0108] In one embodiment of the dedicated process model, the graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. This single application can aggregate other application requests to the graphics engines 431-432, N, thereby providing virtualization within the VM / partition.

[0109] In the dedicated process programming model, the graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires the hypervisor to virtualize the graphics processing engines 431-432, N to allow access by each operating system. For a single-partition system without a hypervisor, the graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431-432, N to provide access to each process or application.

[0110] For a shared programming model, the graphics acceleration module 446 or a separate graphics processing engine 431-432, N uses a process handle to select process elements. In one embodiment, the process elements are stored in the system memory 411 and can be addressed using the effective address to physical address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when it registers its context with the graphics processing engine 431-432, N (i.e., calls system software to add a process element to a linked list of process elements). The lower 16 bits of the process handle can be the offset of the process element within the linked list of process elements.

[0111] Figure 4D A exemplary accelerator integration slice 490 is shown. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 436. An application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to a GPU call 481 from an application 480 executing on the processor 407. The process element 483 contains the process state for the corresponding application 480. The work descriptor (WD) 484 contained within the process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to a job request queue within the address space 482 of the application.

[0112] The graphics acceleration module 446 and / or a separate graphics processing engine 431-432, N can be shared by all or a subset of the processes in the system. Embodiments of the present invention include infrastructure for establishing process state and sending the WD 484 to the graphics acceleration module 446 to begin a job in a virtualized environment.

[0113] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 446 or a separate graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owned partition, and the operating system initializes the accelerator integrated circuit 436 for the owned process when the graphics acceleration module 446 is assigned.

[0114] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be completed by one of the graphics processing engines in the graphics acceleration module 446. Data from the WD 484 can be stored in the register 445 and used by the MMU 439, interrupt management circuit 447, and / or context management circuit 448 as shown. For example, one embodiment of the MMU 439 includes segment / page walk circuitry for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process interrupt events 492 received from the graphics acceleration module 446. When performing a graphics operation, the MMU 439 converts the effective address 493 generated by the graphics processing engines 431 - 432, N into a physical address.

[0115] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431 - 432, N and / or graphics acceleration module 446, and the same set of registers 445 can be initialized by a hypervisor or an operating system. Each of these replicated registers can be included in the accelerator integrated slice 490. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0116] Table 1 - Hypervisor Initialized Registers

[0117] 1 Slice Control Register 2 Actual Address (RA) Scheduled Process Area Pointer 3 Permission Mask Override Register 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector Table Entry Limit 6 Status Register 7 Logical Partition ID 8 Actual Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0118] Table 2 shows exemplary registers that can be initialized by the operating system.

[0119] Table 2 - Operating System Initialized Registers

[0120] 1 Process and Thread Identification 2 Effective Address (EA) Context Save / restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Permission Mask 6 Work Descriptor

[0121] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431 - 432, N. It contains all the information required for the graphics processing engines 431 - 432, N to do their work, or it can be a pointer to a memory location in a command queue where the work to be completed has been established for the application.

[0122] Figure 4E Additional details of one embodiment of the shared model are shown. This embodiment includes the hypervisor physical address space 498 in which the process element list 499 is stored. The hypervisor physical address space 498 can be accessed via the hypervisor 496, which virtualizes the graphics acceleration module engine for the operating system 495.

[0123] The shared programming model allows all or a subset of the processes from all or a subset of the partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time slice sharing and graphics directed sharing.

[0124] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) The job requests of the application must be autonomous (i.e., do not require maintaining state between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 guarantees to complete the job requests of the application within a specified amount of time, including any translation faults, or the graphics acceleration module 446 provides the ability to preempt the processing of jobs. 3) When operating in the directed sharing programming model, fairness of the graphics acceleration module 446 must be guaranteed between processes.

[0125] In one embodiment, for the shared model, it is required that the application 480 makes an operating system 495 system call using the graphics acceleration module 446 type, work descriptor (WD), access mask register (AMR) value, and context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the following forms: a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure for describing the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the user access mask override register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 496 may optionally apply the current access mask override register (AMOR) value before placing the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the valid address of a region in the application's address space 482 for the graphics acceleration module 446 to save and restore the context state. This pointer is optional if state saving between jobs is not required or when a job is preempted. The context save / restore region can be pinned system memory.

[0126] Upon receiving a system call, the operating system 495 may verify that the application 480 is registered and has been granted permission to use the graphics acceleration module 446. The operating system 495 then uses the information shown in Table 3 to call the hypervisor 496.

[0127] Table 3 - OS Hypervisor Call Parameters

[0128] 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) Value (May be Masked) 3 Effective Address (EA) Context Save / restore Area Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0129] Upon receiving a hypervisor call, the hypervisor 496 verifies that the operating system 495 is registered and has been granted permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into the linked list of process elements for the corresponding graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0130] Table 4 - Process Element Information

[0131] 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) Value (May be Masked) 3 Effective Address (EA) Context Save / restore Area Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table Derived from Hypervisor Call Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Actual Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0132] In one embodiment, the hypervisor initializes the registers 445 of multiple accelerator integrated slices 490.

[0133] As Figure 4F shown, one embodiment of the present invention employs unified memory that can be addressed via a common virtual memory address space for accessing the physical processor memories 401 - 402 and the GPU memories 420 - 423. In this implementation, operations executed on the GPUs 410 - 413 utilize the same virtual / effective memory address space to access the processor memories 401 - 402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 401, a second portion is allocated to the second processor memory 402, a third portion is allocated to the GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memories 401 - 402 and the GPU memories 420 - 423, allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0134] In one embodiment, the bias / coherency management circuits 494A - 494E within one or more of the MMUs 439A - 439E ensure cache coherency between the host processor (e.g., 405) and the caches of the GPUs 410 - 413, and implement a bias technique for indicating the physical memory in which certain types of data should be stored. Although in Figure 4FMultiple instances of the bias / coherence management circuits 494A - 494E are shown, but the bias / coherence circuitry may be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0135] One embodiment allows the GPU - attached memories 420 - 423 to be mapped as portions of system memory and accessed using shared virtual memory (SVM) techniques without suffering the typical performance penalties associated with full - system cache coherence. The ability to access the GPU - attached memories 420 - 423 as system memory without heavy cache - coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows the host - processor 405 software to set operands and access computation results without the overhead of traditional I / O direct memory access (DMA) data copies. Such traditional copies involve driver calls, interrupts, and memory - mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory access. At the same time, the ability to access the GPU - attached memories 420 - 423 without cache - coherence overhead can be critical to the execution time of offloaded computations. For example, in the case of a large number of streaming write - memory transactions, the cache - coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 410 - 413. The efficiency of operand setting, result access, and GPU computation all play a role in determining the effectiveness of GPU offloading.

[0136] In one implementation, the choice between GPU bias and host - processor bias is driven by a bias - tracker data structure. For example, a bias table may be used, which may be a page - granularity structure (i.e., controlled at the granularity of memory pages) that includes 1 or 2 bits per GPU - attached memory page. The bias table may be implemented in the stolen - memory ranges of one or more of the GPU - attached memories 420 - 423, with or without a bias cache in the GPUs 410 - 413 (e.g., to cache frequently / most - recently - used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0137] In one implementation, prior to an actual access to the GPU memory, the bias table entries associated with each access to the GPU-attached memories 420-423 are accessed, thereby causing the following operations. First, local requests from the GPUs 410-413 that find their pages in the GPU bias are forwarded directly to the corresponding GPU memories 420-423. (For example, via the high-speed link discussed above) Local requests from the GPUs that find their pages in the host bias are forwarded to the processor 405. In one embodiment, requests from the processor 405 that find the requested page in the host processor bias complete the requests like normal memory reads. Alternatively, requests involving GPU bias pages can be forwarded to the GPUs 410-413. If the GPU is not currently using the page, the GPU can then convert the page to the host processor bias.

[0138] The bias state of a page can be changed via a software-based mechanism, a software-assisted-by-hardware mechanism, or for a limited set of cases a pure hardware mechanism.

[0139] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or enqueues a command descriptor) to the GPU to guide it to change the bias state, and for certain conversions, a cache dump purge operation is performed in the host. The cache dump purge operation is required for the conversion from the host processor 405 bias to the GPU bias, but not for the reverse conversion.

[0140] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages non-cacheable by the host processor 405. To access these pages, the processor 405 can request access from the GPU 410, which may or may not immediately grant access, depending on the implementation. Thus, to reduce the communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU bias pages are those pages that are required by the GPU but not by the host processor 405, and vice versa.

[0141] Graphics Processing Pipeline

[0142] Figure 5 A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor may implement the shown graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein (such as the parallel processor 200 of FIG. 2), which in one embodiment is Figure 1Variants of the (multiple) parallel processors 112. Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., the parallel processing unit 202 of FIG. 2) as described herein. For example, shader units (e.g., the graphics multiprocessor 234 of FIG. 3) may be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assemblers 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 may also be performed by other processing engines and corresponding partitioning units (e.g., the partitioning units 220A-220N of FIG. 2) within a processing cluster (e.g., the processing cluster 214 of FIG. 3). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be performed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., the parallel processor memory 222 as in FIG. 2) via the memory interface 528, which may be an instance of the memory interface 218 of FIG. 2.

[0143] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs vertex data including vertex attributes to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to light and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data and may be programmed to transform the vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0144] A first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0145] The tessellation control processing unit 508 treats the input vertices as control points for geometric patches. The control points are transformed from an input representation (e.g., the basis of the patch) to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also compute tessellation factors for the edges of the geometric patches. The tessellation factors apply to individual edges and quantify the view-dependent level of detail associated with the edges. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and subdivide the patch into a plurality of geometric primitives such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate vertex attributes and surface representations for each vertex associated with the geometric primitives.

[0146] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphics primitives into one or more new graphics primitives and compute parameters for rasterizing the new graphics primitives.

[0147] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying the new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scale, cull, and clip unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometric data. The viewport scale, cull, and clip unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0148] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to the raster operations unit 526. The fragment / pixel processing unit 524 can read data stored in the parallel processor memory or the system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity according to the sampling rate configured for the processing unit.

[0149] The raster operations unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, blending, etc., and outputs the pixel data as processed graphics data for storage in a graphics memory (e.g., the parallel processor memory 222 as shown in FIG. 2, and / or the system memory 104 as shown in Figure 1 ), for display on one or more display devices 110 or for further processing by one of the one or more processors 102 or the (multiple) parallel processors 112. In some embodiments, the raster operations unit 526 is configured to compress the z or color data written to the memory and decompress the z or color data read from the memory.

[0150] Machine Learning Overview

[0151] A machine learning algorithm is an algorithm that can learn based on a set of data. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a data set. For example, an image recognition algorithm can be used to determine which of several categories a given input belongs to; a regression algorithm can output a numerical value given an input; and a pattern recognition algorithm can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0152] A demonstration type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feedforward network. A feedforward network can be implemented as an acyclic graph where nodes are arranged in layers. Generally, a feedforward network topology includes an input layer and an output layer, which are separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating an output in the output layer. The network nodes are fully connected via edges to the nodes in the adjacent layer, but there are no edges between the nodes within each layer. The data received at the nodes of the input layer of the feedforward network is propagated (i.e., "fed forward") via an activation function to the nodes of the output layer, and the activation function calculates the state of the nodes in each successive layer of the network based on coefficients ("weights"), and the coefficients are respectively associated with each of the edges connecting the layers. Depending on the specific model represented by the algorithm being executed, the output from the neural network algorithm can take various forms.

[0153] Before a machine learning algorithm can be used to model a particular problem, a training data set is used to train the algorithm. Training a neural network involves selecting a network topology, using a set of training data representing the problem being modeled by the network, and adjusting the weights until the network model has a minimum error for all instances of the training data set. For example, during the supervised learning training process for a neural network, the output produced by the network in response to an input representing an instance in the training data set is compared with the "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted to minimize the error as the error signal is propagated backward through the layers of the network. When the error for each output generated based on the instances of the training data set is minimized, the network is considered to be "trained".

[0154] The accuracy of a machine learning algorithm can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and may take a large amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks because the computations performed when adjusting the coefficients in a neural network naturally lend themselves to a parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to use the parallel processing hardware within a general-purpose graphics processing device.

[0155] Figure 6It is a generalized diagram of a machine learning software stack 600. The machine learning application 602 can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 602 can include specialized software that can be used to train a neural network before deployment and / or the training and inference functions of the neural network. The machine learning application 602 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0156] Hardware acceleration for the machine learning application 602 can be enabled via the machine learning block rack 604. The machine learning block rack 604 can provide a machine learning primitive library. Machine learning primitives are the basic operations that machine learning algorithms typically perform. Without the machine learning block rack 604, the developers of machine learning algorithms would be required to create and optimize the main computational logic associated with the machine learning algorithms and then re-optimize that computational logic when a new parallel processor is developed. Instead, the machine learning application can be configured to use the primitives provided by the machine learning block rack 604 to perform the necessary computations. Demonstrative primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training a convolutional neural network (CNN). The machine learning block rack 604 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0157] The machine learning block rack 604 can process the input data received from the machine learning application 602 and generate appropriate inputs to the computational block rack 606. The computational block rack 606 can abstract the basic instructions provided to the GPGPU driver 608 so that the machine learning block rack 604 can utilize hardware acceleration via the GPGPU hardware 610 without requiring the machine learning block rack 604 to be very familiar with the architecture of the GPGPU hardware 610. Additionally, the computational block rack 606 can enable hardware acceleration for the machine learning block rack 604 across multiple types and generations of GPGPU hardware 610.

[0158] GPGPU Machine Learning Acceleration

[0159] Figure 7 Illustrated is a highly parallel general-purpose graphics processing unit 700 according to an embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 700 can be configured to be particularly efficient when processing computational workloads of the type associated with training deep neural networks. Additionally, the GPGPU 700 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster to improve the training speed of particularly deep neural networks.

[0160] The GPGPU 700 includes a host interface 702 for enabling connection with a host processor. In one embodiment, the host interface 702 is a PCI Express interface. However, the host interface can also be a vendor-specific communication interface or communication fabric. The GPGPU 700 receives commands from the host processor and distributes execution threads associated with those commands to a set of compute clusters 706A - 706H using a global scheduler 704. The compute clusters 706A - 706H share a cache memory 708. The cache memory 708 can act as a cache in the cache memories within the compute clusters 706A - 706H.

[0161] The GPGPU 700 includes memories 714A - 714B that are coupled to the compute clusters 706A - H via a set of memory controllers 712A - 712B. In various embodiments, the memories 714A - 714B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM) (including graphics double data rate (GDDR) memory) or 3D stacked memory (including but not limited to high bandwidth memory (HBM)).

[0162] In one embodiment, each compute cluster 706A - 706H includes a set of graphics multiprocessors, such as Figure 4A the graphics multiprocessor 400. The graphics multiprocessors of the compute clusters include multiple types of integer and floating-point logic units that can perform computational operations at a range of precisions, including precisions suitable for machine learning computations. For example and in one embodiment, at least one subset of the floating-point units in each of the compute clusters 706A - 706H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0163] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate via host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 700 to GPU link 710, which enables direct connection to other instances of the GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect to transfer data to and receive data from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 are located in separate data processing systems and communicate via a network device that can be accessed via host interface 702. In one embodiment, in addition to or as an alternative to host interface 702, GPU link 710 can be configured to enable connection to a host processor.

[0164] Although the illustrated configuration of GPGPU 700 can be configured to train a neural network, one embodiment provides an alternative configuration of GPGPU 700 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, GPGPU 700 includes fewer computing clusters 706A - 706H relative to the training configuration. Additionally, the memory technologies associated with memories 714A - 714B may differ between the inference configuration and the training configuration. In one embodiment, the inference configuration of GPGPU700 can support inference-specific instructions. For example, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations for deployed neural networks.

[0165] Figure 8 A multi-GPU computing system 800 according to an embodiment is illustrated. The multi-GPU computing system 800 can include a processor 802 that is coupled to multiple GPGPUs 806A - 806D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI express switch device that couples the processor 802 to a PCI express bus through which the processor 802 can communicate with the set of GPGPUs 806A - 806D. Each of the multiple GPGPUs 806A - 806D can be Figure 7An example of the GPGPU 700. The GPGPUs 806A - 806D can be interconnected via a set of high - speed point - to - point GPU - to - GPU links 816. The high - speed GPU - to - GPU links can be connected to each of the GPGPUs 806A - 806D via dedicated GPU links (such as the GPU link 710 as in Figure 7 ). The P2P GPU link 816 enables direct communication between each of the GPGPUs 806A - 806D without requiring communication through the host interface bus to which the processor 802 is connected. In cases where GPU - to - GPU traffic involves the P2P GPU link, the host interface bus can still be used for system memory access or for communicating with other instances of the multi - GPU computing system 800 via, for example, one or more network devices. Although in the illustrated embodiment the GPGPUs 806A - 806D are connected to the processor 802 via the host interface switch 804, in one embodiment the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A - 806D.

[0166] Machine Learning Neural Network Implementation

[0167] The computing architectures provided by the embodiments described herein can be configured to perform types of parallel processing particularly suitable for training and deploying neural networks for machine learning. A neural network can be generally characterized as a network of functions with graph relationships. As is well known in the art, there are multiple types of neural network implementations used in machine learning. One exemplary type of neural network is the feed - forward network as previously described.

[0168] A second exemplary type of neural network is the convolutional neural network (CNN). A CNN is a specialized feed - forward neural network for processing data with a known grid - like topology (such as image data). Thus, CNNs are commonly used in computer vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors inspired by receptive fields found in the retina), and the output of each set of filters is propagated to the nodes in successive layers of the network. The computations for a CNN include applying the convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized kind of mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called the feature map. For example, the input to a convolutional layer can be a multi - dimensional data array that defines the various color components of an input image. The convolution kernel can be a multi - dimensional parameter array, where the parameters are adapted through the training process for the neural network.

[0169] A Recurrent Neural Network (RNN) is a type of feedforward neural network that includes feedback connections between layers. RNN enables modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes a loop. The loop represents the influence of the current value of a variable on its own value at a future time, as at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. Due to the variable nature that language data can include, this feature makes RNNs particularly useful for language processing.

[0170] The figures described below present exemplary feedforward, CNN, and RNN networks and describe the general processes for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non - limiting with respect to any particular embodiments described herein, and generally, the concepts illustrated can be generally applied to deep neural networks and machine learning techniques.

[0171] The exemplary neural networks described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. Contrary to shallow neural networks that include only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Training deeper neural networks is generally more computationally intensive. However, the additional hidden layers of the network enable multi - step pattern recognition, which results in reduced output error relative to shallow machine learning techniques.

[0172] The deep neural networks used in deep learning typically include a front - end network to perform feature recognition coupled to a back - end network representing a mathematical model that can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representation provided to the model. Deep learning enables performing machine learning without requiring hand - crafted feature engineering for the model. Instead, the deep neural network can learn features based on the statistical structure or correlations within the input data. The learned features can be provided to the mathematical model, which can map the detected features into an output. The mathematical model used by the network is generally specialized for the particular task to be performed, and different models will be used to perform different tasks.

[0173] Once the neural network is structured, a learning model can be applied to the network to train the network to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Backpropagation of errors is a commonly used method for training neural networks. An input vector is presented to the network for processing. A loss function is used to compare the output of the network with the desired output, and an error value is calculated for each neuron in the output layer. Then, the error values are propagated backward until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using an algorithm such as the stochastic gradient descent algorithm to update the weights of the neural network.

[0174] Figures 9A - 9B A exemplary convolutional neural network is illustrated. Figure 9A Illustrates the various layers within the CNN. As Figure 9A shown, an exemplary CNN for modeling image processing can receive an input 902 that describes the red, green, and blue (RGB) components of an input image. The input 902 can be processed by a plurality of convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The output from the plurality of convolutional layers can optionally be processed by a set of fully connected layers 908. Neurons in the fully connected layers have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layer 908 can be used to generate an output result from the network. Matrix multiplication rather than convolution can be used to calculate the activations within the fully connected layer 908. Not all CNN implementations use the fully connected layer 908. For example, in some implementations, the convolutional layer 906 can generate the output of the CNN.

[0175] Convolutional layers are sparsely connected, which is different from the traditional neural network configuration found in the fully connected layer 908. Traditional neural network layers are fully connected such that each output unit interacts with each input unit. However, convolutional layers are sparsely connected because the output of the convolution of the domain (rather than the corresponding state values of each node in the domain) is input to the nodes of the subsequent layer, as illustrated. The kernel associated with the convolutional layer performs a convolution operation, and the output of the convolution operation is sent to the next layer. The dimensionality reduction performed within the convolutional layer is one aspect that enables the CNN to be scaled to handle large images.

[0176] Figure 9B Illustrates an exemplary computational stage within the convolutional layer of a CNN. The input 912 to the convolutional layer of the CNN can be processed in three stages of the convolutional layer 914. These three stages can include a convolution stage 916, a detector stage 918, and a pooling stage 920. The convolutional layer 914 can then output the data to a successive convolutional layer. The last convolutional layer of the network can generate output feature map data or provide an input to the fully connected layer, e.g., to generate classification values for the input to the CNN.

[0177] During the convolution stage 916, a number of convolutions are performed in parallel to produce a set of linear activations. The convolution stage 916 may include an affine transformation, which is any transformation that can be specified as a linear transformation plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function (e.g., a neuron) connected to a specific region in the input, and the specific region can be determined as the local region associated with the neuron. The neuron computes the dot product between the weights of the neuron and the region in the local input to which the neuron is connected. The output from the convolution stage 916 defines a set of linear activations processed by successive stages of the convolutional layer 914.

[0178] The linear activations can be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a non-linear activation function. The non-linear activation function increases the non-linear nature of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation functions can be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x) =max( 0 , x ) such that the activation is thresholded at zero.

[0179] The pooling stage 920 uses a pooling function that replaces the output of the convolutional layer 906 with summary statistics of nearby outputs. The pooling function can be used to introduce translational invariance into the neural network such that small translations of the input do not change the pooled output. Invariance to local translations can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 920, including max pooling, average pooling, and l2-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations replace it with an additional convolutional stage that has an increased stride relative to the previous convolutional stage.

[0180] The output from the convolutional layer 914 can then be processed by the next layer 922. The next layer 922 can be either an additional convolutional layer or one of the fully connected layers 908. For example, Figure 9A the first convolutional layer 904 can output to the second convolutional layer 906, and the second convolutional layer can output to the first layer of the fully connected layer 908.

[0181] Figure 10FIG. illustrates a exemplary recurrent neural network 1000. In a recurrent neural network (RNN), the previous state of the network affects the output of the current state of the network. The RNN can be constructed in a variety of ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, an RNN can be used to perform statistical language modeling to predict the upcoming word given a previous sequence of words. The illustrated RNN 1000 can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 that implements a recurrent function, a feedback mechanism 1005 that enables a 'memory' of the previous state, and an output layer 1006 that outputs the result. The RNN 1000 operates based on time steps. The state of the RNN at a given time step is affected by the previous time step via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) can be processed by the hidden layer 1004 using the state information determined during the processing of the initial input (x1). A given state can be calculated as s t = f ( Ux t + Ws t-1 ), where U and W are parameter matrices. The function f is generally non-linear, such as the hyperbolic tangent function (Tanh) or a variant of the rectifier function f (x) = max( 0 , x ). However, the specific mathematical functions used in the hidden layer 1004 can vary depending on the specific implementation details of the RNN 1000.

[0182] In addition to the basic CNN and RNN networks described, variations of those networks can also be enabled. One example of an RNN variant is the long short-term memory (LSTM) RNN. The LSTM RNN is capable of learning long-term dependencies that may be necessary for processing longer language sequences. A variant of the CNN is the convolutional deep belief network, which has a structure similar to the CNN and is trained in a manner similar to the deep belief network. A deep belief network (DBN) is a generative neural network composed of multiple layers of stochastic (random) variables. The DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining a set of optimal initial weights for the neural network.

[0183] Figure 11 Illustrates the training and deployment of a deep neural network. Once a given network has been structured for a task, a training data set 1102 is used to train the neural network. A variety of training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6 the machine learning framework 604 can be configured as a training framework 604. The training framework 604 can be hooked up to an untrained neural network 1106 and enable the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1108.

[0184] To begin the training process, initial weights can be selected randomly or by pre-training using a deep belief network. Then, the training loop is performed in a supervised or unsupervised manner.

[0185] [[ID=⑨]]Supervised learning is a learning method in which training is performed as a mediation operation, such as when the training data set 1102 includes the input paired with the desired output, or when the training data set includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the input and compares the resulting output with a set of expected or desired outputs. Then, the error is backpropagated through the system. The training framework 1104 can be adjusted to adjust the weights that control the untrained neural network 1106. The training framework 1104 can provide tools to monitor how well the untrained neural network 1106 converges towards a model suitable for generating correct answers based on the known input data. The training process occurs repeatedly as the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural network 1108. Then, the trained neural network 1108 can be deployed to perform any number of machine learning operations.

[0186] Unsupervised learning is a learning method in which the network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled input and can determine how individual inputs relate to the overall data set. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1107 that can perform operations useful in reducing data dimensionality. Unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the input data set that deviate from the normal data pattern.

[0187] Note: In the original text, there is a tag "⑨" which seems to be an incorrect tag format. I have translated it as "⑨" in the English version for consistency. If this is not what you intended, please clarify.Variations of supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training data set 1102 includes a mixture of labeled and unlabeled data having the same distribution. Incremental learning is a variant of supervised learning in which input data is continuously used to further train the model. Incremental learning enables the trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge instilled within the network during initial training.

[0188] Regardless of whether it is supervised or unsupervised, the training process for a particularly deep neural network can be computationally too intensive for a single computing node. A distributed network of computing nodes can be used instead of a single computing node to accelerate the training process.

[0189] Figure 12 is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes to perform supervised or unsupervised training of a neural network. Each of the distributed computing nodes can include one or more host processors and one or more of the general processing nodes, such as Figure 7 the highly parallel general-purpose graphics processing unit 700 as in. As illustrated, distributed learning can perform model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1204.

[0190] In model parallelism 1202, different computing nodes in the distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes of the distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of the neural network enables the training of very large neural networks where the weights of all layers will not fit into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0191] In data parallelism 1204, different nodes of a distributed network have a complete instance of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different approaches to data parallelism are possible, data parallel training methods all require techniques for combining the results and synchronizing the model parameters across the nodes. Demonstrative methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are communicated rather than the parameters from the nodes to the parameter server. Additionally, update-based data parallelism can be performed in a decentralized manner where the updates are compressed and communicated between the nodes.

[0192] For example, the combined model and data parallelism 1206 can be implemented in a distributed system in which each computing node includes multiple GPUs. Each node can have a complete instance of the model, where individual GPUs within each node are used to train different parts of the model.

[0193] Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and GPGPUs described herein can each implement various techniques for reducing the overhead of distributed training, including techniques for enabling high-bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

[0194] Demonstration Machine Learning Applications

[0195] Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. The scope of computer vision applications ranges from replicating human visual capabilities such as face recognition to creating new classes of visual capabilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced by objects visible in a video. Machine learning accelerated by parallel processors enables training computer vision applications using training data sets that are significantly larger than previously feasible, and enables deployment of inference systems using low-power parallel processors.

[0196] Machine learning accelerated by parallel processors has autonomous driving applications, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. The accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described herein can enable the rapid training of increasingly complex neural networks for autonomous driving solutions and enable the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0197] Parallel-processor-accelerated deep neural networks have enabled machine learning methods for automatic speech recognition (ASR). ASR includes creating a function that computes the most likely language sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled the replacement of previously used hidden Markov models (HMMs) and Gaussian mixture models (GMMs) for ASR.

[0198] Parallel-processor-accelerated machine learning can also be used to accelerate natural language processing. Automated learning programs can use statistical inference algorithms to produce models that are robust to incorrect or unfamiliar inputs. Demonstrative natural language processor applications include automatic machine translation between human languages.

[0199] The parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are generally highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Demonstrative parallel processors suitable for training include Figure 7 the highly parallel general-purpose graphics processing unit 700 and Figure 8 the multi-GPU computing system 800. In contrast, deployed machine learning platforms generally include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0200] Figure 13Illustrated is an exemplary inference system-on-a-chip (SOC) 1300 suitable for performing inference using a trained model. The SOC 1300 can integrate processing components, including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. The SOC 1300 can additionally include on-chip memory 1305, which can enable a shared on-chip data pool accessible by each of the processing components. The processing components can be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of the SOC 1300 can be used as part of the main control system for an autonomous vehicle. In the case where the SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards for the deployment jurisdiction.

[0201] During operation, the media processor 1302 and the vision processor 1304 can work in concert to accelerate computer vision operations. The media processor 1302 can enable low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 1305. The vision processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames using a trained image recognition model. For example, the vision processor 1304 can accelerate the convolutional operations for a CNN used to perform image recognition on high-resolution video data, and the backend model computations are performed by the GPGPU 1306.

[0202] The multi-core processor 1308 can include control logic to assist in the ordering and synchronization of shared memory operations and data transfers performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 can also act as an application processor to execute software applications that can use the inference computing capabilities of the GPGPU 1306. For example, at least a portion of the navigation and driving logic can be implemented in software executed on the multi-core processor 1308. Such software can directly issue computational workloads to the GPGPU 1306, or can issue computational workloads to the multi-core processor 1,308, which can offload at least a portion of those operations to the GPGPU 1306.

[0203] The GPGPU 1306 may include a computing cluster, such as a low-power configuration of computing clusters 706A - 706H within the highly parallel general-purpose graphics processing unit 700. The computing clusters within the GPGPU 1306 may support instructions that are specifically optimized to perform inference computations on a trained neural network. For example, the GPGPU 1306 may support instructions for performing low-precision computations, such as 8-bit and 4-bit integer vector operations.

[0204] [[ID=

[0205] Embodiments described herein provide high-level machine learning computation primitives that can be used to abstract many of the underlying computational details of performing machine learning computations. The high-level primitives described herein enable software logic to request high-level machine learning operations while abstracting the underlying implementation details of those operations. For example and in one embodiment, software logic may request a convolution operation on an image using a given set of filters. A single high-level instruction may be executed, having operands that define the addresses of buffers storing the filter and / or kernel data and the input and output buffer addresses. The GPGPU may then break the high-level convolution instruction into multiple sub-operations to be executed by the underlying computational units of the GPGPU. In one embodiment, direct hardware support is provided for one or more subroutines of the basic linear algorithm subprogram (BLAS), although embodiments may provide hardware support for other subroutine libraries. Compiler logic and associated runtime libraries may compile source code that utilizes the supported high-level computational subroutines and output the compiled source code (which calls into the machine learning macro instruction unit).

[0206] ​

[0207] Hardware accelerators for computer vision and machine learning can improve the energy efficiency of applications such as object, face, and speech recognition by orders of magnitude. These accelerators use an array of interconnected processing elements (PEs), where the multiply-accumulate circuit is the dominant performance, area, and energy for mapping the key algorithms used in CNN computing operations. For example, some machine learning hardware accelerators use narrow bit-width (16b) fixed-point multiply-accumulate data path building blocks to meet the strict memory, area, and power budgets of SoCs in low-power or embedded spaces. Better result quality can be achieved for certain datasets and algorithms with the higher dynamic range provided by floating-point numbers / computations, while still maintaining the same memory footprint (16b operands). Previous hardware solutions for accommodating both types of numerical computations employed separate fixed-point and floating-point data paths or PEs, incurring a high area cost for implementing such flexibility. In contrast, the embodiments described herein provide a combined integer / floating-point fused multiply-accumulate and multiply-accumulation data path that utilizes an existing signed integer multiply-accumulate circuit to implement a floating-point mantissa multiply-accumulate operation. In one embodiment, floating-point support is enabled in a combined floating-point / integer unit without increasing the input / output data width and data memory footprint by adding only the circuitry required for alignment / normalization shifting and exponent units. A single control signal is used to switch between floating-point and integer computing modes on a per-cycle basis.

[0208] The combined integer / floating-point unit provided by the embodiments can be supplemented with various types of machine learning acceleration units that can be integrated into a GPGPU. The embodiments described herein provide logic for enabling additional instructions that combine fused-multiply-accumulate operations with neural network activation functions such as the rectified linear unit function (RELU), sigmoid function, or hard sigmoid function.

[0209] One embodiment enables an extension of 16-bit floating-point encoding to support alternative encodings from the standard IEEE 754 half-precision floating-point format. The IEEE half-precision floating-point format specifies 1 bit for the sign, 5 bits for the exponent, and 10 bits for the fractional part. The embodiments described herein can selectively support alternative encodings of FP16 data based on the pattern of the data to be encoded. In one embodiment, the supported alternative format specifies 1 bit for the sign, with 8 bits for the exponent and 7 bits for the fractional component. One embodiment allows encoding with 1 bit for the sign, 3 bits for the exponent, and 12 bits for the fractional component. In such embodiments, different instruction sets support different floating-point encodings, allowing developers to select an encoding based on the instructions specified in the program code. In one embodiment, different floating-point encodings can be used when rounding or downsampling floating-point data, such as from an accumulated 32-bit floating-point value to a 16-bit value.

[0210] The merged floating-point unit described herein can selectively perform 16-bit integer or floating-point operations on a per-cycle basis. One embodiment enables dynamic reconfiguration of the floating-point unit described herein to enable multi-format support. For example, using a multi-channel configuration, the 16-bit integer or floating-point unit can be configured to perform two-channel 32-bit operations or four-channel 64-bit operations. Such logic enables floating-point logic optimized for low-precision inference operations to be clustered for higher-precision training operations.

[0211] One embodiment provides a stochastic rounding unit and a statistical accumulator for low-precision networks. Stochastic rounding enables increased accuracy for classical quantization and rounding of low-precision deep neural networks. The rounding unit can operate in different modes. The first mode is a stochastic mode that uses a random number generator to control the rounding unit. The second mode uses the probability distribution of the output on subsequent inputs and utilizes a near-data statistical estimator unit coupled to the GPGPU memory.

[0212] The techniques described herein can be implemented within a general-purpose computing system with machine learning optimizations provided via a machine learning accelerator unit. The multi-processor provided by the embodiments described herein is shown in ​ FIG.

[0213] ​ is a block diagram of a multi-processor unit 1400 according to an embodiment. The multi-processor unit 1400 can be a variant of the graphics multi-processor 234 of ​ . The multi-processor unit 1400 includes a fetch and decode unit 1402, a branch unit 1404, a register file 1406, a thread manager 1406, a single instruction multiple thread unit (SIMT unit 1410), and a voltage and frequency manager 1420. The fetch and decode unit 1402 can fetch instructions for execution by the multi-processor unit 1400. The branch unit 1404 can calculate instruction pointer adjustments based on executed jump instructions. The register file 1406 can store general-purpose and architectural registers used by the SIMT unit 1410. The thread manager 1406 can distribute and re-distribute threads among the compute units of the SIMT unit 1410. In one embodiment, the SIMT unit 1410 is configured to execute a single instruction as multiple threads, where each thread of the instruction is executed by a separate compute unit. In one embodiment, each of compute units 1411 to 1418 includes an integer ALU (e.g., ALU 1411A-1418A) and a floating-point unit (e.g., FPU 1411B-1418B). The voltage and frequency of each compute unit 1411-1418 within the SIMT unit 1410 can be dynamically managed by the voltage and frequency manager 1420, which can increase or decrease the voltage and clock frequency supplied to the various compute units when components of the compute units are enabled and disabled.

[0214] In some previous enabling configurations, each computing unit could execute a single thread of either integer instructions or floating-point instructions. If any of the ALUs 1411A - 1418A was assigned the task of executing a thread of integer instructions, the corresponding FPU 1411B - FPU 1418B was not available for executing a thread of floating-point instructions and could be power gated during the operation of the corresponding ALU 1411A - ALU 1418A. For example, when ALU 1411A could execute a thread of integer instructions while FPU 1413B executed a thread of floating-point instructions, FPU 1411B was power gated while ALU 1411A was active. The embodiments described herein overcome such limitations by, for example, enabling ALU 1411A to execute a thread of instructions while FPU 1411B executes a thread of different instructions. Additionally, one embodiment provides support for mixed-precision or mixed-data type operands such that a single computing unit can simultaneously perform operations on instructions having both floating-point and integer operands and / or operands having different precisions.

[0215] The embodiments described herein enable increased operational throughput for a cluster of computing units by making all the logic units within each computing unit available for performing computations. In such embodiments, logic units within a computing unit that are designed to selectively perform computations in one of multiple precisions or multiple data types can be configured to perform multiple simultaneous operations for each precision or data type supported by the computing unit. For a given computing unit 1411 - 1418, ALUs 1411A - 1418A can perform integer operations while FPU 1411B - 1418B perform floating-point operations. These operations can be performed for a single instruction or for multiple instructions. In one embodiment, a new class of mixed-precision instructions is enabled where one or more operands have one data type or precision while one or more different operands have a different data type or precision. For example, an instruction can accept two or more multi-element operands including both floating-point and integer data types, and a single instruction performs operations on a per-data type or per-precision basis.

[0216] Reconfigurable 16-bit floating-point / integer fused multiply-add unit

[0217] The logic unit design provided by the embodiments described herein has single-cycle and multi-cycle latencies while providing single-cycle throughput for both fused multiply-add (e.g., 3-operand inputs without dependencies across cycles) and multiply-accumulate (e.g., 2-operand inputs with data dependencies across cycles). In contrast, logic unit designs known in the art implement fused multiply-add without considering multi-cycle latencies and single-cycle throughput for multiply-accumulate operations, which can be a limiting factor in the execution of key machine learning operations such as dot product operations.

[0218] One embodiment described herein provides a combined integer / floating-point fused multiply-add data path that utilizes an existing signed integer multiply-add circuit to also implement a floating-point mantissa multiply-add operation. Floating-point support is enabled with only the circuitry required for alignment / normalization shifting and exponent units added. The input / output data width and data memory footprint remain the same, where only a single control signal is required to switch between the two computational modes on a per-cycle basis.

[0219] One embodiment provides a combined 16-bit integer / floating-point fused multiply-add design that improves upon a conventional single-cycle design with separate integer / floating-point data paths. The design described herein implements a multiply-add circuit for a combined int16 / float16 data path that reduces the total area by up to 29%. One embodiment provides an improved floating-point data path that has alignment only for the addend, along with a combined negation and rounding incrementer that contributes 11% to the total area reduction. One embodiment provides a multiply-accumulate variant with two inputs and a two-cycle latency, single-cycle throughput. One embodiment provides an alternative circuit that significantly increases accumulation accuracy by doubling the accumulator width at only 11% cost in increased area.

[0220] ​ The design of a logic unit for performing integer and floating-point fused multiply-add operations according to an embodiment is shown. ​Shows a conventional design of a logic unit 1500 that enables fused multiply - add operations while maintaining full intermediate product accuracy and range. In IEEE half - precision floating - point (float16) or signed 16b integer (int16) mode, a fused multiply - add operation (o = a * b + c) is performed on three 16 - bit input operands 1501. The inputs are provided to a 16 - bit floating - point data path 1510 or a 16 - bit integer data path 1520, where the output port (o 1530) selects the appropriate result (f16 1518 or i16o 1528) based on the operation mode 1532. The int 16 result (i16o1528) is selected and rounded to the nearest upper half of the 32 - bit signed integer result (isum 1525) generated by a signed 16bx16b multiplier 1521 and a 32b adder 1522. The float16 data path 1510 right - shifts (1511) the mantissa of the smaller of the products of an unsigned 11bx11b multiplier 1617 and right - shifts the addend before processing the product via a 22 - bit mantissa adder 1513 for alignment at an alignment shifter 1512A. A 22 - bit leading - zero predictor (LZA 1519) predicts the position of the most significant bit of the result of a floating - point addition performed by the 22 - bit mantissa adder 1513 based on the input to the adder. A left - shift (1514) is performed by a normalization shifter 1515 before providing the intermediate result to a rounding logic 1516.

[0221] ​ is a block diagram of a multiply - add logic unit 1540 according to an embodiment. ​ The logic unit 1540 of maintains separate 16 - bit floating - point / integer circuitry while improving the floating - point data path of the logic unit 1500. In one embodiment, the design of the logic unit 1540 removes the alignment shifter 1512B from the critical path by performing alignment only on the addend (in parallel with the multiplication operation (1541)). A wider 33 - bit sum requires only an 11 - bit incrementer for the high bits. Additionally, for subtraction operations, the output of the adder can be inverted to produce an unsigned mantissa. In one embodiment, the incrementer is removed from the critical path of the data path of the logic unit 1540 by combining the increment operation with a final rounding incrementer (1542). In contrast, ​ the logic unit 1500 of requires the incrementer to complete any required two's - complement inversion operation after the adder. The reduction in the critical path of the 16 - bit floating - point data path of the logic unit 1540 results in fewer gates and allows an 11% area reduction associated with the logic unit 1500 while maintaining the same single - cycle latency.

[0222] ​FIG. 1600 shows a fused multiply - add logic unit having a merged floating - point and integer data path according to an embodiment. The 16 - bit by 16 - bit signed multiplier 1602A and 32 - bit adder 1604 of the integer data path are reused for floating - point mantissa operations, where the high - order operation bits are gated to produce the result of an 11 - bit mantissa (1602B). When the floating - point mode is enabled, the input switches 1601A - 1601C are used to redirect the high 6 bits of the input operands (a, b, c) to the exponent unit 1608. The sign and exponent values from the input are packed and provided to the exponent unit 1608 via a fixed 3 - bit sign operand bus 1609A and 15 - bit exponent bus 1609B. For 16 - bit floating - point operations, the shared 32 - bit adder uses a 1 - bit incrementer 1605 to create the high - order bits 1606 of the 33 - bit sum. The bypass circuits (1610A, 1610B) within the exponent unit 1608 and in the alignment shifter 1612 and normalization shifter 1613 ensure fixed alignment / normalization, which has minimal switching activity in those units used for integer mode, while zero high - order mantissa bits ensure no switching activity within the unused portion of the multiplier in floating - point mode. The rounding logic 1616 and the incrementer of the floating - point data path are reused for integer mode to calculate the lower 10 bits of the integer result i16o by rounding. The high 6 bits of i16o are calculated by mapping the operation to the existing exponent incrementer 1611, which also performs any rounding overflow operations from the mantissa data path in floating - point mode. When the processing is complete, a 16 - bit floating - point or integer value can be provided via the output 1630.

[0223] ​ FIG. 1700 shows a logic unit 1700 according to an embodiment including merged computing circuitry to perform floating - point and integer fused - multiply - accumulate operations. The logic unit 1700 includes an exponent unit 1708 and a mantissa unit 1709, two 16 - bit input ports 1701 and a 16 - bit output port 1730. The input port 1701 includes switches for switching the sign and exponent bits of the input data to the exponent unit 1708. The exponent unit 1708 and mantissa unit 1709 are used when performing integer operations. In one embodiment, the logic unit supports an 8.8 input and 16.0 output format for 16 - bit fixed - point mode. The logic unit 1700 supports dual - cycle latency and single - cycle throughput requirements. Some of the circuits shown are shared between the operating modes, including the signed multipliers 1702A - 1702B and 32 - bit adder 1704 for both integer and floating - point modes. During the accumulation in the second cycle, the 16 - bit accumulator input 1703A is asserted, where the accumulator value is provided to the 32 - bit adder 1704. The high 10 bits of the accumulator input 1703A (e.g., c[15:6]) are dedicated to 16 - bit integer operations. For both computation modes, multiplication is performed in the first cycle, and addition / rounding is performed in the second cycle.

[0224] ​ The logic unit 1700 uses three key techniques to enable an efficient merge design. First, directly pipelining the single-cycle merge design for the accumulation operation will reduce the throughput by half in the first cycle by addend alignment, or increase the cycle time in the critical path of the second cycle by right-shift calculation and 33b alignment. Instead, the design of the logic unit 1700 takes advantage of the timing / area non-criticality of the exponent unit 1708 to pre-compute the larger (or smaller) mantissa and right-shift amount of the alignment shifter 1713. In one embodiment, the logic unit 1700 performs a two-cycle operation while maintaining single-cycle throughput by feeding the output back to the second cycle as an addend input, selecting only the smaller mantissa for 22-bit alignment and pre-computing the smaller mantissa / right-shift amount in the first cycle using the multiplier output and accumulator exponent previously calculated by the second stage. ​ Second, the round-to-nearest operation in 16-bit integer mode uses an 8.8 fixed-point format and eliminates the need to map integer rounding to a floating-point rounding incrementer. Before the adder, a 1 is inserted at bit position 15 instead of a 0 through multiplexer logic 1705 to achieve the same rounding operation.

[0225] Third, flip-flops are reused for mutually exclusive signals between two modes, such as the high 10b of the exponent calculation (e.g., Eun1707, right-shift 1710) and the product (1711). The timing path reduction in the second cycle is also achieved by combining the inverter / rounding incrementer and by using far / near path-based optimizations to reduce the critical path through the alignment shifter 1713 and the normalization shifter 1714.

[0226] As

[0227] As ​As shown, by simply doubling the width of the accumulator to 32 bits, the accuracy of the dual-cycle multiply-accumulate design is significantly increased. The accumulator can accumulate 16-bit integer results in 16.16 fixed-point format and 16-bit floating-point results based on an intermediate result with a 5-bit exponent and a 22-bit mantissa (the implicit leading 1 is not stored). In various embodiments, the 22-bit mantissa of the intermediate result can be rounded, truncated, or quantized into an IEEE standard mantissa. The design of logic unit 1740 mainly limits the cost of doubling the accumulator to the output flip-flop and the final incrementer in the mantissa data path, since the remaining data path after the multiplier is already adapted to the additional width of the product. In one embodiment, the higher accuracy enables rounding to be simplified to a simple truncation to generate a 16-bit output 1750 from the 32-bit accumulator. The post-exponent normalization incrementer is removed from the exponent unit 1708 in logic unit 1740. Instead, when the output of the adder is to be inverted, the invert incrementer 1742 performs a final increment in the mantissa to calculate the two's complement. During accumulation in the second cycle, the 32-bit accumulator input 1703B is asserted, where the value of the accumulator is provided to the 32-bit adder 1704. The upper 10 bits of the accumulator input 1703B (e.g., c[31:22]) are exclusive to the 16-bit integer operation. The total synthesized area of this design only presents an 11% area increase relative to ​ the design of logic unit 1700 while doubling the accumulator precision.

[0228] Although the above description is provided for 16-bit operands, these techniques can be easily extended to larger data widths to achieve similar goals. Additionally, although IEEE half-precision output is described, the designs described herein can also be adjusted to support non-standard floating-point formats. Additionally, different non-standard floating-point formats can be used for intermediate values, as described below.

[0229] The embodiments described above provide various implementations of a reconfigurable 16-bit floating-point / integer fused multiply-add unit that offer several advantages over existing designs. The proposed design does not affect the memory footprint of floating-point or integer storage. The proposed design only increases the multiplier area without changing the remainder of the floating-point data path. In contrast, logic designs known in the art extend the entire floating-point significand / mantissa to the same width as the integer, while the additional storage area for the sign and exponent is separate and exclusive to the floating-point number, causing an increase in the memory footprint of the floating-point storage and the register file size. Existing designs also increase the width of the entire mantissa data path, which can cause a significant area increase. Provide single-cycle (e.g., ​ of logic unit 1600) and multi-cycle (e.g., ​ of logic unit 1700 and ​The logic unit 1740) is designed such that, after an initial latency, multiple cycles generate an output each. ​ The logic unit 1740 provides a combined floating-point / integer multiply-accumulate design with a local accumulator width that is twice as wide as the input operands. This enables much higher accumulation accuracy for operations such as dot products without impacting the memory storage footprint of the input operands and affecting only a small portion of the design (a 11% total area impact only). Additionally, each logic unit maps a portion of the integer operations onto the existing exponent data path to maximize circuit reuse when reconfiguring for integer mode. Further, for floating-point operations with a subtraction operation, ​ the logic unit 1540 and ​ the 1700 combines two's complement increment into a rounding increment for reduced latency and area.

[0230] ​

[0231] One embodiment uses ​ the multi-processor unit 1400 and ​ one or more floating-point / integer logic units can be used as building blocks for a machine learning data processing system that includes hardware, software, and firmware optimized to perform the types of computational operations typically performed when training or inferring using a deep neural network. ​ Shown are a data processing system and associated computational and logic units for performing accelerated training and inference operations for machine learning, e.g., via using a deep neural network. ​ Shown is an exemplary machine learning data processing system provided by the embodiments described herein. ​ Shown are components of a machine learning accelerator according to one embodiment.

[0232] ​The data processing system 1800 is a heterogeneous processing system having a GPGPU 1820 including machine learning acceleration logic, a processor 1802, and a unified memory 1810. The processor 1802 and the GPGPU 1820 can be any processor and GPGPU / parallel processor as described herein. The processor 1802 can execute instructions for a compiler 1815 stored in the system memory 1812. The compiler 1815 is executed on the processor 1802 to compile source code 1814A into compiled code 1814B. The compiled code 1814B can include code executable by the processor 1802 and / or code executable by the GPGPU 1820. During compilation, the compiler 1815 can perform operations to insert metadata, including hints about the level of data parallelism present in the compiled code 1814B and / or hints about the data locality associated with the threads to be dispatched based on the compiled code 1814B. The compiler 1815 can include information required to perform such operations or operations that can be performed with the help of a runtime library 1816. The runtime library 1816 can also facilitate the compiler 1815 in compiling the source code 1814A and can also include instructions that are linked with the compiled code 1814B at runtime to facilitate the execution of the compiled instructions on the GPGPU 1820.

[0233] The unified memory 1810 represents a unified address space that can be accessed by the processor 1802 and the GPGPU 1820. The unified memory includes the system memory 1812 and the GPGPU memory 1818. The GPGPU memory 1818 includes the GPGPU local memories 1834A - 1834B within the GPGPU 1820 and can also include some or all of the system memory 1812. For example, the compiled code 1814B stored in the system memory 1812 can also be mapped into the GPGPU memory 1818 for access by the GPGPU 1820.

[0234] The GPGPU 1820 includes a plurality of compute blocks 1824A - 1824N, which can be Figure 2A instances of the processing clusters 214A - 214N and can include one or more instances of the graphics multiprocessors 234 described herein. In various embodiments, the compute blocks 1824A - 1824N include having Figures 15B - 17BOne or more of the computing units in the logic unit. The GPGPU 1820 also includes a power and performance module 1826, a cache 1827, and a set of registers 1825 that can be used as shared resources for the compute blocks 1824A - 1824N. In one embodiment, the registers 1825 include directly and indirectly accessible registers, where the indirectly accessible registers can be optimized for matrix computation operations. The power and performance module 1826 can be configured to adjust the power delivery and clock frequency of the compute blocks 1824A - 1824N to power gate idle components within the compute blocks 1824A - 1824N under heavy workloads. The GPGPU 1820 includes a GPGPU local memory 1828, which is a physical memory module that shares the graphics card or multi - chip module with the GPGPU 1820.

[0235] In one embodiment, the GPGPU 1820 includes hardware logic that includes an instruction fetch and decode unit 1821, a scheduler controller 1822, and a machine learning accelerator 1823. The instruction fetch and decode unit 1821 is an instruction fetch and decode unit that includes logic for fetching and decoding instructions (including machine - learning - specific instructions) that can define complex, customizable behavior. The instructions can cause the compute logic to schedule a set of operations to be executed via one or more of the compute blocks 1824A - 1824N via the scheduler controller 1822. In one embodiment, the scheduler controller 1822 is an ASIC configurable to perform advanced scheduling operations. In one embodiment, the scheduler controller 1822 is a microcontroller or a low - per - instruction - energy processing core capable of executing instructions loaded from a firmware module.

[0236] In one embodiment, some functions to be executed by the compute blocks 1824A - 1824N can be directly scheduled to or offloaded to the machine learning accelerator 1823. The machine learning accelerator 1823 includes processing element logic configured to efficiently perform matrix and other computational operations typically performed during machine learning.

[0237] In some embodiments, the GPGPU 1820 additionally includes a statistics unit 1829 configurable as a near data computing unit. For example, the statistics unit 1829 may be integrated into one or more memory controllers of the GPGPU local memory 1828 or propagated across the one or more memory controllers. In one embodiment, the statistics unit 1829 is available for determining the probability distribution of weight or activation map data when performing machine learning operations written to or read from the GPGPU local memory 1828 when enabled by the machine learning accelerator 1823. The statistics unit 1829 includes means for determining whether the data accessed in the GPGPU local memory 1828 is within one or more statistical distributions (e.g., Gaussian, uniform, Poisson, etc.) based on the address and data patterns during memory access. In one embodiment, for at least a subset of memory accesses, statistical information (e.g., mean, median, mode, standard deviation, etc.) may be collected during a sampling period. The statistics unit 1829 may be configured such that collecting the statistical information does not significantly increase the latency of the memory accesses performed by the memory controller hosting the statistics unit 1829. The statistical information may be provided to the machine learning accelerator 1823 periodically or the machine learning accelerator 1823 may request data from the statistics unit. In one embodiment, the statistics unit 1829 may check the data associated with the memory access against a set of known possible distributions. A vector including a set of probabilities associated with each known possible distribution may be provided to the machine learning accelerator 1823 on a periodic basis or upon request. In various embodiments, the machine learning accelerator 1823 may use the probabilities and / or statistical information provided by the statistics unit 1829 for various operations. In one embodiment, as Figure 18B and Figure 20 further described herein, the machine learning accelerator 1823 may use the data provided by the statistics unit 1829 to perform stochastic rounding during the quantization of a low-precision neural network.

[0238] Figure 18A The machine learning accelerator 1823 of Figure 18B is further shown in detail herein. In one embodiment, the machine learning accelerator 1823 includes an activation instruction module 1832, an FPU encoding and configuration module 1834, a stochastic quantization unit 1838, and a cache 1836 shared among various modules within the machine learning accelerator 1823.

[0239] The activation instruction module 1832 includes logic for sequencing the execution of combined fused multiply-add and activation in response to a single instruction. In response to the decoding of an FMAC or FMADD plus activation function on the GPGPU 1820, the scheduler unit 1822 may schedule operations via the machine learning accelerator 1823. Via the activation instruction module 1832, the machine learning accelerator 1823 may perform a set of fused multiply-add or fused multiply-accumulate operations on two or three input operands per thread or vector element, and for each thread or element, provide the output to hardware logic configured to perform one of a plurality of selectable activation functions. Different activation functions may be associated with different instructions, or a single instruction may include a field for enabling selection of an activation function. In one embodiment, the activation instruction module may perform vector or wrap operations to generate intermediate FMADD or FMAC results and store the intermediate results in the cache 1836. The activation instruction module 1832 may then apply the activation function to the intermediate data. Exemplary supported activation functions include the rectified linear unit (RELU) function of equation (1), the sigmoid function of equation (2), or the hard sigmoid function of equation (3).

[0240]

[0241] The FPU encoding and configuration module 1834 includes logic for defining parameters for dynamically configuring the floating-point units within the compute blocks 1824A - 1824N of the GPGPU 1820. In one embodiment, Figure 16 and Figures 17A - 17B certain dynamic aspects of the combined integer / floating-point units may be configured via the FPU encoding and configuration module 1834. For example, the compute blocks 1825A - 1824N may be over-provisioned to include more compute units than can be maximally active at any one time given the power budget of a given GPGPU 1820. However, the FPU encoding and configuration module 1834 may configure the dynamic floating-point units to gate certain logic blocks to operate at reduced precision and reduced power consumption. The reduced precision and power requirements per unit may enable a greater number of units to be online, allowing a greater number of threads to be executed for lower precision operations. For example and in one embodiment, a logic unit configured to perform 16-bit integer operations may be configured to perform 8-bit integer operations, reducing the power requirements. In one embodiment, dual 8-bit integer operations may be performed, increasing throughput without significantly increasing power consumption. In one embodiment, multiple half-precision logic units may work in parallel to perform single-precision or double-precision floating-point operations. In one embodiment, higher precision operations may be performed via multiple channels through the logic units.

[0242] In one embodiment, the FPU encoding and configuration module 1834 may also configure the floating-point encoding methods supported by the floating-point unit. In addition to the IEEE 754 floating-point standard for half-precision, single-precision, and double-precision encoding of floating-point values, a number of alternative encoding formats may be supported based on the dynamic range of the data being processed currently. For example, based on the dynamic range and / or distribution of a given data set, by using more or fewer bits for the exponent or mantissa data, the data can be more accurately quantified from higher to lower precision. In one embodiment, the supported alternative format specifies 1-bit sign, with 8-bit exponent and 7-bit fractional components. One embodiment allows encoding with 1-bit sign, 3-bit exponent, and 12-bit fractional components. In such embodiments, different instruction sets support different floating-point encodings, allowing developers to select an encoding based on the instructions specified in the program code. In one embodiment, different floating-point encodings may be used when rounding or downsampling floating-point data, e.g., from an accumulated 32-bit floating-point value to a 16-bit value. In one embodiment, the statistical unit 1829 may be utilized to determine which 16-bit encoding is most suitable for a given data block.

[0243] In one embodiment, the machine learning accelerator 1823 additionally includes a stochastic quantization unit 1838 to enable stochastic quantization for machine learning operations. The stochastic quantization unit 1838 may be used to enable stochastic rounding during quantization operations. One embodiment uses a random number generator to enable stochastic rounding, where small values may be used to determine the rounding probability. One embodiment utilizes the statistical unit 1829 to determine the probability distribution associated with a set of output data from a given layer of a neural network. For each layer, the probability density of the data values may be determined, where the probability density is determined by statistical characteristics, including the mean, standard deviation, and variance of the data determined for each layer of the neural network. Using such data, stochastic rounding may be performed in a manner that does not change the probability distribution of the data within each layer of the neural network.

[0244] Figure 19 Details of the activation instruction module 1832 according to an embodiment are shown. The activation instruction module 1832 includes logic for sequencing the execution of combined fused multiply-add and activation in response to a single instruction. In response to being passed through Figure 18AThe decoding of the FMAC / FMADD + activation function of the instruction fetch and decode unit 1821 can dispatch the instruction execution to the activation instruction module 1832 via the machine learning accelerator 1823. The machine learning accelerator 1823 can use the fused multiply-add / fused multiply-accumulate thread scheduler unit 1902 to schedule a set of fused multiply-add or fused multiply-accumulate operations for the units within the compute blocks 1824A-1824N when receiving the instruction. In one embodiment, the intermediate data output from the compute blocks 1824A-1824N can be stored in the cache memory 1836 within the machine learning accelerator 1823. In one embodiment, chunks of the intermediate data can be processed in a streaming manner within the activation instruction module 1832. In one embodiment, the intermediate data can represent the activation map to which the non-linearity of the activation function will be applied. One of the selected activation functions can be applied by the activation function logic 1904A-1904N. The activation function can be selected based on a particular instruction processed by the activation instruction module 1832 or the parameters supplied in the instruction. The particular instruction can be formatted based on any instruction format of the instruction formats described herein.

[0245] Floating point operations at various points include rounding operations. Rounding is used in floating point calculations because floating point numbers have a finite number of digits and cannot represent all real numbers exactly. Thus, when a number is tasked with representing a value that requires more digits than the selected floating point format allows, the remaining digits are omitted and the number is rounded to the nearest value that can be represented by the floating point format. The particular numbers that can be represented depend on the selected floating point format.

[0246] Various methods can be performed to round during floating point calculations. The embodiments described herein include hardware logic for performing stochastic rounding for machine learning operations. Contrary to other rounding methods (rounding to the nearest number or strictly up or down), the stochastic method rounds numbers randomly. The embodiments described herein enable stochastic rounding for quantization of data values for deep neural networks. A rounding unit is provided that enables hardware stochastic rounding using one of multiple rounding modes. One embodiment enables stochastic rounding using a random number generator. Small values can be used to determine the rounding probability. The random number can be compared with the rounding probability to determine which of the nearest representable values to round to during quantization. Alternatively, one embodiment utilizes statistical accumulator / estimator logic to determine the probability distribution associated with a set of output data from a given layer of a neural network. For each layer, the probability density of the data value distribution can be determined, where the probability density is defined by the mean, standard deviation, and variance of the data determined for each layer of the neural network. Using such data, stochastic rounding can be performed in a manner that does not change the probability distribution of each layer of the neural network.

[0247] Figure 20Shows a random quantization unit 1838 according to an embodiment. In one embodiment, the random quantization unit 1838 is used to quantize the raw output data generated within a layer of a neural network into a format used by the next layer of the neural network. For example, the computational operations used to generate the output data can be processed with a higher precision and the result can be quantized to a lower precision before being provided as input to the next layer. In one embodiment, the output 2002B from a given layer n is processed, for example, in 32 bits and quantized by the quantization unit 2004 into a 16-bit data type. The quantization operation can utilize stochastic rounding, which can be implemented via the stochastic rounding unit 2009. The quantized and rounded values can then be provided to the next layer (layer N + 1) 2010 of the neural network.

[0248] In various embodiments, the random quantization unit 1838 can perform stochastic rounding via the use of a random number generator 2006. In floating-point arithmetic, rounding aims to turn a given value x into a value z with a specified number of significant digits, where z is a multiple of a number m that depends on the magnitude of x. The number m is a power of the base (usually 2 or 10) of the floating-point representation. The number z is a representable value close to the value x. Whether the value x is rounded up or down to achieve the value z is based on a random value selected by the random number generator 2006. The fractional part between the generated random value and the significant representation is compared. The fractional part can be used as the probability of rounding up or down to the nearest representable value. The gap between representable values during quantization depends on the encoding format of the floating-point representation in the appropriate position. As an example, if the quantization is to be rounded to an integer value and the fractional value is 0.3, the probability of rounding up can be equal to 30%, while the probability of rounding down can be equal to 70%. In such a scenario (where the random number generator 2006 is a properly verified true random number generator), the stochastic rounding unit 2009 will round up or down proportionally to the fractional value.

[0249] Alternatively, the stochastic rounding unit 2009 can utilize a statistical accumulator / estimator 2008, which, in one embodiment, is the near-data statistics unit 1829 as Figure 18A shown. The statistical accumulator / estimator 2008 can analyze the outputs from the previous layers 2002A - 2002B to determine the distribution associated with the neural network data. The stochastic rounding unit 2009 can then round the data during quantization such that the quantized data has a similar distribution to the pre-quantized data.

[0250] Figure 21Shows an FPU encoding and configuration module 1834 according to one embodiment. In one embodiment, the GPU encoding and configuration module 1834 includes an FPU configuration module 2102 and an FPU encoding module 2104. The FPU configuration module 2102 can be used to configure a 16-bit integer logic unit to perform 8-bit integer operations (including double 8-bit integer operations). In one embodiment, multiple half-precision logic units can work in parallel to perform single-precision or double-precision floating-point operations. The FPU encoding module 2104 can be used to configure a specific floating-point encoding format to be used within the compute blocks 1824A - 1824N during data computation. In one embodiment, the FPU encoding module 2104 can configure one or more of the compute blocks 1824A - 1824N in response to an instruction specifying that input or output data is to be stored in a non-standard floating-point format. The compute blocks used to execute the instructions can then be configured to interpret data in the non-standard format prior to performing the operations of the instructions. In one embodiment, the FPU encoding module 2104 is to configure one or more of the compute blocks to use a floating-point encoding format that can most efficiently store the data to be processed. Such determination can be performed in part based on the probability and statistical information provided by the statistical unit 1829, which can act as a near-data compute unit within the memory controller 2106 of the GPGPU local memory 1828.

[0251] Figure 22 Shows logic 2200 for processing instructions using dynamically configurable compute units according to an embodiment. The logic 2200 can be hardware or firmware logic within a GPGPU and / or GPGPU multiprocessor (such as the multiprocessor unit 1400 in Figure 14 or the GPGPU 1820 of FIG. 18) as described herein. As shown in block 2202, the logic 2200 is configured to fetch and decode a single instruction to perform a combined multiply-add operation on a set of operands. As shown in block 2204, the logic 2200 can then issue the single instruction for execution by the compute unit for execution by the dynamically configurable compute unit. As shown in block 2206, the logic 2200 can then configure one or more logic units of the compute unit to perform the operation with the precision and data type of the operands. As shown in block 2208, the logic 2200 can then have the compute unit execute the single instruction to generate an output based on the multiplication and addition operations.

[0252] In one embodiment, the combined multiplication and addition operation performed at block 2202 can be a fused floating-point operation that includes a single rounding. For example, the multiplication and addition operation can be a fused multiply-add or fused multiply-accumulate operation. The combined multiplication and addition operation can also be an integer operation. The integer operation can include a rounding operation between the multiplication and addition. The rounding can be performed by inserting zeros at the most significant bit position of the integer data type via a multiplexer within the logic unit. The multiplexer within the logic unit can be positioned after the multiplier and before the adder.

[0253] In one embodiment, the dynamically configurable logic unit of block 2204 is a combined floating-point and integer logic unit configurable to perform integer or floating-point operations. For example, the dynamically configurable logic unit can be Figure 16 logic unit 1600 of Figure 17A 1700 of Figure 17B 1740 of. The computing unit can include multiple different instances of such logic units. In one embodiment, the logic unit is configurable on a per-cycle basis. In one embodiment, the logic unit is a first logic unit configured to perform a single-cycle fused multiply-add operation using a multiplier and an adder shared between a floating-point data path and an integer data path. In one embodiment, the logic unit is a second logic unit configured to perform a two-cycle fused multiply-accumulate operation with a single-cycle throughput. In one embodiment, the logic unit is a third logic unit configured to perform a two-cycle fused multiply-accumulate operation, where the third logic includes an accumulator with twice the bit width of the input and output operands. In one embodiment, the die area of the third logic unit is at most eleven percent larger than the die area of the second logic unit.

[0254] The dynamically configurable logic unit described herein can be configured to perform integer or floating-point operations. In one embodiment, one or more of the logic units can be configured to perform operations with multiple different precisions. In one embodiment, the logic unit can be used to perform operations with multiple different precisions via multi-cycle operations. In one embodiment, different floating-point codings can be selected, including the IEEE 754 half-precision floating-point format, single-precision floating-point format, and double-precision floating-point format. Non-standard floating-point formats can also be used, where different bit allocations are used for the exponent and mantissa of the floating-point value.

[0255] In one embodiment, the output based on the multiplication and addition operation can then be further processed by an activation function. For example, in response to a single instruction, FMADD or FMAC operations can be scheduled by an FMADD / FMAC thread scheduler unit, as Figure 19 shown in. The output of such operations can be provided to activation function logic (e.g., as Figure 19The activation function logic 1904) in generates activation map data of neuron activation data.

[0256] Figure 23A illustrates logic 2300 for executing machine learning instructions according to an embodiment. The logic 2300 can be hardware or firmware logic within a GPGPU and / or GPGPU multiprocessor as described herein (such as the multiprocessor unit 1400 in, or the GPGPU 1820 of FIG. 18). As shown in block 2302, the logic 2300 is configured to fetch and decode a single instruction to execute a set of machine learning operations via a machine learning accelerator unit. The machine learning accelerator unit includes elements of the machine learning accelerator 1823 described herein, including Figure 14 the activation instruction module 1832, the FPU encoding and configuration module 1834, and the stochastic quantization unit 1838 of. As shown in block 2304, the logic 2300 can then issue a single instruction for execution by a set of dynamically configurable computing units. As shown in block 2306, the logic can then configure the set of computing units to execute the set of machine learning operations with a higher precision than the inputs and outputs of the operations. In one embodiment, the configuration is performed by an FPU configuration module as described herein. The FPU configuration module can configure the computing units to perform a convolution operation on 16-bit floating-point matrix data using 32-bit intermediate data, for example. As shown in block 2308, the logic 2300 can then quantize higher-precision intermediate values to lower precision before the output via stochastic rounding logic within the machine learning accelerator. For example, 32-bit intermediate data can be quantized to 16-bit using stochastic rounding for output. Figure 18B

[0257] Figure 23B illustrates logic 2310 for configuring floating-point operations based on the distribution of neural network data according to an embodiment. In one embodiment, the logic 2300 includes the hardware and firmware logic and logic units described herein, including Figure 18B and Figure 20 the stochastic quantization unit 1838 of, Figure 18B the FPU encoding and configuration module 1834 of. Figure 20 The statistical accumulator / estimator 2008 of is included in the statistical unit 1829 in one embodiment. The statistical unit 1829 can be a near-data computing unit included within a memory controller for a GPGPU, as Figure 18A shown in. Figure 21

[0258] ​​As shown at block 2312, using a statistics unit, logic 2310 can determine a set of statistical metrics of neural network data stored in a memory. The logic 2310 can then determine the distribution of the neural network data in the memory via the statistical metrics, as shown at block 2314. In one embodiment, the logic 2310 can configure floating-point encoding for a computing unit to perform a set of machine learning operations, as shown at block 2316. The logic 2310 can then configure stochastic rounding logic within the machine learning accelerator to round based on the distribution, as shown at block 2318. The stochastic rounding logic can be configured to round based on the distribution such that the probability distribution of the quantized neural network data is closer to the pre-quantized data than may be possible using stochastic rounding techniques based on a random number generator.

[0259] Additional exemplary graphics processing system

[0260] The details of the embodiments described above can be incorporated within the graphics processing systems and devices described below. Figures 24 to 37 The graphics processing systems and devices shown illustrate alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

[0261] Overview of additional exemplary graphics processing system

[0262] Figure 24 is a block diagram of a processing system 2400 according to an embodiment. In various embodiments, the system 2400 includes one or more processors 2402 and one or more graphics processors 2408, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2402 or processor cores 2407. In one embodiment, the system 2400 is a processing platform for use in a mobile device, a handheld device, or an embedded device, incorporated within a system-on-chip (SoC) integrated circuit.

[0263] Embodiments of the system 2400 can include a server-based game platform, a game console, which includes a game and media console, a mobile game console, a handheld game console, or an online game console, or incorporated within them. In some embodiments, the system 2400 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. The data processing system 2400 can also include a wearable device (such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device), coupled to, or integrated within, the wearable device. In some embodiments, the data processing system 2400 is a television or a set-top box device having one or more processors 2402 and a graphical interface generated by one or more graphics processors 2408.

[0264] In some embodiments, each of the one or more processors 2402 includes one or more processor cores 2407 for processing instructions that, when executed, implement operations for system and user software. In some embodiments, each of the one or more processor cores 2407 is configured to process a particular instruction set 2409. In some embodiments, the instruction set 2409 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 2407 can each process a different instruction set 2409, which can include instructions for facilitating the emulation of other instruction sets. The processor cores 2407 can also include other processing devices, such as a digital signal processor (DSP).

[0265] In some embodiments, the processor 2402 includes a cache memory 2404. Depending on the architecture, the processor 2402 can have a single internal cache or multiple internal cache levels. In some embodiments, the cache memory is shared among the various components of the processor 2402. In some embodiments, the processor 2402 also uses an external cache (e.g., a level 3 (L3) cache or a last-level cache (LLC)) (not shown), and the external cache can be shared among the processor cores 2407 using known cache coherence techniques. A register file 2406 is additionally included in the processor 2402, which can include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). Some registers can be general-purpose registers, while other registers can be specific to the design of the processor 2402.

[0266] In some embodiments, the processor 2402 is coupled to a processor bus 2410 to transfer communication signals, such as address, data, or control signals, between the processor 2402 and other components in the system 2400. In one embodiment, the system 2400 uses a exemplary 'hub' system architecture that includes a memory controller hub 2416 and an input / output (I / O) controller hub 2430. The memory controller hub 2416 facilitates communication between the memory device and other components of the system 2400, while the I / O controller hub (ICH) 2430 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 2416 is integrated within the processor.

[0267] The memory device 2420 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to act as a process memory. In one embodiment, the memory device 2420 can operate as the system memory of the system 2400 to store data 2422 and instructions 2421 for use when the one or more processors 2402 execute an application or process. The memory controller hub 2416 is also coupled to an optional external graphics processor 2412, which can communicate with one or more of the graphics processors 2408 in the processor 2402 to perform graphics and media operations.

[0268] In some embodiments, the ICH 2430 enables peripheral devices to be connected to the memory device 2420 and the processor 240 through a high-speed I / O bus. The I / O peripheral devices include but are not limited to an audio controller 2446, a firmware interface 2428, a wireless transceiver 2426 (e.g., Wi-Fi, Bluetooth), a data storage device 2424 (e.g., a hard disk drive, a flash memory, etc.), and a legacy I / O controller 2440 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more universal serial bus (USB) controllers 2442 connect input devices such as a keyboard and a mouse 2444 combination. A network controller 2434 can also be coupled to the ICH 2430. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 2410. It will be appreciated that the system 2400 shown is exemplary and not restrictive, as other types of data processing systems with different configurations can also be used. For example, the I / O controller hub 2430 can be integrated within the one or more processors 2402, or the memory controller hub 2416 and the I / O controller hub 2430 can be integrated into a discrete external graphics processor (such as the external graphics processor 2412).

[0269] Figure 25 is a block diagram of an embodiment of a processor 2500 having one or more processor cores 2502A - 2502N, an integrated memory controller 2514, and an integrated graphics processor 2508. Figure 25Those elements having the same reference numbers (or names) as elements in any other figure in this document can operate or function in any manner similar to the manner described elsewhere in this document, but are not limited thereto. The processor 2500 can include additional cores, up to and including additional cores 2502N represented by the dashed blocks. Each of the processor cores 2502A - 2502N includes one or more internal cache units 2504A - 2504N. In some embodiments, each processor core is also capable of accessing one or more shared cache units 2506.

[0270] The internal cache units 2504A - 2504N and the shared cache units 2506 represent the cache memory hierarchy within the processor 2500. The cache memory hierarchy can include at least one level of instruction and data cache within each processor core and one or more levels of shared mid - level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest - level cache before the external memory is classified as the LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 2506 and 2504A - 2504N.

[0271] In some embodiments, the processor 2500 can also include a system agent core 2510 and a set of one or more bus controller units 2516. The one or more bus controller units 2516 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 2510 provides management functions for various processor components. In some embodiments, the system agent core 2510 includes one or more integrated memory controllers 2514 for managing access to various external memory devices (not shown).

[0272] In some embodiments, one or more of the processor cores 2502A - 2502N include support for simultaneous multithreading. In such embodiments, the system agent core 2510 includes components for coordinating and operating the processor cores 2502A - 2502N during multithreaded processing. The system agent core 2510 can additionally include a power control unit (PCU), which includes logic and components for regulating the power states of the processor cores 2502A - 2502N as well as the graphics processor 2508.

[0273] In some embodiments, the processor 2500 additionally includes a graphics processor 2508 for performing graphics processing operations. In some embodiments, the graphics processor 2508 is coupled to a set of shared cache units 2506 and a system agent core 2510, and the system agent core 2510 includes the one or more integrated memory controllers 2514. In some embodiments, a display controller 2511 is coupled to the graphics processor 2508 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 2511 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 2508 or the system agent core 2510.

[0274] In some embodiments, a ring-based interconnect unit 2512 is used to couple the internal components of the processor 2500. However, alternative interconnect units can be used, such as point-to-point interconnects, switched interconnects, or other techniques, including techniques well known in the art. In some embodiments, the graphics processor 2508 is coupled to the ring interconnect 2512 via an I / O link 2513.

[0275] The exemplary I / O link 2513 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2518, such as an eDRAM module. In some embodiments, each of the processor cores 2502A - 2502N and the graphics processor 2508 uses the embedded memory module 2518 as a shared last-level cache.

[0276] In some embodiments, the processor cores 2502A - 2502N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 2502A - 2502N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 2502A - 2502N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 2502A - 2502N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. Additionally, the processor 2500 can be implemented on one or more chips or as a SoC integrated circuit that also has the components shown in addition to other components.

[0277] Figure 26is a block diagram of a graphics processor 2600, which can be a discrete graphics processing unit or can be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and uses commands placed in the processor memory. In some embodiments, the graphics processor 2600 includes a memory interface 2614 for accessing memory. The memory interface 2614 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0278] In some embodiments, the graphics processor 2600 also includes a display controller 2602 for driving display output data to a display device 2620. The display controller 2602 includes hardware for one or more overlapping planes of the display and the composition of multi-layer video or user interface elements. In some embodiments, the graphics processor 2600 includes a video codec engine 2606 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, the one or more media coding formats including but not limited to Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421 M / VC-1 and Joint Photographic Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG) formats).

[0279] In some embodiments, the graphics processor 2600 includes a block image transfer (BLIT) engine 2604 for performing two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2610. In some embodiments, the GPE 2610 is a computing engine for performing graphics operations including three-dimensional (3D) graphics operations and media operations.

[0280] In some embodiments, the GPE 310 includes a 3D pipeline 2612 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2612 includes programmable and fixed function elements that perform various tasks within the element and / or generate a large number of execution threads to the 3D / media subsystem 2615. Although the 3D pipeline 2612 can be used to perform media operations, embodiments of the GPE 2610 also include a media pipeline 2616 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0281] In some embodiments, the media pipeline 2616 includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, in place of, or on behalf of, the video codec engine 2606. In some embodiments, the media pipeline 2616 additionally includes a thread generation unit to generate a large number of threads for execution on the 3D / media subsystem 2615. The generated threads perform computations for media operations on one or more graphics execution units included in the 3D / media subsystem 2615.

[0282] In some embodiments, the 3D / media subsystem 2615 includes logic for executing the threads generated by the 3D pipeline 2612 and the media pipeline 2616. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 2615, which includes thread dispatch logic for arbitrating various requests and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2615 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0283] Additional exemplary graphics processing engine

[0284] Figure 27 is a block diagram of a graphics processing engine 2710 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2710 is Figure 26 a version of the GPE 2610 shown in Figure 27Elements having the same reference numbers (or names) as elements in any other figure in this document can operate or function in any way similar to the ways described elsewhere in this document, but are not limited to such. For example, shown is Figure 26 3D pipeline 2612 and media pipeline 2616. The media pipeline 2616 is optional in some embodiments of the GPE 2710 and may not be explicitly included within the GPE 2710. For example and in at least one embodiment, a separate media and / or image processor is coupled to the GPE 2710.

[0285] In some embodiments, the GPE 2710 is coupled to or includes a command streamer 2703 that provides a command stream to the 3D pipeline 2612 and / or the media pipeline 2616. In some embodiments, the command streamer 2703 is coupled to a memory, which can be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 2703 receives commands from the memory and sends the commands to the 3D pipeline 2612 and / or the media pipeline 2616. The commands are instructions fetched from a ring buffer storing commands for the 3D pipeline 2612 and the media pipeline 2616. In one embodiment, the ring buffer may additionally include a batch command buffer storing batches of multiple commands. Commands for the 3D pipeline 2612 may also include references to data stored in the memory, such as but not limited to vertex and geometry data for the 3D pipeline 2612 and image data and memory objects for the media pipeline 2616. The 3D pipeline 2612 and the media pipeline 2616 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 2714.

[0286] In various embodiments, the 3D pipeline 2612 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2714. The graphics core array 2714 provides a unified execution resource block. The multi-purpose execution logic (e.g., execution units) within the graphics core array 2714 includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

[0287] In some embodiments, the graphics core array 2714 further includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution units additionally include general-purpose logic programmable to perform parallel general-purpose computing operations. The general-purpose logic may perform processing operations in parallel with or in combination with the (multiple) processor cores 2407 of Figure 24 or the general-purpose logic within the processor cores 2502A - 2502N as in Figure 25 .

[0288] Output data generated by threads executing on the graphics core array 2714 may output the data to memory in the unified return buffer (URB) 2718. The URB 2718 may store data for multiple threads. In some embodiments, the URB 2718 may be used to send data between different threads executing on the graphics core array 2714. In some embodiments, the URB 2718 may additionally be used for synchronization between the fixed-function logic within the shared function logic 2720 and the threads on the graphics core array.

[0289] In some embodiments, the graphics core array 2714 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of the GPE 2710. In one embodiment, the execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0290] The graphics core array 2714 is coupled to the shared function logic 2720, which includes a plurality of resources shared among the graphics cores in the graphics core array. The shared functions within the shared function logic 2720 are hardware logic units that provide specialized complementary functions to the graphics core array 2714. In various embodiments, the shared function logic 2720 includes, but is not limited to, sampler 2721, math 2722, and inter-thread communication (ITC) 2723 logic. Additionally, some embodiments implement one or more caches 2725 within the shared function logic 2720. The shared function is implemented when the demand for a given specialized function is not sufficient to be included within the graphics core array 2714. Alternatively, a single instantiation of the specialized function is implemented as an independent entity within the shared function logic 2720 and shared among the execution resources within the graphics core array 2714. A set of exact functions shared among and included within the graphics core array 2714 varies between embodiments.

[0291] Figure 28 is a block diagram of another embodiment of the graphics processor 2800. Figure 28Elements having the same reference number (or name) as an element of any other figure in this document can operate or function in any manner similar to the manner described elsewhere in this document, but are not limited thereto.

[0292] In some embodiments, the graphics processor 2800 includes a ring interconnect 2802, a pipeline front end 2804, a media engine 2837, and graphics cores 2880A - 2880N. In some embodiments, the ring interconnect 2802 couples the graphics processor to other processing units, which include other graphics processors or one or more general - purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi - core processing system.

[0293] In some embodiments, the graphics processor 2800 receives multiple batches of commands via the ring interconnect 2802. The incoming commands are interpreted by a command streamer 2803 in the pipeline front end 2804. In some embodiments, the graphics processor 2800 includes scalable execution logic for performing 3D geometry processing and media processing via the (multiple) graphics cores 2880A - 2880N. For 3D geometry processing commands, the command streamer 2803 supplies the commands to a geometry pipeline 2836. For at least some media processing commands, the command streamer 2803 supplies the commands to a video front end 2834, which is coupled to the media engine 2837. In some embodiments, the media engine 2837 includes a video quality engine (VQE) 2830 for video and image post - processing and a multi - format encoding / decoding (MFX) 2833 engine for providing hardware - accelerated encoding and decoding of media data. In some embodiments, the geometry pipeline 2836 and the media engine 2837 each generate execution threads for execution resources provided by at least one of the graphics cores 2880A.

[0294] In some embodiments, the graphics processor 2800 includes scalable thread execution resources featuring modular cores 2880A-2880N (sometimes referred to as core slices), each of the modular cores 2880A-2880N having multiple sub-cores 2850A-550N, 2860A-2860N (sometimes referred to as corelets). In some embodiments, the graphics processor 2800 can have any number of graphics cores 2880A through 2880N. In some embodiments, the graphics processor 2800 includes a graphics core 2880A that has at least a first sub-core 2850A and a second sub-core 2860A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2850A). In some embodiments, the graphics processor 2800 includes multiple graphics cores 2880A-2880N, each including a set of first sub-cores 2850A-2850N and a set of second sub-cores 2860A-2860N. Each sub-core in the set of first sub-cores 2850A-2850N includes at least a first set of execution units 2852A-2852N and media / texture samplers 2854A-2854N. Each sub-core in the set of second sub-cores 2860A-2860N includes at least a second set of execution units 2862A-2862N and samplers 2864A-2864N. In some embodiments, each sub-core 2850A-2850N, 2860A-2860N shares a set of shared resources 2870A-2870N. In some embodiments, the shared resources include a shared cache memory and pixel operation logic. Other shared resources can also be included in various embodiments of the graphics processor.

[0295] Additional exemplary execution unit

[0296] Figure 29 Thread execution logic 2900 is shown, which includes an array of processing elements employed in some embodiments of the GPE. Figure 29 Elements having the same reference number (or name) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0297] In some embodiments, the thread execution logic 2900 includes a shader processor 2902, a thread dispatcher 2904, an instruction cache 2906, a scalable execution unit array including a plurality of execution units 2908A - 2908N, a sampler 2910, a data cache 2912, and a data port 2914. In one embodiment, the scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution units 2908A, 2908B, 2908C, 2908D through 2908N - 1 and 2908N) based on the computational requirements of the workload. In one embodiment, the components included are interconnected via an interconnect structure that links to each of the components. In some embodiments, the thread execution logic 2900 includes one or more connections to memory (such as system memory or a cache) through the instruction cache 2906, the data port 2914, the sampler 2910, and one or more of the execution units 2908A - 2908N. In some embodiments, each execution unit (e.g., 2908A) is an independent programmable general - purpose computing unit capable of executing multiple simultaneous hardware threads and processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2908A - 2908N is scalable to include any number of individual execution units.

[0298] In some embodiments, the execution units 2908A - 2908N are primarily used to execute shader programs. The shader processor 2902 can process various shader programs and dispatch execution threads associated with the shader programs via the thread dispatcher 2904. In one embodiment, the thread dispatcher includes logic for arbitrating requests for threads initiated from the graphics and media pipelines and instantiating the requested threads on one or more of the execution units 2908A - 2908N. For example, a geometry pipeline (e.g., Figure 28 2836) can dispatch vertex, tessellation, or geometry shaders to the thread execution logic 2900 ( Figure 29 ) for processing. In some embodiments, the thread dispatcher 2904 can also handle runtime thread spawning requests from executing shader programs.

[0299] In some embodiments, execution units 2908A - 2908N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs from graphics libraries (e.g., Direct 3D and OpenGL) to be executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general - purpose processing (e.g., compute and media shaders). Each of execution units 2908A - 2908N has the ability for multi - issue single - instruction multiple - data (SIMD) execution, and multi - threading operations enable an efficient execution environment in the face of higher - latency memory accesses. Each hardware thread within each execution unit has a dedicated high - bandwidth register file and associated independent thread state. For pipelines with integer, single - and double - precision floating - point operations, SIMD branch capabilities, logical operations, transcendental operations, and other miscellaneous operation capabilities, execution is multi - issue per clock. When waiting for data from either memory or a shared function, dependency logic within execution units 2908A - 2908N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during a latency period associated with vertex shader operations, the execution unit can execute operations of a pixel shader, fragment shader, or another type of shader program including a different vertex shader.

[0300] Each execution unit among execution units 2908A - 2908N operates on an array of data elements. The number of data elements is the "execution size", or the number of lanes for the instruction. Execution lanes are the logical units for data - element access, masking, and execution of flow control within the instruction. The number of lanes can be independent of the number of physical arithmetic - logic units (ALUs) or floating - point units (FPUs) for a particular graphics processor. In some embodiments, execution units 2908A - 2908N support integer and floating - point data types.

[0301] The execution - unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256 - bit - wide vector, the 256 - bit vector is stored in a register and the execution unit operates on the vector as four separate 64 - bit compressed data elements (quad - word (QW) - sized data elements), eight separate 32 - bit compressed data elements (double - word (DW) - sized data elements), sixteen separate 16 - bit compressed data elements (word (W) - sized data elements), or thirty - two separate 8 - bit data elements (byte (B) - sized data elements). However, different vector widths and register sizes are possible.

[0302] One or more internal instruction caches (e.g., 2906) are included in the thread execution logic 2900 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 2912) are included to cache thread data during thread execution. In some embodiments, a sampler 2910 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2910 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0303] During execution, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2900 via the thread spawning and dispatching logic. Once a set of geometric objects has been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2902 is invoked to further compute output information and cause the results to be written to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader computes values for various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 2902 then executes a pixel or fragment shader program supplied by an application programming interface (API). To execute the shader program, the shader processor 2902 dispatches threads to the execution units (e.g., 2908A) via the thread dispatcher 2904. In some embodiments, the pixel shader 2902 uses the texture sampling logic in the sampler 2910 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and the input geometric data compute the pixel color data for each geometric fragment, or discard one or more pixels from further processing.

[0304] In some embodiments, the data port 2914 provides a memory access mechanism for the thread execution logic 2900 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 2914 includes or is coupled to one or more caches (e.g., the data cache 2912) to cache data for memory access via the data port.

[0305] Figure 30FIG. 0 is a block diagram showing a graphics processor instruction format 3000 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. The solid blocks show components generally included in an execution unit instruction, while the dashed lines include optional or components included only in a subset of the instructions. In some embodiments, the instruction formats 3000 described and shown are macro-instructions, as they are the instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decoding once the instruction is processed.

[0306] In some embodiments, a graphics processor execution unit natively supports instructions in a 128-bit instruction format 3010. Based on the selected instruction, instruction options, and number of operands, a 64-bit compressed instruction format 3030 may be used for some instructions. The native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 3030. The native instructions available in the 64-bit format 3030 vary by embodiment. In some embodiments, a set of index values in an index field 3013 is used to partially compress the instruction. The execution unit hardware references a set of compression tables based on the index values and uses the compressed table output to reconstruct the native instruction in the 128-bit instruction format 3010.

[0307] For each format, an instruction opcode 3012 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel, where each color channel represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, an instruction control field 3014 enables control of certain execution options, such as channel selection (e.g., predication) and data channel ordering (e.g., swizzling). For instructions in the 128-bit instruction format 3010, an execution size field 3016 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 3016 is not available for use in the 64-bit compressed instruction format 3030.

[0308] Some execution unit instructions have up to three operands, including two source operands - src0 3020, src1 3022, and one destination 3018. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 3024), where the instruction opcode 3012 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0309] In some embodiments, the 128-bit instruction format 3010 includes an access / addressing mode field 3026 that specifies, for example, whether to use a direct register addressing mode or an indirect register addressing mode. When using the direct register addressing mode, the register addresses of one or more operands are provided directly by bits in the instruction.

[0310] In some embodiments, the 128-bit instruction format 3010 includes an access / addressing mode field 3026 that specifies the addressing mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte alignment access mode and a 1-byte alignment access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands.

[0311] In one embodiment, the addressing mode portion of the access / addressing mode field 3026 determines whether the instruction is to use direct addressing or indirect addressing. When using the direct register addressing mode, the bits in the instruction directly provide the register addresses of one or more operands. When using the indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0312] In some embodiments, instructions are grouped based on the 3012-bit opcode fields to simplify opcode decoding 3040. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is merely exemplary. In some embodiments, the move and logic opcode group 3042 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 3042 shares the five most significant bits (MSBs), where the move (mov) instruction takes the form 0000xxxxb and the logic instruction takes the form 0001xxxxb. The flow control instruction group 3044 (e.g., call, jump (jmp)) includes instructions taking the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 3046 includes a mix of instructions, including synchronization instructions (e.g., wait, send) taking the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 3048 includes arithmetic instructions (e.g., add, multiply (mul)) in terms of components taking the form 0100xxxxb (e.g., 0x40). The parallel math group 3048 performs arithmetic operations in parallel across data channels. The vector math group 3050 includes arithmetic instructions (e.g., dp4) taking the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations.

[0313] Additional exemplary graphics pipeline

[0314] Figure 31 is a block diagram of another embodiment of the graphics processor 3100. Figure 31 Elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0315] In some embodiments, the graphics processor 3100 includes a graphics pipeline 3120, a media pipeline 3130, a display engine 3140, thread execution logic 3150, and a render output pipeline 3170. In some embodiments, the graphics processor 3100 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more (not shown) control registers or via commands issued through the ring interconnect 3102 to the graphics processor 3100. In some embodiments, the ring interconnect 3102 couples the graphics processor 3100 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 3102 are interpreted by a command streamer 3103, which supplies instructions to individual components of the graphics pipeline 3120 or the media pipeline 3130.

[0316] In some embodiments, the command streamer 3103 directs the operation of the vertex fetcher 3105, which reads vertex data from memory and executes vertex processing commands provided by the command streamer 3103. In some embodiments, the vertex fetcher 3105 provides vertex data to the vertex shader 3107, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 3105 and the vertex shader 3107 execute vertex processing instructions by dispatching execution threads to the execution units 3152A - 3152B via the thread dispatcher 3131.

[0317] In some embodiments, the execution units 3152A - 3152B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, the execution units 3152A - 3152B have attached L1 caches 3151, which are specific to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0318] In some embodiments, the graphics pipeline 3120 includes a tessellation component for performing hardware - accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 811 configures the tessellation operation. The programmable domain shader 817 provides backend evaluation of the tessellation output. The tessellator 3113 operates in the direction of the hull shader 3111 and includes dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model, which are provided as input to the graphics pipeline 3120. In some embodiments, if tessellation is not used, the tessellation component (e.g., the hull shader 3111, the tessellator 3113, and the domain shader 3117) can be bypassed.

[0319] In some embodiments, the complete geometric object can be processed by the geometry shader 3119 via one or more threads dispatched to the execution units 3152A - 3152B, or can proceed directly to the clipper 3129. In some embodiments, the geometry shader operates on the entire geometric object rather than on vertices or vertex patches as in the previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 3119 receives input from the vertex shader 3107. In some embodiments, the geometry shader 3119 can be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0320] Before rasterization, the clipper 3129 processes vertex data. The clipper 3129 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader capabilities. In some embodiments, the rasterizer and depth test component 3173 in the render output pipeline 3170 dispatches pixel shaders to convert geometric objects into their per-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 3150. In some embodiments, an application can bypass the rasterizer and depth test component 3173 and access the un-rasterized vertex data via the out-of-order unit 3123.

[0321] The graphics processor 3100 has an interconnect bus, an interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed between the major components of the processor. In some embodiments, the execution units 3152A - 3152B and the associated caches 3151, the texture and media sampler 3154, and the texture / sampler cache 3158 are interconnected via the data port 3156 to perform memory accesses and communicate with the render output pipeline components of the processor. In some embodiments, the sampler 3154, the caches 3151, 3158, and the execution units 3152A - 3152B each have separate memory access paths.

[0322] In some embodiments, the render output pipeline 3170 includes a rasterizer and depth test component 3173 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. Associated render cache 3178 and depth cache 3179 are also available in some embodiments. The pixel operation component 3177 performs pixel-based operations on the data, however, in some instances, pixel operations associated with 2D operations (e.g., bit-block blit with blending) are performed by the 2D engine 3141, or at display time by the display controller 3143 using overlapping display planes instead. In some embodiments, a shared L3 cache 3175 is available to all graphics components, allowing data to be shared without using the main system memory.

[0323] In some embodiments, the graphics processor media pipeline 3130 includes a media engine 3137 and a video front end 3134. In some embodiments, the video front end 3134 receives pipeline commands from the command streamer 3103. In some embodiments, the media pipeline 3130 includes a separate command streamer. In some embodiments, the video front end 3134 processes the commands before sending the media commands to the media engine 3137. In some embodiments, the media engine 3137 includes a thread spawning function to spawn threads for dispatch to thread execution logic 3150 via a thread dispatcher 3131.

[0324] In some embodiments, the graphics processor 3100 includes a display engine 3140. In some embodiments, the display engine 3140 is external to the processor 3100 and is coupled to the graphics processor via the ring interconnect 3102 or some other interconnect bus or fabric. In some embodiments, the display engine 3140 includes a 2D engine 3141 and a display controller 3143. In some embodiments, the display engine 3140 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 3143 is coupled to a display device (not shown), which may be a system integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0325] In some embodiments, the graphics pipeline 3120 and the media pipeline 3130 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the driver software for the graphics processor converts API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and compute APIs, all from the Khronos Group. In some embodiments, support can also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, combinations of these libraries can be supported. Support can also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with a compatible 3D pipeline will also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

[0326] Graphics pipeline programming

[0327] Figure 32A is a block diagram showing a graphics processor command format 3200 according to some embodiments. Figure 32B is a block diagram showing a graphics processor command sequence 3210 according to an embodiment. Figure 32AThe solid blocks therein illustrate components that are generally included in a graphics command, while the dashed lines include optional components or components that are only included in a subset of the graphics command. Figure 32A A exemplary graphics processor command format 3200 includes data fields for identifying a target client 3202 of the command, a command operation code (opcode) 3204, and associated data 3206 of the command. Some commands also include a sub-opcode 3205 and a command size 3208.

[0328] In some embodiments, the client 3202 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition further processing of the command and route the command data to an appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 3204 and the sub-opcode 3205 (if present) to determine the operation to be performed. The client unit uses the information in the data field 3206 to execute the command. For some commands, an explicit command size 3208 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, commands are aligned by multiples of doublewords.

[0329] Figure 32B The flow therein illustrates an exemplary graphics processor command sequence 3210. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the illustrated command sequence to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described only for purposes of example, as embodiments are not limited to these particular commands or this command sequence. Moreover, the commands may be issued as a batch of commands in a command sequence such that the graphics processor will process the sequence of commands at least partially concurrently.

[0330] In some embodiments, the graphics processor command sequence 3210 may begin with a pipeline flush clear command 3212 to cause any active graphics pipeline to complete the current outstanding commands for that pipeline. In some embodiments, the 3D pipeline 3222 and the media pipeline 3224 do not operate simultaneously. A pipeline flush clear is performed to cause the active graphics pipeline to complete any outstanding commands. In response to the pipeline flush clear, the command parser for the graphics processor will pause command processing until the active drawing engine has completed the outstanding operations and the associated read caches are invalidated. Optionally, any data marked 'dirty' in the render cache may be flushed to memory. In some embodiments, the pipeline flush clear command 3212 may be used for pipeline synchronization or prior to placing the graphics processor in a low power state.

[0331] In some embodiments, a pipeline select command 3213 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, only one pipeline select command 3213 is required within an execution context prior to issuing pipeline commands, unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush clear command 3212 is required immediately prior to a pipeline switch via the pipeline select command 3213.

[0332] In some embodiments, the pipeline control command 3214 configures the graphics pipeline for operation and programs the 3D pipeline 3222 and the media pipeline 3224. In some embodiments, the pipeline control command 3214 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command 3214 is used for pipeline synchronization and for clearing data from one or more caches within the active pipeline prior to processing a batch of commands.

[0333] In some embodiments, commands specific to the return buffer state 3216 are used to configure a set of return buffers for enabling the corresponding pipeline to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which intermediate data is written during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 3216 includes the size and number of return buffers to be used for a set of pipeline operations.

[0334] The remaining commands in the command sequence vary based on the active pipeline for operation. Based on the pipeline determination 3220, the command sequence is suitable for the 3D pipeline 3222 starting with the 3D pipeline state 3230 or the media pipeline 3224 starting in the media pipeline state 3240.

[0335] Commands for configuring the 3D pipeline state 3230 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured prior to processing 3D primitive commands. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, the 3D pipeline state 3230 commands are also capable of selectively disabling or bypassing certain pipeline elements if those elements will not be used.

[0336] In some embodiments, the 3D primitive 3232 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 3232 commands are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 3232 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 3232 commands are used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 3222 dispatches shader execution threads to the graphics processor execution units.

[0337] In some embodiments, the 3D pipeline 3222 is triggered via an execution 3234 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to flush a clear command sequence through the graphics pipeline. The 3D pipeline will perform geometric processing on the 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0338] In some embodiments, when performing media operations, the graphics processor command sequence 3210 follows the media pipeline 3224 path. Generally, the specific use and manner of programming for the media pipeline 3224 depends on the media or compute operation to be performed. During media decoding, specific media decoding operations may be offloaded to the media pipeline. In some embodiments, the media pipeline may also be bypassed and resources provided by one or more general-purpose processing cores may be used to perform media decoding, either in whole or in part. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs not explicitly related to rendering graphics primitives.

[0339] In some embodiments, the media pipeline 3224 is configured in a manner similar to the 3D pipeline 3222. A set of commands for configuring the media pipeline state 3240 are dispatched or placed into a command queue, before the media object commands 3242. In some embodiments, the media pipeline state commands 3240 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state commands 3240 also support the use of one or more pointers to "indirect" state elements that point to a batch of state settings.

[0340] In some embodiments, the media object commands 3242 supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers that contain video data to be processed. In some embodiments, all media pipeline states must be valid before the media object commands 3242 are issued. Once the pipeline state is configured and the media object commands 3242 are queued, the media pipeline 3224 is triggered via an execute command 3244 or an equivalent execution event (e.g., a register write). The output from the media pipeline 3224 can then be post-processed by operations provided by the 3D pipeline 3222 or the media pipeline 3224. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0341] Graphics software architecture

[0342] Figure 33 A exemplary graphics software architecture of a data processing system 3300 is shown in accordance with some embodiments. In some embodiments, the software architecture includes a 3D graphics application 3310, an operating system 3320, and at least one processor 3330. In some embodiments, the processor 3330 includes a graphics processor 3332 and one or more general purpose processor cores 3334. The graphics application 3310 and the operating system 3320 each execute in the system memory 3350 of the data processing system.

[0343] In some embodiments, the 3D graphics application 3310 includes one or more shader programs that include shader instructions 3312. The shader language instructions can be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 3314 in machine language suitable for execution by the general purpose processor cores 3334. The application also includes graphics objects 3316 defined by vertex data.

[0344] In some embodiments, the operating system 3320 is the Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open-source UNIX-like operating system using a variant of the Linux kernel. The operating system 3320 may support a graphics API 3322, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 3320 uses a front-end shader compiler 3324 to compile any shader instructions 3312 in HLSL into a lower-level shader language. The compilation may be just-in-time (JIT) compilation, or the application may perform shader pre-compilation. In some embodiments, during the compilation of the 3D graphics application 3310, high-level shaders are compiled into low-level shaders. In some embodiments, the shader instructions 3312 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0345] In some embodiments, the user-mode graphics driver 3326 includes a back-end shader compiler 3327 for converting the shader instructions 3312 into a hardware-specific representation. When the OpenGL API is in use, the shader instructions 3312 in the GLSL high-level language are passed to the user-mode graphics driver 3326 for compilation. In some embodiments, the user-mode graphics driver 3326 uses the operating system kernel-mode functionality 3328 to communicate with the kernel-mode graphics driver 3329. In some embodiments, the kernel-mode graphics driver 3329 communicates with the graphics processor 3332 to dispatch commands and instructions.

[0346] IP core implementation

[0347] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit and may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to various consumers or manufacturing facilities that load the hardware model onto a manufacturing machine for fabricating the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

[0348] Figure 34FIG. 3400 is a block diagram showing an IP core development system 3400 that can be used to fabricate integrated circuits to perform operations in accordance with an embodiment. The IP core development system 3400 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). A design facility 3430 can generate a software simulation 3410 of an IP core design in a high-level programming language (e.g., C / C++). The software simulation 3410 can be used to design, test, and verify the behavior of the IP core using a simulation model 3412. The simulation model 3412 can include functional, behavioral, and / or timing simulations. A register transfer level (RTL) design 3415 can then be created or synthesized from the simulation model 3412. The RTL design 3415 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including the associated logic executed using the modeled digital signals. In addition to the RTL design 3415, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

[0349] The RTL design 3415 or equivalent can be further synthesized by the design facility into a hardware model 3420, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. A non-volatile memory 3440 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 3465. Alternatively, the IP core design can be transmitted (e.g., via the Internet) over a wired connection 3450 or a wireless connection 3460. The manufacturing facility 3465 can then fabricate an integrated circuit that is at least partially based on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0350] Exemplary system - on - chip integrated circuit

[0351] Figures 35 - 37 FIG. shows exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores in accordance with various embodiments described herein. In addition to the things shown, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0352] Figure 35is a block diagram showing an exemplary system-on-chip integrated circuit 3500 that can be fabricated using one or more IP cores. The exemplary integrated circuit 3500 includes one or more application processors 3505 (e.g., CPUs), at least one graphics processor 3510, and additionally may include an image processor 3515 and / or a video processor 3520, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 3500 includes peripheral or bus logic, which includes a USB controller 3525, a UART controller 3530, an SPI / SDIO controller 3535, and an I 2 S / I 2 C controller 3540. Additionally, the integrated circuit may include a display device 3545 coupled to one or more of a high-definition multimedia interface (HDMI) controller 3550 and a mobile industry processor interface (MIPI) display interface 3555. Storage may be provided by a flash memory subsystem 3560 that includes a flash memory and a flash memory controller. A memory interface may be provided via a memory controller 3565 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 3570.

[0353] Figure 36 is a block diagram showing an exemplary graphics processor 3610 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores. The graphics processor 3610 may be a Figure 36 variant of the graphics processor 3610. The graphics processor 3610 includes a vertex processor 3605 and one or more fragment processors 3615A - 3615N (e.g., 3615A, 3615B, 3615C, 3615D to 3615N - 1, and 3615N). The graphics processor 3610 can execute different shader programs via separate logic such that the vertex processor 3605 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 3615A - 3615N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 3605 executes the vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. The (multiple) fragment processors 3615A - 3615N use the primitives and vertex data generated by the vertex processor 3605 to produce a frame buffer that is displayed on a display device. In one embodiment, the (multiple) fragment processors 3615A - 3615N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs as provided in the Direct3D API.

[0354] The graphics processor 3610 additionally includes one or more memory management units (MMUs) 3620A - 3620B, (multiple) caches 3625A - 3625B, and (multiple) circuit interconnects 3630A - 3630B. The one or more MMUs 3620A - 3620B are integrated circuits 3610 that provide virtual - to - physical address mapping for the vertex processor 3605 and / or (multiple) fragment processors 3615A - 3615N. The virtual - to - physical address mapping can reference vertex or image / texture data stored in memory in addition to the vertex or image / texture data stored in the one or more caches 3625A - 3625B. In one embodiment, the one or more MMUs 3625A - 3625B can be synchronized with other MMUs within the system, the other MMUs including one or more MMUs associated with Figure 36 the one or more application processors 3605, image processors 3615, and / or video processors 3620 such that each processor 3605 - 3620 can participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 3630A - 3630B enable the graphics processor 3610 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0355] Figure 37 is a block diagram showing an additional exemplary graphics processor 3710 of a system - on - a - chip integrated circuit that can be fabricated using one or more IP cores. The graphics processor 3710 can be Figure 35 a variant of the graphics processor 3510. The graphics processor 3710 includes Figure 35 the one or more MMUs 3520A - 3520B, caches 3525A - 3525B, and circuit interconnects 3530A - 3530B of the integrated circuit 3500.

[0356] Graphics processor 3710 includes one or more shader cores 3715A - 3715N (e.g., 3715A, 3715B, 3715C, 3715D, 3715E, 3715F to 3715N - 1, and 3715N), which provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, and the programmable shader code includes shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present can vary among embodiments and implementations. Additionally, graphics processor 3710 includes an inter - core task manager 3705, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 3715A - 3715N, and a tiling unit 3718 for accelerating tiled operations for tile - based rendering, where rendering operations for a scene are subdivided in image space, e.g., for leveraging local spatial coherence within the scene or for optimizing the use of internal caches.

[0357] The present invention also discloses a set of technical solutions as follows:

[0358] 1. A machine - learning hardware accelerator, comprising:

[0359] A computing unit having adders and multipliers shared between an integer data path and a floating - point data path, where the multiplier is configured to gate the high - order bits of input operands during floating - point operations to enable calculation based on the mantissa product of a first operand and a second operand.

[0360] 2. The machine - learning hardware accelerator according to technical solution 1, wherein the computing unit has a mode input to switch the computing unit between integer operations and floating - point operations.

[0361] 3. The machine - learning hardware accelerator according to technical solution 2, wherein the computing unit includes an exponent unit and a mantissa unit, and the exponent unit and the mantissa unit are included in the floating - point data path and the integer data path.

[0362] 4. The machine - learning hardware accelerator according to technical solution 3, wherein the mode input causes a switch to provide the exponents and signs of the first operand and the second operand to the exponent unit for processing during floating - point operations.

[0363] 5. The machine - learning hardware accelerator according to technical solution 4, wherein the exponent unit includes an incrementer to increment the high - order bits of the sum output by the adder during integer operations.

[0364] 6. The machine learning hardware accelerator as described in Technical Solution 1, wherein the computing unit is configurable to output an integer result during a first cycle and a floating-point result during a second cycle.

[0365] 7. The machine learning hardware accelerator as described in Technical Solution 1, wherein the multiplier of the computing unit performs a multiplication operation during a first stage of a fused multiply-accumulate operation and an addition operation during a second stage of the fused multiply-accumulate operation.

[0366] 8. The machine learning hardware accelerator as described in Technical Solution 7, wherein the first stage of the fused multiply-accumulate operation is to be performed during a first clock cycle, the second stage of the fused multiply-accumulate operation is to be performed during a second clock cycle, and the computing unit is to output a result during each of the first clock cycle and the second clock cycle.

[0367] 9. The machine learning hardware accelerator as described in Technical Solution 8, wherein the computing unit is used to output the result of the second stage during the first clock cycle.

[0368] 10. The machine learning hardware accelerator as described in Technical Solution 9, wherein the computing unit is used to store intermediate floating-point data in a non-IEEE format with a 22-bit mantissa.

[0369] 11. A method for accelerating machine learning operations, the method comprising:

[0370] Obtaining and decoding a single instruction to perform a combined multiplication and addition operation on a set of operands;

[0371] Issuing the single instruction for execution by a dynamically configurable computing unit;

[0372] Configuring one or more logic units of the computing unit to perform operations with the data type and precision of the set of operands; and

[0373] Executing at least a portion of the single instruction at the dynamically configurable computing unit to generate and output based on the multiplication and addition operations.

[0374] 12. The method as described in Technical Solution 11, wherein the combined multiplication and addition operation is a fused multiply-add or fused multiply-accumulate operation.

[0375] 13. The method as described in Technical Solution 11, additionally comprising executing at least a portion of the single instruction via a machine learning accelerator unit.

[0376] 14. The method according to claim 13, wherein performing at least a portion of the single instruction includes quantizing an intermediate value having a first precision to a second precision lower than the first precision, the quantizing including randomly rounding a fractional part of the intermediate data.

[0377] 15. The method according to claim 14, additionally including randomly rounding the fractional part of the intermediate data based on a probability distribution associated with the intermediate data.

[0378] 16. A data processing system, comprising:

[0379] a non-transitory machine-readable medium configured to store instructions for execution by one or more processors of the data processing system; and

[0380] a general-purpose graphics processing unit including a machine learning hardware accelerator and a dynamic precision calculation unit, the machine learning hardware accelerator including hardware logic configured to perform a plurality of machine learning computational operations in response to a single instruction.

[0381] 17. The data processing system according to claim 16, wherein the dynamic precision calculation unit includes calculation logic having adders and multipliers shared between an integer data path and a floating-point data path, the calculation logic being configurable to generate floating-point data encoded in a non-standard format.

[0382] 18. The data processing system according to claim 17, wherein, in response to the single instruction, the plurality of machine learning computational operations include a first operation configured to perform a fused multiply-add operation and a second operation configured to apply an activation function to an output of the fused multiply-add operation.

[0383] 19. The data processing system according to claim 18, wherein the activation function is a sigmoid function.

[0384] 20. The data processing system according to claim 18, wherein the machine learning hardware accelerator includes a stochastic quantization unit configured to perform stochastic rounding during quantization of neural network data during the plurality of machine learning computational operations.

[0385] The embodiments described herein provide a logic unit that includes a combined integer / floating-point data path for both multiply-add (e.g., a * b + c) and multiply-accumulate (e.g., c = c + a * b) operations. In one embodiment, the addend for the addition operation is based on the accumulation from a previous operation. In one embodiment, the integer data path of the logic unit is merged into a floating-point data path that has an addend alignment operation parallel to the multiplication operation. In one embodiment, the integer data path is merged into a floating-point data path that has an addend alignment operation after the multiplication operation. The multiply-add and multiply-accumulate data paths described herein can be single-cycle or multi-cycle.

[0386] In one embodiment, during a two-cycle floating-point multiply-accumulate, the logic unit does not compare the mantissas at the start of the second stage (e.g., the adder stage). Instead, the logic unit pre-computes the larger (or smaller) mantissa based on the accumulator exponent from the second stage and the multiplier output computed during the first stage.

[0387] In one embodiment, the accumulator or addend mantissa bit width is greater than the mantissa bit width of the multiplier input. In one embodiment, integer operations are mapped onto the floating-point unit. In addition to the mantissa circuitry of the floating-point unit, some of the integer operations are also mapped onto the existing exponent circuitry. In one embodiment, the logic unit described herein includes a multiplier unit and an adder unit that are shared between floating-point and integer operations and are used to perform both floating-point and integer operations.

[0388] The following clauses and / or examples relate to specific embodiments or examples thereof. The specific details in the examples can be used anywhere in one or more embodiments. The various features of different embodiments or examples can be combined in various ways with some of the features included and other features excluded to suit a wide variety of different applications. The examples can include subjects such as methods, components for performing the actions of the methods, at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform the actions of the methods or devices or systems according to the embodiments and examples described herein. The various components can be components for performing the described operations or functions. [[ID=I0]]

[0389] One embodiment provides a machine learning hardware accelerator that includes a computing unit having adders and multipliers shared between an integer data path and a floating-point data path, and high-order bits of input operands to the multipliers are to be gated during floating-point operations. In one embodiment, the adders and multipliers are configurable to perform floating-point operations and integer operations. In one embodiment, the computing unit is to perform multiply-add operations via the multipliers and adders. In one embodiment, the computing unit accepts at least two input operands. One embodiment provides the computing unit to perform multiply-accumulate operations using double input operands and an accumulated value. One embodiment provides the computing unit to perform multiply-add operations using three input operands. In one embodiment, the computing unit is to perform multiply-accumulate operations or multiply-add operations in a single cycle. In one embodiment, the computing unit is to perform double-cycle multiply-add operations or double-cycle multiply-accumulate operations. In one embodiment, the multiplier within the computing unit is to produce an output during a first cycle, and the adder is to produce an output during a second cycle. In one embodiment, the computing unit is to perform a double-cycle multiply-accumulate operation, where the first cycle is associated with a first logic stage, the second cycle is associated with a second logic stage, and the computing unit includes an exponent unit to pre-compute a larger mantissa and an alignment shift for the second stage via an accumulated output of a previous cycle of the second stage and a multiplier output from the first stage.

[0390] In one embodiment, the integer data path is merged into the floating-point data path having an addend alignment operation parallel to the multiplication operation. In one embodiment, the integer data path is merged into the floating-point data path having an addend alignment operation after the multiplication operation. The computing unit may have a mode input to switch the computing unit between integer operations and floating-point operations. In one embodiment, the computing unit is configurable for 8.8 fixed-point inputs and 16.0 fixed-point outputs.

[0391] One embodiment provides a data processing system, the data processing system including a non-transitory machine-readable medium to store instructions for execution by one or more processors of the data processing system; and a general-purpose graphics processing unit including a machine learning hardware accelerator and a dynamic precision computing unit, the machine learning hardware accelerator including hardware logic to perform multiple machine learning computing operations in response to a single instruction. In one embodiment, the dynamic precision computing unit is switchable between integer operations and floating-point operations. In one embodiment, the dynamic precision computing unit includes an integer data path and a floating-point data path sharing a multiplier and an adder, wherein the multiplier is to perform multiplication operations on the integer data path and the floating-point data path. In one embodiment, the floating-point data path includes an addend alignment operation performed in parallel with the multiplication operation. In one embodiment, the floating-point data path includes an addend alignment operation performed after the multiplication operation. In one embodiment, the dynamic precision computing unit is configured for single-cycle fused multiply-add operations or double-cycle fused multiply-accumulate operations.

[0392] One embodiment provides a method for accelerating machine learning operations, the method including obtaining and decoding a single instruction to perform combined multiplication and addition operations on an operand set; issuing the single instruction for execution by a dynamically configurable computing unit; configuring one or more logic units of the computing unit to perform operations in the precision and data type of the operand set; and executing at least a portion of the single instruction at the dynamically configurable computing unit to generate and output based on the multiplication and addition operations.

[0393] Embodiments described herein refer to specific configurations of hardware (e.g., application-specific integrated circuits (ASICs)) configured to perform certain operations or having a predetermined functionality. Such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connections. The coupling of the collection of processors and its other components is typically through one or more buses and bridges (also referred to as bus controllers). Storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the storage device of a given electronic device typically stores code and / or data for storage and execution on the collection of one or more processors of the electronic device.

[0394] Of course, one or more portions of the embodiments may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that embodiments may be practiced without some of these specific details. In some instances, well-known structures and functions have not been described in exhaustive detail to avoid obscuring the inventive subject matter of the embodiments. Accordingly, the scope and spirit of the present invention should be judged according to the following claims.

Claims

1. A graphics processing unit (GPU) for accelerating machine learning operations, the graphics processing unit comprising: A multiprocessor for executing multiple threads of a single instruction; The single instruction causes a first computing unit to perform at least a two-dimensional matrix multiplication operation; And Wherein performing the two-dimensional matrix multiplication operation includes calculating a 32-bit intermediate product of two 16-bit operands and calculating a 32-bit sum based on the 32-bit intermediate product.

2. The graphics processing unit according to claim 1, wherein the multiprocessor is used to execute parallel threads of a thread group, and each thread in the thread group has an independent thread state.

3. The graphics processing unit according to claim 2, wherein the multiprocessor includes a scheduler for scheduling the parallel threads to a plurality of computing units within the multiprocessor.

4. The graphics processing unit according to claim 3, wherein the plurality of computing units within the multiprocessor includes a second computing unit for performing integer operations, and the scheduler is used to schedule floating-point operations to the first computing unit and integer operations to the second computing unit.

5. The graphics processing unit according to claim 4, wherein the multiprocessor is used to simultaneously perform floating-point operations on the first computing unit and integer operations on the second computing unit.

6. A data processing system, comprising: A graphics processing unit (GPU) for accelerating machine learning operations, the graphics processing unit comprising a multiprocessor for executing multiple threads of a single instruction, the single instruction causing a first computing unit to perform at least a two-dimensional matrix multiplication operation, wherein performing the two-dimensional matrix multiplication operation includes calculating a 32-bit intermediate product of two 16-bit operands and calculating a 32-bit sum based on the 32-bit intermediate product; and A memory communicatively coupled to the graphics processing unit.

7. The data processing system according to claim 6, wherein the multiprocessor is used to execute parallel threads of a thread group, and each thread in the thread group has an independent thread state.

8. The data processing system according to claim 7, wherein the multiprocessor includes a scheduler for scheduling the parallel threads to a plurality of computing units within the multiprocessor.

9. The data processing system according to claim 8, wherein the plurality of computing units within the multiprocessor includes a second computing unit for performing integer operations, and the scheduler is used to schedule floating-point operations to the first computing unit and integer operations to the second computing unit.

10. The data processing system according to claim 9, wherein the multiprocessor is used to simultaneously perform floating-point operations on the first computing unit and integer operations on the second computing unit.

11. A method for accelerating machine learning operations, the method comprising: Decoding a single instruction on a graphics processing unit (GPU); Executing the single instruction through a multiprocessor within the graphics processing unit, including executing multiple threads of the single instruction; And In response to executing the single instruction by the multi-processor, at least perform a two-dimensional matrix multiplication operation on a first computing unit of the multi-processor, wherein performing the two-dimensional matrix multiplication operation includes calculating a 32-bit intermediate product of two 16-bit operands and calculating a 32-bit sum based on the 32-bit intermediate product.

12. The method according to claim 11, further comprising: Parallel threads of a thread group, each thread in the thread group having an independent thread state.

13. The method according to claim 12, further comprising: Schedule the parallel threads to a plurality of computing units within the multi-processor.

14. The method according to claim 13, wherein the plurality of computing units within the multi-processor include a second computing unit for performing integer operations, and the method further comprises: Schedule floating-point operations to the first computing unit and schedule integer operations to the second computing unit.

15. The method according to claim 14, further comprising: Simultaneously perform floating-point operations on the first computing unit and perform integer operations on the second computing unit.

16. A computing device, comprising components for performing the method according to any one of claims 11-15.

17. A non-transitory machine-readable medium having instructions stored thereon, which when executed by a machine, cause the machine to perform the method according to any one of claims 11-15.

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