Array substrate and liquid crystal display

Abstract

The present invention relates to an array substrate, comprising pixel units distributed in an array, wherein the pixel units comprise: a first electrode layer, arranged on a glass substrate; a dielectric layer, arranged on the surface of the first electrode layer; and a second electrode layer, arranged on the surface of the dielectric layer, wherein the second electrode layer comprises a patterned electrode pattern; wherein the electrode pattern comprises a main electrode pattern and an auxiliary electrode pattern located on at least one side of the main electrode pattern, wherein the auxiliary electrode pattern is electrically connected to the first electrode layer through a via hole, and a parallel electric field for driving liquid crystal deflection is formed between the auxiliary electrode pattern and the main electrode pattern; the beneficial effect of the present invention is that the purpose of reducing the charging time of the pixel unit is achieved by reducing the capacitance between the first electrode layer and the second electrode layer.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a liquid crystal display having the array substrate. Background Art

[0002] At present, liquid crystal display devices have been widely used in various electronic products as display components of electronic devices, and Thin Film Transistor-Liquid Crystal Display (TFT-LCD) is an important component in liquid crystal display devices.

[0003] As shown in the attached figure of the instruction manual Figure 1 As mentioned above, the array substrate of the prior art includes a thin film transistor, which is mainly composed of a backlight, a polarizing plate, an array substrate, a color film substrate and a liquid crystal. Figure 1 As shown, each pixel unit is composed of a glass substrate 101, a shielding layer 102 and a buffer layer 103, wherein polysilicon 104 is sandwiched between the buffer layer 103 and the gate insulating layer 105, an interlayer insulating layer 106 is placed directly above the polysilicon 104, and a source and drain electrode 109 is embedded in a U-shaped structure between the interlayer insulating layer 107 and the flat layer 108. The first electrode layer 110 and the second electrode layer 111 are overlapped by a dielectric layer 112. The gate 106 is a switch electrode, and the insulating layer 105 is used to separate the gate 106 from the source and drain electrodes 109 and the signal line. The scanning line is connected to the gate 106 of the thin film transistor to control the switch of a row of thin film transistor devices. The source and drain electrodes 109 of the thin film transistor are connected to the signal line, and the source and drain electrodes 109 are connected to the pixel electrode of the thin film transistor. When the thin film transistor switch is turned on, the signal on the signal line and the drain electrode 109 are transmitted to the source electrode 109 through the thin film transistor switch, and are added to the liquid crystal molecules of the pixel electrode to control the distortion of the liquid crystal molecules. The lead electrodes are connected to the edge of the array substrate and to module components such as the driving circuit.

[0004] The thin film transistor substrate is an array substrate, and the capacitor formed by the second electrode layer 110 and the first electrode layer 111 in the pixel unit is charged under the control of a clock signal.

[0005] The charging method of the prior art does not control the rotation direction of the liquid crystal between the thin film transistor substrate and the color film substrate by changing the electric field between the second electrode layer 110 and the first electrode layer 111, thereby changing the polarization direction of the light and controlling the light transmission amount in different pixel grids, thereby achieving different display effects.

[0006] In summary, the thin film transistor liquid crystal display in the prior art has the problem of short charging time. Summary of the invention

[0007] An embodiment of the present invention provides an array substrate, which reduces the capacitance between the top transparent electrode and the bottom transparent electrode by adding a new layer of transparent electrode next to the top transparent electrode and overlapping it with the bottom transparent electrode through the passivation layer hole, so as to solve the technical problems of long charging time and low charging efficiency of thin film transistors in the prior art.

[0008] To solve the above problems, the technical solution provided by the present invention is as follows:

[0009] An array substrate, the array substrate includes pixel units distributed in an array, the pixel units include: a first electrode layer, arranged on a glass substrate; a dielectric layer, arranged on the surface of the first electrode layer; and a second electrode layer, arranged on the surface of the dielectric layer, the second electrode layer includes a patterned electrode pattern; wherein the electrode pattern includes a main electrode pattern, and an auxiliary electrode pattern located on at least one side of the main electrode pattern, the auxiliary electrode pattern is electrically connected to the first electrode layer through a via, and a parallel electric field is formed between the auxiliary electrode pattern and the main electrode pattern for driving liquid crystal deflection.

[0010] According to a preferred embodiment of the present invention, the main electrode pattern and the first electrode layer form an overlapping area and a non-overlapping area, and the auxiliary electrode pattern is arranged in a spaced relationship from the main electrode pattern corresponding to the non-overlapping area.

[0011] According to a preferred embodiment of the present invention, the array substrate also includes thin film transistors distributed in an array, a first via is formed on the dielectric layer, the auxiliary electrode pattern is connected to the first electrode layer through the first via; the main electrode pattern is connected to the drain of the thin film transistor through the first via.

[0012] According to a preferred embodiment of the present invention, the auxiliary electrode patterns are distributed at intervals corresponding to the non-overlapping areas, and one of the auxiliary electrode patterns corresponds to at least one of the first via holes.

[0013] According to a preferred embodiment of the present invention, a second via is formed on the first electrode layer, the aperture of the second via is larger than the aperture of the first via, and the second via is nested on the first via corresponding to the overlapping area, so that the main electrode pattern corresponding to the first via is insulated from the first electrode layer by the dielectric layer.

[0014] According to a preferred embodiment of the present invention, the auxiliary electrode pattern and the main electrode pattern are arranged at equal intervals.

[0015] According to a preferred embodiment of the present invention, the main electrode pattern and the first electrode layer are respectively connected to the metal wires of the thin film transistor to form a voltage difference for driving the liquid crystal to deflect.

[0016] According to a preferred embodiment of the present invention, at least one corresponding first via hole is disposed in the dielectric layer.

[0017] According to a preferred embodiment of the present invention, the auxiliary electrode pattern and the main electrode pattern are formed through the same manufacturing process, and both are made of indium tin oxide.

[0018] The beneficial effects of the present invention are as follows: the electrode pattern includes a main electrode pattern and an auxiliary electrode pattern located on at least one side of the main electrode pattern, and the auxiliary electrode pattern is electrically connected to the first electrode layer through a via, thereby reducing the capacitance between the auxiliary electrode pattern and the main electrode pattern, reducing the charging time of the pixel unit, and thus improving work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 The figure is a schematic diagram of the substrate structure of an array substrate in the prior art.

[0021] Figure 2 A schematic diagram of the substrate structure of the first embodiment of the array substrate provided by the present invention;

[0022] Figure 3 A schematic diagram of a cross-sectional structure of a substrate of a first embodiment of an array substrate provided by the present invention;

[0023] Figure 4 This is a top plan structural diagram of a single pixel unit in Embodiment 1 of the array substrate provided by the present invention. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0025] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0026] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplicity and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0027] The length of the charging time of each pixel unit of the array substrate is related to the capacitance formed by the second electrode layer and the first electrode layer. In the series circuit of resistor R and capacitor C, the capacitor charging time is calculated as follows: charging time T = R*C*ln((EV) / E), where: R is the equivalent resistance of the circuit, C is the capacitance value; the external voltage value of the RC series circuit, T is the charging time, V--the voltage to be reached on the capacitor, and ln is the natural logarithm. The larger the capacitance C, the longer the charging time, and the smaller the capacitance C or the resistance R, the smaller the time constant R*C, and the faster the charging and discharging speed of the capacitor, and vice versa. Capacitors exist in almost all electronic circuits, and they can be used as "fast batteries".

[0028] The array substrate is an insulated gate field effect transistor, which is equivalent to a transistor circuit. The gate is connected to the gate line, the source is connected to the signal line, and the drain is connected to the pixel electrode. Liquid crystal material is an insulator and usually has a very low conductivity. The pixel electrode on the array substrate and the common electrode on the color film substrate form electrodes at both ends of the liquid crystal material. Therefore, the pixel electrode part of the liquid crystal screen is equivalent to a capacitor. At the same time, the storage capacitor electrode made at the same time as the pixel electrode and the gate is separated by an insulating film to form a storage capacitor, which is connected in parallel with the liquid crystal capacitor. Therefore, a unit pixel of an active matrix liquid crystal display is equivalent to a transistor switch, which is an equivalent circuit connecting two parallel liquid crystal capacitors and a storage capacitor, wherein the liquid crystal capacitor includes a second electrode layer and a first electrode layer, and the second electrode layer and the first electrode layer bear 80%-90% of the capacitance of the pixel unit. Therefore, increasing the capacitance of the first electrode layer and the second electrode layer can increase the charging time of the pixel unit.

[0029] The control of the switch is connected to the gate line. When the gate of the array substrate is scanned and turned on, a positive high-voltage pulse is applied to the gate, and the array substrate is turned on. The source has a signal input. The turned-on array substrate transmits the image signal to the first electrode layer and the second electrode layer connected to the turned-on array substrate through the on-state current. The two are charged at the same time, and the signal voltage is stored on the first electrode layer and the second electrode layer. The signal voltage of the liquid crystal pixel drives the liquid crystal molecules to rotate to achieve the corresponding display, and the liquid crystal capacitor plays a role in maintaining the image display.

[0030] Embodiment 1

[0031] like Figure 2 As shown, each pixel unit is composed of a glass substrate 201, a shielding layer 202 and a buffer layer 203, wherein polysilicon 204 is sandwiched between the buffer layer 203 and the gate insulating layer 205, an interlayer insulating layer 206 is placed directly above the polysilicon 204, and a source and drain electrode 209 is embedded in a U-shaped structure between the interlayer insulating layer 207 and the flat layer 208. The first electrode layer 210 and the second electrode layer 211 are overlapped by a dielectric layer 212, and the dielectric layer 212 includes at least one corresponding first via hole 212, which is used to reduce the capacitance between the first electrode layer 210 and the second electrode layer 211, and this capacitance forms an electric field for controlling the deflection of the liquid crystal. The gate 206 is a switch electrode, and the insulating layer 205 is used to separate the gate 206 from the source and drain 209 and the signal line. The scanning line is connected to the gate 206 of the thin film transistor to control the switch of a row of thin film transistor devices. The source and drain electrodes 209 of the thin film transistor are connected to the signal line, and the source and drain electrodes 109 are connected to the pixel electrodes of the thin film transistor. When the thin film transistor switch is turned on, the signal on the signal line and the drain electrode 209 are transmitted to the source electrode 209 through the thin film transistor switch, and added to the liquid crystal molecules of the pixel electrode to control the distortion of the liquid crystal molecules. The lead electrode is connected to the edge of the array substrate and to module components such as the drive circuit.

[0032] The thin film transistor substrate is an array substrate, and the capacitor formed by the second electrode layer 210 and the first electrode layer 211 in the pixel unit is charged under the control of a clock signal.

[0033] Figure 2 The essential difference from the prior art is that a first via hole 213 is provided in the dielectric layer 212 in this figure, which reduces the electric field formed for controlling the deflection of the liquid crystal.

[0034] Preferably, the cross-sectional shape of the first via hole 213 is set to be circular or square for easy overlap.

[0035] like Figure 3 As shown, the second electrode layer includes a main electrode pattern 310 and an auxiliary electrode pattern 313. The electric field between the main electrode pattern 310 and the second auxiliary electrode pattern 313 is equivalent to the capacitance structure required for controlling the deflection of the liquid crystal. The capacitance between the main electrode pattern 310 and the first electrode layer 311 is divided into two parts: the capacitance between the main electrode pattern 310 and the first electrode layer 311 and the capacitance between the edge of the main electrode pattern 310 and the first electrode layer 311. The total capacitance between the main electrode pattern 310 and the first electrode layer 311 is the sum of the above two capacitances. By adding a first auxiliary electrode pattern 314 next to the main electrode pattern 310, wherein the second auxiliary electrode pattern 313 is electrically connected to the main electrode pattern through a via hole, the distance between the first electrode layer 311 and the main electrode pattern 310 is reduced, thereby reducing the capacitance between the edge of the main electrode pattern 310 and the first electrode layer 311, thereby reducing the charging time of the pixel unit.

[0036] like Figure 4 for Figure 3 Schematic diagram of the top planar structure of a unit pixel unit. In this embodiment, a first auxiliary electrode pattern 414 is newly added next to the main electrode pattern 410 and overlapped with the first electrode layer 411 through the second auxiliary electrode pattern 413. The main electrode pattern 410 overlaps the main electrode pattern 410 and the first electrode layer 411. The auxiliary electrode pattern and the main electrode pattern are formed through the same manufacturing process, and the components are both indium tin oxide. The auxiliary electrode pattern 423 is inserted between the first electrode layer 411 and the top transparent 410, so as to achieve the purpose of reducing the capacitance between the main electrode pattern 410 and the first electrode layer 411 and reducing the charging time of the pixel unit. Preferably, in this embodiment, a flat layer hole 415 can also be set next to the first electrode layer 411 to facilitate the overlap of the main electrode pattern 410 and the first electrode layer 411.

[0037] Preferably, the main electrode patterns 410 are evenly distributed at one end of the second electrode layer 410 .

[0038] In this embodiment, the pixel sequence may be an OLED (Organic Light-Emitting Diode) array, a QLED (Quantum Dot Light Emitting Diodes) array, or a Micro LED (micro diode) array.

[0039] The beneficial effect is: by adding a new main electrode pattern next to the second electrode layer and overlapping it with the first electrode layer through the auxiliary electrode pattern, the capacitance between the second electrode layer and the first electrode layer is reduced, thereby reducing the charging time of the pixel unit and improving work efficiency.

[0040] In summary, although the present invention has been disclosed as above in terms of preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. An array substrate, characterized in that: The array substrate includes pixel units distributed in an array, and the pixel units include: A first electrode layer is disposed on the glass substrate; a dielectric layer, disposed on a surface of the first electrode layer, comprising at least one first via hole; and a second electrode layer, disposed on a surface of the dielectric layer, the second electrode layer comprising a patterned electrode pattern, the capacitance between the first electrode layer and the second electrode layer being used to control an electric field for liquid crystal deflection, and the first via hole being used to reduce a distance between the first electrode layer and the second electrode layer; The electrode pattern includes a main electrode pattern and an auxiliary electrode pattern located on at least one side of the main electrode pattern, the auxiliary electrode pattern is electrically connected to the first electrode layer through a via hole, and a parallel electric field for driving liquid crystal deflection is formed between the auxiliary electrode pattern and the main electrode pattern; The main electrode pattern and the first electrode layer form an overlapping area and a non-overlapping area, the auxiliary electrode pattern is arranged at intervals with the main electrode pattern corresponding to the non-overlapping area, and the auxiliary electrode pattern is distributed at intervals corresponding to the non-overlapping area; The auxiliary electrode pattern includes a first auxiliary electrode pattern located next to the main electrode pattern and a second auxiliary electrode pattern filled in the via hole, and the second auxiliary electrode pattern is used to connect the first auxiliary electrode pattern and the first electrode layer.

2. The array substrate according to claim 1, wherein: The array substrate also includes thin film transistors distributed in an array. A first via hole is formed on the dielectric layer. The auxiliary electrode pattern is connected to the first electrode layer through the first via hole. The main electrode pattern is connected to the drain of the thin film transistor through the first via hole.

3. The array substrate according to claim 1, wherein: A second via is formed on the first electrode layer. The aperture of the second via is larger than that of the first via, and the second via is nested on the first via corresponding to the overlapping area, so that the main electrode pattern in the first via is insulated from the first electrode layer by the dielectric layer.

4. The array substrate according to claim 1, wherein: The auxiliary electrode pattern and the main electrode pattern are arranged at equal intervals.

5. The array substrate according to claim 1, wherein: The array substrate also includes thin film transistors distributed in an array; The main electrode pattern and the first electrode layer are respectively connected to the metal wires of the thin film transistor to form a voltage difference for driving the liquid crystal to deflect.

6. The array substrate according to claim 1, wherein: The auxiliary electrode pattern and the main electrode pattern are formed through the same manufacturing process, and both are made of indium tin oxide.

7. A liquid crystal display, characterized in that: It comprises an array substrate as claimed in any one of claims 1 to 6.

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