Read and Program Operations in a Memory Device

Abstract

The present invention relates to read and program operations in a memory device. Techniques for a memory device operable to program memory cells in a memory device are described. The memory device may include a plurality of memory cells and a memory controller. The memory controller may receive a data page. The memory controller may split the data page into a group of data segments. The memory controller may program the group of data segments into the memory cells associated with an inhibit tile group (ITG) among the plurality of memory cells. The group of data segments for the data page may be programmed using all bits included in each of the memory cells associated with the ITG.

Description

Background Art

[0001] Memory devices are typically provided as internal semiconductor integrated circuits in a computer or other electronic device. There are many different types of memory, including volatile memory (such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM)) and non-volatile memory (such as flash memory).

[0002] Flash memory devices typically use a one-transistor memory cell that allows for high memory density, high reliability, and low power consumption. By programming a charge storage node (such as a floating gate or charge trapping), a change in the threshold voltage of the cell determines the data state of each cell. Other non-volatile memories such as phase change (PRAM) use other physical phenomena such as physical material change or polarization to determine the data state of each cell. Among other things, common uses of flash memory and other solid state memories also include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular phones, and removable portable memory modules. The use of such memories continues to expand. Brief Description of the Drawings

[0003] The features and advantages of embodiments of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate the features of the invention by way of example; and in which:

[0004] Figure 1A and 1B illustrates storing a data page in memory cells of a memory device in accordance with an example embodiment;

[0005] Figure 2A and 2B illustrates storing a data page in memory cells of a memory device in accordance with an example embodiment;

[0006] Figure 3 illustrates a snap read operation in a memory device in accordance with an example embodiment;

[0007] Figure 4A and 4B illustrates read and program operations in a memory device in accordance with an example embodiment;

[0008] Figure 5A and 5B illustrates read and program operations in a memory device in accordance with an example embodiment;

[0009] Figure 6 illustrates a resynchronization circuit in accordance with an example embodiment;

[0010] Figure 7 Illustrates a resynchronization circuit with word line delay compensation in accordance with an exemplary embodiment;

[0011] Figure 8 Illustrates an operation for programming memory cells in a memory device in accordance with an exemplary embodiment;

[0012] Figure 9 Illustrates an operation for reading data from memory cells in a memory device in accordance with an exemplary embodiment;

[0013] Figure 10 Illustrates an operation for reading data from memory cells in a memory device in accordance with an exemplary embodiment;

[0014] Figure 11 Illustrates a memory device in accordance with an example;

[0015] Figure 12 Illustrates a memory system diagram in accordance with an exemplary embodiment; and

[0016] Figure 13 Illustrates a computing system including a data storage device in accordance with an exemplary embodiment.

[0017] Reference will now be made to the illustrated exemplary embodiments, and specific language will be used herein to describe the exemplary embodiments. However, it will be understood that no limitation of the scope of the invention is thereby intended. Detailed Description

[0018] Before describing embodiments of the disclosed invention, it is to be understood that the present disclosure is not limited to the specific structures, process steps, or materials disclosed herein, but extends to their equivalents as would be recognized by one of ordinary skill in the relevant art. It should also be understood that the terminology used herein is for the purpose of describing particular examples or embodiments only and is not intended to be limiting. Like reference numerals in different figures represent the same elements. The numbers provided in the flowcharts and processes are provided for clarity in illustrating steps and operations and do not necessarily indicate a particular order or sequence.

[0019] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of layouts, distances, network examples, etc., to provide a thorough understanding of the various inventive embodiments. However, those skilled in the relevant art will recognize that such detailed embodiments do not limit the overall inventive concept clearly expressed herein, but are merely representative thereof.

[0020] As used in this written description, the singular forms "a", "an" and "the" include expressions that support plural referents, unless the context clearly indicates otherwise. Thus, for example, a reference to "a bit line" includes a plurality of such bit lines.

[0021] References to "examples" throughout this specification mean that a particular feature, structure, or characteristic described in connection with the examples is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in an example" or "in an embodiment" throughout the specification in various places are not necessarily referring to the same embodiment.

[0022] As used herein, for convenience, a plurality of items, structural elements, constituent elements, and / or materials may be presented in a common list. However, these lists should be construed as: although each member of the list is individually identified as a separate and unique member. Thus, in the absence of contrary indication, the individual members of such a list should not be construed as actual equivalents of any other member of the same list solely based on their presentation in the common group. Additionally, various embodiments and examples may be referred to herein in conjunction with alternatives for their various components. It is to be understood that such embodiments, examples, and alternatives should not be construed as actual equivalents of one another, but rather as separate and autonomous representations in accordance with the present disclosure.

[0023] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided, such as examples of layouts, distances, network examples, etc., to provide a thorough understanding of the embodiments of the invention. However, those skilled in the relevant art will recognize that the technology may be practiced without one or more of the specific details or with other methods, components, layouts, etc. In other instances, well-known structures, materials, or operations may not be shown or described in detail to avoid obscuring aspects of the present disclosure.

[0024] In the present disclosure, terms such as "comprising", "containing", "including", and "having" may have the meanings ascribed to them in United States patent law and may mean "including", "containing", etc., and are generally construed as open-ended terms. The term "consisting of" or "consisting essentially of" is a closed-ended term and includes only the components, structures, steps, etc. specifically listed in conjunction with such terms, and that in accordance with United States patent law. "Consisting essentially of" has the meaning generally ascribed to it by United States patent law. In particular, such terms are generally closed-ended terms, except for allowing the inclusion of additional items, materials, components, steps, or elements that do not substantially affect the basic and novel characteristics or functions of the item(s) used in conjunction therewith. For example, trace elements present in a composition but not affecting the properties or characteristics of the composition would be permissible if present under "consisting essentially of" language, even if not explicitly recited in the list of items following such term. When open-ended terms (such as "containing" or "including") are used in this written description, it should be understood that direct support should also be provided to "consisting essentially of" language as well as "consisting of" language as if explicitly stated, and vice versa.

[0025] If at all, the terms "first", "second", "third", "fourth", etc. in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a particular sequential or chronological order. It is to be understood that any such terms are interchangeable under appropriate circumstances such that the embodiments described herein, for example, can be operated in an order different from the order illustrated or otherwise described herein. Similarly, if a method is described herein as including a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps can be performed, and some of the recited steps may perhaps be omitted and / or some other steps not described herein may perhaps be added to the method.

[0026] As used herein, comparative terms such as "increased", "decreased", "better", "worse", "higher", "lower", "enhanced", etc. refer to an attribute of a device, component, or activity that is measurably different from other devices, components, or activities in the surrounding or adjacent area, in a single device or multiple comparable devices, in a group or class, in multiple groups or classes, or compared to a known prior art level. For example, a data region having an "increased" risk of corruption may refer to a region of a memory device that is more likely to have been written to incorrectly than other regions in the same memory device. Many factors can cause such an increased risk, including location, manufacturing process, the number of program pulses applied to the region, etc.

[0027] As used herein, the term "substantially" refers to the full or nearly full extent or degree of an action, characteristic, property, state, structure, item, or result. For example, a "substantially" enclosed object will mean that the object is either fully enclosed or nearly fully enclosed. The exact allowable degree of deviation from absolute completeness may in some cases depend on the specific context. However, in general, the proximity of completion will result in the same overall outcome as if absolute and total completion had been achieved. The use of "substantially" is equally applicable when used in a negative sense to refer to the complete or near-complete lack of an action, characteristic, property, state, structure, item, or result. For example, a composition "substantially free" of particles will either completely lack particles or so nearly lack particles that the effect will be as if it completely lacks particles. In other words, a composition that is "substantially free" of a component or element may actually still contain such an item as long as there is no measurable effect.

[0028] As used herein, the term "about" is used to provide flexibility to a numerical range endpoint by assuming that a given value may be "slightly higher" or "slightly lower" than the endpoint. However, it is to be understood that even when the term "about" is used in conjunction with a specific numerical value in this specification, support is provided for the exact numerical value recited apart from the "about" term.

[0029] Numerical quantities and data may be expressed or presented herein in a range format. It is to be understood that such range format is used merely for convenience and brevity and should therefore be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also all the individual numerical values or sub-ranges contained within that range as if each numerical value and sub-range were explicitly recited. By way of illustration, a numerical range of "about 1 to about 5" should be interpreted to include not only the explicitly recited values of about 1 to about 5, but also the individual values and sub-ranges within the indicated range. Thus, the individual values (such as 2, 3, and 4) and sub-ranges (such as from 1 - 3, from 2 - 4, and from 3 - 5, etc.) as well as 1, 1.5, 2, 2.3, 3, 3.8, 4, 4.6, 5, and 5.1 are each included within the numerical range.

[0030] The same principle applies to ranges that recite only one numerical value as a minimum or a maximum. Additionally, such an interpretation should apply regardless of the width of the range or the nature of the characteristic being described.

[0031] Example embodiments

[0032] An initial overview of the technical embodiments is provided below and then the specific embodiments are described in further detail later. This initial summary is intended to help the reader understand the technology more quickly, but is not intended to identify key or essential technical features, nor is it intended to limit the scope of the claimed subject matter. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0033] In one example, a memory device may utilize non-volatile memory. Non-volatile memory is a storage medium that does not require power to maintain the state of the data stored in the medium. Non-limiting examples of non-volatile memory may include solid-state memory (such as planar or three-dimensional (3D) NAND flash memory, NOR flash memory, etc.), cross-point array memory including 3D cross-point memory, phase change memory (PCM) (such as chalcogenide PCM), non-volatile dual in-line memory module (NVDIMM), byte-addressable non-volatile memory, ferroelectric memory (FeRAM), silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM), spin transfer torque (STT) memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), magnetic storage memory, magnetoresistive random access memory (MRAM), write-in-place non-volatile MRAM (NVMRAM), nanotube RAM (NRAM), etc., or any combination thereof. In some examples, the non-volatile memory may comply with one or more standards promulgated by the Joint Electron Device Engineering Council (JEDEC), such as JESD218, JESD219, JESD220-1, JESD223B, JESD223-1, or other suitable standards (the JEDEC standards cited herein are available at www.jedec.org). In one specific example, the memory device 100 may utilize 3D cross-point memory. In another specific example, the system memory may be STT memory.

[0034] In one example, the memory device may be a NAND flash memory device including a plurality of memory cells. The memory cells may be single-level cells (SLCs) having 1 bit per cell. The memory cells may be multi-level cells (MLCs) having 2 bits per cell. The memory cells may be triple-level cells (TLCs) having 3 bits per cell. Alternatively, the memory cells may be quad-level cells (QLCs) having 4 bits per cell.

[0035] In one example, a memory device may include a plurality of memory cells, each memory cell attached to a floating gate transistor design. For example, in a given memory cell, electricity can flow through the transistor, and the transistor can be connected to a source, a drain, and a floating gate. With the help of the floating gate, electricity can flow from the source to the drain. For example, electricity can flow when the floating gate is closed, but does not flow when the floating gate is open. The state of the floating gate can be changed by a specific process and can continue to stay in that state, i.e., non-volatile, until the floating gate is changed by another specific process (and then also stays in that re-changed state). The transistor may have a second gate above the floating gate, which is called a control gate. A gate oxide layer can be between the control gate and the floating gate, and a tunnel oxide layer can be between the floating gate and the source and the drain. When the floating gate is closed, electricity can pass between the source and the drain, and this charged state can record the binary value 0. When the floating gate is open, electricity does not pass between the source and the drain, and this uncharged state can record the binary value 1. In other words, depending on whether electricity can or cannot flow between the source and the drain, the memory cell can be programmed with the binary value 0 or the binary value 1.

[0036] In one example, a memory device may include a plurality of memory cells. The memory cells can be an array of columns and rows. The columns of the memory cells can be called bit lines, and the rows of the memory cells can be called word lines. In one example, for a given memory cell, when a relatively high voltage (e.g., 18 volts) is applied to the control gate through the word line and a lower ground voltage is applied to the drain through the bit line, then a strong electric field of electrons can be established. Since electricity cannot flow from the source to the drain, the floating gate is thus charged (i.e., the floating gate is now closed), and the memory cell records the binary value 0. The memory cell may have a certain threshold voltage, such as 1 volt or higher. To reverse the process, a relatively high voltage (e.g., 20 volts) can be applied to the drain through the bit line, and a lower ground voltage can be applied to the control gate through the word line, and a strong reverse electric field of electrons can be established. As electricity can flow from the source to the drain, the floating gate is now open, and the memory cell records the binary value 1. The memory cell now has a certain threshold voltage, such as -3 volts or lower.

[0037] In one example, reading a memory cell can involve measuring the flow of electricity between a source and a drain. The voltage threshold above which current will flow between the source and the drain can vary with the state of the floating gate. A reference or read-point voltage can be applied across the source and the drain, and the current can be tested. If the current is at a certain level, this indicates the binary value 1, and if the current is not at that certain level, this indicates the binary value 0. In other words, the current can be measured to determine whether there is a current flow state.

[0038] For SLC, the binary values are 0 or 1, which indicate 2 states and thus one threshold voltage. For MLC, the binary values are 00, 10, 01, or 11, which indicate 4 states and thus 3 threshold voltages. For TLC, the binary values are 000, 001, 010, 011, 100, 101, 110, or 111, which indicate 8 states and thus 7 threshold voltages. For QLC, the binary values are 0000, 0001, 0010, 0011, 0100, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, or 1111, which indicate 16 states and 15 threshold voltages. Each binary value can have a different threshold voltage. For example, the lowest binary value can have the highest threshold voltage, the highest binary value can have the lowest threshold voltage, and the intermediate binary values can have progressively different threshold voltages. In one example, for QLC, the binary value 0000 has the highest threshold voltage, the binary value 0001 has a lower threshold voltage, the binary value 0010 has the next lower threshold voltage, and so on until the binary value 1111, which has the lowest threshold voltage.

[0039] In one example, when a memory cell is being programmed, the threshold voltage can be set. For a read operation, threshold voltage tests between state groups can be consecutively applied using different threshold voltages. For example, with respect to MLC, a first threshold voltage test can indicate whether the binary value of the memory cell is either (00 or 01) or (10 or 11), and additional tests with modified threshold voltages can be performed to determine the specific binary value. For TLC, a first threshold voltage test can obtain 4 possible binary values, a second threshold voltage test can further obtain 2 possible binary values, and a third threshold voltage test can reveal the actual binary value. For QLC, a first threshold voltage test can obtain 16 possible binary values, a second threshold voltage test can further obtain 8 possible binary values, a third threshold voltage test can obtain 4 possible binary values, a fourth threshold voltage test can obtain 2 possible binary values, and a fifth threshold voltage test can reveal the actual binary value. Thus, reading a memory cell configured with QLC may take a longer period of time compared to reading a memory cell configured with TLC, MLC, or SLC. Similarly, programming and erasing a memory cell configured with QLC may take a longer period of time compared to programming and erasing a memory cell configured with TLC, MLC, or SLC. Additionally, as progression is made from SLC to MLC to SLC and QLC, the overall voltage range used in NAND cell operations has not been adjusted, and thus the reference voltage setting and the accuracy of the resulting current measurements have become more refined in response to the increase in the cell bit content.

[0040] In one example, a read operation for a memory cell can be performed by applying a voltage ramp to the control gate of the memory cell to establish a level at which the programmed memory cell enters a conductive state. The voltage ramp can be generated on a word line in an array of memory cells to read the memory cells associated with the word line.

[0041] In one example, a NAND flash memory cell can include a floating gate, a control gate, a drain, and a source. The memory cell can be set (or programmed) and reset (or erased) by applying charge to or removing charge from the floating gate. Charge can be applied to or removed from the floating gate of the memory cell via Fowler-Nordheim (FN) current tunneling or via hot carrier injection (HCI). FN tunneling and HCI are useful for programming and erasing flash memory, but also make the flash memory cell have a limited lifetime. When charge is applied to or removed from the floating gate, the threshold voltage (VT) of the underlying transistor changes, thereby allowing the flash memory cell to be used as a memory storage device. Additionally, after charge is injected into or removed from the floating gate, the floating gate remains in that state even after power is removed, making the flash memory cell non-volatile.

[0042] Figure 1A Illustrated is an exemplary technique for storing a data page into memory cells of a memory device. The memory device can include multiple planes of memory cells (e.g., plane 0, plane 1, plane 2, and plane 3), and the memory cells can support QLC. Each plane can include multiple inhibit tile groups (ITGs). Each ITG can include multiple memory cells. In this specific example, each plane can include 4 ITGs, and each ITG can have a storage capacity of 4 kilobytes (KB). In one example, a data page (16KB) can be allocated by spreading the bits of the data page across multiple ITGs (e.g., 4 ITGs). The data page can be allocated to a word line using only one bit per memory cell (even though a memory cell supporting QLC can store 4 bits per cell). In this example, the block size for storing the data page across the multiple ITGs can be represented as 1.

[0043] Figure 1BIllustrates an exemplary technique for storing data pages into memory cells of a memory device. The memory device may include multiple planes of memory cells (e.g., plane 0, plane 1, plane 2, and plane 3), and the memory cells may support QLC. Each plane may include multiple inhibit tile groups (ITGs). In this specific example, each plane may include 4 ITGs, and each ITG may have a storage capacity of 4 kilobytes (KB). In one example, a data page (16 KB) may be allocated by storing bits of the data page into a single ITG. The data page may be allocated to a word line using all four bits of each memory cell. This scheme may utilize compression through input / output (I / O) to use all bits of each memory cell in a single ITG. The 4 KB capacity of the ITG and 4 bits per cell may allow for a 16 KB page size. In this example, the block size for storing a data page in a single ITG may be represented as ¼, since the block size for storing a data page across multiple ITGs (as Figure 1A shown) may be represented as 1. By storing the page in a single ITG (as opposed to multiple ITGs) and having a reduced block size of ¼, a reduced number of tiles may be occupied during read and program operations, which may deliver improved performance during read and program operations. For example, the improved performance of the program operation may be due to faster verify operations enabled by the available reduced block size.

[0044] In one example, in Figure 1A , the same bits in different data pages may be stored into the same memory cell, which results in an increased number of ITGs for storing data pages. In other words, the bits of the same data page may be spread across multiple memory cells. On the other hand, in Figure 1B , compression through the I / O concept is shown, where the bits of the same data page may be stored into the same memory cell, thereby resulting in a reduced number of ITGs for storing data pages. The reduced number of ITGs may result in a reduced number of tiles being occupied during read and program operations, which may improve the performance of read and program operations.

[0045] Figure 2AIllustrates an exemplary technique for storing data pages into memory cells of a memory device. The memory device may include multiple planes of memory cells (e.g., plane 0, plane 1, plane 2, and plane 3), and the memory cells may support QLC and SLC. Each plane may include multiple inhibited tile groups (ITGs). In this specific example, each plane may include 4 ITGs, and each ITG may have a storage capacity of 4 kilobytes (KB). In one example, a data page (16KB) may be allocated by storing bits of the data page into multiple ITGs (e.g., 4 ITGs) using QLC or SLC. In this example, a data page may be allocated to a word line using all possible bits of each memory cell (e.g., 1 bit for SLC or 4 bits for QLC). This scheme may utilize compression through input / output (I / O) to store a data page using all possible bits of each memory cell in the multiple ITGs. In other words, in this scheme, bits of the same data page may be stored into the same memory cell.

[0046] Figure 2B Illustrates an exemplary technique for storing data pages into memory cells of a memory device. The memory device may include multiple planes of memory cells (e.g., plane 0, plane 1, plane 2, and plane 3), and the memory cells may support QLC and SLC. Each plane may include multiple inhibited tile groups (ITGs). In this specific example, each plane may include 4 ITGs, and each ITG may have a storage capacity of 4 kilobytes (KB). In one example, a data page (16KB) may be allocated by storing bits of the data page into multiple ITGs (e.g., 4 ITGs) using SLC, or a data page (16KB) may be allocated by storing bits of the data page into a single ITG using QLC. In this example, a data page may be allocated to a word line using all possible bits of each memory cell (e.g., 1 bit for SLC or 4 bits for QLC). This scheme may utilize compression through input / output (I / O) to store a data page using all possible bits of each memory cell in the multiple ITGs. In other words, in this scheme, bits of the same data page may be stored into the same memory cell.

[0047] In one example, the read and verify operations can be implemented using word line ramp sensing. Compared to word line staircase sensing, word line ramp sensing may be more efficient but more complex. With ramp sensing, the word lines of the memory array can ramp up linearly, and the sensing operation can be performed while the word lines are ramping up continuously. In this case, during the sensing operation, the bit lines of the memory array can be sensed while the word lines are ramping up, and then the result (based on the sensed level) can be transferred to a data latch. In conventional word line staircase sensing, the bit lines of the memory array can be precharged to a specific voltage level (e.g., the read voltage level) first, and then the bit lines can be sensed while the word lines are held at that specific voltage level. In this case, the word lines can first stay at that specific voltage level before the sensing operation, and then the sensing operation can be performed while the word lines are held at that specific voltage level.

[0048] In one configuration, in an architecture that supports compression via I / O (i.e., where bits of the same data page can be stored into the same memory cell, resulting in a reduced number of ITGs for storing data pages), an increased ramp rate for word line ramp sensing is desirable. More specifically, the increased ramp rate can be achieved by using word line ramp reads with two separate word line ramps. For example, data can be read from a memory cell using a first word line ramp read and a second word line ramp read. The first word line ramp read can utilize masked bit line even sensing for reading certain data segments, and the second word line ramp read can utilize masked bit line odd sensing for reading certain data segments. Alternatively, the first word line ramp read can utilize masked bit line odd sensing for reading certain data segments, and the second word line ramp read can utilize masked bit line even sensing for reading certain data segments. Two separate word line ramp reads (e.g., masked bit line odd and even sensing) can be utilized with an architecture that supports compression via an I / O data allocation scheme. Using two separate word line ramp reads can improve system performance. When a page is compressed via I / O, a page can be allocated to one word line using all the bits included in each of the memory cells associated with the ITG. In other words, the memory cells do not include bits from different data pages. Instead, bits of the same data page are programmed into the same memory cell.

[0049] In one example, a counter that generates an 8-bit value can be used to perform a word line ramp read, and the 8-bit value can increase from 0 to 256. Each of these values can be one of 256 possible values between the minimum cell voltage (Vt) and the maximum cell Vt in the range to be detected. As an example, for a minimum Vt = 1 and a maximum Vt = 6, there is a digital representation of Vt in steps of ~27 mV. This value can be converted in the -1, 6 V range using a digital-to-analog converter (DAC) and sent to the word line. In parallel, this value can be run across eight latches of a page buffer. When a cell is turned on from the word line value, the corresponding digital value running at the top of the page buffer can be stored in the corresponding latch. Depending on the word line resynchronization circuit, a set of initial values and a set of final values over the entire range can now be used in this conversion, such that no non-linearity on the word line is used. At each of the 256 steps, a sensing phase can be performed inside the page buffer. However, this method for ramp sensing does not work for all bit line (ABL) sensing, where all bit lines are sensed simultaneously. Thus, a shielded bit line (SBL) method can be employed, where the even bit lines can be grounded when the odd bit lines are being sensed, or the odd bit lines can be grounded when the even bit lines are being sensed.

[0050] Figure 3 Illustrated is an exemplary burst read operation in a memory device. The memory device can include multiple planes of memory cells (e.g., plane 0, plane 1, plane 2, and plane 3), and the memory cells can support QLC. Each plane can include multiple inhibited tile groups (ITG). In this specific example, each plane can include 4 ITGs, and each ITG can have a storage capacity of 4 kilobytes (KB). A data page (16 KB) can be allocated by storing the bits of the data page to a single ITG using QLC. In this example, a data page can be allocated to one word line using all possible bits of each memory cell (e.g., 4 bits for QLC). This scheme can store a data page by taking advantage of compression through input / output (I / O) to use all possible bits of each memory cell in a single ITG. In other words, in this scheme, the bits of the same data page can be stored in the same memory cell.

[0051] In one example, a burst read operation can involve reading 8KB of data out of a 16KB data page in a relatively fast manner. The burst read operation can be implemented using one of two separate word line ramp reads. For example, a first word line ramp read can be used to read 8KB out of a 16KB data page, or a second word line ramp read can be used to read the other 8KB out of a 16KB data page. In this example, the first word line ramp read can utilize masked bit line odd sensing, and the second word line ramp read can utilize masked bit line even sensing. In this case, the burst read can be implemented by 8KB on the odd bit lines and 8KB on the even bit lines. Thus, a relatively fast burst read operation can be achieved for reading 8KB of data out of a 16KB data page.

[0052] Figure 4A Illustrated is an exemplary technique for reading a data page from memory cells of a memory device. The memory device can include multiple planes of memory cells (e.g., plane 0, plane 1, plane 2, and plane 3), and the memory cells can support QLC. Each plane can include multiple inhibit tile groups (ITGs). In this specific example, each plane can include 4 ITGs, and each ITG can have a storage capacity of 4 kilobytes (KB). In one example, the data page may have been previously allocated by spreading the bits of the data page (16KB) across multiple ITGs (e.g., 4 ITGs), and thus the data page can be read by extracting the bits of the data page across the multiple ITGs (e.g., 4 ITGs). For example, the data page may have been previously allocated to a word line using only one bit per memory cell (even though a memory cell supporting QLC can store 4 bits per cell), and thus the data page can be read by extracting that one bit of the data page from each of the memory cells in the multiple ITGs. By extracting one bit of the data page from each of the memory cells in the multiple ITGs, a 16KB data page can be read.

[0053] Figure 4BIllustrated is an exemplary technique for programming a data page into memory cells of a memory device. The memory device may include multiple planes of memory cells (e.g., plane 0, plane 1, plane 2, and plane 3), and the memory cells may support QLC. Each plane may include multiple inhibit tile groups (ITGs). In this specific example, each plane may include 4 ITGs, and each ITG may have a storage capacity of 4 kilobytes (KB). In one example, a data page (16KB) may be allocated by spreading the bits of the data page across multiple ITGs (e.g., 4 ITGs). A data page may be allocated to a word line using only one bit of each memory cell (even though a memory cell supporting QLC may store 4 bits per cell). By allocating this one bit of the data page to each of the memory cells in the multiple ITGs, a 16KB data page may be programmed into the memory cells in the multiple ITGs. In one example, three additional 16KB data pages may also be programmed into the memory cells in the multiple ITGs using the three remaining bits in each of the memory cells.

[0054] As Figure 4A and 4B shown, the same bit in different data pages may be read from the same memory cell, and the same bit in different data pages may be stored into the same memory cell respectively, which may result in an increased number of ITGs for reading data pages from and programming data pages into memory cells.

[0055] Figure 5AIllustrated is an exemplary technique for reading a data page from a memory cell of a memory device. The memory device may include multiple planes of memory cells (e.g., plane 0, plane 1, plane 2, and plane 3), and the memory cells may support QLC. Each plane may include multiple inhibit tile groups (ITGs). In this specific example, each plane may include 4 ITGs, and each ITG may have a storage capacity of 4 kilobytes (KB). In one example, the data page may have been previously allocated by storing the bits of the data page (16KB) into a single ITG, and thus the data page can be read by extracting the bits of the data page from that single ITG. For example, the data page may have been previously allocated to a word line using all four bits of each memory cell, and thus the data page can be read by extracting all four bits of the data page from each of the memory cells in that single ITG. By extracting the 4 bits of the data page from each of the memory cells in that single ITG, a 16KB data page can be read. This scheme can utilize compression through input / output (I / O) to use all the bits of each memory cell in a single ITG. By storing the data page in a single ITG (as opposed to multiple ITGs), a reduced number of tiles can be occupied during a read operation, which can deliver improved performance during the read operation.

[0056] As a non-limiting example, the memory device may support an 8KB burst read operation, a 16KB single ITG (1-ITG) read operation, a 64KB four-ITG (4-ITG) read operation, or a 256KB (16KB x 4 x 4) ITG read operation.

[0057] Figure 5B Illustrated is an exemplary technique for programming a data page into a memory cell of a memory device. The memory device may include multiple planes of memory cells (e.g., plane 0, plane 1, plane 2, and plane 3), and the memory cells may support QLC. Each plane may include multiple inhibit tile groups (ITGs). In this specific example, each plane may include 4 ITGs, and each ITG may have a storage capacity of 4 kilobytes (KB). In one example, the data page can be allocated by storing the bits of the data page (16KB) into a single ITG. For example, the data page can be allocated to a word line using all four bits of each memory cell in a single ITG. By allocating 4 bits of the data page to each of the memory cells in a single ITG, a 16KB data page can be programmed. This scheme can utilize compression through input / output (I / O) to use all the bits of each memory cell in a single ITG. By storing the data page in a single ITG (as opposed to multiple ITGs), a reduced number of tiles can be occupied during a programming operation, which can deliver improved performance during the programming operation.

[0058] As Figure 5A and 5B shown, compression through I / O technology can be utilized, where bits of the same data page can be read from the same memory cell and bits of the same data page can be stored into the same memory cell, which can result in a reduced number of ITGs for reading data pages from memory cells and programming data pages into memory cells.

[0059] As a non-limiting example, the memory device can support 16KB single-ITG (1-ITG) programming operations, 64KB quad-ITG (4-ITG) programming operations, or 256KB (16KB x 4 x 4) ITG programming operations.

[0060] Figure 6 An exemplary resynchronization circuit is illustrated. The resynchronization circuit can include a counter, a word line digital-to-analog converter (WLDAC), a digital-to-analog converter (DAC), and a page buffer digital-to-analog converter (PBDAC). The DAC can be connected to a word line (WL). The word line can intersect with a plurality of bit lines (BL), and each bit line can be connected to a separate page buffer. In one example, there may be a mismatch between the word line and the page buffer voltage threshold (Vth) value (PBDAC), and reducing this mismatch can allow for a more efficient use of the voltage threshold (Vth) window. The word line resynchronization circuit can cause a delay in the ramp along the word line itself, and unless a compensation technique is employed, this word line delay can result in a widened read voltage threshold (Vth) window.

[0061] Figure 7 An example of a resynchronization circuit with word line delay compensation is illustrated. The mismatch between the word line and the page buffer voltage threshold (Vth) value can more efficiently cause an efficient use of the voltage threshold (Vth) window, and it is desirable to reduce this mismatch. In other words, the word line resynchronization circuit can cause a delay in the ramp along the word line itself, and this word line delay can result in a widened read voltage threshold (Vth) window. To address this issue, a compensation technique using 4-level matching is employed. For example, the word line can be divided into four slices, and four digital comparators can be placed to recalculate the gap, thereby mitigating the widening of the read voltage threshold (Vth) window.

[0062] Figure 8Illustrated are exemplary operations for programming memory cells in a memory device using a memory controller in the memory device. The memory controller may receive a data page, as in block 810. The memory controller may split the data page into a group of data segments, as in block 820. The memory controller may program the group of data segments into the memory cells associated with an inhibit tile group (ITG) in the plurality of memory cells, as in block 830. The group of data segments for the data page may be programmed using all bits included in each of the memory cells associated with the ITG.

[0063] Figure 9 Illustrated are exemplary operations for reading data from memory cells in a memory device using a memory controller in the memory device. The memory controller may read a group of data segments from the memory cells associated with an inhibit tile group (ITG) in the plurality of memory cells, as in block 910. The group of data segments may have been previously programmed into the memory cells associated with the ITG using all bits included in each of the memory cells. The memory controller may combine the group of data segments to form a data page, as in block 920.

[0064] Figure 10 Illustrated are exemplary operations for reading data from memory cells in a memory device using a memory controller in the memory device. The memory controller may read a first data segment from a memory cell in the plurality of memory cells using a first word line ramp, as in block 1010. The memory controller may read a second data segment from the memory cell using a second word line ramp, as in block 1020. The memory cell may be associated with an inhibit tile group (ITG). The first data segment and the second data segment may form a data page that was previously programmed using all bits included in each of the memory cells associated with the ITG.

[0065] Figure 11FIG. illustrates an exemplary memory device 1100. The memory device may include a plurality of memory cells 1110 and a memory controller 1120. In one configuration, the memory controller 1120 may receive a data page; split the data page into a group of data segments; and program the group of data segments into the memory cells 1110 associated with an inhibit tile group (ITG) among the plurality of memory cells 1110, where the group of data segments for the data page is programmed using all bits included in each of the memory cells 1110 associated with the ITG. In another configuration, the memory controller 1120 may read a group of data segments from the memory cells 1110 associated with an inhibit tile group (ITG) among the plurality of memory cells 1110, where the group of data segments was previously programmed into the memory cells 1110 using all bits included in each of the memory cells 1110 associated with the ITG; and combine the group of data segments to form a data page. In yet another configuration, the memory controller 1120 may read a first data segment from the memory cells 1110 among the plurality of memory cells 1110 using a first word line ramp; and read a second data segment from the memory cells 1110 using a second word line ramp, where the memory cells 1110 are associated with an inhibit tile group (ITG), and where the first data segment and the second data segment form a data page that was previously programmed using all bits included in each of the memory cells 1110 associated with the ITG.

[0066] Figure 12 is a simplified block diagram of a memory device 1200 according to an embodiment of the invention and can practice various methods in connection therewith. The memory device 1200 includes an array 1204 of memory cells arranged in rows and columns. Although various embodiments will be described primarily with reference to a NAND memory array, the various embodiments are not limited to the specific architecture of the memory array 1204. Some examples of other array architectures suitable for embodiments of the present invention include NOR arrays, AND arrays, and virtual ground arrays. However, in general, the embodiments described herein can be adapted to any array architecture that allows generation of a data signal indicative of the threshold voltage of each memory cell.

[0067] A row decoding circuit 1208 and a column decoding circuit 1210 are provided to decode the address signals supplied to the memory device 1200. The address signals are received and decoded to access the memory array 1204. The memory device 1200 further includes an input / output (I / O) control circuit 1212 for managing the input of commands, addresses, and data to the memory device 1200 and the output of data and status information from the memory device 1200. An address register 1214 is coupled between the I / O control circuit 1212 and the row decoder circuit 1208 and the column decoding circuit 1210 for latching the address signals before decoding. A command register 1224 is coupled between the I / O control circuit 1212 and the control logic 1216 for latching incoming commands. The control logic 1216 controls the access to the memory array 1204 in response to the commands and generates status information for an external processor 1230 (also referred to as the memory controller as described earlier). The control logic 1216 is coupled to the row decoding circuit 1208 and the column decoding circuit 1210 for controlling the row decoding circuit 1208 and the column decoding circuit 1210 in response to the addresses.

[0068] The control logic 1216 may be coupled to a sample and hold circuit 1218. The sample and hold circuit 1218 latches either incoming or outgoing data in the form of analog data signals. For example, the sample and hold circuit may include a capacitor or other analog storage device for sampling either an incoming data signal representing data to be written to the memory cells or an outgoing data signal indicating a threshold voltage sensed from the memory cells. The sample and hold circuit 1218 may further provide amplification and / or buffering of the sampled signal to provide a stronger data signal to an external device.

[0069] The processing of the analog data signals may take a method in which the generated charge levels are stored on a capacitor. In response to a data signal causing the capacitor to be subjected to the actual or target threshold voltage of the memory cells indicating reading or programming of the memory cells respectively, charge may be stored on the capacitor. The charge may then be converted into an analog data signal using a differential amplifier having a ground input or other reference signal as a second input. The output of the differential amplifier may then be passed to the I / O control circuit 1212 for output from the memory device in the case of a read operation or for use in comparison during one or more verification operations when programming the memory device. It should be noted that the I / O control circuit 1212 may optionally include analog-to-digital conversion functionality and digital-to-analog conversion (DAC) functionality to convert the read data from the analog data signal into a digital bit pattern and convert the written data from the digital bit pattern into an analog signal so that the memory device 1200 can be adapted for communication with either an analog or digital data interface.

[0070] During a programming operation, a target memory cell of the memory array 1204 is programmed until the voltage indicating its Vt level matches the level held in the sample and hold circuit 1218. As an example, this can be accomplished using a differential sensing device to compare the held voltage level with the threshold voltage of the target memory cell. Much like traditional memory programming, programming pulses can be applied to the target memory cell to increase its threshold voltage until the desired value is reached or exceeded. In a read operation, the Vt level of the target memory cell is passed to the sample and hold circuit 1218 for transmission to an external processor (not shown in Figure 12 ), either directly as an analog signal or as a digital representation of the analog signal, depending on whether ADC / DAC functionality is provided external to or within the memory device.

[0071] The threshold voltage of a cell can be determined in a variety of ways. For example, the voltage of an access line (such as those commonly referred to as word lines) can be sampled when the target memory cell becomes active. Alternatively, an elevated voltage can be applied to the first source / drain side of the target memory cell, and the threshold voltage can be considered the difference between its control gate voltage and the voltage at its other source / drain side. By coupling a voltage to a capacitor, charge will be shared with the capacitor to store the sampled voltage. Note that the sampled voltage does not need to be equal to the threshold voltage, but only indicates that voltage. For example, in the case where an elevated voltage is applied to the first source / drain side of a memory cell and a known voltage is applied to its control gate, the voltage developed at the second source / drain side of the memory cell can be considered a data signal since the developed voltage indicates the threshold voltage of the memory cell.

[0072] The sample and hold circuit 1218 can include a cache, i.e., multiple storage locations for each data value, such that the memory device 1200 can read the next data value while transferring the first data value to an external processor, or receive the next data value while writing the first data value to the memory array 1204. A status register 1222 is coupled between the I / O control circuit 1212 and the control logic 1216 to latch status information for output to an external processor.

[0073] The memory device 1200 receives control signals at the control logic 1216 via a control link 1232. The control signals can include chip enable CE#, command latch enable CLE, address latch enable ALE, and write enable WE#. The memory device 1200 can receive commands (in the form of command signals), addresses (in the form of address signals), and data (in the form of data signals) from an external processor via a multiplexed input / output (I / O) bus 1234 and output data to the external processor via the I / O bus 1234.

[0074] In a specific example, commands are received at the I / O control circuit 1212 via the input / output (I / O) pins [7:0] of the I / O bus 1234 and written into the command register 1224. Addresses are received at the I / O control circuit 1212 via the input / output (I / O) pins [7:0] of the bus 1234 and written into the address register 1214. Data can be received at the I / O control circuit 1212 via the input / output (I / O) pins [7:0] of a device capable of receiving eight parallel signals or the input / output (I / O) pins [15:0] of a device capable of receiving sixteen parallel signals and transmitted to the sample and hold circuit 1218. Data can also be output via the input / output (I / O) pins [7:0] of a device capable of transmitting eight parallel signals or the input / output (I / O) pins [15:0] of a device capable of transmitting sixteen parallel signals. Those skilled in the art will appreciate that additional circuits and signals can be provided and the Figure 12 memory device has been simplified to help focus on the embodiments of the present disclosure.

[0075] Although Figure 12 has been described with respect to the sample and hold circuit 1218, it should be understood that the control logic 1216 can be coupled to a data latch instead of the sample and hold circuit 1218 without departing from the scope of the present disclosure. The data latch latches data either incoming or outgoing. During a write operation, for example, the target memory cells of the memory array 1204 are programmed using two sets of programming pulses as described above until the voltage indicating its Vt level matches the data held in the data latch. As an example, this can be achieved using a differential sensing device to compare the held data with the threshold voltage of the target memory cell.

[0076] Additionally, although Figure 12 the memory device has been described in accordance with popular conventions for receiving and outputting various signals, note that the various embodiments are not limited by the specific signals and I / O configurations described. For example, command and address signals can be received at inputs separate from those for receiving data signals, or data signals can be transmitted serially via a single I / O line of the I / O bus 1234. Since the data signal represents a bit pattern rather than individual bits, serial communication of an 8-bit data signal can be as efficient as parallel communication of eight signals representing individual bits.

[0077] Figure 13FIG. illustrates a general computing system or device 1300 that may be employed in the present technology. The computing system 1300 may include a processor 1302 in communication with a memory 1304. The memory 1304 may include any device, combination of devices, circuitry, etc. capable of storing, accessing, organizing, and / or retrieving data. Non-limiting examples include SAN (Storage Area Network), cloud storage network, volatile or non-volatile RAM, phase change memory, optical media, hard drive type media, etc., including combinations thereof.

[0078] The computing system or device 1300 further includes a local communication interface 1306 for connectivity between the various components of the system. For example, the local communication interface 1306 may be a local data bus and / or any associated address or control bus, as may be desired.

[0079] The computing system or device 1300 may also include an I / O (input / output) interface 1308 for controlling the I / O functions of the system and for I / O connectivity to devices external to the computing system 1300. A network interface 1310 may also be included for network connectivity. The network interface 1310 may control network communication both within and external to the system. The network interface may include a wired interface, wireless interface, Bluetooth interface, optical interface, etc., including suitable combinations thereof. Additionally, the computing system 1300 may further include a user interface 1312, a display device 1314, and various other components that would be beneficial to such a system.

[0080] The processor 1302 may be a single or multiple processors, and the memory 1304 may be a single or multiple memories. The local communication interface 1306 may serve as a path to facilitate communication between any of a single processor, multiple processors, single memory, multiple memories, various interfaces, etc. in any useful combination.

[0081] Various technologies or certain aspects or portions thereof may take the form of program code (i.e., instructions) embodied in a tangible medium such as a floppy disk, CD-ROM, hard disk drive, non-transitory computer-readable storage medium, or any other machine-readable storage medium, where when the program code is loaded into a machine such as a computer and executed by the machine, the machine becomes an apparatus for practicing the various technologies. Circuits may include hardware, firmware, program code, executable code, computer instructions, and / or software. A non-transitory computer-readable storage medium may be a computer-readable storage medium that does not include signals. In the case of executing program code on a programmable computer, the computing device may include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. Volatile and non-volatile memory and / or storage elements may be RAM, EPROM, flash drive, optical drive, magnetic hard drive, solid state drive, or other media for storing electronic data. Nodes and wireless devices may also include transceiver modules, counter modules, processing modules, and / or clock modules or timer modules. One or more programs that may implement or utilize the various technologies described herein may use application programming interfaces (APIs), reusable controls, etc. Such programs may be implemented in a high-level procedural programming language or an object-oriented programming language to communicate with a computer system. However, the (multiple) programs may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language and may be combined with a hardware implementation. Exemplary systems or devices may include, but are not limited to, laptop computers, tablet computers, desktop computers, smart phones, computer terminals and servers, storage databases, and other electronic devices that utilize circuits and programmable memory, such as home appliances, smart TVs, digital video disc (DVD) players, heating, ventilation, and air conditioning (HVAC) controllers, light switches, etc.

[0082] Example

[0083] The following examples relate to specific invention embodiments and point out specific features, elements, or steps that may be used or otherwise combined in implementing such embodiments.

[0084] In one example, a system is provided that is operable to program memory cells. The system may include a plurality of memory cells and a memory controller. The memory controller may include logic to receive a data page. The memory controller may include logic to divide the data page into a group of data segments. The memory controller may include logic to program the group of data segments to memory cells associated with an inhibit tile group (ITG) among the plurality of memory cells, wherein the group of data segments for the data page is programmed using all bits included in each of the memory cells associated with the ITG.

[0085] In one example of the system, the memory controller is configured to allocate the data page to a word line using all bits included in each of the memory cells associated with the ITG such that bits on the same data page are stored in the same memory cells.

[0086] In one example of the system, the memory cells do not include data segments from different data pages.

[0087] In one example of the system, the memory controller is configured to program the data page to the memory cells associated with the ITG using compression over input-output (IO), wherein bits of the same data page are stored in the same memory cells.

[0088] In one example of the system, the memory controller is configured to program the data page to the memory cells using the ITG and using all bits included in each of the memory cells associated with the ITG to reduce the block size.

[0089] In one example of the system, the memory controller is configured to program the data page to the memory cells using the ITG and using all bits included in each of the memory cells associated with the ITG to reduce the number of tiles utilized during a programming operation.

[0090] In one example of the system, the ITG supports 4 kilobytes (KB) of data, and the data page is 16 KB, and each data segment is 4 KB, wherein the data page is programmed to the memory cells associated with the ITG using compression over input-output (IO).

[0091] In one example of the system, the memory controller is configured to receive the data page from a processor communicatively coupled to the memory controller.

[0092] In one example of the system, the ITG is a single ITG.

[0093] In one example of the system, the plurality of memory cells includes a plurality of quad-level cells (QLCs), and each of the plurality of quad-level cells (QLCs) supports 4-bit data.

[0094] In one example of the system, the system is a NAND flash memory device.

[0095] In one example, a memory device is provided that is operable to read data from memory cells in a memory device. The memory device may include a plurality of memory cells and a memory controller. The memory controller may include logic for reading a set of data segments from the memory cells associated with an inhibit tile group (ITG) among the plurality of memory cells, wherein all bits included in each of the memory cells associated with the ITG were previously used to program the set of data segments into the memory cells. The memory controller may include logic for combining the set of data segments to form a data page.

[0096] In one example of the memory device, a set of data segments is assigned to a word line using all bits included in each of the memory cells associated with the ITG such that bits on the same data page are stored in the same memory cells and the memory cells do not include data segments from different data pages.

[0097] In one example of the memory device, the ITG was previously used and a set of data segments was programmed into the memory cells using all bits included in each of the memory cells associated with the ITG to reduce the block size.

[0098] In one example of the memory device, the ITG was previously used and a set of data segments was programmed into the memory cells using all bits included in each of the memory cells associated with the ITG to reduce the number of tiles utilized during subsequent read operations.

[0099] In one example of the memory device, a set of data segments was previously programmed into the memory cells associated with the ITG using compression via input-output (IO), wherein bits of the same data page were programmed into the same memory cells.

[0100] In one example of the memory device, the memory controller is configured to provide a data page to a processor communicatively coupled to the memory device.

[0101] In one example of the memory device, the plurality of memory cells includes a plurality of quad-level cells (QLCs), and each of the plurality of quad-level cells (QLCs) supports 4-bit data.

[0102] In one example of the memory device, the memory device is a NAND flash memory device.

[0103] In one example, a memory device is provided that is operable to read data from memory cells in a memory device. The memory device may include a plurality of memory cells and a memory controller. The memory controller may include logic to read a first data segment from a memory cell among the plurality of memory cells using a first word line ramp. The memory controller may include logic to read a second data segment from the memory cell using a second word line ramp, where the memory cell is associated with an inhibit tile group (ITG), and where the first data segment and the second data segment form a data page previously programmed using all bits included in each of the memory cells associated with the ITG.

[0104] In one example of the memory device, the first word line ramp read utilizes masked bit line odd sensing for reading the first data segment, and the second word line ramp read utilizes masked bit line even sensing for reading the second data segment.

[0105] In one example of the memory device, the first word line ramp read utilizes masked bit line even sensing for reading the first data segment, and the second word line ramp read utilizes masked bit line odd sensing for reading the second data segment.

[0106] In one example of the memory device, a data page is assigned to one word line using all bits included in each of the memory cells associated with the ITG, such that bits on the same data page are stored in the same memory cell, and the memory cell does not include data segments from different data pages.

[0107] In one example of the memory device, an ITG was previously used and a data page was programmed into the memory cell using all bits included in each of the memory cells associated with the ITG to reduce the block size.

[0108] In one example of the memory device, an ITG was previously used and a data page was programmed into the memory cell using all bits included in each of the memory cells associated with the ITG to reduce the number of tiles utilized during subsequent read operations.

[0109] In one example of the memory device, a data page was previously programmed into the memory cell associated with the ITG using compression via input-output (IO), where bits of the same data page were programmed into the same memory cell.

[0110] In one example of the memory device, the plurality of memory cells includes a plurality of quad-level cells (QLCs), and each of the plurality of quad-level cells (QLCs) supports 4-bit data.

[0111] In one example of the memory device, the memory device is a NAND flash device.

[0112] In one example, a method for programming memory cells in a memory device is provided. The method may include receiving a data page at a memory controller of the memory device. The method may include splitting the data page into a group of data segments at the memory controller. The method may include programming the group of data segments into the memory cells associated with an inhibit tile group (ITG) in the plurality of memory cells in the memory device, wherein the group of data segments for the data page is programmed using all bits included in each of the memory cells associated with the ITG.

[0113] In one example of a method for programming memory cells in a memory device, the method may include allocating a data page to a word line using all bits included in each of the memory cells associated with the ITG such that bits on the same data page are stored in the same memory cells.

[0114] In one example of a method for programming memory cells in a memory device, the memory cells do not include data segments from different data pages.

[0115] In one example of a method for programming memory cells in a memory device, the method may include programming the data page into the memory cells associated with the ITG using compression over input-output (IO), wherein bits of the same data page are stored in the same memory cells.

[0116] In one example of a method for programming memory cells in a memory device, the method may include using the ITG and using all bits included in each of the memory cells associated with the ITG to program the data page into the memory cells to reduce the block size.

[0117] In one example of a method for programming memory cells in a memory device, the method may include using the ITG and using all bits included in each of the memory cells associated with the ITG to program the data page into the memory cells to reduce the number of tiles utilized during a programming operation.

[0118] In one example of a method for programming memory cells in a memory device, the ITG supports 4 kilobytes (KB) of data, and the data page is 16 KB, and each data segment is 4 KB, wherein the data page is programmed into the memory cells associated with the ITG using compression over input-output (IO).

[0119] In one example of a method for programming memory cells in a memory device, the method may include receiving a data page from a processor communicatively coupled to the memory controller.

[0120] In one example of a method for programming memory cells in a memory device, the ITG is a single ITG.

[0121] In one example of a method for programming memory cells in a memory device, the plurality of memory cells includes a plurality of quad-level cells (QLCs), and each of the plurality of quad-level cells (QLCs) supports 4-bit data.

[0122] While the foregoing examples illustrate the principles of the inventive embodiments in one or more particular applications, it will be apparent to those of ordinary skill in the art that many modifications may be made in the form of implementation, use, and details without the exercise of creative faculty and without departing from the principles and concepts of the present disclosure.

Claims

1. A system operable to program memory cells, the system comprising: A plurality of memory cells; And A memory controller including logic to: Receive a data page; Partition the data page into a group of data segments; And Program the group of data segments into the memory cells associated with a memory cell region among the plurality of memory cells, wherein the group of data segments for the data page is programmed using all bits included in each of the memory cells associated with the memory cell region, and wherein the data page is allocated to one word line using all bits included in each of the memory cells associated with the memory cell region, such that bits on the same data page are stored in the same memory cells.

2. The system according to claim 1, wherein the memory cells do not include data segments from different data pages.

3. The system according to claim 1, wherein the memory controller is configured to program the data page into the memory cells associated with the memory cell region using compression over input-output (IO), wherein bits of the same data page are stored in the same memory cells.

4. The system according to claim 1, wherein the memory controller is configured to program the data page into the memory cells using the memory cell region and using all bits included in each of the memory cells associated with the memory cell region to reduce the block size.

5. The system according to claim 1, wherein the memory controller is configured to program the data page into the memory cells using the memory cell region and using all bits included in each of the memory cells associated with the memory cell region to reduce the number of tiles utilized during a programming operation.

6. The system according to claim 1, wherein the memory cell region supports data with a storage capacity of 4 kilobytes (KB), the data page is 16 KB, and each data segment is 4 KB, and wherein the data page is programmed into the memory cells associated with the memory cell region using compression over input-output (IO).

7. The system according to claim 1, wherein the memory controller is configured to receive the data page from a processor communicatively coupled to the memory controller.

8. The system according to claim 1, wherein the memory cell region is a single memory cell region.

9. The system according to claim 1, wherein the plurality of memory cells includes a plurality of quad-level cells (QLC), each of the plurality of quad-level cells (QLC) supporting 4-bit data.

10. The system according to claim 1, wherein the system is a NAND flash device.

11. A memory device operable to read data from memory cells in a memory device, the memory device comprising: A plurality of memory cells; And A memory controller including logic to: Read a group of data segments from the memory cells associated with a memory cell region among the plurality of memory cells, wherein the group of data segments was previously programmed into the memory cells associated with the memory cell region using all bits included in each of the memory cells; and Groups of combined data segments are formed into data pages, wherein groups of data segments are assigned to a word line using all bits included in each of the memory cells associated with the memory cell region such that bits on the same data page are stored in the same memory cell.

12. The memory device according to claim 11, wherein the memory cells do not include data segments from different data pages.

13. The memory device according to claim 11, wherein the memory cell region was previously used and groups of data segments were programmed into the memory cells associated with the memory cell region using all bits included in each of the memory cells associated with the memory cell region to reduce the block size.

14. The memory device according to claim 11, wherein the memory cell region was previously used and groups of data segments were programmed into the memory cells associated with the memory cell region using all bits included in each of the memory cells associated with the memory cell region to reduce the number of tiles utilized during subsequent read operations.

15. The memory device according to claim 11, wherein groups of data segments were previously programmed into the memory cells associated with the memory cell region using compression via input-output (IO), wherein bits of the same data page are programmed into the same memory cell.

16. The memory device according to claim 11, wherein the memory controller is configured to provide data pages to a processor communicatively coupled to the memory device.

17. The memory device according to claim 11, wherein the plurality of memory cells includes a plurality of quad-level cells (QLCs), each of the plurality of quad-level cells (QLCs) supporting 4-bit data.

18. The memory device according to claim 11, wherein the memory device is a NAND flash device.

19. A method for programming memory cells in a memory device, the method comprising: receiving a data page at a memory controller of the memory device; splitting the data page into groups of data segments at the memory controller; and programming the groups of data segments into the memory cells associated with a memory cell region among the plurality of memory cells in the memory device, wherein the groups of data segments for the data page are programmed using all bits included in each of the memory cells associated with the memory cell region; and assigning the data page to a word line using all bits included in each of the memory cells associated with the memory cell region such that bits on the same data page are stored in the same memory cell.

20. The method according to claim 19, wherein the memory cells do not include data segments from different data pages.

21. The method according to claim 19, further comprising programming the data page into the memory cells associated with the memory cell region using compression via input-output (IO), wherein bits of the same data page are stored in the same memory cell.

22. The method according to claim 19, further comprising using a memory cell region and programming a data page into the memory cells using all bits included in each of the memory cells associated with the memory cell region to reduce the block size.

23. The method according to claim 19, further comprising using a memory cell region and programming a data page into the memory cells using all bits included in each of the memory cells associated with the memory cell region to reduce the number of tiles utilized during a programming operation.

24. The method according to claim 19, wherein the memory cell region supports data with a storage capacity of 4 kilobytes (KB), the data page is 16 KB, and each data segment is 4 KB, wherein the data page is programmed into the memory cells associated with the storage capacity using compression via input-output (IO).

25. The method according to claim 19, further comprising receiving a data page from a processor communicatively coupled to a memory controller.

26. The method according to claim 19, wherein the memory cell region is a single memory cell region.

27. The method according to claim 19, wherein the plurality of memory cells includes a plurality of quad-level cells (QLCs), and each of the plurality of quad-level cells (QLCs) supports 4-bit data.

28. A computer-readable storage medium having instructions stored thereon that, when executed by a processor, cause the processor to perform the method according to any one of claims 19-27.

29. A computer program product comprising instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 19-27.

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