Detecting Silent Data Corruption on Mass Storage Devices

Abstract

One embodiment provides a storage controller. The storage controller includes: host data segmentation logic, the host data segmentation logic is used to respond to a write command from a host domain for writing the data payload to a storage device, divide a data payload into a plurality of data segments; cyclic redundancy check (CRC) encoding logic, the cyclic redundancy check (CRC) encoding logic is used to generate a CRC code for each data segment; and CRC reordering encoding logic, the CRC reordering encoding logic is used to assign each CRC code to another data segment among the plurality of data segments.

Description

Technical Field

[0001] The present disclosure relates to detecting silent data corruption for mass storage devices. Background Art

[0002] A sector is the smallest granularity of storage that a host can access on a storage device. Host commands address these sectors using logical block addresses (LBAs), where each LBA points to a specific sector. The optimal sector size (512 bytes, 1k, 2k, 4k, ...) varies depending on the host application requirements. However, on the implementation side, hardware and media layout optimization (for performance, resilience, and cost) dictate the media sector size. Typically, the host sector size is several times the media sector size. Host applications require that writes be atomic. That means that the entire host sector is either committed to the media or not committed to the media. If a read of a partially committed (broken) host sector does not return a failure, the result is a silent data corruption. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Features and advantages of the claimed subject matter will become apparent from the following detailed description of embodiments consistent therewith, which description should be considered with reference to the accompanying drawings, in which:

[0004] Figure 1 A storage system consistent with several embodiments of the present disclosure is illustrated;

[0005] Figure 2 illustrates an example of data flow in various domains during a data write operation according to one embodiment;

[0006] Figure 3 illustrates a generalized data flow example according to various embodiments of the present disclosure;

[0007] Figure 4 is a flow chart of operations according to various embodiments of the present disclosure;

[0008] Figure 5 is a flow chart of operations according to various embodiments of the present disclosure;

[0009] Figure 6 is a flow chart illustrating operations consistent with one embodiment of the present disclosure; and

[0010] Figure 7 is a flow chart illustrating operations consistent with one embodiment of the present disclosure.

[0011] While the following detailed description will proceed with reference to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art. DETAILED DESCRIPTION

[0012] Figure 1 A system 100 consistent with several embodiments of the present disclosure is illustrated. System 100 may include storage controller circuitry 102, storage device 104, host processor circuitry 106, and host system memory 108. Host system memory 108 may include volatile random access memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc. In some embodiments, storage device 104 may be formed as part of storage controller circuitry 102 and packaged with storage controller circuitry 102 as an integrated circuit (which may also include memory circuitry (e.g., DRAM-type memory, not shown)). Host processor circuitry 106 may correspond to a single-core or multi-core general-purpose processor, such as those provided by Intel® Corp., etc. Host processor 106 and host system memory 108 may also be referred to herein as "host domain 150."

[0013] Storage device 104 may include, for example, solid-state device (SSD) circuitry (eg, non-volatile memory (NVM) circuitry), for example, storage media that does not require power to maintain the state of data stored by the storage media. The non-volatile memory may include, but is not limited to, NAND flash memory (e.g., triple-level cell (TLC) NAND or any other type of NAND (e.g., single-level cell (SLC), multi-level cell (MLC), quad-level cell (QLC), etc.)), NOR memory, solid-state memory (e.g., planar or three-dimensional (3D) NAND flash memory or NOR flash memory), a memory device using a chalcogenide phase change material (e.g., chalcogenide glass), a byte-addressable non-volatile memory device, a ferroelectric memory, a silicon-oxide-nitride-oxide-silicon (SONOS) memory, a polymer memory (e.g., a ferroelectric polymer memory), a byte-addressable random-access 3D cross-point memory, a ferroelectric transistor random access memory (Fe-TRAM), a magnetoresistive random access memory (MRAM), a phase change memory (PCM, PRAM), a resistive memory, a ferroelectric memory (F-RAM, FeRAM), a spin-transfer torque memory (STT), a heat-assisted switching memory (TAS), a millipede memory, a floating junction gate memory (FJG Memory 104 may include a plurality of sectors (“media sectors” or “storage device sectors”): sector 0 (124-0), sector 1 (124-1), …, sector Y (124-Y); where Y is an integer greater than 1. The size of each media sector generally depends on the type of device, layout optimization, etc. The media sector size is typically fixed for a given device, such as a media sector size of 512 bytes. Storage device 104 may also be referred to herein as a "storage domain 154."

[0014] The host system memory 108 may host an operating system (OS) 110 and an associated file system (not shown). When an application (not shown) is executed by the host processor circuit system 106, read and / or write operations targeting the storage device 104 may be issued by the file system associated with the OS 110. Such read and write operations generally include a logical block address (LBA) with an associated LBA sector size to be read from and / or written to the storage device 104. In some embodiments, the LBA sector size may be a single fixed size, for example, 512 bytes, and in other embodiments (as will be described below), the LBA sector size may be different for different applications / use models. The LBA sector size as issued by the host processor circuit system 106 is referred to herein as the "host sector size". Typically, the host sector size is generally several times the media sector size, and the length of the host sector may be based on, for example, the operating environment, application requirements / optimizations, etc.

[0015] Storage controller circuitry 102 (hereinafter referred to as "controller 102") is generally configured to control read and write operations between host processor circuitry 106 and storage device 104. Controller 102 is also referred to herein as "storage controller domain 152". To execute a read or write command, controller 102 is generally configured to address physical sectors 124-0, 124-1, ..., 124-Y of storage device 104 using at least one LBA issued from host processor circuitry 106. During a write operation, controller 102 is configured to segment host data (associated with a host sector) into a plurality of segments. Controller 102 may also be configured to further divide a segment into a plurality of media sector-sized data portions (sectorization), as will be described in more detail below.

[0016] The controller 102 includes host data segmentation logic 112, which is generally configured to segment a data payload issued with a write command from the host domain 150 into a plurality of smaller segments. In at least one embodiment, the host data segmentation logic 112 is configured to segment the data payload into two N segments; where N is an integer. The size of each segment may be based on, for example, processing overhead requirements for error correction calculations for the data payload (generally speaking, smaller segments require less processing overhead for error correction than larger segments). The controller 102 also includes CRC (cyclic redundancy check) encoding / decoding logic 114, which is generally configured to encode a CRC code for each segment (and, during a read operation, decode the CRC code to confirm data integrity). The CRC code generated by the CRC encoding / decoding logic 114 may include a short (e.g., 4-bit) check value paired with the segment. The CRC encoding / decoding logic 114 may generate the CRC code, for example, as a remainder of a polynomial division of the segment.

[0017] As described above, silent data corruption may occur when one segment of the data payload is correctly written to the storage device, but a system interruption event (e.g., power failure, system reset, etc.) occurs before the remaining segments are written to the storage device. Therefore, in a conventional storage system, there is "correct" data in the segments that were successfully written, but there is "stale" data in the segments that were not written before the system interruption event occurred. Such "stale" data is data that generally has a "correct" CRC code for each segment (as written during a previous write operation), but the stale data is incorrect for the current (partially failed) write operation. Therefore, when the stale data is read, it will be "correct" in the sense that it will have a correct CRC code, but it is incorrect because it is not the data expected to be written during the failed write operation. Therefore, such data may return incorrect results during a read operation, but such incorrect results will become undetected in a conventional storage system.

[0018] Accordingly, in order to enable detection of silent data corruption during a write operation, the controller 102 of the present embodiment also includes a CRC reordering encoding logic 116, which is generally configured to "swap" or "shift" the CRC code of each segment during a write operation. In one embodiment, the logic 116 is configured to shift the CRC code of each segment to the rear segment, and shift the CRC code of the last segment to the first segment. In another embodiment, the logic 116 is configured to shift the CRC code of each segment to the front segment, and shift the CRC code of the first segment to the last segment. In other embodiments, the logic 116 is configured to shift the CRC code to a certain number of rear and / or front segments, for example, shifting each CRC code to a segment outside two segments. In other embodiments, the logic 116 is configured to randomly shift the CRC code while ensuring that each segment receives a "new" CRC code from another segment. Therefore, and as will be described in more detail below, when reading (during a read operation) a data payload from storage device 104, if there is a system interrupt event before all segments are written to memory, the CRC decode operation will produce a CRC failure for any segments that were not successfully written before the system interrupt event occurred, and therefore, the entire data payload will be marked as a failed read operation.

[0019] As described above, depending on the sector size of the storage device 104 and during a data write operation, each segment of the payload data (from the host domain 150) may be further divided into sector length portions, each sector length portion having a bit length equal to (or less than) the size of the sectors 124-0, 124-1, ..., and / or 124-Y of the storage device 104. Accordingly, the controller 102 may also include segment sectorization logic 118, which is generally configured to divide each segment into a plurality of sector length portions. In at least one embodiment, the segment sectorization logic 118 is configured to sectorize each segment into 2 X sector-sized portion; 2 X ≥ 2 N , and X is an integer. Of course, for some write operations, the size of each segment may match the sector size of storage device 104, in which case further partitioning of the payload data may not be necessary.

[0020] The controller 102 may also include ECC encoding / decoding logic 120. The ECC encoding / decoding logic 120 is configured to encode each segment and / or sector length portion with an error correction code during a write operation, and to decode the error correction code during a read operation to provide error checking functionality for the controller 102. For example, the ECC encoding / decoding logic 120 may be configured to attach parity information, such as ECC, to data stored (i.e., during a write operation) in the storage device 104. In response to and / or as part of a read operation, the ECC encoding / decoding logic 120 may be further configured to determine a parity check (i.e., an error syndrome), which may then be utilized to detect errors, identify erroneous bits, and / or correct data read from the storage device 104. One or more techniques may be used for error correction and / or detection, such as, for example, Hamming codes, Reed-Solomon codes, low-density parity check codes (LDPC), Bose-Chaudhuri-Hocquenghem (BCH) codes, and the like. Of course, the listed error correction codes are merely examples, and other ECCs configured to detect memory cell errors, identify erroneous cells, and / or correct multiple detected errors may be utilized consistent with the present disclosure. In the context of the present disclosure, the ECC encoding / decoding logic 120 may be applied to read and write operations for each segment and / or sector length portion, and therefore, the ECC encoding / decoding logic 120 may be configured to select an error correction scheme that is appropriately sized based on the size of the segment and / or sector length portion.

[0021] During a write operation, and assuming that the segment sectorization logic 118 has divided each segment of the data payload into two XIn order to generate multiple sector length portions, the segment sectorization logic 118 can be configured to attach a CRC code (determined by the CRC encoding / decoding logic 114 for the segment) to the last sector length portion of the segment, and to attach an empty set of "spacers" to the remaining sector length portions of the segment. Each sector length portion may include an ECC code. The "spacer" (or "filler") may have the same bit length as the CRC code, but does not operate as a CRC code. Therefore, in the case of a partial write (where only one or more sector length portions are written to the storage device before the interrupt event occurs), subsequent reads and ECC decoding operations of those sector length portions with the "spacer" CRC code will result in data read failures.

[0022] The controller 102 also includes CRC reorder decoding logic 122, which is generally configured to "swap back" each CRC code to each original CRC code / data segment pair during a read operation and before the CRC encoding / decoding logic decodes the CRC code for each segment. Thus, if one or more segments (and / or sector length portions) failed to be written during a previous write operation, the CRC code swapped from the stale segment to the "fresh" segment will fail the CRC decoding process, and the read operation will be marked as a read failure (fatal failure).

[0023] Figure 2 FIG200 illustrates an example of data flow in various domains during a data write operation according to one embodiment. Figure 1 ,exist Figure 2In the example of , assume that the host domain 150 issues a write command with a 2KB data payload 202. Furthermore, assume that for this example, the storage controller domain 152 is configured to generate CRC codes for 1K byte segments, and that the storage domain has a sector size of 512 bytes. Accordingly, the storage controller domain 152 generates two 1KB segments: 204 (data B) and 206 (data A). In addition, the storage controller domain 152 generates a CRC code for each segment: CRCa 208 for segment 206 and CRCb 210 for segment 204. Before submitting segments 204 and 206 to the storage domain 154 and before silent data corruption detection is enabled, the storage controller domain 152 swaps the CRC codes for each segment 204 and 206 such that CRCa 208 is appended to segment 206 and CRCb 210 is appended to segment 204, as shown by the arrows. In addition, the storage controller domain 152 may further divide each segment into sector length portions 212, 218, 222, and 228. Portions 212 and 218 correspond to the data A segment 206, and portions 222 and 228 correspond to the data B segment 204. In addition, the storage controller domain 152 is configured to generate ECC codes 216, 220, 226, and 230 and append the ECC codes to each respective portion 212, 218, 222, and 228. In addition, the storage controller domain 152 is configured to generate a spacer field 214 of the first portion 212 and a spacer field 224 of the portion 222. CRCb 210 may be appended to the last portion 218 of the data A segment 206, and CRCa may be appended to the last portion 228 of the data B segment 204, as shown. The storage controller domain 152 may attempt to write the data portion 212, the spacer field 214, and the ECC code 216 to a sector (e.g., sector 0) of the storage domain 154. The storage controller domain 152 may attempt to write the data portion 218, the CRCb 210, and the ECC code 220 to a sector (e.g., sector 1) of the storage domain 154. The storage controller domain 152 may attempt to write the data portion 222, the spacer field 224, and the ECC code 226 to a sector (e.g., sector 2) of the storage domain 154. The storage controller domain 152 may attempt to write the data portion 228, the CRCa 208, and the ECC code 230 to a sector (e.g., sector 3) of the storage domain 154. Of course, in other embodiments, it may not be necessary to write each data portion to sequential sectors, and sectors 0, 1, 2, and 3 may be any sectors, but are described herein for purposes of illustration and not limitation. Figure 2 Depicted in.

[0024] If there is a system interrupt event during these write operations, the storage controller domain 152 may detect the following data corruption conditions during a subsequent read operation (eg, a read command issued by the host domain 150):

[0025] Scenario 1

[0026] Assume that the data portion 212 is partially committed (e.g., to sector 0), for example, DataA 206 is corrupted. When the storage controller domain 152 reads this sector, the ECC logic 120 will decode ECC0 216 and return an error. Therefore, the read operation for Data A and Data B will generate a read error (fatal error).

[0027] Scenario 2

[0028] Assume that data portion 212 is correctly submitted to the storage device, but an interrupt event occurs before data portion 218 has begun to be written to the storage device. In this case, when the storage controller domain 152 reads sector 0, the ECC logic 120 will not detect any errors for this sector, but when the storage controller domain 152 reads sectors 1, 2, and 3, the CRC logic 120 will decode the "stale" ECC code in fields 220 and 230, and because the data in sector 1 is "stale", the ECC code will return a read error.

[0029] Scenario 3

[0030] Assume that Data 0 212 and Data 1 218 have been correctly committed to the storage device, but an interrupt event occurs before Data 2 (222) and Data 3 (228) have begun. Therefore, CRCb 210 is committed, and the CRC code of Data B 204 is "stale." In this case, the storage controller domain 152 reads Data A 206 and Data B (from sectors 0, 1, 2, and 3), and the CRC codes are reordered so that the "stale" CRCa is appended to Data A, and the "new" CRCb is appended to the "stale" Data B. In this way, each CRC code will return an error, thus reducing or eliminating silent data corruption.

[0031] Figure 3 A generalized data flow example 300 is illustrated according to various embodiments of the present disclosure. Figure 1 ,exist Figure 3 In the example of FIG. 1 , it is assumed that the host domain 150 issues a write command of a data payload 302 having a length of Z bytes. The storage controller domain 152 is typically configured to segment the data payload into a plurality of segments 302-1, 302-3, 302-4, ..., 302-2 N ; Where Z>N and N is an integer. Each segment 302-1, 302-3, 302-3, 302-4, ..., 302-2 N With data length Z / 2 NThe storage controller domain 152 is also configured to generate each corresponding segment 302-1, 302-3, 302-3, 302-4, ..., 302-2 N CRC codes 304-1, 304-2, 304-3, 304-4, ..., 304-2 N The storage controller domain 152 is further configured to assign each CRC code to the next segment and to assign the last CRC code to the first segment (as indicated by the arrows), thereby enabling silent data corruption detection. The storage controller domain 152 is further configured to sectorize each segment by generating at least an ECC code for the segment and appending the ECC code and the (interchanged) CRC code to each sector length portion. More generally, and assuming that the sector length of the storage device is less than the length of each segment, the storage controller domain 152 is further configured to divide each segment into two X , thereby generating a plurality of sector length parts, each of which has (Z / 2 (N+X) ) length; 2 X ≥ 2 N , and X is an integer. For example, segment 302-1 may be divided into sector length portions 306-1, 306-2, ..., 306-2 X Using segment 302-1 as an example, before committing the segment to storage, the storage controller domain 152 is configured to "swap" the CRC code 310 and the ECC code 310-2. X Attached to the last sector length portion 306-2 X , and append the empty set ("filler" 308-1, 308-2, ...) and ECC code (310-1, 310-2, ...) to the remaining sector length portion. The remaining segments can be processed in a similar manner, as in Figure 3 As depicted in . Figure 3 The generalized data stream enables detection of silent data corruption using CRC code "shifts" or "swaps" as described herein, as well as detection of other write errors using ECC codes as described above.

[0032] certainly, Figure 3The example of illustrates the shifting or assignment of CRC codes to later segments, but in other embodiments, the CRC codes may be shifted to earlier segments. Thus, for example, if there are 4 data segments, the CRC code for data segment 1 may be shifted to the last data segment, the CRC code for data segment 2 may be shifted to data segment 1, and so on. In still other embodiments, the storage controller domain 152 may be configured to shift the CRC codes by "skipping" one or more data segments. Thus, for example, if there are 8 data segments, the CRC code for data segment 1 may be shifted to data segment 3, the CRC code for data segment 2 may be shifted to data segment 4, and so on, and the CRC codes for data segments 7 and 8 may be shifted to data segments 1 and 2, respectively. Of course, these are merely examples of the types of CRC shifts that may be configured to be performed by the storage controller domain 152, and in general, the storage controller domain 152 is typically configured to shift or assign CRC codes among multiple data segments to ensure that no original CRC code / data segment pairs are submitted to the storage device 104 as original pairs. Therefore, in still other embodiments, storage controller domain 152 may be configured to randomly shift or assign CRC codes among multiple data segments.

[0033] Figure 4 400 is a flow chart of operations according to various embodiments of the present disclosure. Specifically, flow chart 400 illustrates a write operation and a CRC code exchange to enable silent data corruption detection. The operation includes receiving a data write command from a host domain, the data write command having a data payload of length Z bytes, 402. The operation also includes segmenting the data payload into two N data segments; where N is an integer, 404. The operations also include generating a CRC code for each data segment, 406. The operations also include reordering the CRC codes by assigning each CRC code to another data segment among the plurality of data segments, 408. In some embodiments, the operations may also include sectorizing each data segment into 2 X sector length portions; where X is an integer and each sector length has a byte length of a sector of the storage device, 410. The operations may also include generating an ECC code for each sector length portion, 412. The operations may also include generating a null field for each sector length portion of the segments except for the last sector length portion of each segment, 414. The operations may also include assembling the sector length portions except for the last sector length portion of each segment and the corresponding ECC code and the null field, 416. The operations may also include assembling the last sector length portion except for the last sector length portion of each segment, the assigned CRC code, and the ECC code, 418. The operations may also include attempting to commit each sector length portion to a corresponding sector of the storage device, 420.

[0034] Figure 5is a flow chart 500 of operations according to various embodiments of the present disclosure. Specifically, flow chart 500 illustrates a read operation and detection of data corruption, including silent data corruption. The operation includes receiving a read command from a host, wherein the read command has an expected data payload of Z bytes in length, 502. The operation also includes determining a first number of segments of the data payload and a second number of sector length portions of each segment, 504. The operation also includes reading each sector length portion from a storage device, including a CRC code associated with each segment and an ECC code associated with each sector length portion, 506. The operation also includes reordering the CRC code of each segment by reassigning each CRC code of each segment, 508. The operation also includes decoding the ECC code of each sector length portion and determining whether the ECC code passes for each sector length portion, 510. If the ECC does not pass for a given sector length portion, the operation also includes returning a read failure, 512. If the ECC code passes, the operation also includes the operation also includes decoding the CRC code of each segment and determining whether the ECC passes for each segment, 514. If the CRC does not pass for a given segment, the operation also includes returning a read failure, 516. A failed CRC decode for this operation indicates a silent data corruption. If both the CRC and ECC pass, the operation also includes returning a successful read result to the host, 518.

[0035] Figure 6 is a flow chart 600 illustrating operations consistent with one embodiment of the present disclosure. Specifically, flow chart 600 illustrates CRC code exchange for enabling silent data corruption detection. Operations of this embodiment include, in response to a write command from a host domain (which is used to write a data payload to a storage device), dividing a data payload into a plurality of data segments, 602. Operations also include generating a CRC code for each data segment, 604. Operations also include assigning each CRC code to another data segment among the plurality of data segments, 606.

[0036] Figure 7 700 is a flowchart illustrating operations consistent with one embodiment of the present disclosure. Specifically, flowchart 700 silences data corruption detection. Operations of this embodiment include, in response to a data read command from a host domain (which is used to read a data payload from a storage device), reassigning a CRC code for each data segment, 702. Operations also include decoding the CRC code for each data segment to determine a data integrity status, 704.

[0037] although Figure 4-7 The flowcharts of the present invention illustrate the operation according to various embodiments, but it is understood that the present invention is not Figure 4-7 All operations described in are necessary for other embodiments. In addition, it is fully contemplated herein that in other embodiments of the present disclosure, Figure 4 ,5 The operations depicted in , 6 and / or 7 and / or other operations described herein may be combined in a manner not explicitly shown in any of the figures, and such embodiments may include more than those in Figure 4 , 5 , 6 and / or 7. Therefore, claims directed to features and / or operations not specifically shown in one drawing are considered to be within the scope and content of the present disclosure.

[0038] This application provides the following technical solutions:

[0039] Technical Solution 1. A storage controller, comprising:

[0040] host data segmentation logic for dividing the data payload into a plurality of data segments in response to a write command from a host domain for writing the data payload to a storage device;

[0041] Cyclic redundancy check (CRC) encoding logic for generating a CRC code for each data segment; and

[0042] CRC reorder encoding logic is used to assign each CRC code to another data segment among the plurality of data segments.

[0043] Technical Solution 2. The storage controller as described in Technical Solution 1 further includes segment sectorization logic, which is used to divide each data segment into multiple sector length parts; wherein each sector length part has a bit length based on the sector size of the storage device.

[0044] Technical Solution 3. The storage controller as described in Technical Solution 2, wherein the host data segmentation logic is used to divide the data payload into 2 N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

[0045] Technical Solution 4. The storage controller as described in Technical Solution 2 further includes an error correction code (ECC) encoding logic, wherein the error correction code (ECC) encoding logic is used to generate an ECC code for each sector length portion.

[0046] Technical Solution 5. A storage controller as described in Technical Solution 3, wherein the segment sectorization logic is further used to generate an empty field for each sector length part except the last sector length part of the segment, and assemble the empty field and the ECC code of each sector length part; and is further used to assemble the ECC code and the assigned CRC code for the last sector length part of the segment.

[0047] Technical Solution 6. The storage controller according to Technical Solution 3 further comprises:

[0048] CRC reorder decoding logic for reassigning a corresponding CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device;

[0049] CRC decoding logic to decode the corresponding CRC code of each data segment to determine a first data integrity status; and

[0050] ECC decoding logic is used to decode the ECC code of each sector length portion to determine a second data integrity state.

[0051] Technical Solution 7. The storage controller according to Technical Solution 1 further comprises:

[0052] CRC reorder decoding logic for reassigning a corresponding CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; and

[0053] CRC decoding logic for decoding the corresponding CRC code of each data segment to determine a data integrity status.

[0054] Technical Solution 8. The storage controller as described in Technical Solution 1, wherein the host data segmentation logic is used to divide the data payload into two N Parts; where N is an integer.

[0055] Technical Solution 9. A method comprising:

[0056] In response to a write command from a host domain for writing a data payload to a storage device, dividing the data payload into a plurality of data segments;

[0057] generating a cyclic redundancy check (CRC) code for each data segment; and

[0058] Each CRC code is assigned to another data segment among the plurality of data segments.

[0059] Technical Solution 10. The method as described in Technical Solution 9 further includes: dividing each segment into a plurality of sector length parts; wherein each sector length part has a bit length based on the sector size of the storage device.

[0060] Technical Solution 11. The method as described in Technical Solution 10, comprising dividing the data payload into 2 N Each data segment is divided into 2 （N+X） wherein N and X are integers.

[0061] Technical Solution 12. The method as described in Technical Solution 10 further includes generating an error correction code (ECC) code for each sector length portion.

[0062] Technical Solution 13. The method according to Technical Solution 12 further comprises:

[0063] in response to a data read command from the host domain for reading the data payload from the storage device, reassigning a corresponding CRC code of each data segment; and

[0064] decoding the corresponding CRC code of each data segment to determine a first data integrity status; and

[0065] The ECC code of each sector length portion is decoded to determine a second data integrity status.

[0066] Technical Solution 14. The method according to Technical Solution 11 further comprises:

[0067] generating a null field for each sector length portion except for a last sector length portion of a segment, and assembling the null field and the ECC code for each sector length portion; and

[0068] The ECC code and the assigned CRC code are assembled for the last sector length portion of the segment.

[0069] Technical Solution 15. The method according to Technical Solution 9 further comprises:

[0070] in response to a data read command from the host domain for reading the data payload from the storage device, reassigning a corresponding CRC code of each data segment; and

[0071] The corresponding CRC code of each data segment is decoded to determine the data integrity status.

[0072] Technical Solution 16. The method as described in Technical Solution 9 includes dividing the data payload into 2 N Parts; where N is an integer.

[0073] Technical Solution 17. A storage system comprising:

[0074] A storage device having a plurality of sectors; and

[0075] A storage controller, the storage controller comprising:

[0076] host data segmentation logic for dividing the data payload into a plurality of data segments in response to a write command from a host domain for writing the data payload to the storage device;

[0077] Cyclic redundancy check (CRC) encoding logic for generating a CRC code for each data segment; and

[0078] CRC reorder encoding logic is used to assign each CRC code to another data segment among the plurality of data segments.

[0079] Technical Solution 18. The storage system as described in Technical Solution 17 further includes segment sectorization logic, which is used to divide each data segment into multiple sector length parts; wherein each sector length part has a bit length based on the sector size of the storage device.

[0080] Technical Solution 19. A storage system as described in Technical Solution 18, wherein the host data segmentation logic is used to divide the data payload into two N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

[0081] Technical Solution 20. The storage system as described in Technical Solution 18 further includes 11 including error correction code (ECC) encoding logic, and the error correction code (ECC) encoding logic is used to generate an ECC code for each sector length portion.

[0082] Technical Solution 21. A storage system as described in Technical Solution 20, wherein the segment sectorization logic is further used to generate an empty field for each sector length part except the last sector length part of the segment, and assemble the empty field and the ECC code of each sector length part; and is further used to assemble the ECC code and the assigned CRC code for the last sector length part of the segment.

[0083] Technical Solution 22. The storage system according to Technical Solution 19 further comprises:

[0084] CRC reorder decoding logic, the CRC reorder decoding logic being used to reassign a corresponding CRC code of each data segment to a preceding data segment in response to a data read command from the host domain for reading the data payload from the storage device;

[0085] CRC decoding logic to decode the corresponding CRC code of each data segment to determine a first data integrity status; and

[0086] ECC decoding logic is used to decode the ECC code of each sector length portion to determine a second data integrity state.

[0087] Technical Solution 23. The storage system according to Technical Solution 17 further comprises:

[0088] CRC reorder decoding logic for reassigning a corresponding CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; and

[0089] CRC decoding logic for decoding the corresponding CRC code of each data segment to determine a data integrity status.

[0090] Technical Solution 24. A storage system as described in Technical Solution 17, wherein the host data segmentation logic is used to divide the data payload into two N Parts; where N is an integer.

[0091] As used in any embodiment herein, the term "logic" may refer to an application, software, firmware, and / or circuitry configured to perform any of the foregoing operations. Software may be implemented as a software package, code, instructions, instruction sets, and / or data recorded on a non-transitory computer-readable storage medium. Firmware may be implemented as code, instructions, or instruction sets, and / or data that are hard-coded (e.g., non-volatile) in a memory device.

[0092] As used in any embodiment herein, "circuitry" may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, logic and / or firmware storing instructions executable by programmable circuitry, alone or in any combination. The circuitry may be implemented as an integrated circuit, such as an integrated circuit chip, such as an application specific integrated circuit (ASIC), etc. In some embodiments, the circuitry may be formed at least in part by a processor (e.g., host processor circuitry 106 and / or controller 102) that executes code and / or instruction sets (e.g., software, firmware, etc.) corresponding to the functionality described herein, thereby transforming a general-purpose processor into a dedicated processing environment to perform one or more of the operations described herein. In some embodiments, various components or circuitry of a storage controller circuitry or other system may be combined in a system on a chip (SoC) architecture.

[0093] The foregoing provides an example system architecture and methodology, however, modifications to the present disclosure are possible. The processor may include one or more processor cores and may be configured to execute system software. The system software may include, for example, an operating system. The device memory may include an I / O memory buffer configured to store one or more data packets to be transmitted or received by the network interface.

[0094] Operating system (OS) 110 may be configured to manage system resources and control tasks running on, for example, system 100. For example, the OS may be implemented using Microsoft® Windows®, HP-UX®, Linux®, or UNIX®, although other operating systems may be used. In another example, Android TM , iOS, Windows Phone®, or BlackBerry® to implement the OS. In some embodiments, the OS may be replaced with a virtual machine monitor (or hypervisor), which may provide a layer of abstraction for the underlying hardware to various operating systems (virtual machines) running on one or more processing units. The operating system and / or virtual machine may implement a protocol stack. The protocol stack may execute one or more programs to process packets. An example of a protocol stack is a TCP / IP (Transmission Control Protocol / Internet Protocol) protocol stack, which includes one or more programs for handling (e.g., processing or generating) packets to be transmitted and / or received over a network.

[0095] The memories 108 may each include one or more of the following types of memory: semiconductor firmware memory, programmable memory, non-volatile memory, read-only memory, electrically programmable memory, random access memory, flash memory, magnetic disk storage, and / or optical disk storage. Additionally or alternatively, the system memory may include other and / or later developed types of computer-readable memory.

[0096] Embodiments of the operations described herein may be implemented on a computer-readable storage device having stored thereon instructions that, when executed by one or more processors, perform the method. The processor may include, for example, a processing unit and / or a programmable circuit system. The storage device may include a machine-readable storage device, which includes any type of tangible, non-transitory storage device, such as any type of disk including a floppy disk, an optical disk, a compact disk read-only memory (CD-ROM), a rewritable compact disk (CD-RW), and a magneto-optical disk; a semiconductor device such as a read-only memory (ROM), a random access memory (RAM) (such as dynamic and static RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEEPROM), a flash memory; a magnetic card or an optical card; or any type of storage device suitable for storing electronic instructions.

[0097] In some embodiments, a hardware description language (HDL) may be used to specify circuit and / or logic implementations for various logic and / or circuit systems described herein. For example, in one embodiment, the hardware description language may conform to or be compatible with the Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), which may be capable of implementing semiconductor fabrication of one or more circuits and / or logic described herein. VHDL may be compatible with IEEE Standard 1076-1987, IEEE Standard 1076.2, IEEE 1076.1, IEEE Draft 3.0 of VHDL-2006, IEEE Draft 4.0 of VHDL-2008, and / or other versions of the IEEE VHDL standard and / or other hardware description standards.

[0098] In some embodiments, the Verilog hardware description language (HDL) may be used to specify circuit and / or logic implementations for the various logic and / or circuit systems described herein. For example, in one embodiment, the HDL may conform to or be compatible with IEEE Std 62530-2011: SystemVerilog - Unified Hardware Design, Specification, and Qualification Language, dated July 7, 2011; IEEE Std 1800 TM - 2012: IEEE Standard for SystemVerilog - Unified Hardware Design, Specification, and Qualification Language, dated February 21, 2013; IEEE Std 1364-2005: IEEE Standard for Verilog Hardware Description Language, dated April 18, 2006; and / or other versions of the Verilog HDL and / or SystemVerilog standards.

[0099] Example

[0100] Examples of the present disclosure include subject matter such as methods, components for performing actions of methods, apparatus, or devices or systems related to storage systems with multiple indirection unit granularity, as discussed below.

[0101] Example 1. According to this example, a storage controller is provided. The storage controller includes: host data segmentation logic, the host data segmentation logic is used to respond to a write command from a host domain for writing the data payload to a storage device, divide the data payload into a plurality of data segments; cyclic redundancy check (CRC) encoding logic, the cyclic redundancy check (CRC) encoding logic is used to generate a CRC code for each data segment; and CRC reordering encoding logic, the CRC reordering encoding logic is used to assign each CRC code to another data segment among the plurality of data segments.

[0102] Example 2. This example includes elements of Example 1, further comprising segment sectorization logic for dividing each data segment into a plurality of sector length portions; wherein each sector length portion has a bit length based on a sector size of the storage device.

[0103] Example 3. This example includes elements of Example 2, further comprising including error correction code (ECC) encoding logic, the error correction code (ECC) encoding logic being used to generate an ECC code for each sector length portion.

[0104] Example 4. This example includes elements of Example 3, wherein the segment sectorization logic is further used to generate an empty field for each sector length portion except the last sector length portion of the segment, and assemble the empty field and the ECC code for each sector length portion; and is further used to assemble the ECC code and the assigned CRC code for the last sector length portion of the segment.

[0105] Example 5. This example includes elements of Example 1, further including: CRC reordering decoding logic, the CRC reordering decoding logic is used to reassign the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; and CRC decoding logic, the CRC decoding logic is used to decode the CRC code of each data segment to determine a data integrity status.

[0106] Example 6. This example includes elements of Example 3, further comprising: CRC reorder decoding logic, the CRC reorder decoding logic being used to reassign each CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; CRC decoding logic, the CRC decoding logic being used to decode the CRC code of each data segment to determine a first data integrity state; and ECC decoding logic, the ECC decoding logic being used to decode the ECC code of each sector length portion to determine a second data integrity state.

[0107] Example 7. This example includes elements of Example 1, wherein the host data segmentation logic is used to divide the data payload into two N Parts; where N is an integer.

[0108] Example 8. This example includes elements of Example 2, wherein the host data segmentation logic is used to divide the data payload into two N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

[0109] Example 9. According to this example, a method is provided. The method includes: dividing the data payload into a plurality of data segments by host data segmentation logic in response to a write command from a host domain for writing the data payload to a storage device; generating a cyclic redundancy check (CRC) code for each data segment by CRC encoding logic; and assigning each CRC code to another data segment among the plurality of data segments by CRC reordering encoding logic.

[0110] Example 10. This example includes elements of Example 9, further comprising dividing each segment into a plurality of sector length portions by segment sectorization logic; wherein each sector length portion has a bit length based on a sector size of the storage device.

[0111] Example 11. This example includes elements of Example 10, further comprising generating an error correction code (ECC) code for each sector length portion by an ECC encoding logic.

[0112] Example 12. This example includes elements of Example 11, further comprising: generating an empty field for each sector length portion except the last sector length portion of the segment, and assembling the empty field and the ECC code for each sector length portion; and assembling the ECC code and the assigned CRC code for the last sector length portion of the segment.

[0113] Example 13. This example includes elements of Example 9, further comprising: in response to a data read command from the host domain for reading the data payload from the storage device, reassigning the CRC code of each data segment; and decoding the CRC code of each data segment by CRC decoding logic to determine a data integrity status.

[0114] Example 14. This example includes elements of Example 11, further comprising: reassigning, by CRC reorder decoding logic, the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; and decoding, by CRC decoding logic, the CRC code of each data segment to determine a first data integrity state; and decoding, by ECC decoding logic, the ECC code of each sector length portion to determine a second data integrity state.

[0115] Example 15. This example includes elements of Example 9, wherein the host data segmentation logic is used to divide the data payload into two N Parts; where N is an integer.

[0116] Example 16. This example includes elements of Example 10, wherein the host data segmentation logic is used to divide the data payload into two N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

[0117] Example 17. This example provides a storage system. The storage system includes a storage device having a plurality of sectors; and a storage controller, the storage controller including: a host data segmentation logic, the host data segmentation logic is used to respond to a write command from a host domain for writing a data payload to the storage device, divide the data payload into a plurality of data segments; a cyclic redundancy check (CRC) encoding logic, the cyclic redundancy check (CRC) encoding logic is used to generate a CRC code for each data segment; and a CRC reordering encoding logic, the CRC reordering encoding logic is used to assign each CRC code to another data segment among the plurality of data segments.

[0118] Example 18. This example includes elements of Example 17, further comprising segment sectorization logic to divide each data segment into a plurality of sector length portions; wherein each sector length portion has a bit length based on a sector size of the storage device.

[0119] Example 19. This example includes elements of Example 18, further comprising including error correction code (ECC) encoding logic to generate an ECC code for each sector length portion.

[0120] Example 20. This example includes elements of Example 19, wherein the segment sectorization logic is further used to generate an empty field for each sector length portion except the last sector length portion of the segment, and assemble the empty field and the ECC code for each sector length portion; and further used to assemble the ECC code and the assigned CRC code for the last sector length portion of the segment.

[0121] Example 21. This example includes elements of Example 17, further including: CRC reordering decoding logic, the CRC reordering decoding logic is used to reassign the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; and CRC decoding logic, the CRC decoding logic is used to decode the CRC code of each data segment to determine a data integrity status.

[0122] Example 22. This example includes elements of Example 19, further including: CRC reorder decoding logic, the CRC reorder decoding logic being used to reassign each CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; CRC decoding logic, the CRC decoding logic being used to decode the CRC code of each data segment to determine a first data integrity state; and ECC decoding logic, the ECC decoding logic being used to decode the ECC code of each sector length portion to determine a second data integrity state.

[0123] Example 23. This example includes elements of Example 17, wherein the host data segmentation logic is used to divide the data payload into two N Parts; where N is an integer.

[0124] Example 24. This example includes elements of Example 18, wherein the host data segmentation logic is used to divide the data payload into two N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

[0125] Example 25. According to this example, there is provided a computer-readable storage device having instructions stored thereon, which, when executed by one or more processors, causes the following operations, including: in response to a write command from a host domain for writing a data payload to the storage device, dividing the data payload into multiple data segments; generating a CRC code for each data segment; and assigning each CRC code to another data segment among the multiple data segments.

[0126] Example 26. This example includes elements of Example 25, wherein the instructions when executed by one or more processors cause the following additional operations, the operations comprising dividing each segment into a plurality of sector length portions; wherein each sector length portion has a bit length based on a sector size of the storage device.

[0127] Example 27. This example includes elements of Example 26, wherein the instructions when executed by one or more processors cause the following additional operations, the operations comprising generating an ECC code for each sector length portion.

[0128] Example 28. This example includes elements of Example 27, wherein the instructions when executed by one or more processors cause the following additional operations, the operations comprising: generating an empty field for each sector length portion except the last sector length portion of the segment, and assembling the empty field and the ECC code for each sector length portion; and assembling the ECC code and the assigned CRC code for the last sector length portion of the segment.

[0129] Example 29. This example includes elements of Example 27, wherein the instructions when executed by one or more processors cause the following additional operations, the operations comprising: in response to a data read command from the host domain for reading the data payload from the storage device, reassigning the CRC code of each data segment; and decoding the CRC code of each data segment to determine a first data integrity state; and decoding the ECC code of each sector length portion to determine a second data integrity state.

[0130] Example 30. This example includes elements of Example 25, wherein the instructions when executed by one or more processors cause the following additional operations, the operations comprising: reassigning the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; and decoding the CRC code of each data segment to determine a data integrity status.

[0131] Example 31. This example includes elements of Example 25, wherein the host data segmentation logic is used to divide the data payload into two NParts; where N is an integer.

[0132] Example 32. This example includes elements of Example 26, wherein the host data segmentation logic is used to divide the data payload into two N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

[0133] Example 33. This example includes elements of Example 1, wherein assigning each CRC code to another data segment includes assigning each CRC code to a subsequent data segment and assigning the CRC code of the last data segment to the first data segment.

[0134] Example 34. This example includes elements of Example 1, wherein assigning each CRC code to another data segment includes assigning each CRC code to a preceding data segment and assigning the CRC code of the first data segment to a last data segment.

[0135] Example 35. This example includes elements of Example 1, wherein assigning each CRC code to another data segment includes randomly assigning each CRC code to another data segment.

[0136] Example 36. This example includes elements of Example 9, wherein assigning each CRC code to another data segment includes assigning each CRC code to a subsequent data segment and assigning the CRC code of the last data segment to the first data segment.

[0137] Example 37. This example includes elements of Example 9, wherein assigning each CRC code to another data segment includes assigning each CRC code to a preceding data segment and assigning the CRC code of the first data segment to a last data segment.

[0138] Example 38. This example includes elements of Example 9, wherein assigning each CRC code to another data segment includes randomly assigning each CRC code to another data segment.

[0139] Example 39. This example includes elements of Example 17, wherein assigning each CRC code to another data segment includes assigning each CRC code to a subsequent data segment and assigning the CRC code of the last data segment to the first data segment.

[0140] Example 40. This example includes elements of Example 17, wherein assigning each CRC code to another data segment includes assigning each CRC code to a preceding data segment and assigning the CRC code of the first data segment to a last data segment.

[0141] Example 41. This example includes elements of Example 17, wherein assigning each CRC code to another data segment includes randomly assigning each CRC code to another data segment.

[0142] Example 42. This example includes elements of Example 25, wherein assigning each CRC code to another data segment includes assigning each CRC code to a subsequent data segment and assigning the CRC code of the last data segment to the first data segment.

[0143] Example 43. This example includes elements of Example 25, wherein assigning each CRC code to another data segment includes assigning each CRC code to a preceding data segment and assigning the CRC code of the first data segment to a last data segment.

[0144] Example 44. This example includes elements of Example 25, wherein assigning each CRC code to another data segment includes randomly assigning each CRC code to another data segment.

[0145] Example 45. This example provides a storage system. The storage system includes:

[0146] a storage domain including a storage device having a storage medium including a plurality of sectors; and

[0147] A storage controller domain, the storage controller domain comprising:

[0148] host data segmentation logic for dividing the data payload into a plurality of data segments in response to a write command from a host domain for writing the data payload to a storage device;

[0149] Cyclic redundancy check (CRC) encoding logic for generating a CRC code for each data segment; and

[0150] CRC reorder encoding logic is used to assign each CRC code to another data segment among the plurality of data segments.

[0151] Example 46. This example includes elements of Example 45, further comprising segment sectorization logic to divide each data segment into a plurality of sector length portions; wherein each sector length portion has a bit length based on a sector size of the storage device.

[0152] Example 47. This example includes elements of Example 46, further comprising including error correction code (ECC) encoding logic to generate an ECC code for each sector length portion.

[0153] Example 48. This example includes elements of Example 47, wherein the segment sectorization logic is further used to generate an empty field for each sector length portion except the last sector length portion of the segment, and assemble the empty field and the ECC code for each sector length portion; and further used to assemble the ECC code and the assigned CRC code for the last sector length portion of the segment.

[0154] Example 49. This example includes elements of Example 45, further including: CRC reordering decoding logic, the CRC reordering decoding logic is used to reassign the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; and CRC decoding logic, the CRC decoding logic is used to decode the CRC code of each data segment to determine a data integrity status.

[0155] Example 50. This example includes elements of Example 47, further including: CRC reorder decoding logic, the CRC reorder decoding logic being used to reassign each CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; CRC decoding logic, the CRC decoding logic being used to decode the CRC code of each data segment to determine a first data integrity state; and ECC decoding logic, the ECC decoding logic being used to decode the ECC code of each sector length portion to determine a second data integrity state.

[0156] Example 51. This example includes elements of Example 45, wherein the host data segmentation logic is used to divide the data payload into two N Parts; where N is an integer.

[0157] Example 52. This example includes elements of Example 46, wherein the host data segmentation logic is used to divide the data payload into two N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

[0158] Example 53. This example includes elements of Example 45, wherein assigning each CRC code to another data segment includes assigning each CRC code to a subsequent data segment and assigning the CRC code of the last data segment to the first data segment.

[0159] Example 54. This example includes elements of Example 45, wherein assigning each CRC code to another data segment comprises assigning each CRC code to a preceding data segment and assigning the CRC code of the first data segment to a last data segment.

[0160] Example 55. This example includes elements of Example 45, wherein assigning each CRC code to another data segment includes randomly assigning each CRC code to another data segment.

[0161] Example 56. This example includes a system comprising at least one device arranged to perform the method of any of Examples 9 to 16 or any of Examples 36-38.

[0162] Example 57. This example includes components for performing the method of any of Examples 9 to 16 or any of Examples 36-38.

[0163] Example 58. This example includes a computer-readable storage device having stored thereon instructions that, when executed by one or more processors, cause the following operations, the operations including the method according to any one of Examples 9 to 16 or any one of Examples 36-38.

[0164] The terms and expressions which have been employed herein have been used as terms of description and not of limitation, and in the use of such terms and expressions, there is no intention to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents.

[0165] Various features, aspects and embodiments have been described herein. As will be appreciated by those skilled in the art, features, aspects and embodiments are susceptible to mutual combination and variations and modifications. Therefore, the present disclosure should be deemed to cover such combinations, variations and modifications.

Claims

1. A storage controller, comprising: host data segmentation logic for dividing the data payload into a plurality of data segments in response to a write command from a host domain for writing the data payload to a storage device; Cyclic redundancy check (CRC) encoding logic, the cyclic redundancy check (CRC) encoding logic is used to generate a CRC code for each data segment; as well as CRC reorder encoding logic is used to assign each CRC code to another data segment among the plurality of data segments.

2. The storage controller of claim 1 further comprising segment sectorization logic for dividing each data segment into a plurality of sector length portions; wherein each sector length portion has a bit length based on a sector size of the storage device.

3. The storage controller of claim 2, further comprising error correction code (ECC) encoding logic for generating an ECC code for each sector length portion.

4. A storage controller as described in claim 3, wherein the segment sectorization logic is further used to generate an empty field for each sector length portion except the last sector length portion of the segment, and assemble the empty field and the ECC code of each sector length portion; and further used to assemble the ECC code and the assigned CRC code for the last sector length portion of the segment.

5. The storage controller of claim 1, further comprising: CRC reorder decoding logic for reassigning the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; as well as CRC decoding logic, the CRC decoding logic is used to decode the CRC code of each data segment to determine the data integrity status.

6. The storage controller of claim 3, further comprising: CRC reorder decoding logic for reassigning each CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; CRC decoding logic to decode the CRC code of each data segment to determine a first data integrity status; as well as ECC decoding logic is used to decode the ECC code of each sector length portion to determine a second data integrity state.

7. The storage controller of claim 1, wherein the host data segmentation logic is used to divide the data payload into two N Parts; where N is an integer.

8. The storage controller of claim 2, wherein the host data segmentation logic is used to divide the data payload into two N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

9. A method comprising: In response to a write command from a host domain for writing the data payload to a storage device, dividing the data payload into a plurality of data segments by the host data segmentation logic; Generate a cyclic redundancy check (CRC) code for each data segment through CRC encoding logic; and Each CRC code is assigned to another data segment among the plurality of data segments by CRC reorder encoding logic.

10. The method of claim 9, further comprising: Each segment is divided into a plurality of sector length portions by segment sectorization logic; wherein each sector length portion has a bit length based on a sector size of the storage device.

11. The method of claim 10, further comprising generating an error correction code (ECC) code for each sector length portion by ECC encoding logic.

12. The method of claim 11, further comprising: generating a null field for each sector length portion except for a last sector length portion of a segment, and assembling the null field and the ECC code for each sector length portion; as well as The ECC code and the assigned CRC code are assembled for the last sector length portion of the segment.

13. The method of claim 9, further comprising: reassigning the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; as well as The CRC code of each data segment is decoded by CRC decoding logic to determine the data integrity status.

14. The method of claim 11, further comprising: reassigning, by CRC reorder decoding logic, the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; as well as decoding the CRC code of each data segment by CRC decoding logic to determine a first data integrity status; as well as The ECC code of each sector length portion is decoded by ECC decoding logic to determine a second data integrity state.

15. The method of claim 9, wherein the host data segmentation logic is used to divide the data payload into two N Parts; where N is an integer.

16. The method of claim 10, wherein the host data segmentation logic is used to divide the data payload into two N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

17. A storage system for detecting silent data corruption, comprising: A storage device having a plurality of sectors; as well as A storage controller, the storage controller comprising: host data segmentation logic for dividing the data payload into a plurality of data segments in response to a write command from a host domain for writing the data payload to the storage device; Cyclic redundancy check (CRC) encoding logic, the cyclic redundancy check (CRC) encoding logic is used to generate a CRC code for each data segment; as well as CRC reorder encoding logic is used to assign each CRC code to another data segment among the plurality of data segments.

18. The storage system of claim 17, further comprising segment sectorization logic for dividing each data segment into a plurality of sector length portions; wherein each sector length portion has a bit length based on a sector size of the storage device.

19. The storage system of claim 18, further comprising 11 comprising an error correction code (ECC) encoding logic, the error correction code (ECC) encoding logic being used to generate an ECC code for each sector length portion.

20. A storage system as described in claim 19, wherein the segment sectorization logic is further used to generate an empty field for each sector length portion except the last sector length portion of the segment, and assemble the empty field and the ECC code of each sector length portion; and further used to assemble the ECC code and the assigned CRC code for the last sector length portion of the segment.

21. The storage system of claim 17, further comprising: CRC reorder decoding logic for reassigning the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; as well as CRC decoding logic, the CRC decoding logic is used to decode the CRC code of each data segment to determine the data integrity status.

22. The storage system of claim 19, further comprising: CRC reorder decoding logic, the CRC reorder decoding logic being used to reassign the CRC code of each data segment to a preceding data segment in response to a data read command from the host domain for reading the data payload from the storage device; CRC decoding logic to decode the CRC code of each data segment to determine a first data integrity status; as well as ECC decoding logic is used to decode the ECC code of each sector length portion to determine a second data integrity state.

23. The storage system of claim 17, wherein the host data segmentation logic is used to divide the data payload into two N Parts; where N is an integer.

24. The storage system of claim 18, wherein the host data segmentation logic is used to divide the data payload into two N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

25. A computer-readable storage device having stored thereon instructions which, when executed by one or more processors, cause the following operations, the operations comprising: A method according to any one of claims 9 to 16.

26. An apparatus comprising: means for dividing the data payload into a plurality of data segments by the host data segmentation logic in response to a write command from the host domain for writing the data payload to the storage device; means for generating a cyclic redundancy check (CRC) code for each data segment by means of CRC encoding logic; as well as Means for assigning, by CRC reorder encoding logic, each CRC code to another data segment among the plurality of data segments.

27. The apparatus of claim 26, further comprising: A component is used to divide each segment into a plurality of sector length portions by segment sectorization logic; wherein each sector length portion has a bit length based on a sector size of the storage device.

28. The apparatus of claim 27, further comprising means for generating an error correction code (ECC) code for each sector length portion by an ECC encoding logic.

29. The apparatus of claim 28, further comprising: means for generating a null field for each sector length portion except a last sector length portion of a segment, and assembling said null field and said ECC code for each sector length portion; as well as Means for assembling the ECC code and the assigned CRC code for a last sector length portion of the segment.

30. The apparatus of claim 26, further comprising: means for reassigning the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device; as well as Means for decoding the CRC code of each data segment via CRC decoding logic to determine a data integrity status.

31. The apparatus of claim 28, further comprising: means for reassigning the CRC code of each data segment in response to a data read command from the host domain for reading the data payload from the storage device by CRC reorder decoding logic; as well as means for decoding, by CRC decoding logic, the CRC code of each data segment to determine a first data integrity status; as well as Means for decoding, by ECC decoding logic, the ECC code of each sector length portion to determine a second data integrity state.

32. The apparatus of claim 26, wherein the host data segmentation logic is used to divide the data payload into two N Parts; where N is an integer.

33. The apparatus of claim 27, wherein the host data segmentation logic is used to divide the data payload into two N and wherein the segment sectorization logic is used to divide each data segment into 2 （N+X） wherein N and X are integers.

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