Single-layer polycrystalline EEPROM based on standard CMOS process

Abstract

The present invention discloses a single-layer polycrystalline structure EEPROM, comprising a P-type silicon substrate, a first N-type well and a second N-type well both arranged on the P-type silicon substrate, a coupling capacitor tube and a PMOS transistor; the coupling capacitor tube comprises a first floating gate, a coupling capacitor terminal and a first gate oxide layer, the coupling capacitor terminal and the first gate oxide layer are both arranged on the first N-type well, and the first floating gate is arranged on the first gate oxide layer; the PMOS transistor comprises a second floating gate, a PMOS transistor and a first N-type well both arranged on the second N-type well. + Source doping region, P + Drain doping region, N + The substrate doping region and the second gate oxide layer, the second floating gate is arranged on the second gate oxide layer; the second floating gate is electrically connected to the first floating gate through the floating gate. The single-layer polycrystalline structure EEPROM of the present invention improves the structure of the EEPROM so that it can withstand the operating voltage during erasure, and at the same time can be produced based on the standard CMOS process instead of being limited to certain specific processes, thereby improving the compatibility of the single-layer polycrystalline structure EEPROM and helping to reduce the manufacturing cost.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor storage, and in particular relates to a single-layer polycrystalline EEPROM based on a standard CMOS process. Background Art

[0002] Electrically Erasable Programmable Read-Only Memory (EEPROM) has the characteristics of reversible erasing and writing, fast erasing speed, and no data loss after power failure. It is widely used in embedded memory, Internet of Things and other fields.

[0003] like Figure 1 As shown, it is the circuit diagram of the traditional single-layer polycrystalline structure EEPROM memory. Figure 2 Shown Figure 1 The cross-sectional diagram of the EEPROM memory shown in FIG. The storage unit is composed of NMOS tubes and PMOS tubes. The PMOS tube is used as a coupling capacitor tube, and the NMOS tube is used as a tunnel tube and a readout tube. The PMOS tube is set on an N-type well, the N-type well is set on a P-type silicon substrate, and the NMOS tube is set on a P-type silicon substrate. The gates of the PMOS tube and the NMOS tube are connected as the floating gate of the EEPROM. The NMOS tube of the PMOS tube + doped regions and two P + The doped regions are connected to form a coupling capacitor end (C end); the P + The doped region is grounded, an N + The doped region forms the drain terminal, an N + The doped region forms the source terminal. When performing an erase operation in a traditional single-layer polycrystalline EEPROM memory, a low voltage (0V) is applied to the coupling capacitor terminal (C terminal) of the PMOS tube, a high voltage (10-15V) is applied to the source terminal (S terminal) and the drain terminal (D terminal) of the NMOS tube, and the P-type silicon substrate (Psub) is grounded (0V). For a specific process, this structure of EEPROM can work normally, but in some processes, the NMOS tube's N + source terminal and P-type silicon substrate, and N + The diode formed by the drain terminal and the P-type silicon substrate cannot withstand high voltage, resulting in limitations in practical applications of EEPROMs of this structure. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a single-layer polycrystalline structure EEPROM. By improving the structure of the EEPROM, it can withstand the operating voltage during erasure. At the same time, it can be produced based on a standard CMOS process rather than being limited to certain specific processes, thereby improving the compatibility of the single-layer polycrystalline structure EEPROM and helping to reduce manufacturing costs.

[0005] In order to solve the above technical problems, the present invention provides a single-layer polycrystalline structure EEPROM based on a standard CMOS process, comprising:

[0006] P-type silicon substrate;

[0007] A first N-type well, which is disposed on the P-type silicon substrate;

[0008] A second N-type well, which is disposed on the P-type silicon substrate;

[0009] A coupling capacitor tube, comprising a first floating gate, a coupling capacitor terminal and a first gate oxide layer, wherein the coupling capacitor terminal and the first gate oxide layer are both arranged on the first N-type well, and the first floating gate is arranged on the first gate oxide layer;

[0010] The PMOS transistor is used as a tunneling tube and a readout tube of the EEPROM; it includes a second floating gate, a P + Source doping region, P + Drain doping region, N + The substrate doping region and the second gate oxide layer; the P + Source doping region, P + Drain doping region, N + The substrate doping region and the second gate oxide layer are both arranged on the second N-type well, and the second floating gate is arranged on the second gate oxide layer; the second floating gate is conductively connected to the first floating gate through the floating gate.

[0011] In a preferred embodiment of the present invention, the coupling capacitor is a PMOS transistor, which includes an N-type transistor and an N-type transistor. + doped regions and the two first P + doped region, the N + doped regions and the two first P + The doped regions are conductively connected to form the coupling capacitor terminals.

[0012] In a preferred embodiment of the present invention, the P-type silicon substrate further includes a second P-type well disposed between the first N-type well and the second N-type well. + Doped region.

[0013] In a preferred embodiment of the present invention, the floating gate, the first floating gate and the second floating gate are all single-layer polysilicon structures.

[0014] In a preferred embodiment of the present invention, the first floating gate and the second floating gate are further connected through floating gate conductive connection, so that a first gate oxide layer capacitor formed by the first gate oxide layer and a second gate oxide layer capacitor formed by the second gate oxide layer are connected in series; the coupling coefficient of the coupling capacitor tube is the ratio of the first gate oxide layer capacitor to the second gate oxide layer capacitor.

[0015] In a preferred embodiment of the present invention, the coupling coefficient of the coupling capacitor is 5-15.

[0016] Beneficial effects of the present invention: The single-layer polycrystalline structure EEPROM of the present invention changes the structural design of the traditional single-layer polycrystalline structure EEPROM, uses a PMOS tube as a tunnel tube and a readout tube, and when performing an erase operation, the heavily doped PMOS tube + The source and heavily doped P + There is no voltage drop between the drain terminal and the first N-type well, and the voltage drop is loaded between the diode structure formed by the lightly doped first N-type well that can withstand high voltage and the lightly doped P-type silicon substrate, so that the EEPROM device can withstand the operating high voltage during erasing. At the same time, it can be produced based on standard CMOS process, rather than being limited to certain specific processes, so as to improve the compatibility of single-layer polycrystalline structure EEPROM and help reduce manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is the circuit diagram of the traditional single-layer polycrystalline structure EEPROM memory;

[0018] Figure 2 yes Figure 1 A cross-sectional schematic diagram of the EEPROM memory;

[0019] Figure 3 is a circuit diagram of a single-layer polycrystalline structure EEPROM in a preferred embodiment of the present invention;

[0020] Figure 4 yes Figure 3 A cross-sectional diagram of a single-layer polycrystalline structure EEPROM;

[0021] Figure 5 is an equivalent circuit diagram of a single-layer polycrystalline structure EEPROM in a programming mode in a preferred embodiment of the present invention;

[0022] Figure 6 It is an equivalent circuit diagram of a single-layer polycrystalline structure EEPROM in an erase mode in a preferred embodiment of the present invention.

[0023] Figure 3-4In the diagram: CP1→coupling capacitor; CP2→PMOS; S→PMOS source; D→PMOS drain; W→PMOS N-well substrate; FG→floating gate; GND→0V; C→coupling capacitor; 11a→first floating gate; 11b→second floating gate; 12a→first gate oxide layer; 12b→second gate oxide layer; P + →P-type heavily doped region; N + →N-type heavily doped region; Nwell1→first N-type well; Nwell2→second N-type well; Psub→P-type silicon substrate;

[0024] C1→first gate oxide layer capacitance; C2→second gate oxide layer capacitance. DETAILED DESCRIPTION

[0025] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0026] Example

[0027] like Figure 3-4 As shown, this embodiment discloses a single-layer polycrystalline structure EEPROM, which can be produced based on a standard CMOS process, but is not limited to a specific CMOS process. Its preferred structure is as follows:

[0028] It includes a P-type silicon substrate Psub, a first N-type well Nwell1, a second N-type well Nwell2, a coupling capacitor tube CP1, and a PMOS transistor CP2 used as a tunnel tube and a readout tube. The first N-type well Nwell1 and the second N-type well Nwell2 are formed on the P-type silicon substrate Psub by diffusion or ion implantation; the coupling capacitor tube CP1 is arranged on the first N-type well Nwell1, and the PMOS transistor CP2 is arranged on the second N-type well Nwell2.

[0029] Specifically, the coupling capacitor tube CP1 includes a first floating gate 11a, a coupling capacitor terminal C and a first gate oxide layer 12a. The coupling capacitor terminal C and the first gate oxide layer 12a are both arranged on the first N-type well Nwell1, and the first floating gate 11a is arranged on the first gate oxide layer 12a; the first gate oxide layer 12a forms a first gate oxide layer capacitor, and the first floating gate 11a and the first N-type well Nwell1 respectively form two plates of the first gate oxide layer capacitor.

[0030] The PMOS transistor CP2 includes a second floating gate 11b, a P + Source doping region, P + Drain doping region, N + The substrate doping region and the second gate oxide layer 12b; the above-mentioned P+ Source doping region, P + Drain doping region, N + The substrate doped region and the second gate oxide layer 12b are both formed on the second N-type well Nwell2 by ion implantation, and the second floating gate 11b is arranged on the second gate oxide layer 12b; the second gate oxide layer 12b forms a second gate oxide layer capacitor, and the second floating gate 11b and the second N-type well Nwell2 respectively form two plates of the second gate oxide layer capacitor.

[0031] The second floating gate 11b is conductively connected to the first floating gate 11a through the floating gate FG, so that the first gate oxide layer capacitor and the second gate oxide layer capacitor are connected in series. In the technical solution of this embodiment, the first floating gate 11a, the second floating gate 11b and the floating gate FG are integrally formed using a single layer of polysilicon material in the process to form a floating gate overall structure. The coupling coefficient of the coupling capacitor tube CP1 is the ratio of the first gate oxide layer capacitor to the second gate oxide layer capacitor.

[0032] The coupling capacitor CP1 is used as a capacitor. In one embodiment, the coupling capacitor CP1 is directly a capacitor. In another embodiment, the coupling capacitor CP1 preferably uses a PMOS transistor. Compared with the capacitor, in the technical solution of this embodiment, the coupling capacitor CP1 preferably uses a PMOS transistor. Under the premise of having the same coupling capacitance, the size of the PMOS transistor can be made smaller. The coupling capacitor CP1 using the PMOS tube includes an N-type well Nwell1 formed by ion implantation. + doped regions and the two first P + Doped region, the above N + doped regions and the two first P + The doped regions are conductively connected to form the coupling capacitor terminal C mentioned above.

[0033] In the single-layer polycrystalline EEPROM of the above structure, one PMOS tube is used as a coupling capacitor tube, and one PMOS tube is used as a tunnel tube and a readout tube. The gate ends of the two PMOS tubes are connected to serve as the floating gate of the EEPROM storage unit. The floating gate is mainly used to store charge and is not connected to other parts. The two PMOS tubes are both in an N-type well, and the N-type well is on a P-type silicon substrate. A second P-type well is provided on the P-type silicon substrate between the first N-type well Nwell1 and the second N-type well Nwell2. + The doped region is grounded, and the EEPROM of this structure complies with the standard CMOS process. The coupling coefficient of the coupling capacitor tube CP1 is the ratio of the first gate oxide layer capacitor to the second gate oxide layer capacitor. In the technical solution of this embodiment, the coupling coefficient of the coupling capacitor tube is 5 to 15. The coupling coefficient of the coupling capacitor tube determines the voltage division capability of the first gate oxide layer capacitor and the second gate oxide layer capacitor.

[0034] The single-layer polycrystalline structure EEPROM proposed in the present invention has three operation modes, namely programming mode, erasing mode and reading mode. Table 1 shows the operation voltages of the present invention in different operation modes. The working process of the single-layer polycrystalline structure EEPROM of the present invention is described below in conjunction with Table 1.

[0035] Table 1

[0036] Operation Mode C S D W programming VP 0 0 0 Erase 0 VE VE VE Read VR VDD PullDown VDD

[0037] (I) In programming mode:

[0038] The programming voltage VP is applied to the C terminal of the coupling capacitor tube CP1 (here the programming voltage VP is a high voltage of 10V to 20V), and the source terminal S, the drain terminal D and the substrate W of the PMOS tube CP2 are all applied with a low voltage (0V). The first gate oxide layer capacitor C1 of the coupling capacitor tube CP1 and the second gate oxide layer capacitor C2 of the PMOS tube CP2 are connected in series to divide the voltage. Due to the large coupling coefficient (5 to 15), most of the programming voltage VP acts on the second gate oxide layer capacitor C2 of the PMOS tube CP2.

[0039] In one embodiment of the present application, the coupling coefficient of the coupling capacitor CP1 is selected to be 15 / 2, and the programming voltage VP is 17V. Figure 5 The equivalent circuit diagram in programming mode is shown. In an ideal state, the programming voltage VP has 2V loaded on the first gate oxide capacitor C1, and 15V loaded on the second gate oxide capacitor C2. The potential of the floating gate FG (the first floating gate 11a, the second floating gate 11b, and the floating gate FG are connected, and the three have the same potential) is 15V, and the potential of the second N-type well Nwell2 is 0V (the second N-type well Nwell2 is connected to the substrate W of the PMOS tube CP2 and has the same potential 0V). The electrons in the second N-type well Nwell2 undergo FN tunneling effect under the high electric field strength formed between the floating gate FG and the second N-type well Nwell2 and enter the floating gate FG.

[0040] (II) In erase mode:

[0041] The C terminal of the coupling capacitor tube CP1 is added with a low voltage of 0V, and the source terminal S, the drain terminal D and the substrate W of the PMOS tube CP2 are all added with an erase voltage VE (here, the erase voltage VE is a high voltage of 10V to 20V). The first gate oxide layer capacitor C1 of the coupling capacitor tube CP1 and the second gate oxide layer capacitor C2 of the PMOS tube CP2 are connected in series to divide the voltage. Similarly, due to the large coupling coefficient (5 to 15), most of the erase voltage VE acts on the second gate oxide layer capacitor C2 of the PMOS tube CP2.

[0042] In one embodiment of the present application, the coupling coefficient of the coupling capacitor CP1 is selected to be 15 / 2, and the erase voltage VE is 17V. Figure 6 The equivalent circuit diagram in the erase mode is shown. In an ideal state, the erase voltage VE is 2V loaded on the first gate oxide capacitor C1, and 15V is loaded on the second gate oxide capacitor C2. The potential of the floating gate FG (the first floating gate 11a, the second floating gate 11b, and the floating gate FG are connected, and the three have the same potential) is 2V, and the potential of the second N-type well Nwell2 is 15V (the second N-type well Nwell2 is connected to the substrate W of the PMOS tube CP2 and has the same potential 15V). The electrons in the floating gate FG undergo the FN tunneling effect under the high electric field strength formed between the second N-type well Nwell2 and the floating gate FG, and "run out" from the floating gate FG.

[0043] When performing an erase operation, the source terminal S, the drain terminal D of the PMOS tube CP2 are connected to the substrate W, and the substrate W is connected to the second N-type well Nwell2. + The source terminal S and heavily doped P + There is no voltage drop between the drain terminal D and the second N-type well Nwell2, and the voltage drop is loaded between the diode structure formed by the lightly doped second N-type well Nwell2 and the lightly doped P-type silicon substrate, and the lightly doped second N-type well Nwell2 and the lightly doped P-type silicon substrate Psub can withstand high voltage, so that the EEPROM device can withstand the erase voltage VE (high voltage) during erasure, and at the same time can be produced based on standard CMOS process, rather than being limited to certain specific processes, so as to improve the compatibility of single-layer polycrystalline structure EEPROM and help reduce manufacturing costs.

[0044] (III) In read mode:

[0045] The C terminal of the coupling capacitor tube CP1 is added with a read voltage VR, the source terminal S and the substrate W of the PMOS tube CP2 are both added with the power supply voltage VDD, and the drain terminal D is pulled down. The read voltage VR is less than the power supply voltage VDD, and the drain terminal D of the PMOS tube CP2 is externally connected to a sensitive amplifier circuit to obtain a read current. Since the number of electrons on the floating gate will affect the threshold voltage of the PMOS tube CP2, the state of the storage unit can be determined by the magnitude of the read current.

[0046] The above-described embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Equivalent substitutions or changes made by those skilled in the art based on the present invention are within the protection scope of the present invention. The protection scope of the present invention shall be subject to the claims.

Claims

1. A single-layer polycrystalline EEPROM based on standard CMOS technology, characterized in that: include, P-type silicon substrate; A first N-type well, which is disposed on the P-type silicon substrate; A second N-type well, which is disposed on the P-type silicon substrate; A coupling capacitor tube, comprising a first floating gate, a coupling capacitor terminal and a first gate oxide layer, wherein the coupling capacitor terminal and the first gate oxide layer are both arranged on the first N-type well, and the first floating gate is arranged on the first gate oxide layer; A PMOS transistor, which is used as a tunneling transistor and a readout transistor of the EEPROM; It includes a second floating gate, a P + Source doping region, P + Drain doping region, N + The substrate doping region and the second gate oxide layer; the P + Source doping region, P + Drain doping region, N + The substrate doping region and the second gate oxide layer are both arranged on the second N-type well, and the second floating gate is arranged on the second gate oxide layer; the second floating gate is conductively connected to the first floating gate through the floating gate; wherein the PMOS transistor P + Source doping region, P + Drain doping region and N + The substrate doping regions are all subjected to an erase voltage, wherein the erase voltage is 10V to 20V; The coupling capacitor is a PMOS transistor, which includes an N-type transistor and an N-type transistor. + doped regions and the two first P + doped region, the N + doped regions and the two first P + The doped regions are conductively connected to form the coupling capacitor terminal; The first floating gate and the second floating gate are conductively connected via the floating gate, so that a first gate oxide layer capacitor formed by the first gate oxide layer and a second gate oxide layer capacitor formed by the second gate oxide layer are connected in series; the coupling coefficient of the coupling capacitor tube is the ratio of the first gate oxide layer capacitor to the second gate oxide layer capacitor; The coupling coefficient of the coupling capacitor is 5-15; The P-type silicon substrate is provided with a second P-type well between the first N-type well and the second N-type well. + Doped region.

2. The single-layer polycrystalline EEPROM based on standard CMOS technology as claimed in claim 1, characterized in that: The floating gate, the first floating gate and the second floating gate are all single-layer polysilicon structures.

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