Bit-matrix multiplication

Abstract

The present application discloses bit matrix multiplication. Embodiments of bit matrix multiplication in a processor are detailed. For example, in some embodiments, a processor is described, comprising: decoding circuitry for decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate value; and execution circuitry for executing the decoded instruction to perform a matrix multiplication of S-bit elements of an identified first source bit matrix with S-bit elements of an identified second source bit matrix, wherein a multiplication and accumulation operation is selected by an operation selector and a result of the matrix multiplication is stored in an identified destination bit matrix, wherein S indicates a complex bit size.

Description

Background Art

[0001] Many examples of bioinformatics, software-defined radio, imaging, and cryptography applications (several encryption algorithms, secure hashing, etc.) use bit-matrix multiplication (BMM). When implemented as BMM, operations such as S-box, bit permutation, Hadamard transform, bitwise neural network, Galois field multiplication (used in cryptography and channel coding), and several other operations for bit manipulation can be more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The present invention is illustrated by way of example and not by way of limitation in the accompanying figures and in which like references indicate similar elements and in which:

[0003] Figure 1 Illustrate an embodiment of a selected portion of the execution of a BMM instruction having a source of an 8x8 bit matrix and an 8x64 bit matrix;

[0004] Figure 2 Illustrate an embodiment of a selected portion of execution of a BMM instruction having a source of a 64x8 bit matrix and an 8x8 bit matrix;

[0005] Figure 3 Illustrate an embodiment of a selected portion of execution of a BMM instruction having a source of an 8x64 bit matrix and a 64x64 bit matrix;

[0006] Figure 4 Illustrate an embodiment of a selected portion of execution of a BMM instruction having a source of a 64x64 bit matrix and a 64x8 bit matrix;

[0007] Figure 5 illustrates an embodiment of hardware for processing instructions such as BMM instructions;

[0008] Figure 6 An embodiment of a method for processing a BMM instruction performed by a processor is illustrated;

[0009] Figure 7 A more detailed description of the execution of a BMM instruction is shown;

[0010] Figures 8A-8B is a block diagram illustrating a general vector friendly instruction format and instruction templates thereof according to an embodiment of the present invention;

[0011] Figure 9A is a block diagram illustrating an exemplary specific vector friendly instruction format according to an embodiment of the present invention;

[0012] Figure 9B is a block diagram illustrating the fields of a specific vector friendly instruction format 900 that make up the full opcode field 874 in accordance with one embodiment of the present invention;

[0013] Figure 9C is a block diagram illustrating fields of a specific vector friendly instruction format 900 that make up the register index field 844 according to one embodiment of the present invention;

[0014] Figure 9D is a block diagram illustrating fields of a specific vector friendly instruction format 900 that make up the augmented operation field 850 according to one embodiment of the present invention;

[0015] Figure 10 is a block diagram of a register architecture 1000 according to one embodiment of the present invention;

[0016] Figure 11A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register-renaming out-of-order issue / execution pipeline according to an embodiment of the present invention;

[0017] Figure 11B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the present invention;

[0018] Figure 12A -B is a block diagram illustrating a more specific exemplary in-order core architecture, which would be one of multiple logic blocks in a chip (including other cores of the same and / or different types);

[0019] Figure 13 is a block diagram of a processor 1300 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to an embodiment of the present invention;

[0020] Figure 14 A block diagram illustrating a system according to one embodiment of the present invention;

[0021] Figure 15 is a block diagram of a first more specific exemplary system according to an embodiment of the present invention;

[0022] Figure 16 is a block diagram of a second more specific exemplary system according to an embodiment of the present invention;

[0023] Figure 17 is a block diagram of a SoC according to an embodiment of the present invention; and

[0024] Figure 18 is a block diagram comparing the use of a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In the following description, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the understanding of this description.

[0026] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is understood that it is within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0027] Typically, processor cores are optimized around word processing rather than bit processing, and therefore typically do not support complex bit-level operations.

[0028] Detailed description herein is an embodiment of the BMM instruction and its execution. Depending on the implementation, the instructions detailed herein may use general purpose registers (e.g., 64-bit GPRs), packed data (sometimes referred to as vectors, or single instruction multiple data (SIMD)) registers or register blocks, or memory-based (e.g., 64-bit, 512-bit, 4096-bit, etc.) operands. These instructions are an improvement to the computer itself because they provide support for BMM that was not previously possible. Specifically, the execution of the BMM instruction causes a bit matrix multiplication of two source matrices to be performed, wherein the specific circuits used in the multiplication and addition aspects are selected via the instruction. In some embodiments, element-by-element multiplication is performed using AND, and term-by-term summation is performed using XOR. As described in detail below, the embodiments of the BMM instruction detailed herein have selectable multiplication and / or summation circuits. For example, an immediate number (or other operand(s)) specifies what multiplication and addition circuits will be used in the BMM. Exemplary multiplication Circuits include, but are not limited to, bitwise AND, NAND, XOR, XNOR, and / or NOR. Example addition (⊕) circuits include, but are not limited to, bitwise XOR, NOR, OR, XNOR; majority (1 if majority is 1), and minority. In the following discussion, brackets [] denote specific bit values, represents bitfield multiplication (eg, AND), and ⊕ represents bit accumulation (eg, XOR).

[0029] Figure 1 An embodiment of a selected portion of the execution of a BMM instruction with a source of an 8x8 bit matrix and an 8x64 bit matrix is ​​illustrated. The format of the BMM instruction includes fields for an opcode ("VBMM8x64" is the opcode mnemonic in the illustration), a first source bit matrix operand identifier (shown as "Source 1"), a second source bit matrix operand identifier (shown as "Source 2 / MEM"), an immediate value, and a destination bit matrix operand identifier (shown as "Destination").

[0030] The two source operand fields represent the locations of the first source bit matrix operand 101 and the second source bit matrix operand 103. These locations may be memory locations (eg, addresses in a memory such as a disk or RAM) or one or more registers.

[0031] In this illustration, the first source bit matrix operand 101 is an 8x8 bit matrix. In some embodiments of the BMM instruction, the 8x8 bit matrix is ​​stored in memory or one or more registers as a sequence of eight 8-bit rows starting with row 0. Thus, accessing a bit located in row I, column J of matrix M would be: M[I,J]=M[I*8+J], and if stored in memory: (M[I]>>J)&1.

[0032] In this illustration, the second source bit matrix operand 103 is an 8x64 bit matrix. In some embodiments, the 8x64 bit matrix (eight 64-bit rows) is stored in memory or one or more registers as a sequence of 64-bit rows starting with row 0. Thus, accessing a bit located in row I, column J of matrix M would be: M[I,J]=M[I*64+J] (this is a bit reference, not a byte reference), or differently, to obtain the value of bit M[I,J] stored in memory, one would use (M[I*8]>>J)&1, assuming byte addressing.

[0033] The destination bit matrix operand field represents the destination bit matrix operand 121 storing the result of the bit matrix multiplication operation. As previously detailed, this operand 121 may be stored in a register (eg, a 512-bit register), a register set, or a location in memory.

[0034] As shown, the execution circuit 111 includes multiple multiplication arrays 113 and multiple adder arrays 115. The immediate value of the instruction is used to select the type of multiplication array 113 and the type of adder array 115. For example, in some embodiments, bits 4:7 of the 8-bit immediate value are used by the multiplication selector 117 to select the multiplication circuit from the multiple multiplication arrays 113. For example, imm8[4:7] selects from the exclusive OR (XOR), AND (AND), OR (OR), NOR (NOR), NAND (NAND), and XNOR (XNOR) circuits for multiplication. In some embodiments, bits 0:3 of the 8-bit immediate value are used by the adder selector 119 to select the addition circuit from the multiple adder arrays 115. For example, imm8[0:3] selects from the exclusive OR (XOR), AND (AND), OR (OR), NOR (NOR), and XNOR (XNOR) circuits for addition. Any particular arrangement can be used to signal the selection, however, an exemplary selection table is as follows:

[0035]

[0036] Table 1

[0037] The diagram shows two locations of the calculated results (destination[0] and destination

[168] ). Destination[0] is calculated as follows: The destination is calculated as follows

[168] :

[0038] Figure 2 An embodiment of a selected portion of the execution of a BMM instruction with a source of a 64x8 bit matrix and an 8x8 bit matrix is ​​illustrated. The format of the BMM instruction includes fields for an opcode ("VBMM64x8" is the opcode mnemonic in the illustration), a first source bit matrix operand identifier (shown as "Source 1"), a second source bit matrix operand identifier (shown as "Source 2 / MEM"), an immediate value, and a destination bit matrix operand identifier (shown as "Destination").

[0039] The two source operand fields represent the locations of the first source bit matrix operand 201 and the second source bit matrix operand 203. These locations may be memory locations (eg, addresses in a memory such as a disk or RAM) or one or more registers.

[0040] In this illustration, the first source bit matrix operand 201 is a 64x8 bit matrix. In some embodiments of the BMM instruction, a 64x8 bit matrix (eight 64-bit rows) is stored as a sequence of eight 64-bit rows. Thus, accessing a bit located in row I, column J of matrix M would be: M[I,J]=M[I*64+J] (this is a bit reference, not a byte reference), or differently, to retrieve the value of bit M[I,J] stored in memory, one would use (M[I*8]>>J)&1, assuming byte addressing. Loading this type of matrix into a 512-bit register involves reading from the starting address of the first row.

[0041] In this illustration, the second source bit matrix operand 203 is an 8x8 bit matrix. In some embodiments of the BMM instruction, the 8x8 bit matrix is ​​stored in memory or one or more registers as a sequence of eight 8-bit rows starting with row 0. Thus, accessing a bit located in row I, column J of matrix M would be: M[I,J]=M[I*8+J], and if stored in memory: (M[I]>>J)&1.

[0042] The destination bit matrix operand field represents the destination bit matrix operand 221 storing the result of the bit matrix multiplication operation. As previously detailed, this operand 221 may be stored in a register (eg, a 512-bit register), a register set, or a location in memory.

[0043] As shown, the execution circuit 211 includes multiple multiplication arrays 213 and multiple adder arrays 215. The immediate value of the instruction is used to select the type of multiplication array 213 and the type of adder array 215. For example, in some embodiments, there is a multiplication selector 217 that uses bits 4:7 of the 8-bit immediate value to select a multiplication circuit from the multiple multiplication arrays 213. For example, imm8[4:7] selects from the exclusive OR (XOR), AND (AND), OR (OR), NOR (NOR), NAND (NAND), and XNOR (XNOR) circuits for multiplication. In some embodiments, the adder selector 219 uses bits 0:3 of the 8-bit immediate value to select an addition circuit from the multiple adder arrays 215. For example, imm8[0:3] selects from the exclusive OR (XOR), AND (AND), OR (OR), NOR (NOR), and XNOR (XNOR) circuits for addition. Any particular arrangement can be used to signal the selection, however, an exemplary selection table is as follows:

[0044]

[0045] Table 2

[0046] The diagram shows two locations of the calculated results (destination[0] and destination

[511] ). Destination[0] is calculated as follows: The destination

[511] is calculated as:

[0047] Figure 3 An embodiment of a selected portion of the execution of a BMM instruction with a source of an 8x64 bit matrix and a 64x64 bit matrix is ​​illustrated. The format of the BMM instruction includes fields for an opcode ("VBMM8x64x64" is the opcode mnemonic in the illustration), a first source bit matrix operand identifier (shown as "Source 1"), a second source bit matrix operand identifier (shown as "Source 2 / MEM"), an immediate value, and a destination bit matrix operand identifier (shown as "Destination").

[0048] The two source operand fields represent the locations of the first source bit matrix operand 301 and the second source bit matrix operand 303. These locations may be memory locations (eg, addresses in a memory such as a disk or RAM) or one or more registers.

[0049] In this illustration, the first source bit matrix operand 301 is an 8x64 bit matrix. In some embodiments, the 8x64 bit matrix (eight 64-bit rows) is stored in memory or one or more registers as a sequence of 64-bit rows starting with row 0. Thus, accessing a bit located in row I, column J of matrix M would be: M[I,J]=M[I*64+J] (this is a bit reference, not a byte reference), or differently, to retrieve the value of bit M[I,J] stored in memory, one would use (M[I*8]>>J)&1, assuming byte addressing.

[0050] In this illustration, the second source bit matrix operand 303 is a 64x64 bit matrix. In some embodiments of the BMM instruction, the 64x64 bit matrix is ​​stored in memory as a sequence of 64 64-bit rows starting with row 0. Therefore, to access the bit located in row I, column J of matrix M, one would use: M[I,J]=M[I*64+J] (this is a bit reference, not a byte reference), or differently, to obtain the value of the bit M[I,J] stored in memory, one would use (M[I*8]>>J)&1, assuming byte addressing.

[0051] The destination bit matrix operand field represents the destination bit matrix operand 321 storing the result of the bit matrix multiplication operation. As previously detailed, this operand 321 may be stored in a register (eg, a 512-bit register), a register set, or a location in memory.

[0052] As shown, the execution circuit 311 includes multiple multiplication arrays 313 and multiple adder arrays 315. The immediate value of the instruction is used to select the type of multiplication array 313 and the type of adder array 315. For example, in some embodiments, bits 4:7 of the 8-bit immediate value are used by the multiplication selector 317 to select the multiplication circuit from the multiple multiplication arrays 313. For example, imm8[4:7] selects from the exclusive OR (XOR), AND (AND), OR (OR), NOR (NOR), NAND (NAND), and XNOR (XNOR) circuits for multiplication. In some embodiments, bits 0:3 of the 8-bit immediate value are used by the adder selector 319 to select the addition circuit from the multiple adder arrays 315. For example, imm8[0:3] selects from the exclusive OR (XOR), AND (AND), OR (OR), NOR (NOR), and XNOR (XNOR) circuits for addition. Any particular arrangement can be used to signal the selection, however, an exemplary selection table is as follows:

[0053]

[0054] Table 3

[0055] The diagram shows two locations of the calculated results (destination[0] and destination

[168] ). Destination[0] is calculated as follows: The destination is calculated as follows

[168] :

[0056] Figure 4 An embodiment of a selected portion of the execution of a BMM instruction with a source of a 64x64 bit matrix and a 64x8 bit matrix is ​​illustrated. The format of the BMM instruction includes fields for an opcode ("VBMM8x64x64" is the opcode mnemonic in the illustration), a first source bit matrix operand identifier (shown as "Source 1"), a second source bit matrix operand identifier (shown as "Source 2 / MEM"), an immediate value, and a destination bit matrix operand identifier (shown as "Destination").

[0057] The two source operand fields represent the locations of the first source bit matrix operand 401 and the second source bit matrix operand 403. These locations may be memory locations (eg, addresses in a memory such as a disk or RAM) or one or more registers.

[0058] In this illustration, the first source bit matrix operand 401 is a 64x64 bit matrix. In some embodiments of the BMM instruction, the 64x64 bit matrix is ​​stored in memory as a sequence of 64 64-bit rows starting with row 0. Therefore, to access a bit located in row I, column J of matrix M, one would use: M[I,J]=M[I*64+J] (this is a bit reference, not a byte reference), or differently, to obtain the value of bit M[I,J] stored in memory, one would use (M[I*8]>>J)&1, assuming byte addressing.

[0059] In this illustration, the second source bit matrix operand 403 is a 64x8 bit matrix. In some embodiments of the BMM instruction, a 64x8 bit matrix (eight 64-bit rows) is stored as a sequence of eight 64-bit rows. Thus, accessing a bit located in row I, column J of matrix M would be: M[I,J]=M[I*64+J] (this is a bit reference, not a byte reference), or differently, to retrieve the value of bit M[I,J] stored in memory, one would use (M[I*8]>>J)&1, assuming byte addressing. Loading this type of matrix into a 512-bit register involves reading from the starting address of the first row.

[0060] The destination bit matrix operand field represents the destination bit matrix operand 421 storing the result of the bit matrix multiplication operation. As previously detailed, this operand 421 may be stored in a register (eg, a 512-bit register), a register set, or a location in memory.

[0061] As shown, the execution circuit 411 includes multiple multiplication arrays 413 and multiple adder arrays 415. The immediate value of the instruction is used to select the type of multiplication array 413 and the type of adder array 415. For example, in some embodiments, bits 4:7 of the 8-bit immediate value are used by the multiplication selector 417 to select the multiplication circuit from the multiple multiplication arrays 413. For example, imm8[4:7] selects from the exclusive OR (XOR), AND (AND), OR (OR), NOR (NOR), NAND (NAND), and XNOR (XNOR) circuits for multiplication. In some embodiments, bits 0:3 of the 8-bit immediate value are used by the adder selector 419 to select the addition circuit from the multiple adder arrays 415. For example, imm8[0:3] selects from the exclusive OR (XOR), AND (AND), OR (OR), NOR (NOR), and XNOR (XNOR) circuits for addition. Any particular arrangement can be used to signal the selection, however, an exemplary selection table is as follows:

[0062]

[0063] Table 4

[0064] The diagram shows two locations of the calculated results (destination [0] and destination

[25] ). Destination [0] is calculated as follows: The destination is calculated as follows

[25] :

[0065] In addition, in some embodiments, the multiplication and / or addition operation can be a logic operation (AND / OR / XOR / Same OR / NAND) or an arithmetic operation (addition, subtraction, multiplication) with saturation and without saturation. This can cause various definitions, and some of these definitions can utilize the immediate operand to select and realize as a selector. Thus, some operations can be more than just AND / NAND / etc., but are based on tables. For example, 2 bits can be interpreted as 0, 1, 2, 3 or -0, 1, -2, -1 or 0, 1, invalid, -1. If saturation is enabled, then -1+-1 can be -1, otherwise -2. If it is unsigned 2 bits (-1, 0, 1, no 2), then 1+1 can be 1. These tables can be predefined, and the immediate operand selects one of these tables. AND / NAND is just a special case, and can also be implemented as a table. Table 5 and Table 6 below provide the example of the table of immediate number.

[0066]

[0067] Table 5

[0068]

[0069] Table 6

[0070] Figure 5 An embodiment of hardware for processing instructions such as BMM instructions is illustrated. As shown, storage 503 stores BMM instructions 501 to be executed.

[0071] Instruction 501 is received by decode circuitry 505. For example, decode circuitry 505 receives the instruction from fetch logic / circuitry. The instruction includes fields for an opcode, a first bit matrix source and a second bit matrix source, a destination, and an immediate value. In some embodiments, the source and destination are registers, and in other embodiments, one or more of the source and destination are memory locations.

[0072] More detailed embodiments with at least one instruction format will be described later. Decoding circuitry 505 decodes the instruction into one or more operations. In some embodiments, the decoding includes generating a plurality of micro-operations to be executed by execution circuitry (such as execution circuitry 509). Decoding circuitry 505 also decodes instruction prefixes.

[0073] In some embodiments, the register renaming, register allocation and / or scheduling circuitry 507 provides functionality for one or more of: 1) renaming logical operand values ​​to physical operand values ​​(e.g., a register alias table in some embodiments); 2) assigning status bits and flags to decoded instructions, and 3) scheduling decoded instructions out of an instruction pool for execution on execution circuitry (e.g., using a reservation station in some embodiments).

[0074] Registers (register file) and / or memory 508 store data as operands for instructions to be operated on by execution circuitry 509. Exemplary register types include packed data registers, general purpose registers, and floating point registers.

[0075] The decoded instruction is executed by execution circuitry 509. Execution of the decoded instruction causes the execution circuitry to perform a bit-matrix multiplication on the source bit-matrix, with the specific circuitry used in the multiplication and addition aspects being selected via the instruction.

[0076] In some embodiments, retirement / writeback circuitry 511 architecturally commits the destination register into registers or memory 508 and retires the instruction.

[0077] An example of a format for a BMM instruction is BMMOPCODE DST, SRC1, SRC2, IMM. BMMOPCODE is the opcode for the instruction. Exemplary opcode mnemonics have been detailed above. DST is a field identifying the destination bit matrix operand. SRC1 and SRC2 are one or more fields for source operand identifiers, such as registers, register banks, and / or memory locations. IMM is a field for immediate values. In some embodiments, the operand fields are encoded using the VVVV field 920, MOD R / M 940, and / or SIB 950.

[0078] In some embodiments, the BMM instruction is applied to multiple bit (e.g., 2-bit, 4-bit, and 8-bit) operands. In these embodiments, the opcode defines the bit size to be used, the row and column size of the source, and the row and column size of the destination. The latter size can be seen in the previous example. For example, the opcode V[S]BMM[R1][C1=R2][C2] mnemonic illustrates a method for defining these terms. In this example, [S] indicates the bit size; R1, C1 define the row and column size of the first source bit matrix; C1, C2 define the row and column size of the second source bit matrix; and R1, C2 define the row and column size of the destination bit matrix.

[0079] Examples of these instructions and their functions are detailed below. In each of these examples, the immediate value (imm8) is used as detailed above:

[0080] -V2BMM8x8x32dest,src1,src2 / m512,imm8—multiplies an 8x8, 2-bit matrix (SRC1) by an 8x32, 2-bit matrix (SRC2) and stores the result in an 8x32, 2-bit destination matrix (dest).

[0081] -V2BMM32x8x8dest,src1,src2 / m512,imm8—multiplies a 32x8, 2-bit matrix (SRC1) by an 8x8, 2-bit matrix (SRC2) and stores the result in a 32x8, 2-bit destination matrix (dest).

[0082] -V2BMM8x8x32dest,src1,src2 / m512,imm8—multiplies an 8x8, 2-bit matrix (SRC1) by an 8x32, 2-bit matrix (SRC2) and stores the result in an 8x32, 2-bit destination matrix (dest).

[0083] -V2BMM32x8x8dest,src1,src2 / m512,imm8—multiplies a 32x8, 2-bit matrix (SRC1) by an 8x8, 2-bit matrix (SRC2) and stores the result in a 32x8, 2-bit destination matrix (dest).

[0084] -V2BMM8x32x32dest,src1,mem,imm8—Multiplies an 8x32, 2-bit matrix (src1) with a 32x32, 2-bit matrix in memory (mem) and stores the result in an 8x32, 2-bit destination matrix (dest).

[0085] -V2BMM32x32x8dest,mem,src2,imm8—Multiplies a 32x32, 2-bit matrix in memory (mem) by a 32x8, 2-bit matrix (src2) and stores the result in a 32x8, 2-bit destination matrix (dest).

[0086] -V4BMM8x8x16dest,src1,src2 / m512,imm8—multiplies an 8x8 4-bit matrix (SRC1) by an 8x16 4-bit matrix (SRC2) and stores the result in an 8x16 4-bit destination matrix (dest).

[0087] -V4BMM16x8x8dest,src1,src2 / m512,imm8—multiplies a 16x8 4-bit matrix (SRC1) by an 8x8 4-bit matrix (SRC2) and stores the result in a 16x8 4-bit destination matrix (dest).

[0088] -V4BMM8x16x16dest,src1,mem,imm8—Multiplies an 8x16, 4-bit matrix (src1) with a 16x16, 4-bit matrix in memory (mem) and stores the result in an 8x16, 4-bit destination matrix (dest).

[0089] -V4BMM16x16x8dest,mem,src2,imm8—Multiplies a 16x16 4-bit matrix in memory (mem) by a 16x8 4-bit matrix (src2) and stores the result in a 16x8 4-bit destination matrix (dest).

[0090] In one embodiment, the encoding of the instruction includes a scale-index-base (SIB) type memory addressing operand that indirectly identifies a plurality of indexed destination locations in memory (e.g., field 950). In one embodiment, the SIB type memory operand may include an encoding that identifies a base register. The contents of the base register may represent a base address in memory from which the address of a particular destination location in memory is calculated. For example, the base address may be the address of the first location in a block of possible destination locations for an extend vector instruction. In one embodiment, the SIB type memory operand may include an encoding that identifies an index register. Each element of the index register may specify an index or offset value that can be used to calculate the address of a corresponding destination location within the block of possible destination locations based on the base address. In one embodiment, the SIB type memory operand may include an encoding that specifies a scaling factor to be applied to each index value when calculating the corresponding destination address. For example, if a scaling factor value of 4 is encoded in the SIB type memory operand, each index value obtained from an element of the index register may be multiplied by 4 and then added to the base address to calculate the destination address.

[0091] In one embodiment, a SIB-type memory operand of the form vm32{x,y,z} can identify a vector array of memory operands specified using SIB-type memory addressing. In this example, a common base address register, a constant scaling factor, and a vector index register comprising individual elements (each of which is a 32-bit index value) are used to specify the array of memory addresses. The vector index register can be a 128-bit (e.g., XMM) register (vm32x), a 256-bit (e.g., YMM) register (vm32y), or a 512-bit (e.g., ZMM) register (vm32z). In another embodiment, a SIB-type memory operand of the form vm64{x,y,z} can identify a vector array of memory operands specified using SIB-type memory addressing. In this example, a common base address register, a constant scaling factor, and a vector index register comprising individual elements (each of which is a 64-bit index value) are used to specify the array of memory addresses. The vector index register may be a 128-bit (eg, XMM) register (vm64x), a 256-bit (eg, YMM) register (vm64y), or a 512-bit (eg, ZMM) register (vm64z).

[0092] Example Execution of BMM Instructions

[0093] Figure 6 An embodiment of a method performed by a processor for processing BMM instructions is illustrated.

[0094] At 601, an instruction is fetched. For example, a BMM instruction is fetched. The BMM instruction includes fields for an opcode, a first source bit matrix operand identifier, a second source bit matrix operand identifier, a destination bit matrix operand identifier, and an immediate value. In some embodiments, the instruction is fetched from an instruction cache. The opcode of the BMM instruction indicates the size of the matrix. In some embodiments, the opcode also indicates the bit size involved in the bit matrix multiplication.

[0095] The fetched instruction is decoded at 603. For example, the fetched BMM instruction is decoded by a decoding circuit such as described in detail herein.

[0096] At 605, the data value associated with the identified source operand of the decoded instruction is retrieved (as needed) and the decoded instruction is dispatched. For example, when the identified source operand is a memory operand, data from the indicated memory location is retrieved.

[0097] At 607, the decoded instruction is executed by execution circuitry (hardware), such as described in detail herein. For a BMM instruction, execution causes the execution circuitry to perform a matrix multiplication of the identified first source bit matrix operand and the identified second source bit matrix operand, and to store the result of the matrix multiplication in the identified destination bit matrix operand, wherein the immediate data of the decoded instruction specifies the multiplication and addition circuitry of the execution circuitry to be used in the matrix multiplication.

[0098] In some embodiments, at 609 , the instruction is committed or retired.

[0099] Figure 7 A more detailed description of the execution of a BMM instruction is shown. Typically, this is performed by an execution circuit such as that described in detail above. In some embodiments, execution is achieved based on a state machine implemented in hardware.

[0100] At 701, a multiplication circuit array type is selected based on the immediate value. For example, a multiplication circuit is selected from circuits such as exclusive OR (XOR), AND, OR, NOR, NAND, and XNOR circuits.

[0101] At 703, an addition circuit array type is selected based on the immediate value. For example, an addition circuit is selected from circuits such as exclusive OR (XOR), AND, OR, NOR, and XNOR circuits.

[0102] For each S-bit position of the identified destination operand, a plurality of operations are performed at 705. The "S" value is determined by the opcode and is a value of 1, 2, 4, or 8.

[0103] At 707, the values ​​of the bit positions from the corresponding rows in the identified first source bit matrix are multiplied by the values ​​of the corresponding S bit positions of the corresponding columns in the identified second source bit matrix. These multiplications are performed using the selected multiplication circuits.

[0104] Each of the multiplications are accumulated (added together) at 709. These additions are performed using the selected adding circuitry.

[0105] At 711 , the accumulated result is stored.

[0106] Detailed below are exemplary instruction formats, architectures, and systems that can be used with the instructions detailed above. For example, an exemplary pipeline of support instructions including circuits for executing the methods detailed herein is described.

[0107] instruction set

[0108] An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, bit positions) to specify the operation to be performed (e.g., opcode) and the operand(s) and / or other data fields (e.g., mask) on which the operation is to be performed, among others. Some instruction formats are further decomposed through the definition of instruction templates (or subformats). For example, instruction templates for a given instruction format may be defined as having different subsets of the fields of that instruction format (the included fields are typically in the same order, but at least some fields have different bit positions because fewer fields are included), and / or as having given fields interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, according to a given one of the instruction templates for that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD (addition) instruction has a specific opcode and instruction format, the specific instruction format including an opcode field for specifying the opcode and an operand field for selecting operands (source 1 / destination and source 2); and the ADD instruction appears in an instruction stream with specific contents in the operand field for selecting specific operands. A set of SIMD extensions known as Advanced Vector Extensions (AVX) (AVX1 and AVX2) and utilizing the Vector Extensions (VEX) encoding scheme have been introduced and / or released (see, for example, Intel 1994, September 2014). 64 and IA-32 Architectures Software Developer's Manual; and see the October 2014 Intel Advanced Vector Extensions Programming Reference).

[0109] Example instruction format

[0110] The embodiments of the instruction(s) described herein can be embodied in different formats. In addition, exemplary systems, architectures, and pipelines are described in detail below. The embodiments of the instruction(s) can be executed on such systems, architectures, and pipelines, but are not limited to those described in detail.

[0111] Generic vector-friendly instruction format

[0112] The vector friendly instruction format is an instruction format suitable for vector instructions (e.g., there are specific fields dedicated to vector operations). Although embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations through the vector friendly instruction format.

[0113] Figure 8A-8B is a block diagram illustrating a general vector friendly instruction format and instruction templates thereof according to an embodiment of the present invention. Figure 8Ais a block diagram illustrating a general vector friendly instruction format and its class A instruction template according to an embodiment of the present invention; and Figure 8B 800 is a block diagram illustrating a generic vector friendly instruction format and its class B instruction templates according to an embodiment of the present invention. Specifically, class A and class B instruction templates are defined for the generic vector friendly instruction format 800, both of which include instruction templates with no memory access 805 and instruction templates with memory access 820. The term "generic" in the context of the vector friendly instruction format refers to an instruction format that is not tied to any particular instruction set.

[0114] Although embodiments of the present invention will be described in which the vector friendly instruction format supports: 64-byte vector operand length (or size) with 32-bit (4-byte) or 64-bit (8-byte) data element width (or size) (and thus, a 64-byte vector consists of 16 doubleword-sized elements, or alternatively, 8 quadword-sized elements); 64-byte vector operand length (or size) with 16-bit (2-byte) or 8-bit (1-byte) data element width (or size); 32-byte vector operand length (or size) with 32-bit (4-byte) or 64-bit (8-byte) data element width (or size); byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element width (or size); and 16-byte vector operand length (or size) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element width (or size); however, alternative embodiments may support larger, smaller, and / or different vector operand sizes (e.g., 256-byte vector operands) and larger, smaller, or different data element widths (e.g., 128-bit (16-byte) data element width).

[0115] Figure 8A The Class A instruction templates include: 1) within the instruction templates without memory access 805, there are shown instruction templates for full rounding control type operations 810 without memory access and instruction templates for data transformation type operations 815 without memory access; and 2) within the instruction templates with memory access 820, there are shown instruction templates for temporal memory access 825 and instruction templates for non-temporal memory access 830. Figure 8B The Class B instruction templates include: 1) within the instruction template without memory access 805, an instruction template for a partial rounding control type operation 812 with write mask control without memory access and an instruction template for a vsize type operation 817 with write mask control without memory access are shown; and 2) within the instruction template without memory access 820, an instruction template for a write mask control 827 with memory access is shown.

[0116] The generic vector friendly instruction format 800 includes the following listed in accordance with Figures 8A-8B The following fields are in the order shown in the figure.

[0117] Format field 840 - The specific value in this field (the instruction format identifier value) uniquely identifies the vector friendly instruction format, and thus identifies that the instruction appears in the vector friendly instruction format in the instruction stream. Thus, this field is optional in the sense that it is not required for instruction sets that only have the general vector friendly instruction format.

[0118] Basic operation field 842 - its content distinguishes different basic operations.

[0119] Register index field 844 - its contents specify the location of the source or destination operand in a register or in memory, either directly or through address generation. These fields include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. Although in one embodiment N may be up to three source registers and one destination register, alternative embodiments may support more or fewer source and destination registers (e.g., up to two sources may be supported, one of which may also serve as a destination; up to three sources may be supported, one of which may also serve as a destination; up to two sources and one destination may be supported).

[0120] Modifier field 846 - its content distinguishes instructions appearing in the general vector instruction format that specify memory access from instructions appearing in the general vector instruction format that do not specify memory access; that is, distinguishes between instruction templates with no memory access 805 and instruction templates with memory access 820. Memory access operations read and / or write to the memory hierarchy (in some cases, using values ​​in registers to specify the source and / or destination addresses), while non-memory access operations do not (e.g., the source and destination are registers). Although in one embodiment, this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, fewer, or different ways to perform memory address calculations.

[0121] Extended Operation Field 850 - Its contents distinguish which of various operations are to be performed in addition to the base operation. This field is context-specific. In one embodiment of the present invention, this field is divided into a class field 868, an alpha field 852, and a beta field 854. The extended operation field 850 allows for common groups of operations to be performed in a single instruction rather than two, three, or four instructions.

[0122] Scale field 860 - its content allows for memory address generation (e.g., for use with (2 比例 * The address of (index + base address) is generated by scaling the contents of the index field.

[0123] Displacement field 862A - its contents are used as part of memory address generation (e.g., for use with (2 比例 *Address generation of (index + base address + displacement).

[0124] Displacement Factor field 862B (note that the concatenation of displacement field 862A directly over displacement factor field 862B indicates that one or the other is used) - its contents are used as part of address generation; it specifies the displacement factor by which the size (N) of the memory access will be scaled - where N is the number of bytes in the memory access (e.g., for use with (2 比例 * index + base address + scaled displacement). Redundant low-order bits are ignored, and therefore the contents of the displacement factor field are multiplied by the total size of the memory operand (N) to generate the final displacement to be used in calculating the effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 874 (described later herein) and the data manipulation field 854C. The displacement field 862A and the displacement factor field 862B are optional in the sense that they are not used in instruction templates without memory access 805 and / or different embodiments may implement only one or neither of the two.

[0125] Data element width field 864 - its contents distinguish which of multiple data element widths will be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that it is not required if only one data element width is supported and / or some aspect of the opcode is used to support the data element width.

[0126] Writemask field 870—its contents control, on a per-data-element-position basis, whether the data element positions in the destination vector operand reflect the results of the base and augmented operations. Class A instruction templates support merge-writemasking, while class B instruction templates support both merge-writemasking and zero-writemasking. When merged, the vector mask allows any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base and augmented operations); in another embodiment, the old value of each element of the destination where the corresponding mask bit has a 0 is preserved. Conversely, when zeroed, the vector mask allows any set of elements in the destination to be zeroed during the execution of any operation (specified by the base and augmented operations); in one embodiment, elements of the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span from the first to the last element being modified); however, the modified elements do not necessarily have to be contiguous. Thus, writemask field 870 allows for partial vector operations, including loads, stores, arithmetic, logical, and more. Although embodiments of the present invention are described in which the contents of write mask field 870 select one of a plurality of write mask registers that contains a write mask to be used (and thereby, the contents of write mask field 870 indirectly identify the masking to be performed), alternative embodiments alternatively or additionally allow the contents of mask write field 870 to directly specify the masking to be performed.

[0127] Immediate field 872 - its contents allow specification of an immediate value. This field is optional in the sense that it is not present in implementations that do not support the generic vector friendly format for immediate values ​​and is not present in instructions that do not use immediate values.

[0128] Class field 868 - its content distinguishes between instructions of different classes. Figure 8A-8B , the content of this field selects between class A and class B instructions. Figure 8A-8B In , a rounded square is used to indicate that a specific value exists in a field (for example, in Figure 8A-8B Class A 868A and Class B 868B for class field 868, respectively).

[0129] Class A instruction template

[0130] In the case of the class A non-memory access 805 instruction templates, the α field 852 is interpreted as an RS field 852A whose content distinguishes which of the different extended operation types is to be performed (e.g., the instruction templates for the no-memory access rounding operation 810 and the no-memory access data transformation operation 815 specify rounding 852A.1 and data transformation 852A.2, respectively), while the β field 854 distinguishes which of the specified types of operations is to be performed. In the no-memory access 805 instruction templates, the scale field 860, the displacement field 862A, and the displacement scale field 862B are not present.

[0131] Instruction templates with no memory access – fully rounded control type operations

[0132] In the instruction templates for the no-memory-access, full-round-controlled operation 810, the beta field 854 is interpreted as a round control field 854A that provides static rounding for its contents. Although in the described embodiment of the invention, the round control field 854A includes a suppress all floating-point exceptions (SAE) field 856 and a round operation control field 858, alternative embodiments may support both concepts, may encode both concepts into the same field, or may have only one or the other of these concepts / fields (e.g., may have only the round operation control field 858).

[0133] SAE field 856 - its content distinguishes whether exception event reporting is disabled; when the content of SAE field 856 indicates that suppression is enabled, the given instruction does not report any kind of floating point exception flags and does not invoke any floating point exception handler.

[0134] Round operation control field 858 - its contents distinguish which of a set of rounding operations is to be performed (e.g., round up, round down, round toward zero, and round to nearest). Thus, the round operation control field 858 allows the rounding mode to be changed on an instruction-by-instruction basis. In one embodiment of the present invention in which the processor includes a control register for specifying the rounding mode, the contents of the round operation control field 850 override the register value.

[0135] Instruction templates without memory access - data transformation operations

[0136] In instruction templates for data transform type operations 815 with no memory access, the beta field 854 is interpreted as a data transform field 854B, the contents of which distinguish which of multiple data transforms is to be performed (eg, no data transform, blend, broadcast).

[0137] In the case of an instruction template of type A memory access 820, the alpha field 852 is interpreted as an eviction hint field 852B, the contents of which distinguish which of the eviction hints is to be used (in Figure 8A In the example, the instruction templates for memory access temporal 825 and memory access non-temporal 830 specify temporal 852B.1 and non-temporal 852B.2, respectively, and the beta field 854 is interpreted as a data manipulation field 854C, the contents of which distinguish which of a plurality of data manipulation operations (also known as primitives) is to be performed (e.g., no manipulation, broadcast, upcast of the source, and downcast of the destination). The instruction template for memory access 820 includes a scale field 860 and optionally includes a displacement field 862A or a displacement scale field 862B.

[0138] Vector memory instructions use the translation support to perform vector loads from memory and vector stores to memory. Like normal vector instructions, vector memory instructions transfer data to and from memory in an element-wise manner, where the actual elements transferred are specified by the contents of the vector mask selected as the writemask.

[0139] Memory access instruction templates - time-sensitive

[0140] Temporal data is data that is likely to be reused quickly enough to benefit from cache operations. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint completely.

[0141] Memory access instruction templates - non-temporal

[0142] Non-temporal data is data that is unlikely to be reused quickly enough to benefit from cache operations in the first level cache and should be given eviction priority. However, this is a hint, and different processors can implement it in different ways, including ignoring the hint completely.

[0143] Class B instruction template

[0144] In the case of class B instruction templates, the alpha field 852 is interpreted as a write mask control (Z) field 852C, the contents of which distinguish whether the write mask controlled by the write mask field 870 should be merge or zero.

[0145] In the case of the B-type non-memory access 805 instruction templates, a portion of the β field 854 is interpreted as the RL field 857A, the contents of which distinguish which of the different extended operation types is to be performed (e.g., the instruction templates for the no-memory-access write mask control partial rounding control type operation 812 and the instruction templates for the no-memory-access write mask control VSIZE type operation 817 specify rounding 857A.1 and vector length (VSIZE) 857A.2, respectively), while the remainder of the β field 854 distinguishes which of the specified types of operations is to be performed. In the no-memory-access 805 instruction templates, the scale field 860, the displacement field 862A, and the displacement scale field 862B are not present.

[0146] In the instruction template for the write mask control partial round control type operation 810 without memory access, the remainder of the beta field 854 is interpreted as the round operation field 859A, and exception event reporting is disabled (the given instruction does not report any kind of floating point exception flags and does not invoke any floating point exception handler).

[0147] Round Operation Control Field 859A - As with round operation control field 858, its contents distinguish which of a set of rounding operations (e.g., round up, round down, round toward zero, and round to nearest) is to be performed. Thus, round operation control field 859A allows the rounding mode to be changed on an instruction-by-instruction basis. In one embodiment of the present invention in which the processor includes a control register for specifying the rounding mode, the contents of round operation control field 850 override the register value.

[0148] In the instruction template for the write mask control VSIZE type operation 817 without memory access, the remainder of the β field 854 is interpreted as a vector length field 859B, the contents of which distinguish which of multiple data vector lengths is to be performed (e.g., 128 bytes, 256 bytes, or 512 bytes).

[0149] In the case of a class B memory access 820 instruction template, a portion of the beta field 854 is interpreted as a broadcast field 857B, the contents of which distinguish whether a broadcast-type data manipulation operation is to be performed, while the remainder of the beta field 854 is interpreted as a vector length field 859B. The memory access 820 instruction template includes a scale field 860 and optionally includes a displacement field 862A or a displacement scale field 862B.

[0150] For the generic vector friendly instruction format 800, the full opcode field 874 is shown to include the format field 840, the base operation field 842, and the data element width field 864. Although one embodiment is shown in which the full opcode field 874 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 874 includes less than all of these fields. The full opcode field 874 provides an operation code (opcode).

[0151] The augment operation field 850, the data element width field 864, and the write mask field 870 allow these features to be specified on an instruction-by-instruction basis in the generic vector friendly instruction format.

[0152] The combination of the write mask field and the data element width field creates various types of instructions because these instructions allow the mask to be applied based on different data element widths.

[0153] The various instruction templates found within classes A and B are beneficial in different situations. In some embodiments of the present invention, different processors or different cores within a processor may support only class A, only class B, or both classes. For example, a high-performance general-purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and / or scientific (throughput) computing may support only class A, and a core intended for both general-purpose computing and graphics and / or scientific (throughput) computing may support both classes A and B (of course, cores with some mix of templates and instructions from both classes, but not all templates and instructions from both classes, are within the scope of the present invention). Similarly, a single processor may include multiple cores, all of which support the same class, or where different cores support different classes. For example, in a processor with separate graphics and general-purpose cores, one of the graphics cores intended primarily for graphics and / or scientific computing may support only class A, while one or more of the general-purpose cores may be a high-performance general-purpose core with out-of-order execution and register renaming intended for general-purpose computing that supports only class B. Another processor that does not have a separate graphics core may include one or more general-purpose in-order or out-of-order cores that support both Class A and Class B. Of course, in different embodiments of the invention, features from one class may also be implemented in the other class. A program written in a high-level language will be made (e.g., just-in-time or statically compiled) into a variety of different executable forms, including: 1) a form with only instructions of the class(es) supported by the target processor for execution; or 2) a form with alternative routines written using different combinations of instructions from all classes and with control flow code that selects these routines to execute based on the instructions supported by the processor currently executing the code.

[0154] Exemplary dedicated vector friendly instruction format

[0155] Figure 9A is a block diagram illustrating an exemplary specific vector friendly instruction format according to an embodiment of the present invention. Figure 9A A specific vector friendly instruction format 900 is shown that specifies the location, size, interpretation, and order of various fields, as well as the values ​​of some of those fields. The specific vector friendly instruction format 900 is specific in the sense that it specifies the location, size, interpretation, and order of various fields, as well as the values ​​of some of those fields. The specific vector friendly instruction format 900 can be used to extend the x86 instruction set, and thus some of the fields are similar or identical to those used in the existing x86 instruction set and its extensions (e.g., AVX). The format remains consistent with the prefix encoding field, real opcode byte field, MOD R / M field, SIB field, displacement field, and immediate field of the existing x86 instruction set with extensions. The fields from FIG. 8 are shown, and the fields from Figure 9A The fields of are mapped to the fields from Figure 8.

[0156] It should be understood that although embodiments of the present invention are described with reference to the specific vector friendly instruction format 900 in the context of the general vector friendly instruction format 800 for illustrative purposes, the present invention is not limited to the specific vector friendly instruction format 900 unless otherwise stated. For example, the general vector friendly instruction format 800 contemplates various possible sizes for various fields, while the specific vector friendly instruction format 900 illustrates fields having specific sizes. As a specific example, although the data element width field 864 is illustrated as a one-bit field in the specific vector friendly instruction format 900, the present invention is not limited thereto (i.e., the general vector friendly instruction format 800 contemplates other sizes for the data element width field 864).

[0157] The generic vector friendly instruction format 800 includes the following listed in accordance with Figure 9A The following fields are in the order shown in the figure.

[0158] EVEX prefix (bytes 0-3) 902 - encoded in four bytes.

[0159] Format field 840 (EVEX byte 0, bits [7:0]) - The first byte (EVEX byte 0) is the format field 840, and it contains 0x62 (a unique value used to distinguish the vector friendly instruction format in one embodiment of the present invention).

[0160] The second through fourth bytes (EVEX bytes 1-3) include a number of bit fields that provide specific capabilities.

[0161] REX field 905 (EVEX byte 1, bits [7-5]) - consists of the EVEX.R bit field (EVEX byte 1, bits [7]-R), the EVEX.X bit field (EVEX byte 1, bits [6]-X), and (857BEX byte 1, bits [5]-B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit fields and are encoded using 1's complement form, i.e., ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. The other fields of these instructions encode the lower three bits of the register index (rrr, xxx, and bbb) as known in the art, whereby Rrrr, Xxxx, and Bbbb can be formed by adding EVEX.R, EVEX.X, and EVEX.B.

[0162] REX' field 810 - This is the first portion of the REX' field 810 and is the EVEX.R' bit field (EVEX byte 1, bit [4] - R') used to encode the upper 16 or lower 16 registers of the extended 32 register set. In one embodiment of the present invention, this bit is stored in a bit-reversed format along with the other bits indicated below to distinguish it (in 32-bit mode of the well-known x86) from the BOUND instruction, which has a real opcode byte of 62 but does not accept a value of 11 in the MOD field in the MODR / M field (described below); alternative embodiments of the present invention do not store this indicated bit and the other indicated bits below in a reversed format. A value of 1 is used to encode the lower 16 registers. In other words, R'Rrrr is formed by combining EVEX.R', EVEX.R, and the other RRRs from the other fields.

[0163] Opcode map field 915 (EVEX byte 1, bits [3:0] – mmmm) - its contents encode the implied leading opcode byte (0F, 0F 38, or 0F 3).

[0164] Data element width field 864 (EVEX byte 2, bit [7] – W) – denoted by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the data type (32-bit data element or 64-bit data element).

[0165] EVEX.vvvv 920 (EVEX byte 2, bits [6:3]-vvvv) - The role of EVEX.vvvv may include the following: 1) EVEX.vvvv encodes the first source register operand specified in inverted (ones complement) form and is valid for instructions with two or more source operands; 2) EVEX.vvvv encodes the destination register operand specified in one's complement form for a specific vector displacement; or 3) EVEX.vvvv does not encode any operand, this field is reserved and should contain 1111b. Thus, EVEX.vvvv field 920 encodes the four low-order bits of the first source register designator stored in inverted (ones complement) form. Depending on the instruction, additional different EVEX bit fields are used to extend the designator size to 32 registers.

[0166] EVEX.U 868 Class field (EVEX byte 2, bit [2] - U) - If EVEX.U = 0, it indicates Class A or EVEX.U0; if EVEX.U = 1, it indicates Class B or EVEX.U1.

[0167] Prefix encoding field 925 (EVEX byte 2, bits [1:0]-pp) - provides additional bits for the base operation field. In addition to supporting legacy SSE instructions in EVEX prefix format, this also has the benefit of compressing the SIMD prefix (the EVEX prefix only requires 2 bits, rather than requiring a byte to express the SIMD prefix). In one embodiment, to support legacy SSE instructions using SIMD prefixes (66H, F2H, F3H) in both legacy and EVEX prefix formats, these legacy SIMD prefixes are encoded into the SIMD prefix encoding field; and at runtime, they are expanded into legacy SIMD prefixes before being provided to the decoder's PLA (thus, the PLA can execute these legacy instructions in both legacy and EVEX format without modification). While newer instructions may use the contents of the EVEX prefix encoding field directly as an opcode extension, for consistency, certain embodiments expand in a similar manner, but allow for different meanings specified by these legacy SIMD prefixes. Alternative embodiments may redesign the PLA to support 2-bit SIMD prefix encodings, thereby eliminating the need for expansion.

[0168] Alpha field 852 (EVEX byte 3, bit [7] - EH, also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.WriteMaskControl, and EVEX.N; also illustrated as alpha) - As previously described, this field is context specific.

[0169] Beta field 854 (EVEX byte 3, bits [6:4] - SSS, also known as EVEX.s 2-0 EVEX.r 2-0 , EVEX.rr1, EVEX.LL0, EVEX.LLB, also illustrated as βββ) - As mentioned earlier, this field is context-specific.

[0170] REX' field 810 - This is the remainder of the REX' field and is the EVEX.V' bit field (EVEX byte 3, bit [3] - V') that can be used to encode the upper 16 or lower 16 registers of the extended 32 register set. This bit is stored in a bit-reversed format. A value of 1 is used to encode the lower 16 registers. In other words, V'VVVV is formed by combining EVEX.V', EVEX.vvvv.

[0171] Write mask field 870 (EVEX byte 3, bits [2:0] - kkk) - its contents specify the index of a register in the write mask register, as previously described. In one embodiment of the invention, the special value EVEX.kkk = 000 has special behavior that implies no write mask is used for the particular instruction (this can be implemented in various ways, including using a write mask hardwired to all objects or hardware that bypasses the masking hardware).

[0172] The real opcode field 930 (byte 4) is also called the opcode byte. A portion of the opcode is specified in this field.

[0173] The MOD R / M field 940 (byte 5) includes a MOD field 942, a Reg field 944, and an R / M field 946. As previously described, the contents of the MOD field 942 distinguish memory access operations from non-memory access operations. The role of the Reg field 944 can be summarized as follows: encoding a destination register operand or a source register operand; or being treated as an opcode extension and not used to encode any instruction operand. The role of the R / M field 946 can include the following: encoding an instruction operand that references a memory address; or encoding a destination register operand or a source register operand.

[0174] Scale, Index, Base (SIB) Byte (Byte 6) - As previously described, the contents of the scale field 850 are used for memory address generation. SIB.xxx 954 and SIB.bbb 956 - The contents of these fields have been mentioned previously for register indices Xxxx and Bbbb.

[0175] Displacement field 862A (bytes 7-10) - When the MOD field 942 contains 10, bytes 7-10 are the displacement field 862A, and it works the same as a traditional 32-bit displacement (disp32) and works at byte granularity.

[0176] Displacement Factor Field 862B (Byte 7)—When MOD field 942 contains 01, byte 7 is the displacement factor field 862B. This field is located in the same location as the traditional x86 instruction set 8-bit displacement (disp8), which operates at byte granularity. Because disp8 is sign-extended, it can only address offsets between -128 and 127 bytes. In terms of a 64-byte cache line, disp8 uses 8 bits that can be set to only four truly useful values: 128, -64, 0, and 64. Because a larger range is often needed, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, displacement factor field 862B is a reinterpretation of disp8. When displacement factor field 862B is used, the actual displacement is determined by multiplying the contents of the displacement factor field by the size (N) of the memory operand being accessed. This type of displacement is referred to as disp8*N. This reduces the average instruction length (a single byte is used for the displacement, but with a much larger range). This type of compressed displacement is based on the assumption that the effective displacement is a multiple of the granularity of the memory access, and thus the redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field 862B replaces the traditional x86 instruction set 8-bit displacement. Thus, the displacement factor field 862B is encoded in the same manner as the x86 instruction set 8-bit displacement (thus, there is no change in the ModRM / SIB encoding rules), the only difference being that disp8 is overloaded to disp8*N. In other words, there is no change in the encoding rules or encoding length, only in the hardware's interpretation of the displacement value (which requires scaling the displacement by the size of the memory operand to obtain a byte-based address offset). The immediate field 872 operates as previously described.

[0177] Full opcode field

[0178] Figure 9B 874 of the specific vector friendly instruction format 900. Specifically, the full opcode field 874 includes a format field 840, a base operation field 842, and a data element width (W) field 864. The base operation field 842 includes a prefix encoding field 925, an opcode map field 915, and a real opcode field 930.

[0179] Register index field

[0180] Figure 9C844, a MODR / Mr / m field 946, a VVVV field 920, a xxx field 954, and a bbb field 956.

[0181] Expand the operation field

[0182] Figure 9D 852A.1) is a block diagram illustrating the fields of the specific vector friendly instruction format 900 that make up the extended operation field 850 according to one embodiment of the present invention. When the class (U) field 868 contains 0, it indicates EVEX.U0 (class A 868A); when it contains 1, it indicates EVEX.U1 (class B 868B). When U=0 and the MOD field 942 contains 11 (indicating a no memory access operation), the alpha field 852 (EVEX byte 3, bit [7] - EH) is interpreted as the rs field 852A. When the rs field 852A contains 1 (round 852A.1), the beta field 854 (EVEX byte 3, bits [6:4] - SSS) is interpreted as the round control field 854A. The round control field 854A includes a one-bit SAE field 856 and a two-bit round operation field 858. When the rs field 852A contains 0 (data transformation 852A.2), the beta field 854 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a three-bit data transformation field 854B. When U=0 and the MOD field 942 contains 00, 01, or 10 (indicating a memory access operation), the alpha field 852 (EVEX byte 3, bits [7]-EH) is interpreted as an eviction hint (EH) field 852B, and the beta field 854 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a three-bit data manipulation field 854C.

[0183] When U=1, the alpha field 852 (EVEX byte 3, bit [7]–EH) is interpreted as the write mask control (Z) field 852C. When U=1 and the MOD field 942 contains 11 (indicating no memory access operation), a portion of the beta field 854 (EVEX byte 3, bit [4]–S0) is interpreted as the RL field 857A; when it contains 1 (rounded 857A.1), the remainder of the beta field 854 (EVEX byte 3, bits [6-5]–S0) is interpreted as the RL field 857A. 2-1 ) is interpreted as the rounding operation field 859A, and when the RL field 857A contains 0 (VSIZE 857.A2), the remainder of the beta field 854 (EVEX byte 3, bits [6-5]-S 2-1) is interpreted as the vector length field 859B (EVEX byte 3, bits [6-5]–L 1-0 When U=1 and the MOD field 942 contains 00, 01, or 10 (indicating a memory access operation), the beta field 854 (EVEX byte 3, bits [6:4]–SSS) is interpreted as the vector length field 859B (EVEX byte 3, bits [6-5]–L 1-0 ) and the broadcast field 857B (EVEX byte 3, bit [4]–B).

[0184] Exemplary Register Architecture

[0185] Figure 10 1 is a block diagram of a register architecture 1000 according to one embodiment of the present invention. In the illustrated embodiment, there are 32 512-bit wide vector registers 1010; these registers are referenced as zmm0 through zmm31. The lower-order 256 bits of the lower 16 zmm registers are overlaid on registers ymm0-16. The lower-order 128 bits of the lower 16 zmm registers (the lower-order 128 bits of the ymm registers) are overlaid on registers xmm0-15. The specific vector friendly instruction format 900 operates on these overlaid register files, as illustrated in the following table.

[0186]

[0187] In other words, the vector length field 859B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the previous length, and instruction templates that do not have a vector length field 859B operate on the maximum vector length. Furthermore, in one embodiment, the class B instruction templates of the dedicated vector friendly instruction format 900 operate on packed or scalar single / double precision floating point data and packed or scalar integer data. Scalar operations are operations performed on the lowest-order data element position in the zmm / ymm / xmm register; depending on the embodiment, higher-order data element positions either remain the same as before the instruction or are reset to zero.

[0188] Write mask registers 1015 - In the illustrated embodiment, there are eight write mask registers (k0 through k7), each 64 bits in size. In an alternative embodiment, the write mask registers 1015 are 16 bits in size. As previously mentioned, in one embodiment of the present invention, vector mask register k0 cannot be used as a write mask; when the encoding that normally indicates k0 is used as a write mask, it selects a hardwired write mask of 0xFFFF, effectively disabling write masking for that instruction.

[0189] General purpose registers 1025 - In the embodiment shown, there are sixteen 64-bit general purpose registers that are used with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0190] A scalar floating-point stack register file (x87 stack) 1045, on which an MMX packed integer flat register file 1050 is overlaid—in the illustrated embodiment, the x87 stack is an eight-element stack used to perform scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set extension; while MMX registers are used to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between MMX and XMM registers.

[0191] Alternative embodiments of the present invention may use wider or narrower registers. Additionally, alternative embodiments of the present invention may use more, fewer, or different register files and registers.

[0192] Exemplary Core Architectures, Processors, and Computer Architectures

[0193] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a specialized core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU that includes one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor that includes one or more specialized cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as dedicated logic or as a dedicated core, such as integrated graphics and / or scientific (throughput) logic); and 4) a system on a chip, which may include the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessor described above, and additional functionality on the same die. An exemplary core architecture is described next, followed by a description of an exemplary processor and computer architecture.

[0194] Exemplary Core Architecture

[0195] In-order and out-of-order core block diagram

[0196] Figure 11A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register-renaming out-of-order issue / execution pipeline according to various embodiments of the present invention. Figure 11B is a block diagram illustrating an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue / execution architecture core to be included in a processor according to embodiments of the present invention. Figures 11A-11B The solid line boxes in illustrate the in-order pipeline and in-order core, while the optional addition of dashed line boxes illustrates the register renaming, out-of-order issue / execution pipeline and core. Considering that the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0197] exist Figure 11A , the processor pipeline 1100 includes a fetch stage 1102, a length decode stage 1104, a decode stage 1106, an allocation stage 1108, a rename stage 1110, a schedule (also known as dispatch or issue) stage 1112, a register read / memory read stage 1114, an execute stage 1116, a write back / memory write stage 1118, an exception handling stage 1122, and a commit stage 1124.

[0198] Figure 11B A processor core 1190 is shown, comprising a front end unit 1130 coupled to an execution engine unit 1150, and both the front end unit 1130 and the execution engine unit 1150 are coupled to a memory unit 1170. The core 1190 may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 1190 may be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general purpose computing graphics processing unit (GPGPU) core, a graphics core, and the like.

[0199] Front end unit 1130 includes a branch prediction unit 1132, which is coupled to an instruction cache unit 1134, which is coupled to an instruction translation lookaside buffer (TLB) 1136, which is coupled to an instruction fetch unit 1138, which is coupled to a decode unit 1140. Decode unit 1140 (or decoder) can decode an instruction and generate as output one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from, reflect, or derived from the original instruction. Decode unit 1140 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), and the like. In one embodiment, core 1190 includes a microcode ROM or other medium (e.g., in decode unit 1140 or otherwise within front end unit 1130) that stores microcode for certain macroinstructions. The decode unit 1140 is coupled to the rename / allocator unit 1152 in the execution engine unit 1150 .

[0200] Execution engine unit 1150 includes a rename / allocator unit 1152 coupled to a retirement unit 1154 and a set of one or more scheduler units 1156. Scheduler unit(s) 1156 represent any number of different schedulers, including reservation stations, central instruction windows, and the like. Scheduler unit(s) 1156 are coupled to physical register file(s) units 1158. Each of physical register file(s) units 1158 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating point, packed integers, packed floating point, vector integers, vector floating point, state (e.g., an instruction pointer, which is the address of the next instruction to be executed), and the like. In one embodiment, physical register file(s) units 1158 include a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general purpose registers. Physical register file(s) units 1158 are overlapped by retirement unit 1154 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using reorder buffer(s) and retirement register file(s); using future file(s), history buffer(s), retirement register file(s); using register maps and register pools, etc.). Retirement unit 1154 and physical register file(s) units 1158 are coupled to execution cluster(s) 1160. Execution cluster(s) 1160 include a set of one or more execution units 1162 and a set of one or more memory access units 1164. Execution units 1162 can perform various operations (e.g., shifts, additions, subtractions, multiplications) and can operate on various data types (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point). While some embodiments may include multiple execution units dedicated to a particular function or set of functions, other embodiments may include only one execution unit or multiple execution units that all perform all functions. Scheduler unit(s) 1156, physical register file(s) 1158, and execution cluster(s) 1160 are shown as potentially multiple because some embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline, each with its own scheduler unit, physical register file(s) and / or execution cluster—and in the case of separate memory access pipelines, certain embodiments are implemented in which only the execution cluster of that pipeline has memory access unit(s) 1164). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, and the remaining pipelines may be in-order.

[0201] A set of memory access units 1164 is coupled to a memory unit 1170, which includes a data TLB unit 1172, which is coupled to a data cache unit 1174, which is coupled to a level 2 (L2) cache unit 1176. In one exemplary embodiment, the memory access unit 1164 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 1172 in the memory unit 1170. The instruction cache unit 1134 is also coupled to a level 2 (L2) cache unit 1176 in the memory unit 1170. The L2 cache unit 1176 is coupled to one or more other levels of cache and ultimately to main memory.

[0202] As an example, the exemplary register renaming out-of-order issue / execution core architecture may implement the pipeline 1100 as follows: 1) instruction fetch 1138 executes the fetch stage 1102 and the length decode stage 1104; 2) the decode unit 1140 executes the decode stage 1106; 3) the rename / allocator unit 1152 executes the allocate stage 1108 and the rename stage 1110; 4) (multiple) scheduler units 1156 execute the schedule stage 1112; 5) (multiple) physical register file units 1158 and memory units 1170 execute the register read / memory read stage 1114; the execution cluster 1160 executes the execute stage 1116; 6) the memory unit 1170 and the (multiple) physical register file units 1158 execute the write back / memory write stage 1118; 7) each unit may be involved in the exception handling stage 1122; and 8) the retirement unit 1154 and the (multiple) physical register file units 1158 execute the commit stage 1124.

[0203] Core 1190 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set from MIPS Technologies, Inc. of Sunnyvale, California; the ARM instruction set from ARM Holdings, Inc. of Sunnyvale, California (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one embodiment, core 1190 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0204] It should be understood that a core may support multithreading (executing two or more sets of operations or threads in parallel) and that this multithreading may be accomplished in a variety of ways, including time-shared multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that the physical core is simultaneously multithreading), or a combination thereof (e.g., time-shared fetch and decode and later generations such as Intel Hyper-Threading (Simultaneous Multithreading).

[0205] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiment of the processor also includes separate instruction and data cache units 1134 / 1174 and a shared L2 cache unit 1176, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a first level (L1) internal cache or multiple levels of internal cache. In some embodiments, the system may include a combination of internal caches and external caches external to the core and / or processor. Alternatively, all caches may be external to the core and / or processor.

[0206] Specific exemplary in-order core architecture

[0207] Figures 12A-12B A block diagram illustrating a more specific exemplary in-order core architecture is shown, which would be one logic block among several logic blocks in a chip (including other cores of the same and / or different types). Depending on the application, the logic block communicates with some fixed function logic, memory I / O interfaces, and other necessary I / O logic via a high-bandwidth interconnect network (e.g., a ring network).

[0208] Figure 12A 1 is a block diagram of a single processor core and its connection to the on-die interconnect network 1202 and its local subset 1204 of the second level (L2) cache according to an embodiment of the present invention. In one embodiment, the instruction decoder 1200 supports the x86 instruction set with the packed data instruction set extension. The L1 cache 1206 allows low-latency access to cache memory in the scalar and vector units. Although in one embodiment (to simplify the design), the scalar unit 1208 and the vector unit 1210 use separate register sets (scalar registers 1212 and vector registers 1214, respectively), and data transferred between these registers is written to memory and then read back from the first level (L1) cache 1206, alternative embodiments of the present invention may use different approaches (e.g., using a single register set or including a communication path that allows data to be transferred between the two register files without being written and read back).

[0209] The local subset 1204 of the L2 cache is part of the global L2 cache, which is divided into multiple separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 1204 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 1204 and can be quickly accessed in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 1204 and flushed from other subsets when necessary. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide in each direction.

[0210] Figure 12B According to an embodiment of the present invention Figure 12A An expanded view of a portion of a processor core in FIG. Figure 12B Includes the L1 data cache 1206A portion of the L1 cache 1204, as well as more details about the vector unit 1210 and vector registers 1214. Specifically, the vector unit 1210 is a 16-wide vector processing unit (VPU) (see 16-wide ALU 1228) that executes one or more of integer, single-precision floating-point, and double-precision floating-point instructions. The VPU supports blending of register inputs via blend unit 1220, numerical conversion via numerical conversion units 1222A-B, and copying of memory inputs via copy unit 1224. Write mask register 1226 allows for predicted vector writes.

[0211] Figure 13 is a block diagram of a processor 1300 that may have more than one core, may have an integrated memory controller, and may have integrated graphics according to an embodiment of the present invention. Figure 13 The solid line box in the figure illustrates a processor 1300 having a single core 1302A, a system agent 1310, a set 1316 of one or more bus controller units, while the optional addition of the dashed line box illustrates an alternative processor 1300 having multiple cores 1302A-N, a set 1314 of one or more integrated memory controller units in the system agent unit 1310, and dedicated logic 1308.

[0212] Thus, different implementations of processor 1300 may include: 1) a CPU, wherein specialized logic 1308 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 1302A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two); 2) a coprocessor, wherein cores 1302A-N are a large number of specialized cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor, wherein cores 1302A-N are a large number of general-purpose in-order cores. Thus, processor 1300 may be a general-purpose processor, a coprocessor, or a specialized processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many-integrated-core (MIC) coprocessor (including 30 or more cores), an embedded processor, or the like. The processor may be implemented on one or more chips. Processor 1300 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a variety of process technologies (such as, for example, BiCMOS, CMOS, or NMOS).

[0213] The memory hierarchy includes one or more cache levels within the core, a set of one or more shared cache units 1306, and external memory (not shown) coupled to a set of integrated memory controller units 1314. The set of shared cache units 1306 may include one or more intermediate levels of cache, such as a second level (L2), a third level (L3), a fourth level (L4), or other levels of cache, a last level cache (LLC), and / or combinations thereof. While in one embodiment, a ring-based interconnect unit 1312 interconnects the integrated graphics logic 1308 (which is an example of dedicated logic and is also referred to herein as dedicated logic), the set of shared cache units 1306, and the system agent unit 1310 / integrated memory controller unit(s) 1314, alternative embodiments may use any number of well-known techniques to interconnect such units. In one embodiment, coherency is maintained between the one or more cache units 1306 and the cores 1302A-N.

[0214] In some embodiments, one or more cores 1302A-N may be multithreaded. System agent 1310 includes components that coordinate and operate cores 1302A-N. System agent unit 1310 may include, for example, a power control unit (PCU) and a display unit. The PCU may include or include the logic and components required to regulate the power state of cores 1302A-N and integrated graphics logic 1308. The display unit is used to drive one or more externally connected displays.

[0215] The cores 1302A-N may be homogeneous or heterogeneous with respect to architectural instruction sets; that is, two or more of the cores 1302A-N may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of the instruction set or a different instruction set.

[0216] Exemplary Computer Architecture

[0217] Figure 14-17 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network appliances, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, a wide variety of systems or electronic devices that can include a processor and / or other execution logic as disclosed herein are generally suitable.

[0218] Now refer to Figure 14 , a block diagram of a system 1400 according to one embodiment of the present invention is shown. System 1400 may include one or more processors 1410, 1415 coupled to a controller hub 1420. In one embodiment, controller hub 1420 includes a graphics memory controller hub (GMCH) 1490 and an input / output hub (IOH) 1450 (which may be on separate chips); GMCH 1490 includes memory and a graphics controller, to which memory 1440 and coprocessor 1445 are coupled; and IOH 1450 couples input / output (I / O) devices 1460 to GMCH 1490. Alternatively, one or both of the memory and graphics controller are integrated within the processor (as described herein), with memory 1440 and coprocessor 1445 coupled directly to processor 1410, and controller hub 1420 and IOH 1450 being on a single chip.

[0219] The optional addition of processor 1415 is Figure 14 Each processor 1410 , 1415 may include one or more of the processing cores described herein and may be a version of processor 1300 .

[0220] The memory 1440 may be, for example, dynamic random access memory (DRAM), phase change memory (PCM), or a combination of the two. For at least one embodiment, the controller hub 1420 communicates with the processor(s) 1410, 1415 via a multi-drop bus such as a front-side bus (FSB), a point-to-point interface such as a Quick Path Interconnect (QPI), or similar connection 1495.

[0221] In one embodiment, the coprocessor 1445 is a special purpose processor such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, etc. In one embodiment, the controller hub 1420 may include an integrated graphics accelerator.

[0222] There may be various differences between the physical resources 1410 , 1415 in terms of a range of quality metrics including architectural, microarchitectural, thermal, and power consumption characteristics.

[0223] In one embodiment, processor 1410 executes instructions that control general types of data processing operations. Embedded within these instructions may be coprocessor instructions. Processor 1410 recognizes these coprocessor instructions as being of a type that should be executed by attached coprocessor 1445. Accordingly, processor 1410 issues these coprocessor instructions (or control signals representing coprocessor instructions) to coprocessor 1445 over a coprocessor bus or other interconnect. Coprocessor(s) 1445 accept and execute the received coprocessor instructions.

[0224] Now see Figure 15 , shown is a block diagram of a first more specific exemplary system 1500 according to an embodiment of the present invention. Figure 15 As shown in FIG, multiprocessor system 1500 is a point-to-point interconnect system and includes a first processor 1570 and a second processor 1580 coupled via a point-to-point interconnect 1550. Each of processors 1570 and 1580 may be a version of processor 1300. In one embodiment of the invention, processors 1570 and 1580 are processors 1410 and 1415, respectively, and coprocessor 1538 is coprocessor 1445. In another embodiment, processors 1570 and 1580 are processor 1410 and coprocessor 1445, respectively.

[0225] Processors 1570 and 1580 are shown as including integrated memory controller (IMC) units 1572 and 1582, respectively. Processor 1570 also includes point-to-point (PP) interfaces 1576 and 1578 as part of its bus controller unit; similarly, second processor 1580 includes PP interfaces 1586 and 1588. Processors 1570, 1580 can exchange information via PP interface 1550 using point-to-point (PP) interface circuits 1578, 1588. Figure 15 As shown in FIG, IMCs 1572 and 1582 couple the processors to respective memories, namely, memory 1532 and memory 1534, which may be portions of main memory locally attached to the respective processors.

[0226] Processors 1570, 1580 may each exchange information with a chipset 1590 via respective PP interfaces 1552, 1554 using point-to-point interface circuits 1576, 1594, 1586, 1598. Chipset 1590 may optionally exchange information with a coprocessor 1538 via a high-performance interface 1592. In one embodiment, coprocessor 1538 is a special-purpose processor such as, for example, a high-throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, or the like.

[0227] A shared cache (not shown) may be included in either processor, or external to both processors but connected to the processors via the PP interconnect, such that if the processors are placed in a low power mode, local cache information of either or both processors may be stored in the shared cache.

[0228] Chipset 1590 may be coupled to first bus 1516 via interface 1596. In one embodiment, first bus 1516 may be a Peripheral Component Interconnect (PCI) bus or a bus such as PCI Express or another third generation I / O interconnect bus, although the scope of the invention is not limited in this regard.

[0229] like Figure 15, various I / O devices 1514 may be coupled to the first bus 1516, along with a bus bridge 1518 that couples the first bus 1516 to a second bus 1520. In one embodiment, one or more additional processors 1515, such as a coprocessor, a high throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor, are coupled to the first bus 1516. In one embodiment, the second bus 1520 may be a low pin count (LPC) bus. In one embodiment, various devices may be coupled to the second bus 1520, including, for example, a keyboard and / or mouse 1522, communication devices 1527, and a storage unit 1528, such as a disk drive or other mass storage device, which may include instructions / code and data 1530. Additionally, an audio I / O 1524 may be coupled to the second bus 1520. Note that other architectures are possible. For example, instead of Figure 15 Instead of a point-to-point architecture, the system can implement a multi-drop bus or other such architecture.

[0230] Now refer to Figure 16 , shown is a block diagram of a second more specific exemplary system 1600 according to an embodiment of the present invention. Figure 15 and 16 Similar elements in the same reference numerals are used, and Figure 16 Omitted Figure 15 Some aspects of the Figure 16 other aspects.

[0231] Figure 16 The illustrated processors 1570, 1580 may respectively include integrated memory and I / O control logic ("CL") 1572 and 1582. Thus, the CL 1572, 1582 includes an integrated memory controller unit and includes I / O control logic. Figure 16 The illustration shows not only memories 1532, 1534 coupled to CLs 1572, 1582, but also I / O devices 1614 coupled to control logic 1572, 1582. Legacy I / O devices 1615 are coupled to chipset 1590.

[0232] Now refer to Figure 17 , which is a block diagram of a SoC 1700 according to an embodiment of the present invention. Figure 13 Similar elements in the FIGURE 1 use similar reference numerals. In addition, the dashed boxes are optional features on more advanced SoCs. Figure 17, interconnect unit(s) 1702 are coupled to: an application processor 1710, which includes a set of one or more cores 1302A-N and a shared cache unit(s) 1306, the set of one or more cores 1302A-N including cache units 1304A-N; a system agent unit 1310; bus controller unit(s) 1316; integrated memory controller unit(s) 1314; a set of one or more coprocessors 1720, which may include integrated graphics logic, image processors, audio processors, and video processors; a static random access memory (SRAM) unit 1730; a direct memory access (DMA) unit 1732; and a display unit 1740 for coupling to one or more external displays. In one embodiment, coprocessor(s) 1720 include special-purpose processors such as, for example, a network or communication processor, a compression engine, a GPGPU, a high-throughput MIC processor, or an embedded processor, among others.

[0233] The various embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementations. Embodiments of the present invention may be implemented as a computer program or program code executed on a programmable system comprising at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0234] Program code (such as Figure 15 The code 1530 illustrated in FIG. 15 is applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0235] The program code can be implemented in a high-level process-oriented programming language or an object-oriented programming language to communicate with the processing system. If necessary, the program code can also be implemented in assembly language or machine language. In fact, the mechanism described herein is not limited to the scope of any specific programming language. In any case, the language can be a compiled language or an interpreted language.

[0236] One or more aspects of at least one embodiment may be implemented as representative instructions stored on a machine-readable medium that represent various logic within a processor, which, when read by a machine, causes the machine to fabricate logic for performing the techniques described herein. Such representations, known as "IP cores," may be stored on a tangible, machine-readable medium and supplied to various customers or manufacturing facilities to load into fabrication machines that actually manufacture the logic or processor.

[0237] Such machine-readable storage media may include, but are not limited to, a non-transitory, tangible arrangement of an article of manufacture manufactured or formed by a machine or apparatus, including storage media such as a hard disk; any other type of disk, including a floppy disk, an optical disk, a compact disk read only memory (CD-ROM), a compact disk rewritable (CD-RW), and a magneto-optical disk; a semiconductor device, such as a read-only memory (ROM), a random access memory (RAM) such as a dynamic random access memory (DRAM) and a static random access memory (SRAM), an erasable programmable read-only memory (EPROM), flash memory, an electrically erasable programmable read-only memory (EEPROM); a phase change memory (PCM); a magnetic or optical card; or any other type of medium suitable for storing electronic instructions.

[0238] Therefore, embodiments of the present invention also include non-transitory tangible machine-readable media containing instructions or containing design data, such as hardware description language (HDL), which defines the structures, circuits, devices, processors and / or system features described herein. These embodiments are also referred to as program products.

[0239] Simulation (including binary conversion, code deformation, etc.)

[0240] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may transform (e.g., using static binary transformation, dynamic binary transformation including dynamic compilation), morph, emulate, or otherwise convert an instruction into one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on-processor, off-processor, or partially on-processor and partially off-processor.

[0241] Figure 18 1 is a block diagram illustrating a method for converting binary instructions in a source instruction set into binary instructions in a target instruction set using a software instruction converter according to an embodiment of the present invention. In the illustrated embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 18It is shown that an x86 compiler 1804 can be used to compile a program in a high-level language 1802 to generate x86 binary code 1806 that can be natively executed by a processor 1816 having at least one x86 instruction set core. A processor 1816 having at least one x86 instruction set core represents any processor that performs substantially the same functionality as an Intel processor having at least one x86 instruction set core by compatibly executing or otherwise performing: 1) an essential portion of the instruction set of the Intel x86 instruction set core, or 2) an object code version of an application or other software that is targeted to run on an Intel processor having at least one x86 instruction set core to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The x86 compiler 1804 represents a compiler that is operable to generate x86 binary code 1806 (e.g., object code) that can be executed on a processor 1816 having at least one x86 instruction set core with or without additional linking processing. Similarly, Figure 18 An alternative instruction set compiler 1808 is shown as being used to compile a program in a high-level language 1802 to generate alternative instruction set binary code 1810 that can be natively executed by a processor 1814 that does not have at least one x86 instruction set core (e.g., a processor having a core that executes the MIPS instruction set of MIPS Technologies, Inc., of Sunnyvale, California, and / or the ARM instruction set of ARM Holdings, Inc., of Sunnyvale, California). An instruction converter 1812 is used to convert the x86 binary code 1806 into code that can be natively executed by the processor 1814 that does not have an x86 instruction set core. This converted code is unlikely to be identical to the alternative instruction set binary code 1810, as an instruction converter capable of doing so would be difficult to manufacture; however, the converted code will perform general operations and be composed of instructions from the alternative instruction set. Thus, the instruction converter 1812 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device that does not have an x86 instruction set processor or core to execute the x86 binary code 1806, through emulation, simulation, or any other process.

[0242] Examples of various embodiments are described in detail below.

[0243] Example 1: A processor comprising: a decoding circuit for decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate value; and an execution circuit for: executing the decoded instruction to perform a bit matrix multiplication of the identified first source bit matrix and the identified second source bit matrix, wherein a multiplication and accumulation operation is selected by an operation selector; and storing a result of the bit matrix multiplication in the identified destination bit matrix.

[0244] Example 2. The processor of Example 1, wherein the operation selector is an 8-bit immediate value.

[0245] Example 3. The processor of any of Examples 1-2, wherein four bits of the immediate value are used to select an accumulation operation from the group of exclusive OR (XOR), AND (AND), OR (OR), and NOR (NOR).

[0246] Example 4. The processor of any of Examples 1-2, wherein four bits of the immediate value are used to select a multiplication operation from the group of exclusive-or (XOR), and (AND), or (OR), and not-or (NOR).

[0247] Example 5. The processor of any of Examples 1-4, wherein the identified first source matrix is ​​an 8x8 bit matrix and the identified second source bit matrix is ​​an 8x64 bit matrix.

[0248] Example 6. The processor of any of Examples 1-4, wherein the identified first source matrix is ​​a 64x8 bit matrix and the identified second source bit matrix is ​​an 8x8 bit matrix.

[0249] Example 7. The processor of any of Examples 1-4, wherein the identified first source matrix is ​​an 8x64 bit matrix and the identified second source bit matrix is ​​a 64x64 bit matrix.

[0250] Example 8. The processor of any of Examples 1-7, wherein the identified second source bit matrix is ​​stored in a memory.

[0251] Example 9. The processor of any of Examples 1-4, wherein the identified first source matrix is ​​a 64x8 bit matrix and the identified second source bit matrix is ​​a 64x8 bit matrix.

[0252] Example 10. The processor of any of Examples 1-8, wherein the identified first source bit matrix is ​​stored in a memory.

[0253] Example 11. The processor of any of Examples 1-10, wherein the bit matrix multiplication comprises: for each bit position in the destination, multiplying the value of each bit position from the corresponding row in the identified first source bit matrix by the value of the corresponding S bit position of the corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing the accumulated results.

[0254] Example 12. A processor comprising: decoding circuitry for decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate value; and execution circuitry for: executing the decoded instruction to perform a matrix multiplication of S-bit elements of the identified first source bit matrix and S-bit elements of the identified second source bit matrix, wherein a multiplication and accumulation operation is selected by an operation selector; and storing a result of the matrix multiplication in an identified destination bit matrix, wherein S indicates a complex bit size.

[0255] Example 13. The processor of Example 12, wherein S indicates a bit size of 1, 2, 4, or 8.

[0256] Example 14. The processor of any of Examples 12-13, wherein the operation selector is an 8-bit immediate value.

[0257] Example 15. The processor of any of Examples 12-14, wherein four bits of the immediate value are used to select an accumulation operation from the group of exclusive OR (XOR), AND, OR, and NOR.

[0258] Example 16. The processor of any of Examples 12-15, wherein four bits of the immediate value are used to select a multiplication operation from the group of exclusive OR (XOR), AND, OR, and NOR.

[0259] Example 17. The processor of any of Examples 12-16, wherein the identified first source matrix is ​​an 8x8 bit matrix and the identified second source bit matrix is ​​an 8x64 bit matrix.

[0260] Example 18. The processor of any of Examples 12-16, wherein the identified first source matrix is ​​a 64x8 bit matrix and the identified second source matrix is ​​an 8x8 bit matrix.

[0261] Example 19. The processor of any of Examples 12-16, wherein the identified first source matrix is ​​an 8x64 bit matrix and the identified second source bit matrix is ​​a 64x64 bit matrix.

[0262] Example 20. The processor of any of Examples 12-19, wherein the identified second source bit matrix is ​​stored in a memory.

[0263] Example 21. The processor of any of Examples 12-16, wherein the identified first source matrix is ​​a 64x8 bit matrix and the identified second source bit matrix is ​​a 64x8 bit matrix.

[0264] Example 22. The processor of any of Examples 12-21, wherein the identified first source bit matrix is ​​stored in a memory.

[0265] Example 23. The processor of any of Examples 12-22, wherein the bit matrix multiplication comprises: for each S-bit position group in the destination, multiplying the S-bit group value of each S-bit position group of the corresponding row in the identified first source bit matrix by the value of the corresponding S-bit position group of the corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing the accumulated results.

[0266] Example 24. A method comprising:

[0267] decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate value; and executing the decoded instruction to: perform a matrix multiplication of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, where a multiplication and accumulation operation is selected by an operation selector; and store a result of the matrix multiplication in the identified destination bit matrix, where S indicates a complex bit size.

[0268] Example 25. The method of Example 24, wherein S indicates a bit size of 1, 2, 4, or 8.

[0269] Example 26. The method of any of Examples 24-25, wherein the operation selector is an 8-bit immediate value.

[0270] Example 27. The method of any of Examples 24-26, wherein four bits of the immediate value are used to select an accumulation operation from the group of exclusive OR (XOR), AND (AND), OR (OR), and NOR (NOR).

[0271] Example 28. The method of any of Examples 24-27, wherein four bits of the immediate value are used to select a multiplication operation from the group of exclusive OR (XOR), AND, OR, and NOR.

[0272] Example 29. The method of any of Examples 24-28, wherein the identified first source matrix is ​​an 8x8 bit matrix and the identified second source bit matrix is ​​an 8x64 bit matrix.

[0273] Example 30. The method of any of Examples 24-28, wherein the identified first source matrix is ​​a 64x8 bit matrix and the identified second source matrix is ​​an 8x8 bit matrix.

[0274] Example 31. The method of any of Examples 24-28, wherein the identified first source matrix is ​​an 8x64 bit matrix and the identified second source bit matrix is ​​a 64x64 bit matrix.

[0275] Example 32. The method of any of Examples 24-31, wherein the identified second source bit matrix is ​​stored in a memory.

[0276] Example 33. The method of any of Examples 24-27, wherein the identified first source matrix is ​​a 64x8 bit matrix and the identified second source matrix is ​​a 64x8 bit matrix.

[0277] Example 34. The method of any of Examples 24-33, wherein the identified first source bit matrix is ​​stored in a memory.

[0278] Example 35. The method of any of Examples 24-34, wherein the bit matrix multiplication comprises: for each S-bit position group in the destination, multiplying the S-bit group value of each S-bit position group of the corresponding row in the identified first source bit matrix by the value of the corresponding S-bit position group of the corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing the accumulated results.

[0279] Example 36. A non-transitory machine-readable medium storing instructions that, when executed by a processor, cause the processor to perform a method comprising: decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate value; and executing the decoded instruction to: perform a matrix multiplication of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein a multiply and accumulate operation is selected by an operation selector; and storing a result of the matrix multiplication in an identified destination bit matrix, wherein S indicates a complex bit size.

[0280] Example 37. The non-transitory machine-readable medium of Example 36, wherein S indicates a bit size of 1, 2, 4, or 8.

[0281] Example 38. The non-transitory machine-readable medium of any of Examples 36-37, wherein the operation selector is an 8-bit immediate value.

[0282] Example 39. The non-transitory machine-readable medium of any of Examples 36-38, wherein four bits of the immediate value are used to select an accumulation operation from the group of exclusive OR (XOR), AND (AND), OR (OR), and NOR (NOR).

[0283] Example 40. The non-transitory machine-readable medium of any of Examples 36-39, wherein four bits of the immediate value are used to select a multiplication operation from the group of exclusive OR (XOR), AND, OR, and NOR.

[0284] Example 41. The non-transitory machine-readable medium of any of Examples 36-40, wherein the identified first source matrix is ​​an 8x8 bit matrix and the identified second source bit matrix is ​​an 8x64 bit matrix.

[0285] Example 42. The non-transitory machine-readable medium of any of Examples 36-40, wherein the identified first source matrix is ​​a 64x8 bit matrix and the identified second source bit matrix is ​​an 8x8 bit matrix.

[0286] Example 43. The non-transitory machine-readable medium of any of Examples 36-40, wherein the identified first source matrix is ​​an 8x64 bit matrix and the identified second source bit matrix is ​​a 64x64 bit matrix.

[0287] Example 44. The non-transitory machine-readable medium of any of Examples 36-40, wherein the identified second source bit matrix is ​​stored in a memory.

[0288] Example 45. The non-transitory machine-readable medium of any of Examples 36-40, wherein the identified first source matrix is ​​a 64x8 bit matrix and the identified second source bit matrix is ​​a 64x8 bit matrix.

[0289] Example 46. The non-transitory machine-readable medium of any of Examples 36-45, wherein the identified first source bit matrix is ​​stored in a memory.

[0290] Example 47. A non-transitory machine-readable medium as in any of Examples 36-46, wherein the bit matrix multiplication comprises: for each S-bit position group in the destination, multiplying the S-bit group value of each S-bit position group of the corresponding row in the identified first source bit matrix by the value of the corresponding S-bit position group of the corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing the accumulated results.

[0291] Example 48. An apparatus comprising: decoding means for decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate value; and executing means for executing the decoded instruction to: perform a matrix multiplication of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, wherein a multiplication and accumulation operation is selected by an operation selector; and store a result of the matrix multiplication in an identified destination bit matrix, wherein S indicates a complex bit size.

[0292] Example 49. The apparatus of Example 48, wherein S indicates a bit size of 1, 2, 4, or 8.

[0293] Example 50. The apparatus of any of Examples 48-49, wherein the operation selector is an 8-bit immediate value.

[0294] Example 51. The apparatus of any of Examples 48-50, wherein four bits of the immediate value are used to select an accumulation operation from the group of exclusive-or (XOR), and (AND), or (OR), and not-or (NOR).

[0295] Example 52. The apparatus of any of Examples 48-51, wherein four bits of the immediate value are used to select a multiplication operation from the group of exclusive-or (XOR), and (AND), or (OR), and not-or (NOR).

[0296] Example 53. The apparatus of any of Examples 48-52, wherein the identified first source matrix is ​​an 8x8 bit matrix and the identified second source bit matrix is ​​an 8x64 bit matrix.

[0297] Example 54. The apparatus of any of Examples 48-52, wherein the identified first source matrix is ​​a 64x8 bit matrix and the identified second source matrix is ​​an 8x8 bit matrix.

[0298] Example 55. The apparatus of any of Examples 48-52, wherein the identified first source matrix is ​​an 8x64 bit matrix and the identified second source bit matrix is ​​a 64x64 bit matrix.

[0299] Example 56. The apparatus of any of Examples 48-55, wherein the identified second source bit matrix is ​​stored in a memory.

[0300] Example 57. The apparatus of any of Examples 48-52, wherein the identified first source matrix is ​​a 64x8 bit matrix and the identified second source matrix is ​​a 64x8 bit matrix.

[0301] Example 58. The apparatus of any of Examples 48-57, wherein the identified first source bit matrix is ​​stored in a memory.

[0302] Example 59. The apparatus of any of Examples 48-58, wherein the bit matrix multiplication comprises: for each S-bit position group in the destination, multiplying the S-bit group value of each S-bit position group of the corresponding row in the identified first source bit matrix by the value of the corresponding S-bit position group of the corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing the accumulated results.

Claims

1. A processor, comprising: a decoding circuit for decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate value; as well as The execution circuit is configured to: execute the decoded instruction to perform a bit matrix multiplication of the identified first source bit matrix and the identified second source bit matrix, wherein a multiplication and accumulation operation is selected by an operation selector; and store a result of the bit matrix multiplication in the identified destination bit matrix.

2. The processor according to claim 1, wherein The operation selector is an 8-bit immediate value.

3. The processor according to any one of claims 1 to 2, wherein: The four bits of the immediate value are used to select an accumulation operation in the group of XOR, AND, OR and NOR.

4. The processor according to any one of claims 1 to 2, wherein: The four bits of the immediate value are used to select a multiplication operation in the group of XOR, AND, OR, and NOR.

5. The processor according to any one of claims 1 to 2, wherein: The identified first source matrix is ​​an 8x8 bit matrix and the identified second source bit matrix is ​​an 8x64 bit matrix.

6. The processor according to any one of claims 1 to 2, wherein: The identified first source matrix is ​​a 64x8 bit matrix and the identified second source bit matrix is ​​an 8x8 bit matrix.

7. The processor according to any one of claims 1 to 2, wherein: The identified first source matrix is ​​an 8x64 bit matrix, and the identified second source bit matrix is ​​a 64x64 bit matrix.

8. The processor according to any one of claims 1 to 2, wherein: The identified second source bit matrix is ​​stored in a memory.

9. The processor according to any one of claims 1 to 2, wherein: The identified first source matrix is ​​a 64x8 bit matrix, and the identified second source bit matrix is ​​a 64x8 bit matrix.

10. The processor according to any one of claims 1 to 2, wherein: The identified first source bit matrix is ​​stored in a memory.

11. The processor according to any one of claims 1 to 2, wherein: The bit matrix multiplication includes: for each bit position in the destination, multiplying the value of each bit position from the corresponding row in the identified first source bit matrix by the value of the corresponding S bit position of the corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing the accumulated results.

12. A processor comprising: a decoding circuit for decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate value; as well as An execution circuit is configured to: execute the decoded instruction to perform a matrix multiplication of S-bit elements of the identified first source bit matrix and S-bit elements of the identified second source bit matrix, wherein a multiplication and accumulation operation is selected by an operation selector; and store a result of the matrix multiplication in the identified destination bit matrix, wherein S indicates a complex bit size.

13. The processor of claim 12, wherein: S indicates the bit size is 1, 2, 4, or 8.

14. The processor according to any one of claims 12 to 13, wherein: The operation selector is an 8-bit immediate value.

15. The processor according to any one of claims 12 to 13, wherein: The four bits of the immediate value are used to select an accumulation operation in the group of XOR, AND, OR and NOR.

16. The processor according to any one of claims 12 to 13, wherein: The four bits of the immediate value are used to select a multiplication operation in the group of XOR, AND, OR, and NOR.

17. The processor according to any one of claims 12 to 13, wherein: The identified first source matrix is ​​an 8x8 bit matrix and the identified second source bit matrix is ​​an 8x64 bit matrix.

18. The processor according to any one of claims 12 to 13, wherein: The identified first source matrix is ​​a 64x8 bit matrix and the identified second source bit matrix is ​​an 8x8 bit matrix.

19. The processor according to any one of claims 12 to 13, wherein: The identified first source matrix is ​​an 8x64 bit matrix, and the identified second source bit matrix is ​​a 64x64 bit matrix.

20. The processor according to any one of claims 12 to 13, wherein: The identified second source bit matrix is ​​stored in a memory.

21. The processor according to any one of claims 12 to 13, wherein: The identified first source matrix is ​​a 64x8 bit matrix, and the identified second source bit matrix is ​​a 64x8 bit matrix.

22. The processor according to any one of claims 12 to 13, wherein: The identified first source bit matrix is ​​stored in a memory.

23. The processor according to any one of claims 12 to 13, wherein: The bit matrix multiplication includes: for each S-bit position group in the destination, multiplying the S-bit group value of each S-bit position group of the corresponding row in the identified first source bit matrix by the value of the corresponding S-bit position group of the corresponding column in the identified second source bit matrix, accumulating each of the multiplications, and storing the accumulated results.

24. A method comprising: decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate value; as well as The decoded instruction is executed to: perform a matrix multiplication of S-bit elements of the identified first source bit matrix with S-bit elements of the identified second source bit matrix, where a multiplication and accumulation operation is selected by the operation selector; and store a result of the matrix multiplication in the identified destination bit matrix, where S indicates a complex bit size.

25. A device comprising: Decoding means for decoding an instruction having fields for an opcode, an identifier of a first source bit matrix, an identifier of a second source bit matrix, an identifier of a destination bit matrix, and an immediate value; as well as An execution device is configured to: execute the decoded instruction to perform a matrix multiplication of S-bit elements of the identified first source bit matrix and S-bit elements of the identified second source bit matrix, wherein a multiplication and accumulation operation is selected by an operation selector; and store a result of the matrix multiplication in the identified destination bit matrix, wherein S indicates a complex bit size.

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