Heterogeneous interconnect with linear and nonlinear conductive pathways

Abstract

Disclosed herein are electrical interconnects having nonlinear conductive pathways, and related apparatuses and methods. In some embodiments, an electrical interconnect can include a nonlinear conductive pathway electrically coupling a top conductive portion and a bottom conductive portion. In some embodiments, an electrical interconnect can include a nonlinear conductive pathway that propagates an electrical signal that generates an electromagnetic field having an electric field that is orthogonal to a direction of electromagnetic wave propagation. In some embodiments, an electrical interconnect can include a nonlinear conductive pathway portion and a linear conductive pathway portion. Also disclosed are connectors including electrical interconnects having nonlinear conductive pathways. In some embodiments, a connector can include a first electrical interconnect having a nonlinear conductive pathway that generates a first electromagnetic field, and a second electrical interconnect having a linear conductive pathway that generates a second electromagnetic field that is orthogonal to the first electromagnetic field.

Description

BACKGROUND

[0001] Integrated circuit (IC) devices are conventionally connected to and communicate with other IC devices via connectors having a large number of electrical interconnections that carry high speed signals. The electrical interconnections are in close proximity and typically suffer from signal crosstalk and other interference, which degrades signal integrity and causes errors in the received signals. BRIEF DESCRIPTION OF DRAWINGS

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For purposes of illustrating the embodiments, like reference numerals are used to identify like structural elements in the figures. The embodiments are illustrated by way of example and not limitation in the figures.

[0003] Figure 1A is a side view of one interconnect with a linear conductive path between two interconnects with non-linear conductive paths illustrating orthogonal electric fields in accordance with various embodiments.

[0004] Figure 1B is a side view of one interconnect with a linear conductive path between two interconnects with non-linear conductive paths illustrating orthogonal magnetic fields in accordance with various embodiments.

[0005] Figures 2A-2C are various views of an exemplary interconnect with a non-linear conductive path in accordance with various embodiments.

[0006] Figures 3A-3B are various views of another exemplary interconnect with a non-linear conductive path in accordance with various embodiments.

[0007] Figure 4 is a side view of another exemplary interconnect with a non-linear conductive path in accordance with various embodiments.

[0008] Figures 5A-5B is a side view of an exemplary interconnect with a non-linear conductive path portion and a linear conductive path portion in accordance with various embodiments.

[0009] Figures 6A-6B is a side view of another example of an interconnect with a non-linear conductive path portion and a linear conductive path portion in accordance with various embodiments.

[0010] Figures 7A-7C is an exemplary pin array of a pin grid array (PGA) package including various interconnects with non-linear conductive paths in accordance with various embodiments.

[0011] Figure 8 is an exemplary combined PGA and LGA package including interconnects with non-linear conductive paths in accordance with various embodiments.

[0012] Figures 9A-9B is an example board-to-board connector with interconnects having nonlinear conductive pathways according to various embodiments.

[0013] Figures 10A-10B is various views of an example manufacturing test socket including various interconnects having nonlinear conductive pathways according to various embodiments.

[0014] Figure 11A and 11B is a top view of a wafer and die that can be used with any of the embodiments of IC packages with patterned protective layers disclosed herein.

[0015] Figure 11C is a cross-sectional side view of an IC device that can be used with any of the embodiments of electrical interconnects with nonlinear conductive pathways disclosed herein.

[0016] Figure 12 is a block diagram of an example computing device that can include any of the embodiments of electrical interconnects with nonlinear conductive pathways disclosed herein. DETAILED DESCRIPTION

[0017] Disclosed herein are electrical interconnects with nonlinear conductive pathways, and related structures, devices, and methods. In some embodiments, an electrical interconnect can include: a conductive top portion, a conductive bottom portion, and a nonlinear conductive pathway electrically coupling the top and bottom portions. In some embodiments, an electrical interconnect can include: a nonlinear conductive pathway, wherein the nonlinear conductive pathway is helical. In some embodiments, an electrical interconnect can include: a nonlinear conductive pathway, wherein the nonlinear conductive pathway is sinusoidal. In some embodiments, an electrical interconnect can include: a nonlinear conductive pathway portion, and a linear conductive pathway portion, wherein an electrical signal travels along the nonlinear and linear conductive pathway portions. In some embodiments, an electrical interconnect can include: a nonlinear conductive pathway; wherein the electrical interconnect propagates an electrical signal such that the electrical signal has an electromagnetic field whose electric field is orthogonal to the direction of electromagnetic wave propagation. In some embodiments, an electrical interconnect with a nonlinear conductive pathway can be a spring-loaded interconnect. In some embodiments, an electrical interconnect with a nonlinear conductive pathway can be a stamped interconnect.

[0018] Also disclosed herein are connectors with electrical interconnects having non-linear conductive pathways. In some embodiments, a connector can include a first electrical interconnect having a non-linear conductive pathway, wherein a signal traveling along the non-linear conductive pathway generates a first electromagnetic field; and a second electrical interconnect having a linear conductive pathway, wherein a signal traveling along the linear conductive pathway generates a second electromagnetic field; wherein the second electromagnetic field is orthogonal to the first electromagnetic field. In some embodiments, a connector can include a first electrical interconnect having a non-linear conductive pathway; and a second electrical interconnect having a linear conductive pathway, wherein the second electrical interconnect is adjacent to the first electrical interconnect. In some embodiments, a connector with electrical interconnects having non-linear conductive pathways can be a temporary manufacturing test device. In some embodiments, a connector with electrical interconnects having non-linear conductive pathways can be a pin grid array (PGA) silicon package or a hybrid PGA and land grid array (LGA) silicon package. In some embodiments, a connector with electrical interconnects having non-linear conductive pathways can be a board-to-board connector.

[0019] Also disclosed herein are methods for arranging electrical interconnects having non-linear conductive pathways and electrical interconnects having linear conductive pathways in a connector. In some embodiments, a connector can include a plurality of first electrical interconnects having non-linear conductive pathways; and a plurality of second electrical interconnects having linear conductive pathways, wherein the plurality of first and second electrical interconnects are arranged in a checkerboard pattern. In some embodiments, a connector can include a plurality of first electrical interconnects having non-linear conductive pathways; and a plurality of second electrical interconnects having linear conductive pathways, wherein the plurality of first and second electrical interconnects are arranged symmetrically. In some embodiments, a connector can include an array of first electrical interconnects having non-linear conductive pathways; and an array of second electrical interconnects having linear conductive pathways, wherein the array of first and second electrical interconnects are arranged asymmetrically. As used herein, "plurality" and "array" can be used interchangeably.

[0020] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration embodiments that can be practiced. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0021] Various operations can be described as multiple discrete actions or operations, in turn, that are in an example order. However, the ordering of various operations can not be construed as a requirement and the descriptions are not intended to imply that these operations are necessarily order-dependent. In some examples, the operations can be performed in a different order, or operations can be performed concurrently or in parallel. Various additional operations can also be performed or described operations can be omitted in additional examples. Commonly used tags can be used to identify common elements in different figures.

[0022] For purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0023] The description uses the phrases "in an embodiment," or "in embodiments," which can each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "containing," etc. shall be construed as open-ended when used with respect to the embodiments of the present disclosure.

[0024] Connectors can include a large number of conductive vertical interconnects such as spring-loaded probes, stamped pins, elastomeric pins, etch-formed pins, and wire pins to provide temporary or permanent electrical coupling. Interconnects are generally conductive elements that electrically connect two or more devices for the transmission of data and are typically housed in a connector. Types of connectors can include, for example, a silicon package socket, a USB device or other device that plugs into a motherboard, a cable, a dual in-line memory module (DIMM), a small outline dual in-line memory module (SODIMM) connection, and a single inlet, among others. In the case of temporary use, a connector couples an integrated circuit such as a microprocessor unit to other hardware used to aid in testing such circuits during manufacturing. In the case of permanent use, a connector couples integrated circuits of two or more devices (e.g., printed circuit boards (PCBs)) to another PCB or a die to a silicon package. Conductive vertical interconnects placed in close proximity in a connector can cause crosstalk by acting as unintended and inefficient transmit and receive antennas. Current connector technology typically uses a single type of interconnect architecture for all pins of a connector. Conventional methods for mitigating crosstalk can include reducing pin height, using shielded pins, increasing the number of ground pins around a signal pin, and / or adding additional capacitive electrical coupling to cancel magnetic coupling. These conventional methods are limited because they are frequency dependent, use the same type of pin, and have the same electromagnetic field orientation such that electromagnetic field coupling is likely to occur and cause signal interference. These conventional methods are not only expensive, but can also cause mechanical instability and are incompatible with fine pitch packaging.

[0025] Conventional integrated circuit (IC) devices have been constrained by the use of electrical interconnects with conductive vias that generate electromagnetic fields with the same orientation rather than orthogonal orientations to transmit data to another IC device. Close proximity electrical interconnects (also referred to herein as “interconnects,” “vertical interconnects,” “interconnect pins,” or “pins”) conventionally suffer from crosstalk due to electrical and magnetic field interference between adjacent interconnect pins.

[0026] Disclosed herein are interconnects with nonlinear conductive pathways (also referred to herein as "H pins") that excite electromagnetic fields that are orthogonal to the electromagnetic fields excited by interconnects with linear conductive pathways (also referred to herein as "E pins"). H pins can be magnetic-current-driven interconnects that support a transverse electric (TE) mode. In a TE mode, the electric field is orthogonal to the direction of electromagnetic wave propagation. E pins can be electric-current-driven interconnects that support a transverse magnetic (TM) mode. In a TM mode, the magnetic field is orthogonal to the direction of electromagnetic wave propagation. TM and TE modes are orthogonal to each other such that the coupling coefficient between a purely TM mode and a purely TE mode is zero in theory. As used herein, the direction of the electromagnetic field and the direction of the electromagnetic field refer to the dominant mode. Also, as used herein, the direction of the electromagnetic field refers primarily to the far-field region and not necessarily the near-field region. An interconnect can excite other field components or other modes in addition to its fundamental mode, however, the fundamental mode will be the dominant mode even if it is not pure. While an interconnect can be electrically large in a particular frequency range, the coupling mechanism between nearby interconnects is likely to be dominated by the fundamental mode (i.e., either the TM mode or the TE mode). The coupling fields of multiple interconnects in close proximity with the same fundamental mode are likely to cause signal interference. In contrast, the coupling fields of multiple interconnects in close proximity with different fundamental modes (i.e., a combination of TM and TE modes) are unlikely to cause signal interference due to the orthogonality of the electromagnetic fields. The electromagnetic fields (including directionality) can be measured, for example, by a near-field scanner.

[0027] Also disclosed herein are connectors with two or more interconnect structures or architectures. For example, a connector can include a first E pin with a first structure and a second E pin with a second structure. The E pins can be made of any suitable conductive material(s), including copper, tin, nickel, aluminum, titanium, stainless steel, beryllium, molybdenum, tungsten, silicon carbide, conductive rubber, metal-plated elastomers, and tungsten carbide. The E pins can be prepared using any suitable manufacturing process, including sheet metalization, stamping, and machining. The E pins can have any suitable structure, including a spring-loaded structure, a stamped structure, a clasp structure, an elastomer structure, an etch-formed structure, or a wiring structure, among others. In another example, a connector can include a first interconnect with a nonlinear conductive pathway (i.e., an H pin) and a second interconnect with a linear conductive pathway (i.e., an E pin). In another example, a connector can include an H pin with a first structure, such as a spring-loaded structure or a stamped structure, and an E pin with a second structure, such as a spring-loaded structure, a stamped structure, a clasp structure, an elastomer structure, an etch-formed structure, or a wiring structure.

[0028] Figure 1Ais a side view of one interconnect with a linear conductive path placed between two interconnects with non-linear conductive paths that illustrate orthogonal electric fields according to various embodiments. Figure 1A Figures 2A and 2B illustrate an E pin 102 between two H pins 104A, 104B and the resulting respective electric fields 106, 108A, 108B. The E pin 102 is an electric-current-driven interconnect with a linear signal path 110 that generates an electric field 106 that is orthogonal to the direction 120 of electromagnetic wave propagation. The H pins 104A, 104B are magnetic-current-driven interconnects with non-linear signal paths 112A, 112B that generate electric fields 108A, 108B that are orthogonal to the direction 120 of electromagnetic wave propagation.

[0029] Figure 1B is a side view of one interconnect with a linear conductive path placed between two interconnects with non-linear conductive paths that illustrate orthogonal magnetic fields according to various embodiments. Figure 1B Figures 3A and 3B illustrate an E pin 102 between two H pins 104A, 104B and the resulting respective magnetic fields 107, 109A, 109B. The E pin 102 is an electric-current-driven interconnect with a linear signal path 110 that generates a magnetic field 107 that is orthogonal to the direction 120 of electromagnetic wave propagation (i.e., the generated magnetic field always loops orthogonally to the direction of wave propagation). The H pins 104A, 104B are magnetic-current-driven interconnects with non-linear signal paths 112A, 112B that generate magnetic fields 109A, 109B that are along the direction 120 of electromagnetic wave propagation (i.e., the generated magnetic field always loops in the direction of wave propagation). As in Figure 1A and 1B Figures 3A and 3B, the electromagnetic field originating from the E pin 102 is orthogonal to the electromagnetic field originating from the H pins 104A, 104B. The orthogonality of the electromagnetic fields can help reduce cross-talk because the coupling coefficient of adjacent orthogonal fields can approach zero.

[0030] Although Figure 1A and 1B depict the non-linear signal paths 112A, 112B as being circular, the non-linear signal paths can be in any non-linear form to generate electromagnetic fields in the TE mode, including looped, spiraled, helical, sinusoidal, and serpentine, among others.

[0031] Figures 2A-2C are various views of an exemplary interconnect with a non-linear conductive path according to various embodiments. In particular, Figure 2A is a side view of a spring-loaded interconnect 200 with a non-linear conductive path, Figure 2B is an exploded view of the assembly 200 of Figure 2A and Figure 2C is a perspective view of the assembly 200 of Figure 2AFIG. 2 is a side cross-sectional view of an assembly 200. The interconnect assembly 200 can include a top conductive element 202, a bottom conductive element 204, a guide rod 206 to provide a sliding mechanism between the top and bottom elements, and a nonlinear conductive pathway 208 electrically coupled to the conductive top element 202 and the conductive bottom element 204. As shown in FIG. 2, the nonlinear conductive pathway 208 can be a spring or a similarly shaped structure. Figures 2A-2C

[0032] The interconnect assembly 200 can have any suitable dimensions and can be formed to fit into a connector and can have dimensions that are interchangeable with other types of interconnects. For example, depending on the connector and application, the interconnect can have a z-height ranging from 1 millimeter to more than 1 inch. In some embodiments, the interconnect can have a z-height ranging from 2 millimeters to 0.5 inches. In some embodiments, the interconnect can have a z-height greater than 2 inches.

[0033] Figure 2B is Figure 2A an exploded view of the assembly 200 including the top conductive element 202, the bottom conductive element 204, the guide rod 206, and the nonlinear conductive pathway 208. The top conductive element 202 and the bottom conductive element 204 can be configured to have any suitable shape and geometry and can be configured based on a connection interface such as a conical or crown shape for a ball grid array (BGA) or for a land grid array (LGA). The top conductive element 202 and the bottom conductive element 204 can be made of any suitable conductive material including copper, tin, nickel, aluminum, titanium, stainless steel, beryllium, molybdenum, tungsten, silicon carbide, conductive rubber, metal plated elastomers, and tungsten carbide, or combinations of these materials.

[0034] The guide rod 206 can have any suitable size and shape to allow the top element 202 and the bottom element 204 to move relative to each other. The guide rod 206 can be made of any suitable dielectric material including one or more of the following: polymeric compounds, polyresin molding compounds, non-conductive elastomer molding compounds, and epoxy resins.

[0035] The nonlinear conductive pathway 208 can have any suitable size and dimensions to provide a nonlinear conductive pathway and electrically couple the top conductive element and the bottom conductive element. In some embodiments, the nonlinear conductive pathway 208 can be curved or twisted in three-dimensional space to form a helical or spiral shape. For example, the helical nonlinear conductive pathway 208 can be constructed to have specific properties such as matching a target impedance and can be designed to have any suitable shape including any number of coils, linear or conical structures, any pitch angle, and any diameter. In some embodiments, as shown in Figures 2A-2C ​As shown, the nonlinear conductive path 208 can be a spiral that acts as a mechanical spring to provide force under the load applied when the spring is compressed.

[0036] In some embodiments, the nonlinear conductive path 208 can be bent in two-dimensional space to form a waveform, such as a sine curve or a serpentine shape.

[0037] The nonlinear conductive path 208 can be made of any (one or more) suitable conductive material, including copper, tin, nickel, aluminum, titanium, stainless steel, beryllium, molybdenum, tungsten, silicon carbide, conductive rubber, metal-plated elastomers, and tungsten carbide, among others. In some embodiments, the nonlinear conductive path 208, the top conductive element 202, and the bottom conductive element 204 can be made of the same (one or more) conductive material. In some embodiments, the nonlinear conductive path 208 can be made of a different (one or more) conductive material than the top conductive element 202 and / or the bottom conductive element 204.

[0038] Figure 2C yes Figure 2A A side sectional view of component 200. (See also...) Figure 2C As shown, the bottom conductive element 204 may include an opening 210 for receiving the guide rod 206, such that the top conductive element 202 and the bottom conductive element 204 can be compressed together or removed when the nonlinear conductive path 208 is activated or deactivated. Although Figure 2C A specific structure for moving the top and bottom elements relative to each other is shown, but it is understood that other mechanical structures may be used.

[0039] Figures 3A-3B These are various diagrams illustrating another exemplary interconnection with nonlinear conductive paths according to various embodiments. In particular, Figure 3A This is a side view of another example of a spring-loaded interconnect 300 with a non-linear conductive path, and Figure 3B yes Figure 3A A side sectional view of component 300. Interconnect component 300 may include a top conductive element 302, a bottom conductive element 304, a coil or spring 306 for providing a mechanism for moving the top element 302 and the bottom element 304 relative to each other, and a non-linear conductive path 308 electrically coupled to the conductive top element 302 and the conductive bottom element 304. (See also...) Figure 3AAs shown, the nonlinear conductive path 308 can be a helical tube or similarly shaped element that surrounds the coil 306 and provides a nonlinear conductive path. The nonlinear conductive path 308 can be made of any suitable material and can have any suitable size, as described above with reference to Figure 2. The interconnect assembly 300 can consist of multiple elements or can be a single unit combining different elements.

[0040] Figure 3B yes Figure 3A A side sectional view of component 300. (See also...) Figure 3B As shown, the top conductive element 302 and the bottom conductive element 304 can be mechanically connected to a coil or spring 306, which can be activated or deactivated to move the top conductive element 302 and the bottom conductive element 304 together or apart. The coil 306 can be made of any suitable non-conductive or conductive material. Non-conductive materials can include, for example, polymer compounds, polyresin molding compounds, non-conductive elastomer molding compounds, and epoxy resins, or combinations thereof. Conductive materials can include, for example, copper, tin, nickel, aluminum, titanium, stainless steel, beryllium, molybdenum, tungsten, silicon carbide, conductive rubber, metal-plated elastomers, and tungsten carbide, or combinations thereof. In some embodiments, the conductive coil can be insulated from non-linear conductive paths.

[0041] Figure 4 This is a side view of another exemplary stamped interconnect 400 having a nonlinear conductive path according to various embodiments. The interconnect 400 may have a nonlinear conductive path 406 and a top conductive element 402 and a bottom conductive element 404. The interconnect 400 can be formed using any suitable process, including stamping, electroforming, or metal fabrication by bending, cutting, or assembly processes. The top conductive element 402 and the bottom conductive element 404 can have any suitable shape and size and can be formed to optimize contact with the conductive surfaces of the connector. The nonlinear conductive path 406 can have any suitable size and shape to provide a nonlinear signal path, as described above with reference to FIG3. In some embodiments, such as in Figure 4 As shown, the nonlinear conductive path 406 may have a spiral shape with a hollow center and a rectangular cross-section. In some embodiments, the nonlinear conductive path 406 may have a spiral shape (not shown) with a hollow center and a spherical cross-section.

[0042] Figures 5A-5Bis a side view of example interconnects 500, 501 having a nonlinear conductive portion and a linear conductive portion according to various embodiments. The interconnects 500, 501 can have a nonlinear conductive spiral portion 506, 507, a linear conductive portion 508, 509, and a top conductive element 502 and a bottom conductive element 504. The nonlinear conductive portion can be referred to herein as a magnetic-current-driven portion, and the linear conductive portion can be referred to herein as an electric-current-driven portion. The nonlinear conductive portion generates electromagnetic fields in the TE mode, while the linear conductive portion generates electromagnetic fields in the TM mode, which is orthogonal to the TE mode. As described above, reference to generated electromagnetic fields herein refers to the electromagnetic fields generated in a dominant manner. Interconnects having linear and nonlinear portions can be referred to herein as "heterogeneous interconnects."

[0043] The heterogeneous interconnects 500, 501 can be formed using any suitable process, including stamping, electroforming, or metal fabrication by flexing, cutting, or assembly processes. The top and bottom conductive elements 502, 504 can have any suitable size and shape, and can be formed to optimize contact with the conductive surfaces of a connector. The linear conductive portions 508, 509 can have any suitable size and shape, including, for example, a tubular shape. In some embodiments, the linear conductive portions 508, 509 can have a hollow center or a barrel shape. In some embodiments, the diameter can vary along the length of the interconnect 500, 501. The interconnects 500, 501 can be made of any suitable conductive material(s), including the materials described above with reference to FIG. 2.

[0044] The interconnects 500, 501 can be designed and paired as shown in FIG. 5, where the interconnect 500 and the interconnect 501 have nonlinear conductive portions 506, 507 adjacent linear conductive portions 509, 508, respectively. The heterogeneous interconnect 500 has a nonlinear portion 506 at the top of the interconnect and a linear portion 508 at the bottom of the interconnect. The heterogeneous interconnect 501 has a linear portion 509 at the top of the interconnect and a nonlinear portion 507 at the bottom of the interconnect. When placed adjacent to each other, the interconnect 500 and the interconnect 501 have linear portions adjacent nonlinear portions. The alternating linear and nonlinear conductive portions in the adjacent interconnects 500, 501 can reduce coupling of electromagnetic fields, as the electromagnetic fields generated in the nonlinear portion 506 of the interconnect 500 are likely to be orthogonal to the electromagnetic fields generated in the linear portion 509 of the adjacent interconnect 501. Similarly, the electromagnetic fields generated in the linear portion 508 of the interconnect 500 are likely to be orthogonal to the electromagnetic fields generated in the nonlinear portion 507 of the adjacent interconnect 501. While FIG. 5 shows a pair of interconnects having one nonlinear conductive portion and one linear conductive portion, it will be appreciated that the interconnects can have any number of nonlinear and linear portions.

[0045] Figures 6A-6B is a side view of another example of a heterogeneous interconnect having a non-linear conductive portion and a linear conductive portion according to various embodiments. Interconnects 600, 601 can have a non-linear conductive spiral portion 606, 607, a linear conductive portion 608, 609, and a top conductive element 602 and a bottom conductive element 604. The heterogeneous interconnects 600, 601 can be formed using any suitable process, including stamping, electroforming, or metal fabrication by flexing, cutting, or assembly. The top conductive element 602 and the bottom conductive element 604 can have any suitable size and shape, and can be formed to optimize contact with a conductive surface of a connector. The linear conductive portion 608, 609 can have any suitable size and shape, including, for example, a tubular shape. In some embodiments, the linear conductive portion 608, 609 can have a hollow center or a barrel shape. In some embodiments, the diameter can vary along the length of the interconnect 600, 601. The heterogeneous interconnects 600, 601 can be made of any suitable conductive material(s), including the materials described above with reference to FIG. 2.

[0046] The heterogeneous interconnects 600, 601 can be designed and mated as shown in FIG. 5, where interconnect 600 and interconnect 601 have a non-linear conductive portion 606, 607 adjacent to a linear conductive portion 609, 608, respectively. Heterogeneous interconnect 600 has a non-linear portion 606 at the bottom of the interconnect and a linear portion 608 at the top of the interconnect. Heterogeneous interconnect 601 has a linear portion 609 at the bottom of the interconnect and a non-linear portion 607 at the top of the interconnect. When placed adjacent to each other, interconnect 600 and interconnect 601 have a linear portion adjacent to a non-linear portion. The alternating linear conductive portions and non-linear conductive portions in adjacent interconnects 600, 601 can suppress crosstalk by reducing the coupling of electromagnetic fields, as the electromagnetic field generated in the non-linear portion 606 of interconnect 600 is likely to be orthogonal to the electromagnetic field generated in the linear portion 609 of adjacent interconnect 601. Similarly, the electromagnetic field generated in the linear portion 608 of interconnect 600 is likely to be orthogonal to the electromagnetic field generated in the non-linear portion 607 of adjacent interconnect 601. While FIG. 6 shows a mated interconnect having one non-linear conductive portion and one linear conductive portion, it can be appreciated that the interconnects can have any number of non-linear conductive portions and linear conductive portions.

[0047] Figures 7A-7C is a simplified schematic diagram of an exemplary pin grid array (PGA) package including various interconnects having non-linear conductive pathways along which electrical signals travel according to various embodiments. In particular, Figure 7Ais a top-down view of an exemplary PGA package 700A, also referred to herein as a socket assembly, the interconnects having serpentine-shaped conductive vias, Figure 7B is a side view of an exemplary PGA package 700B including stamped interconnects having non-linear conductive vias, and Figure 7C is a top-down view of an exemplary PGA package 700C including heterogeneous interconnects having non-linear conductive portions and linear conductive portions. Interconnects having non-linear conductive vias and interconnects having linear conductive vias can be arranged to reduce electromagnetic field coupling and to suppress crosstalk.

[0048] A socket, which is a type of connector, can include a support structure, referred to herein as a "socket body," and a plurality of pin interconnects extending at least partially in the socket body. The socket body can be a single contiguous support structure of the socket, or alternatively an assembly or subassembly of multiple constituent bodies. The socket body can be affixed to a surface area of an electronic device by a frame or other support structure, the surface area of the electronic device having conductive contacts for coupling to a respective plurality of the pin interconnects to allow for signal exchange. For example, signals can be exchanged via a PCB and a connector coupled thereto, or between the connector and a test unit to assess functionality of the test unit.

[0049] Figure 7A depicts a checkerboard arrangement in the socket body 702, with interconnects having non-linear conductive vias 704 alternating with interconnects having linear conductive vias 706. Figure 7B depicts a C-shaped arrangement in the socket body 703, with interconnects having non-linear conductive vias 705 forming a semicircle around interconnects having linear conductive vias 707.

[0050] Figure 7C depicts a socket body 722 with homogeneous interconnects 726 having only linear conductive vias, and heterogeneous interconnects 724, 725 having linear conductive vias and non-linear conductive vias. Some heterogeneous interconnects 724 have non-linear portions on the bottom and linear portions on the top. Some heterogeneous interconnects 725 have non-linear portions on the top and linear portions on the bottom. In Figure 7C adjacent heterogeneous interconnects are arranged with alternating non-linear portions and linear portions. As shown in Figure 7C interconnects 726 having only linear conductive vias are in a C-shaped arrangement. Figures 7A-7CSeveral exemplary arrangements for interconnects with non-linear conductive paths are shown, however, many other arrangements can be employed, including symmetric arrangements and asymmetric arrangements. For example, interconnects with non-linear conductive paths and interconnects with linear conductive paths can be arranged to alternate based on a determined ratio (e.g., two interconnects with non-linear conductive paths for every one interconnect with linear conductive path).

[0051] While Figures 7A-7C A 3 by 3 array is depicted, however, the connector can have any number of interconnects, for example, the number of interconnects in the connector can range from 3 to more than 3000. The connector can have a "pinout map" that identifies different connections (e.g., ground pins, power pins, signal pins, and non-connection pins) as well as interconnect positions. In some embodiments, the connector can have interconnects arranged into signal groups, for example, interconnects for USB signals can be grouped or memory signals can be grouped. It can be appreciated that any number of interconnects with non-linear conductive paths can be used and can be used in a portion of the connector or for a particular signal (i.e., not throughout the entire connector). For example, interconnects with non-linear conductive paths can be used for high speed signals, such as for PCIe (Peripheral Component Interconnect Express) signals, and not for low speed control signals. In some embodiments, interconnects with non-linear conductive paths can be used for power signals, ground signals, or low speed control signals.

[0052] Figure 8 is an exemplary combined PGA and LGA socket assembly 800 including interconnects with non-linear conductive paths according to various embodiments. The assembly 800 can include a combined PGA and LGA package 802, a PCB 808, and a socket 810. Dies can be packaged in various ways, including the combined PGA and LGA package 802. A PGA has an array of pins or interconnects that serve as external electrical communication nodes for the package. An LGA has an array of flat contact pads or lands that serve as external electrical communication nodes on a package substrate. The combined PGA and LGA package 802 has both interconnects 804 and lands 806 that serve as external electrical communication nodes. The socket 810 can include a socket housing 812, a plurality of PGA connectors 814, and a plurality of LGA interconnects 816. In some embodiments, as in Figure 8As shown in FIG. 8, the PGA interconnect 804 can have linear conductive pathways, and the LGA interconnect 816 can have non-linear conductive pathways. In some embodiments, the arrangement can be reversed, where the PGA interconnect can have non-linear conductive pathways and the LGA interconnect can have linear conductive pathways. In some embodiments, the LGA interconnect 816 with non-linear conductive pathways can be a heterogeneous interconnect. In some embodiments, the PGA interconnect 804 with non-linear conductive pathways can be a heterogeneous interconnect. In some embodiments, the PGA interconnect 804 can be a homogeneous interconnect with non-linear conductive pathways, and the LGA interconnect 816 can be a heterogeneous interconnect with non-linear conductive portions on the bottom and linear conductive portions on the top, such that the PGA non-linear conductive pathways and the LGA linear conductive portions alternate in the area of interconnect overlap (i.e., within the Z-height region). In some embodiments, the PGA interconnect 804 and the LGA interconnect 816 can be heterogeneous interconnects, and can be arranged to alternate adjacent linear conductive portions and non-linear conductive portions.

[0053] Figures 9A-9B FIGS. 8-10 illustrate exemplary board-to-board connectors with interconnects having non-linear conductive pathways, according to various embodiments. In particular, Figure 9A is an exemplary board-to-board connector with asymmetric pair interconnects, where one pair of interconnects has non-linear conductive pathways, and Figure 9B is an exemplary board-to-board connector with symmetric pair interconnects, where both pairs of interconnects have non-linear conductive pathways. In Figure 9A , the assembly 900 can include a board-to-board connector 902 (e.g., a PCB-to-PCB connector) that connects a display 904 to a PCB 906, or in another example, a motherboard 906 to a daughter card 904, or in another example, a motherboard 906 to a PCB 904 that has a USB device mounted thereon. An interconnect 908 (indicated by dashed lines) on the board-to-board connector 902 is enlarged. The interconnect 908 can include three ground signal interconnects 914, a differential pair transmitter signal interconnect 910, and a differential pair receiver signal interconnect 912. As shown in Figure 9A , the differential pair transmitter interconnect 910 has linear conductive pathways 922, and the adjacent differential pair receiver interconnect 912 has non-linear conductive pathways 920.

[0054] In Figure 9B , the assembly 901 can include a board-to-board connector 903 (e.g., a PCB-to-PCB connector) that connects a display 904 to a PCB 906. An interconnect 909 (indicated by dashed lines) on the board-to-board connector 903 is enlarged. The interconnect 909 can include three ground signal interconnects 915, a differential pair transmitter signal interconnect 911, and a differential pair receiver signal interconnect 913. As shown inFigure 9B As shown in FIG. 9B, both the differential pair transmitter interconnect 911 and the adjacent differential pair receiver interconnect 913 have nonlinear conductive pathways 924, 926.

[0055] While Figures 9A-9B While two differential pair interconnects are illustrated, the board-to-board connectors 902, 903 can have any number of differential pairs, can have a combination of differential pair and single-ended interconnects, and the interconnects with nonlinear conductive pathways can be arranged symmetrically or asymmetrically on the board-to-board connectors.

[0056] Figures 10A-10B is a top view of an exemplary manufacturing test socket arrangement for testing double data rate random access memory (DDR) including various interconnects with nonlinear conductive pathways in accordance with various embodiments. In particular, Figure 10A is a side-to-top view of an exemplary manufacturing test socket arrangement for testing double data rate random access memory (DDR) including various interconnects with nonlinear conductive pathways, and Figure 10B is Figure 10A is a top view of the components of FIG. 9A. The asymmetric DDR interconnect pattern 1000 for a test socket (not shown) includes five types of interconnects: H-pin ground interconnects 1002, E-pin power interconnects 1004, differential pair interconnects 1006, E-pin signal interconnects 1008, and H-pin signal interconnects 1010. As shown in FIG. 9B, both the differential pair transmitter interconnect 911 and the adjacent differential pair receiver interconnect 913 have nonlinear conductive pathways 924, 926. Figure 10B As shown in FIG. 9B, both the differential pair transmitter interconnect 911 and the adjacent differential pair receiver interconnect 913 have nonlinear conductive pathways 924, 926.

[0057] Figures 10A-10BAn exemplary manufacturing test socket arrangement is depicted. Testing semiconductor dies or other integrated circuit devices during manufacturing involves establishing electrical connections between test equipment, such as a test board, and the circuitry of the dies or IC devices. Testing can be performed on unpackaged dies that have been singulated from a semiconductor wafer, on a portion of a die that is still part of a wafer, or on all of the dice on a wafer. Testing can also be performed on bare dies that have undergone a packaging step, such as flip chips. The device to be tested will be referred to hereinafter as a device under test (DUT), regardless of the singulation or packaging status of the die. Returning to the testing process, the PCB with the socket connected is placed in a cavity, where the DUT is tested while subjected to elevated temperatures. Such testing is referred to as burn-in testing. The contacts of the socket provide electrical communication between the DUT and signals sent from the test equipment through the PCB. Once testing is complete, the DUT is removed from the socket. DUTs that do not pass testing are discarded, and DUTs that pass testing can be subjected to additional testing and ultimately used as components in electronic devices.

[0058] Various embodiments are described herein with particular reference to manufacturing test socket assemblies to couple DUTs to hardware to run tests on the DUTs or to socket assemblies coupled to PCBs. However, such descriptions can be extended to apply, additionally or alternatively, to any of a variety of other applications in which a socket assembly is to be coupled to an IC device. The techniques described herein can be implemented in one or more electronic devices. Non-limiting examples of electronic devices that can utilize the techniques described herein include any kind of mobile and / or stationary device, such as a camera, a cellular telephone, a computer terminal, a desktop computer, an electronic reader, a facsimile machine, a kiosk, a netbook computer, a notebook computer, an Internet appliance, a payment terminal, a personal digital assistant, a media player and / or recorder, a server, a set-top box, a smart phone, a slate personal computer, an ultra-mobile personal computer, a wired telephone, combinations thereof, and the like. Such devices can be portable or stationary. More generally, the techniques described herein can be employed in any of a variety of electronic devices, including sockets or other such devices to couple integrated circuit devices (e.g., IC chips or packaged devices) to substrates of PCBs.

[0059] Figure 11A-B is a top view of a wafer 1101 and die 1105 that may be included in an IC assembly that can be electrically coupled to a connector having an interconnect with non-linear conductive paths as described herein. The wafer 1101 may be composed of a semiconductor material and may include one or more dies 1105 having IC elements formed on the surface of the wafer 1101. Each of the dies 1105 may be a repeating unit of a semiconductor product including any suitable IC. After the semiconductor product is manufactured, the wafer 1101 may undergo a monolithization process in which each of the dies 1105 is separated from each other to provide a discrete “chip” of the semiconductor product. Dies 1105 may include one or more transistors (e.g., Figure 11C Some of the transistors 1140 in the chip (discussed below) and / or supporting circuitry for routing electrical signals to the transistors, as well as any other IC components. In some embodiments, the die 1101 or die 1105 may include memory devices (e.g., static random access memory (SRAM) devices), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Multiple devices of these devices may be combined on a single die 1105. For example, a memory array formed by multiple memory devices may be formed on the same die 1105 as a processing device (e.g., Figure 12 The processing device 1202 or other logic is configured to store information in a memory device or execute instructions stored in a memory array. In some embodiments, die 1105 may include circuitry that is coupled to and interacts with circuitry provided by constituent devices in the package substrate after die 1105 is coupled to the package substrate, as discussed above.

[0060] Figure 11C This is a cross-sectional side view of an IC device 1100 that can be included in a die that can be coupled to a package substrate. Specifically, one or more of the IC devices 1100 can be included in one or more dies. The IC device 1100 can be formed on a substrate 1102 (e.g., Figure 11A On the wafer 1101) and included in the die (e.g., Figure 11Bsemiconductor substrate composed of a semiconductor material system including, for example, an N-type or P-type material system. The substrate 1102 can include a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure, for example. In some embodiments, the substrate 1102 can be formed using alternative materials that can or can not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as Group II- VI, Group III-V, or Group IV can also be used to form the substrate 1102. While several examples of materials from which the substrate 1102 can be formed are described herein, any material that can serve as a foundation for the IC device 1100 can be used. The substrate 1102 can be a singulated die (e.g., Figure 11B or a wafer (e.g., Figure 11A portion of a wafer 1101).

[0061] The IC device 1100 can include one or more device layers 1104 disposed on the substrate 1102. The device layers 1104 can include features of one or more transistors 1140 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1102. The device layers 1104 can include, for example, one or more source and / or drain (S / D) regions 1120; gates 1122 to control current in the transistors 1140 between the S / D regions 1120; and one or more S / D contacts 1124 to route electrical signals to / from the S / D regions 1120. The transistors 1140 can include additional features not depicted for clarity, such as device isolation regions, gate contacts, and the like. The transistors 1140 are not limited to the types and configurations depicted in Figure 11C and can include a wide variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors, such as dual-gate transistors or tri-gate transistors, as well as gate-all-around or gate-fully-enclosing transistors such as nanoribbon and nanowire transistors.

[0062] Each transistor 1140 can include a gate 1122 formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer can include a stack of one or more layers. One or more of the layers can include silicon oxide, silicon dioxide, and / or a high-k dielectric material. The high-k dielectric material can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum hafnium oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead niobium zinc oxide. In some embodiments, an annealing process can be performed on the gate dielectric layer when a high-k material is used to improve its quality.

[0063] The gate electrode layer can be formed on the gate dielectric layer and can include at least one P-type or N-type work function metal, depending on whether the transistor 1140 is to be a PMOS or NMOS transistor. In some implementations, the gate electrode layer can be composed of a stack of two or more metal layers, one or more of which is a work function metal layer, and at least one of which is a fill metal layer. Additional metal layers can be included for other purposes, such as barrier layers. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For NMOS transistors, metals that can be used for the gate electrode can include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0064] In some embodiments, the gate electrode can be composed of a U-shaped structure that includes a bottom portion that is substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate when viewed as a cross-section of the transistor 1140 along the source-channel-drain direction. In other embodiments, at least one of the metal layers that forms the gate electrode can simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode can be composed of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode can be composed of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0065] In some embodiments, a pair of sidewall spacers can be formed on opposite sides of the gate stack to enclose the gate stack. The sidewall spacers can be formed of a material such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers can be used; for example, two, three, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack.

[0066] The S / D regions 1120 can be formed within the substrate 1102 adjacent to the gates 1122 of each transistor 1140. The S / D regions 1120 can be formed using, for example, implantation / diffusion processes or etching / deposition processes. In the former processes, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic can be implanted into the substrate 1102 to form the S / D regions 1120. An annealing process to activate the dopants and to diffuse them further into the substrate 1102 can be performed subsequent to the ion implantation process. In the latter processes, the substrate 1102 can first be etched to form a recess at the location of the S / D regions 1120. An epitaxial deposition process can then be performed to fill the recess with a material used to fabricate the S / D regions 1120. In some implementations, a silicon alloy such as silicon germanium or silicon carbide can be used to fabricate the S / D regions 1120. In some embodiments, the epitaxially deposited silicon alloy can be doped in situ with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials such as germanium or a III-V material or alloy can be used to form the S / D regions 1120. In further embodiments, one or more metal and / or metal alloy layers can be used to form the S / D regions 1120.

[0067] Electrical signals such as power signals and / or input / output (I / O) signals can be routed to and / or from the transistors 1140 of the device layer 1104 through one or more interconnect layers (illustrated in Figure 11C as interconnect layers 1106-1110) disposed on the device layer 1104. For example, the conductive features (e.g., gates 1122 and S / D contacts 1124) of the device layer 1104 can be electrically coupled with interconnect structures 1128 of the interconnect layers 1106-1110. The one or more interconnect layers 1106-1110 can form an interlayer dielectric (ILD) stack 1119 of the IC device 1100.

[0068] The interconnect structures 1128 can be arranged within the interconnect layers 1106-1110 to route electrical signals in accordance with a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of the interconnect structures 1128 depicted in Figure 11C . Although the interconnect structures 1128 are depicted as being formed in the interconnect layers 1106-1110, in some embodiments, one or more of the interconnect structures 1128 can be formed in the device layer 1104. Figure 11CA particular number of interconnect layers 1106-1110 are depicted, but embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0069] In some embodiments, the interconnect structures 1128 can include trench structures 1128a (sometimes referred to as “lines”) and / or via structures 1128b (sometimes referred to as “holes”) filled with a conductive material such as a metal. The trench structures 1128a can be arranged to route electrical signals in a direction substantially parallel to the surface of the substrate 1102 on which the device layers 1104 are formed. For example, the trench structures 1128a can route electrical signals in a direction that is substantially parallel to the plane of the substrate 1102 on which the device layers 1104 are formed. The via structures 1128b can be arranged to route electrical signals in a direction substantially perpendicular to the surface of the substrate 1102 on which the device layers 1104 are formed. In some embodiments, the via structures 1128b can electrically couple the trench structures 1128a of different interconnect layers 1106-1110 together. Figure 11C

[0070] The interconnect layers 1106-1110 can include dielectric material 1126 disposed between the interconnect structures 1128, as shown in FIG. 11B. In some embodiments, the dielectric material 1126 disposed between the interconnect structures 1128 in different ones of the interconnect layers 1106-1110 can have different compositions; in other embodiments, the composition of the dielectric material 1126 between different interconnect layers 1106-1110 can be the same. Figure 11C The first interconnect layer 1106 (referred to as metal 1 or “M1”) can be formed directly on the device layers 1104. In some embodiments, the first interconnect layer 1106 can include trench structures 1128a and / or via structures 1128b, as shown. The trench structures 1128a of the first interconnect layer 1106 can be coupled with the contacts (e.g., S / D contacts 1124) of the device layers 1104.

[0071]

[0072] ​​A second interconnect layer 1108 (referred to as metal 2 or "M2") can be formed directly on the first interconnect layer 1106. In some embodiments, the second interconnect layer 1108 can include via structures 1128b to couple the trench structures 1128a of the second interconnect layer 1108 with the trench structures 1128a of the first interconnect layer 1106. While the trench structures 1128a and the via structures 1128b are depicted structurally with lines within each interconnect layer (e.g., within the second interconnect layer 1108) for clarity, in some embodiments the trench structures 1128a and the via structures 1128b can be structurally and / or materially continuous (e.g., filled simultaneously during a dual-damascene process).

[0073] A third interconnect layer 1110 (referred to as metal 3 or "M3") (and additional interconnect layers as desired) can be successively formed on the second interconnect layer 1108 according to similar techniques and configurations described in connection with the second interconnect layer 1108 or the first interconnect layer 1106.

[0074] The IC device 1100 can include a solder resist material 1134 (e.g., polyimide or similar material) and one or more bond pads 1136 formed on the interconnect layers 1106-1110. The bond pads 1136 can provide contacts to couple to, for example, first level interconnects. The bond pads 1136 can be electrically coupled with the interconnect structures 1128 and configured to route electrical signals of the transistor(s) 1140 to other external devices. For example, solder bonds can be formed on the one or more bond pads 1136 to mechanically and / or electrically couple a chip including the IC device 1100 with another component (e.g., a circuit board). The IC device 1100 can have other alternative configurations to route electrical signals from the interconnect layers 1106-1110 than those depicted in other embodiments. For example, the bond pads 1136 can be replaced by or further include other similar features (e.g., posts) that route electrical signals to external components.

[0075] Figure 12 is a block diagram of an example computing device 1200 that can include a connector having interconnects with nonlinear conductive pathways as disclosed herein. For example, any suitable number of the components of the computing device 1200 can include or be included in an IC assembly including a die with direct diagonal connections according to any of the embodiments disclosed herein. The components are Figure 12The components included in the computing device 1200 are those typically found in computing devices of this type. However, these components can be omitted or supplemented while remaining within the scope of the present disclosure. In some embodiments, some or all of the components included in the computing device 1200 can be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system on a chip (SoC) die.

[0076] In addition, in various embodiments, the computing device 1200 can include interface circuitry for coupling to one or more components. For example, the computing device 1200 can not include a display device 1206, but can include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1206 can be coupled. In another set of examples, the computing device 1200 can not include an audio input device 1224 or an audio output device 1208, but can include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1224 or an audio output device 1208 can be coupled.

[0077] The computing device 1200 can include a processing device 1202 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” can refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1202 can include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 1200 can include a memory 1204, which can itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 1204 can include memory that shares a die with the processing device 1202. This memory can be used as cache memory and can include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0078] In some embodiments, the computing device 1200 can include communication chips 1212 (e.g., one or more communication chips). For example, the communication chips 1212 can be configured to manage wireless communications for the transfer of data to and from the computing device 1200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0079] The communication chips 1212 can implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), Bluetooth, IEEE 802.16 (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project

[0080] In some embodiments, the communication chip 1212 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As noted above, the communication chip 1212 can include multiple communication chips. For instance, a first communication chip 1212 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 1212 can be dedicated to longer-range wireless

[0081] The computing device 1200 can include a battery / power circuit 1214. The battery / power circuit 1214 can include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry to couple components of the computing device 1200 to an energy source separate from the computing device 1200 (e.g., an AC line power source).

[0082] The computing device 1200 can include a display device 1206 (or corresponding interface circuitry, as discussed above). The display device 1206 can include any visual

[0083] The computing device 1200 can include an audio output device 1208 (or corresponding interface circuitry, as discussed above). The audio output device 1208 can include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0084] The computing device 1200 can include an audio input device 1224 (or corresponding interface circuitry, as discussed above). The audio input device 1224 can include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a musical instrument digital interface (MIDI) output).

[0085] The computing device 1200 can include a global positioning system (GPS) device 1218 (or corresponding interface circuitry, as discussed above). The GPS device 1218 can communicate with satellite-based systems and can receive a location of the computing device 1200, as is known in the art.

[0086] The computing device 1200 can include other output devices 1210 (or corresponding interface circuitry, as discussed above). Examples of the other output devices 1210 can include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0087] The computing device 1200 can include other input devices 1220 (or corresponding interface circuitry, as discussed above). Examples of the other input devices 1220 can include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0088] The computing device 1200 can have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 1200 can be any other electronic device that processes data.

[0089] The following examples pertain to further embodiments. Various features of the different embodiments can be combined with each other in a wide variety of combinations.

[0090] Example 1 is an electrical interconnect comprising: a top conductive element; a bottom conductive element; and a conductive pathway electrically coupling the top element and the bottom element, wherein the conductive pathway comprises a non-linear conductive pathway.

[0091] Example 2 can include subject matter of Example 1, and can further specify that the non-linear conductive pathway is helical.

[0092] Example 3 can include subject matter of Example 1, and can further specify that the non-linear conductive pathway is sinusoidal.

[0093] Example 4 can include subject matter of any of Examples 1-3, and can further specify that the non-linear conductive pathway comprises one or more of: copper, tin, nickel, aluminum, titanium, stainless steel, beryllium, molybdenum, tungsten, silicon carbide, conductive rubber, metal-plated elastomers, and tungsten carbide.

[0094] Example 5 can include the subject matter of any one of Examples 1-4, and can further specify that the electrical interconnect is a spring-loaded interconnect.

[0095] Example 6 can include the subject matter of any one of Examples 1-4, and can further specify that the electrical interconnect is a stamped interconnect.

[0096] Example 7 can include the subject matter of any one of Examples 1-6, and can further specify that the electrical interconnect is to propagate an electrical signal such that the electrical signal has an electromagnetic field with an electric field that is orthogonal to an electromagnetic field wave propagation direction.

[0097] Example 8 can include the subject matter of Example 1, and can further specify that the electrically conductive pathway further comprises: a linear electrically conductive pathway, wherein the linear electrically conductive pathway is in a first portion of the electrically conductive pathway, and wherein the non-linear electrically conductive pathway is in a second portion of the electrically conductive pathway.

[0098] Example 9 is a connector comprising: a body; and an electrical interconnect extending into the body comprising: a top electrically conductive element; a bottom electrically conductive element; and an electrically conductive pathway electrically coupling the top element and the bottom element, wherein the electrically conductive pathway is a non-linear electrically conductive pathway.

[0099] Example 10 can include the subject matter of Example 9, and can further specify that the non-linear electrically conductive pathway is helical.

[0100] Example 11 can include the subject matter of Example 9, and can further specify that the non-linear electrically conductive pathway is sinusoidal.

[0101] Example 12 can include the subject matter of Example 9, and can further specify that the non-linear electrically conductive pathway comprises one or more of: copper, tin, nickel, aluminum, titanium, stainless steel, beryllium, molybdenum, tungsten, silicon carbide, electrically conductive rubber, metal-plated elastomer, and tungsten carbide.

[0102] Example 13 can include the subject matter of Example 9, and can further specify that the electrical interconnect is a spring-loaded interconnect.

[0103] Example 14 can include the subject matter of Example 9, and can further specify that the electrical interconnect is a stamped interconnect.

[0104] Example 15 can include the subject matter of Example 9, and can further specify that the electrical interconnect is to propagate an electrical signal that generates an electromagnetic field with an electric field that is orthogonal to an electromagnetic field wave propagation direction.

[0105] Example 16 can include the subject matter of Example 9, and can further specify that the electrical interconnect further comprises: a linear electrically conductive pathway, wherein the linear electrically conductive pathway is in a first portion of the electrically conductive pathway, and wherein the non-linear electrically conductive pathway is in a second portion of the electrically conductive pathway.

[0106] Example 17 can include the subject matter of Example 9, and can further specify that the electrical interconnect is a first electrical interconnect, and further comprising: a second electrical interconnect comprising: a second top conductive element; a second bottom conductive element; and a second conductive via electrically coupling the second top element and the second bottom element, wherein the second conductive via is a linear conductive via.

[0107] Example 18 can include the subject matter of Example 17, and can further specify that the second electrical interconnect is to propagate an electrical signal that generates an electromagnetic field having a magnetic field that is orthogonal to a direction of propagation of the electromagnetic field wave.

[0108] Example 19 can include the subject matter of Example 17, and can further specify that the first electrical interconnect propagates an electrical signal that generates an electromagnetic field in a first direction, wherein the second electrical interconnect propagates an electrical signal that generates an electromagnetic field in a second direction, and wherein the second direction is orthogonal to the first direction.

[0109] Example 20 can include the subject matter of Example 17, and can further specify that the first electrical interconnect is adjacent to the second electrical interconnect.

[0110] Example 21 can include the subject matter of Example 17, and can further specify that the connector comprises conductive contacts for electrically coupling an integrated circuit (IC) device to a test board.

[0111] Example 22 can include the subject matter of Example 17, and can further specify that the connector is a board-to-board connector.

[0112] Example 23 can include the subject matter of Example 17, and can further specify that the connector comprises conductive contacts for electrically coupling an integrated circuit (IC) device having a pin grid array.

[0113] Example 24 can include the subject matter of Example 17, and can further specify that the connector comprises conductive contacts for electrically coupling an integrated circuit (IC) device having a hybrid pin grid array and land grid array.

[0114] Example 25 can include the subject matter of Example 17, and can further specify that the first electrical interconnect and the second electrical interconnect are part of an array of interconnects, and wherein the array of interconnects is arranged in an alternating manner of the first electrical interconnect and the second electrical interconnect.

[0115] Example 26 is a connector comprising: a body; and a first electrical interconnect having a first structure extending into the body; and a second electrical interconnect having a second structure extending into the body, wherein the second structure is different than the first structure.

[0116] Example 27 can include the subject matter of Example 26, and can further specify that the first structure is a spring-carrying structure, and wherein the second structure is not a spring-carrying structure.

[0117] Example 28 can include the subject matter of Example 26, and can further specify that the first structure is a stamped structure, and the second structure is not a stamped structure.

[0118] Example 29 can include the subject matter of Example 26, and can further specify that the first structure is an elastomeric structure, and the second structure is not an elastomeric structure.

[0119] Example 30 can include the subject matter of Example 26, and can further specify that the first structure is a wiring structure, and wherein the second structure is not a wiring structure.

[0120] Example 31 can include the subject matter of Example 26, and can further specify that the first structure is a buckle structure, and wherein the second structure is not a buckle structure.

[0121] Example 32 is a computing device comprising: a connector comprising: a body; and an electrical interconnect extending into the body comprising: a top conductive element; a bottom conductive element; and a conductive pathway electrically coupling the top element and the bottom element, wherein the conductive pathway is a non-linear conductive pathway; a first circuit board electrically coupled to the connector; and a second circuit board electrically coupled to the connector, and via the conductive signal pathway of the connector between the first circuit board and the second circuit board.

[0122] Example 33 can include the subject matter of Example 32, and can further specify that the non-linear conductive pathway is helical.

[0123] Example 34 can include the subject matter of Example 32, and can further specify that the non-linear conductive pathway is sinusoidal.

[0124] Example 35 can include the subject matter of any of Examples 32-34, and can further specify that the non-linear conductive pathway comprises one or more of: copper, tin, nickel, aluminum, titanium, stainless steel, beryllium, molybdenum, tungsten, silicon carbide, conductive rubber, metal-plated elastomer, and tungsten carbide.

[0125] Example 36 can include the subject matter of any of Examples 32-35, and can further specify that the electrical interconnect is a spring-carrying interconnect.

[0126] Example 37 can include the subject matter of any of Examples 32-35, and can further specify that the electrical interconnect is a stamped interconnect.

[0127] Example 38 can include the subject matter of any one of Examples 32-37, and can further specify that the electric signal is propagated through the electrically conductive signal path between the first circuit board and the second circuit board such that the electric signal has an electromagnetic field with an electric field that is orthogonal to a direction of electromagnetic field wave propagation.

Claims

1. An electrical interconnect comprising: a top conductive element; a bottom conductive element; and a conductive pathway electrically coupling the top element and the bottom element, wherein the conductive pathway comprises a non-linear conductive pathway, and wherein the electrical interconnect is configured to propagate an electrical signal such that the electrical signal has an electromagnetic field with an electric field that is orthogonal to a direction of electromagnetic field wave propagation.

2. The electrical interconnect of claim 1, wherein the non-linear conductive pathway is helical.

3. The electrical interconnect of claim 1, wherein the non-linear conductive pathway is sinusoidal.

4. The electrical interconnect of any one of claims 1-3, wherein the electrical interconnect is a spring-loaded interconnect.

5. The electrical interconnect of any one of claims 1-3, wherein the electrical interconnect is a stamped interconnect.

6. The electrical interconnect of claim 1, wherein the conductive pathway further comprises: a linear conductive pathway, wherein the linear conductive pathway is in a first portion of the conductive pathway, and wherein the non-linear conductive pathway is in a second portion of the conductive pathway.

7. A connector comprising: a body; and an electrical interconnect extending into the body, comprising: a top conductive element; a bottom conductive element; and a conductive pathway electrically coupling the top element and the bottom element, wherein the conductive pathway is a non-linear conductive pathway, and wherein the electrical interconnect is configured to propagate an electrical signal that generates an electromagnetic field with an electric field that is orthogonal to a direction of electromagnetic field wave propagation.

8. The connector of claim 7, wherein the non-linear conductive pathway is helical.

9. The connector of claim 7, wherein the non-linear conductive pathway is sinusoidal.

10. The connector of claim 7, wherein the electrical interconnect further comprises: a linear conductive pathway, wherein the linear conductive pathway is in a first portion of the conductive pathway, and wherein the non-linear conductive pathway is in a second portion of the conductive pathway.

11. The connector of claim 7, wherein the electrical interconnect is a first electrical interconnect, and further comprising: a second electrical interconnect, comprising: a second top conductive element; a second bottom conductive element; and a second conductive pathway electrically coupling the second top element and the second bottom element, wherein the second conductive pathway is a linear conductive pathway.

12. The connector of claim 11, wherein the second electrical interconnect is configured to propagate an electrical signal that generates an electromagnetic field with a magnetic field that is orthogonal to a direction of electromagnetic field wave propagation.

13. The connector of claim 11, wherein the first electrical interconnect propagates an electrical signal that generates an electromagnetic field in a first direction, wherein the second electrical interconnect propagates an electrical signal that generates an electromagnetic field in a second direction, and wherein the second direction is orthogonal to the first direction.

14. The connector of claim 11, wherein the first electrical interconnect is adjacent to the second electrical interconnect.

15. The connector of claim 11, wherein the connector is a board-to-board connector. ​ ​ 16. The connector of claim 11, wherein the first electrical interconnect and the second electrical interconnect are part of an interconnect array, and wherein the interconnect array is arranged in an alternating fashion of the first electrical interconnect with the second electrical interconnect.

17. A connector comprising: a body; and a first electrical interconnect extending into the body having a first structure; and a second electrical interconnect extending into the body having a second structure, wherein the second structure is different than the first structure, wherein the first electrical interconnect is for propagating an electrical signal that generates an electromagnetic field having an electric field that is orthogonal to an electromagnetic field wave propagation direction.

18. The connector of claim 17, wherein the first structure is a spring-loaded structure, and wherein the second structure is not a spring-loaded structure.

19. The connector of claim 17, wherein the first structure is a stamped structure, and wherein the second structure is not a stamped structure.

20. A computing device comprising: a connector comprising: a body; and an electrical interconnect extending into the body comprising: a top conductive element; a bottom conductive element; and a conductive pathway electrically coupling the top element and the bottom element, wherein the conductive pathway is a non-linear conductive pathway; a first circuit board electrically coupled to the connector; and a second circuit board electrically coupled to the connector, and a conductive signal pathway between the first circuit board and the second circuit board via the connector, wherein the conductive signal pathway between the first circuit board and the second circuit board propagates an electrical signal such that the electrical signal has an electromagnetic field having an electric field that is orthogonal to an electromagnetic field wave propagation direction.

21. The computing device of claim 20, wherein the non-linear conductive pathway is helical.

22. The computing device of claim 20, wherein the non-linear conductive pathway is sinusoidal. ​

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