Fin Field-Effect Transistor Device Structure

Abstract

A fin field-effect transistor device structure and a method for forming the same are provided. The fin field-effect transistor device structure includes a fin structure extending on a substrate, and a gate structure formed on an intermediate portion of the fin structure. The intermediate portion of the fin structure is covered by the gate structure. The fin field-effect transistor device structure includes a source / drain structure adjacent to the gate structure, and the source / drain structure includes a doped region located in an outer portion of the source / drain structure, and the doped region includes gallium. The fin field-effect transistor device structure includes a metal silicide layer formed on the doped region of the source / drain structure, and the metal silicide layer is in direct contact with the doped region of the source / drain structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor structure, and particularly to a fin field effect transistor device structure and a method for forming the same. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the above material layers using a lithography process to form circuit components and elements on the semiconductor substrate. Usually, many integrated circuits are manufactured on a single semiconductor wafer, and the individual dies are separated by cutting along scribe lines between the integrated circuits. The above individual dies are typically separately encapsulated in, for example, a multi-chip module or other types of packages.

[0003] As the semiconductor industry has entered the nm technology process node, in the pursuit of higher device density, higher performance, and lower cost, etc., challenges from manufacturing and design problems have led to the development of three-dimensional designs, such as fin field effect transistors (FinFETs). A fin field effect transistor has thin vertical "fins" (or fin structures) extending from a substrate. The channel of the fin field effect transistor is formed in the vertical fins. The gate is located above the fins. The advantages of fin field effect transistors may include reduced short-channel effects and higher current flow.

[0004] Although existing fin field effect transistor devices and their manufacturing methods are generally sufficient to achieve the expected goals, they cannot fully meet all requirements. Summary of the Invention

[0005] An embodiment of the present invention provides a fin field effect transistor device structure, including: a fin structure extending above a substrate; a gate structure formed above an intermediate portion of the fin structure, wherein the intermediate portion of the fin structure is covered by the gate structure; a source / drain structure adjacent to the gate structure, wherein the source / drain structure includes a doped region located in an outer portion of the source / drain structure, and the doped region includes gallium; and a metal silicide layer formed above the doped region of the source / drain structure, wherein the metal silicide layer directly contacts the doped region of the source / drain structure.

[0006] Another embodiment of the present invention also provides a fin field effect transistor device structure, comprising: a fin structure extending over a substrate; a gate structure formed over an intermediate portion of the fin structure; a source / drain structure formed on one side of the gate structure, wherein the source / drain structure includes a gallium-doped region; an interlayer dielectric layer surrounding the source / drain structure, wherein the interlayer dielectric layer is doped with gallium; a metal silicide layer formed over the gallium-doped region; and a source / drain contact structure formed over the metal silicide layer.

[0007] Another embodiment of the present invention provides a method for forming a fin field effect transistor device structure, comprising: forming a fin structure, wherein the fin structure extends over a substrate; forming a gate structure, wherein the gate structure is formed over an intermediate portion of the fin structure; forming a source / drain structure over the fin structure, wherein the source / drain structure is adjacent to the gate structure; doping an outer portion of the source / drain structure to form a doped region, wherein the doped region includes gallium; forming a metal silicide layer over the doped region; and forming a source / drain contact structure over the metal silicide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description is presented in conjunction with the accompanying drawings to provide a complete disclosure. It should be noted that, in accordance with the general practice in the industry, the drawings are not necessarily drawn to scale. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced for clarity of illustration.

[0009] Figures 1A to 1J A perspective view illustrating various process stages of forming a fin field effect transistor device structure in accordance with some embodiments of the present invention.

[0010] Figures 2A to 2E A cross-sectional view illustrating various process stages of a fin field effect transistor device structure in accordance with some embodiments of the present invention after forming the structure as Figure 1J illustrated.

[0011] Figure 2E’ A cross-sectional view illustrating a fin field effect transistor device structure in accordance with some embodiments of the present invention.

[0012] Figures 3A to 3E A cross-sectional view illustrating various process stages of a fin field effect transistor device structure in accordance with some embodiments of the present invention after forming the structure as Figure 1J illustrated.

[0013] Figure 3E’ A cross-sectional view illustrating a fin field effect transistor device structure in accordance with some embodiments of the present invention.

[0014] Figures 4A to 4DCross-sectional views of various process stages of a fin field-effect transistor device structure according to some embodiments of the present invention are shown.

[0015] Figure 4D’ A cross-sectional view of a fin field-effect transistor device structure according to some embodiments of the present invention is shown.

[0016] Figures 5A to 5D Cross-sectional views of various process stages of a fin field-effect transistor device structure according to some embodiments of the present invention are shown.

[0017] Figure 5D’ A cross-sectional view of a fin field-effect transistor device structure according to some embodiments of the present invention is shown.

[0018] Among them, the reference numerals are explained as follows:

[0019] 11 - Ion implantation process

[0020] 100 - Fin field-effect transistor device structure

[0021] 100’ - Fin field-effect transistor device structure

[0022] 102 - Substrate

[0023] 104 - Dielectric layer

[0024] 106 - Mask layer

[0025] 108 - Photoresist layer

[0026] 110 - Fin structure

[0027] 110a - First fin structure

[0028] 110b - Second fin structure

[0029] 111 - Notch

[0030] 112 - Insulating layer

[0031] 114 - Isolation structure

[0032] 116 - dummy gate dielectric layer

[0033] 118 - dummy gate electrode layer

[0034] 120 - dummy gate structure

[0035] 122 - Gate spacer layer

[0036] 123 - Fin sidewall spacer

[0037] 124 - Source / drain structure

[0038] 124A - Upward crystal plane

[0039] 124B - Downward crystal plane

[0040] 126 - Contact etch stop layer

[0041] 128 - Interlayer dielectric layer

[0042] 133 - Trench

[0043] 134 - Merged source / drain structure

[0044] 134A - Upward crystal plane

[0045] 134B - Downward crystal plane

[0046] 135 - Recessed portion

[0047] 136 - Gate dielectric layer

[0048] 138 - Gate electrode layer

[0049] 140 - Gate structure

[0050] 151 - Contact opening

[0051] 200 - Fin field - effect transistor device structure

[0052] 200’ - Fin field - effect transistor device structure

[0053] 210 - Doped region

[0054] 212 - Metal layer

[0055] 214 - Metal nitride layer

[0056] 216 - Metal silicide layer

[0057] 220 - Source / drain contact structure

[0058] 300 - Fin field - effect transistor device structure

[0059] 300’ - Fin field - effect transistor device structure

[0060] θ - Angle Detailed implementation mode

[0061] The following disclosure provides many different embodiments or examples for implementing different features of the present case. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present specification describes a first component formed on or above a second component, it means that it may include embodiments in which the above-mentioned first component and the above-mentioned second component are in direct contact, and may also include embodiments in which additional components are formed between the above-mentioned first component and the second component, so that the above-mentioned first component and the second component may not be in direct contact. Additionally, the different examples disclosed below may reuse the same reference symbols and / or marks. These repetitions are for the purpose of simplification and clarity, and are not intended to limit a specific relationship between the different embodiments and / or structures discussed.

[0062] The following describes various variations of the embodiments. Through various views and the illustrated embodiments, similar element numbers are used to label similar elements. It should be understood that additional operation steps may be provided before, between, or after the described method, and in other embodiments of the described method, the order of the described partial steps may be changed, replaced, or omitted.

[0063] The fin can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the fin, where the lithography process can include double patterning or multiple patterning processes. Generally, the double patterning or multiple patterning process combines lithography with a self-aligned process, and thus can create a pattern with a small pitch, and the pitch of this pattern is less than, for example, the pitch that can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a lithography process. A spacer is formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and then the remaining spacer can be used to pattern the fin.

[0064] Embodiments of the present invention provide embodiments for forming a FinFET device structure. Figures 1A to 1J A perspective view showing the respective process stages of forming a FinFET device structure 100 according to some embodiments of the present invention.

[0065] Please refer to Figure 1A, a substrate 102 is provided. The substrate 102 can be formed of silicon or other semiconductor materials. Additionally and alternatively, the substrate 102 may include other elemental semiconductors, such as germanium. In some embodiments, the substrate 102 is formed of a compound semiconductor, such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is formed of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 has an epitaxial layer on top of a bulk semiconductor.

[0066] After that, a dielectric layer 104 and a capping layer 106 are formed on the substrate 102, and a photoresist layer 108 is formed on the capping layer 106. The photoresist layer 108 is patterned through a patterning process. The patterning process includes a lithography process and an etching process. The lithography process includes photoresist coating (e.g., spin coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

[0067] The dielectric layer 104 is a buffer layer between the substrate 102 and the capping layer 106. Additionally, when removing the capping layer 106, the dielectric layer 104 is used as a stop layer. The dielectric layer 104 can be formed of silicon oxide. The capping layer 106 can be formed of silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. In some other embodiments, more than one capping layer 106 is formed on the dielectric layer 104.

[0068] A dielectric layer 104 and a capping layer 106 are formed by a deposition process, which includes, for example, a chemical vapor deposition (CVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, a sputtering process, or other suitable processes.

[0069] According to some embodiments, as Figure 1B illustrated, after patterning the photoresist layer 108, the dielectric layer 104 and the capping layer 106 are patterned by using the patterned photoresist layer 108 as a mask. In this way, a patterned dielectric layer 104 and a patterned capping layer 106 are obtained. Then, the patterned photoresist layer 108 is removed.

[0070] Next, an etching process is performed on the substrate 102 by using the patterned dielectric layer 104 and the patterned capping layer 106 as masks to form a fin structure 110. The etching process can be a dry etching process or a wet etching process.

[0071] In some embodiments, the substrate 102 is etched using a dry etching process. The dry etching process includes using a fluorine-based gas, such as sulfur hexafluoride (SF6), carbon fluoride (C x F y )), nitrogen trifluoride (NF3), or a combination of the above. The etching process can be a time-controlled process and continues until the fin structure 110 reaches a predetermined height. In some embodiments, the fin structure 110 has a width, and this width gradually increases from the upper part to the lower part.

[0072] According to some embodiments, as Figure 1C illustrated, after forming the fin structure 110, an insulating layer 112 is formed to cover the fin structure 110 located on the substrate 102.

[0073] In some embodiments, the insulating layer 112 is formed of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-k dielectric materials. The insulating layer 112 can be deposited by a chemical vapor deposition process, a spin-on-glass process, or other suitable processes.

[0074] Thereafter, the insulating layer 112 is thinned or planarized to expose the top surface of the patterned capping layer 106. In some embodiments, the insulating layer 112 is thinned by a chemical mechanical polishing (CMP) process. Thereafter, the patterned dielectric layer 104 and the patterned capping layer 106 are removed.

[0075] Thereafter, according to some embodiments, as Figure 1D illustrated, a portion of the insulating layer 112 is removed to form an isolation structure 114. The isolation structure 114 can be a shallow trench isolation (STI) structure surrounding the fin structure 110. The lower portion of the fin structure 110 is surrounded by the isolation structure 114, and the upper portion of the fin structure 110 extends protruding above the isolation structure 114. In other words, a portion of the fin structure 110 is buried in the isolation structure 114. The isolation structure 114 is used to avoid electrical interference or crosstalk.

[0076] Thereafter, according to some embodiments, as Figure 1E illustrated, a dummy gate structure 120 is formed across the fin structure 110 and extends over the isolation structure 114.

[0077] In some embodiments, the dummy gate structure 120 includes a dummy gate dielectric layer 116 and a dummy gate electrode layer 118, where the dummy gate electrode layer 118 is located above the dummy gate dielectric layer 116. After forming the dummy gate structure 120, a gate spacer layer 122 is formed on the sidewall surfaces on opposite sides of the dummy gate structure 120. The gate spacer layer 122 can be a single layer or multiple layers. Fin sidewall spacers 123 are formed on the sidewall surfaces on opposite sides of the fin structure 110. The fin sidewall spacers 123 can be a single layer or multiple layers.

[0078] Thereafter, according to some embodiments, as Figure 1F illustrated, the upper portion of the fin structure 110 is removed to form a notch 111. The bottom surface of the notch 111 is lower than the top surface of the isolation structure 114.

[0079] Thereafter, according to some embodiments, as Figure 1G illustrated, a source / drain (S / D) structure 124 is formed on the fin structure 110.

[0080] In some embodiments, the portion of the fin structure 110 adjacent to the dummy gate structure 120 is recessed to form notches on both sides of the fin structure 110, and a strained material is grown in the notches by an epitaxial process to form the source / drain structure 124. The source / drain structure 124 is formed on the fin structure 110.

[0081] In addition, the lattice constant of the stress material can be different from that of the substrate 102. In some embodiments, the source / drain structure 124 includes germanium (Ge), silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), gallium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP), or the like. In some embodiments, the source / drain structure 124 is formed of silicon germanium (Si x Ge y , where x is in the range of 0.05 - 0.5 and Y is in the range of 0.5 - 0.95), and the percentage of germanium atoms is in the range of 50 to 95. In some embodiments, the source / drain structure 124 is formed of doped silicon germanium (Si x Ge y , where x is in the range of 0.05 - 0.5 and Y is in the range of 0.5 - 0.95), where the doped silicon germanium can be, for example, boron-doped silicon germanium (Si x Ge y , where x is in the range of 0.05 - 0.5 and Y is in the range of 0.5 - 0.95).

[0082] After that, according to some embodiments, as Figure 1H shown, after forming the source / drain structure 124, a contact etch stop layer (CESL) 126 is formed on the substrate 102, and an inter-layer dielectric (ILD) layer 128 is formed on the contact etch stop layer 126.

[0083] In some other embodiments, the contact etch stop layer 126 is formed of silicon nitride, silicon oxynitride, and / or other suitable materials. The contact etch stop layer 126 can be formed by a plasma enhanced chemical vapor deposition (PECVD) process, a low-pressure chemical vapor deposition (LPCVD) process, an atomic layer deposition (ALD) process, or other suitable processes.

[0084] The interlayer dielectric layer 128 may include a multi-layer structure formed of various dielectric materials, where the dielectric materials may include, for example, silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant dielectric materials, and / or other suitable dielectric materials. Examples of low dielectric constant dielectric materials may include, but are not limited to: fluorine-doped silicate glass, carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The interlayer dielectric layer 128 may be formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, or other suitable processes.

[0085] After that, a polishing process is performed on the interlayer dielectric layer 128 until the top surface of the dummy gate structure 120 is exposed. In some embodiments, the interlayer dielectric layer 128 is planarized by a chemical mechanical polishing process.

[0086] After that, according to some embodiments, as Figure 1I illustrated, the dummy gate structure 120 is removed to form a trench 133 in the interlayer dielectric layer 128. The dummy gate dielectric layer 116 and the dummy gate electrode layer 118 are removed by an etching process, for example, a dry etching process or a wet etching process.

[0087] After that, according to some embodiments, as Figure 1J illustrated, a gate structure 140 is formed in the trench 133. The gate structure 140 is formed on the isolation structure 114. The gate structure 140 includes a gate dielectric layer 136 and a gate electrode layer 138, where the gate electrode layer 138 is located on the gate dielectric layer 136.

[0088] The gate dielectric layer 136 may be a single layer or multiple layers. The gate dielectric layer 136 is formed of the following materials: silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), a dielectric material with a high dielectric constant (high-k), or a combination of the above. In some embodiments, the gate dielectric layer 136 is formed by a plasma enhanced chemical vapor deposition process or a spin coating process.

[0089] The gate electrode layer 138 is formed of a conductive material, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. The gate electrode layer 138 is formed by a deposition process, for example, chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, high density plasma chemical vapor deposition process, metal-organic chemical vapor deposition (MOCVD) process, or plasma enhanced chemical vapor deposition process.

[0090] In some embodiments, a work function layer is formed between the gate dielectric layer 136 and the gate electrode layer 138. The work function layer is formed of a metal material, and this metal material may include an N-type work function metal or a P-type work function metal. The N-type work function metal includes tungsten, copper, titanium, silver (Ag), aluminum, titanium-aluminum alloy (TiAl alloy), titanium-aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or a combination of the above. The P-type work function metal includes titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or a combination of the above.

[0091] Figures 2A to 2E Illustrates cross-sectional views of various process stages of the fin field-effect transistor device structure 100 according to some embodiments of the present invention after forming the structure as Figure 1J shown.

[0092] Figure 2A Illustrates a cross-sectional view along the Figure 1J I-I' cross-section line of the fin field-effect transistor device structure 100. A contact etch stop layer 126 is formed on the source / drain structure 124, and an interlayer dielectric layer 128 is formed on the contact etch stop layer 126. The source / drain structure 124 includes an upwardly facing facet 124A and a downwardly facing facet 124B.

[0093] After that, according to some embodiments, as Figure 2B shown, a portion of the interlayer dielectric layer 128 and a portion of the contact etch stop layer 126 are removed to form a contact opening 151. In this way, a portion of the source / drain structure 124 is exposed. More specifically, the outer portion of the source / drain structure 124 is exposed. In some embodiments, the upwardly facing facet 124A and the downwardly facing facet 124B of the source / drain structure 124 are exposed.

[0094] After that, according to some embodiments, such as Figure 2C As shown, a portion of the source / drain structure 124 is doped to form a doped region 210 within the source / drain structure 124. The doped region 210 is formed by performing an ion implantation process 11. More specifically, the source / drain structure 124 includes an outer portion and an inner portion, and the outer portion of the source / drain structure 124 is doped. The exposed surfaces of the upward-facing plane 124A and the downward-facing plane 124B of the source / drain structure 124 are doped with an impurity to form the doped region 210.

[0095] Since the source / drain structure 124 has a rhombic shape, the doped region 210 has different doping concentrations. In some embodiments, the doped region 210 has a first portion located on the upward-facing plane 124A and a second portion located on the downward-facing plane 124B. The doping concentration of the first portion of the doped region 210 is higher than that of the second portion of the doped region 210. In other words, the doping degree of the first portion of the doped region 210 is more severe than that of the second portion of the doped region 210.

[0096] In some embodiments, the outer portion of the source / drain structure 124 is doped with a dopant to form the doped region 210, and this dopant includes gallium (Ga). The doped region 210 is a gallium-doped region. The doped region 210 is used to reduce the contact resistance between the source / drain structure 124 and the metal silicide 126 (to be formed subsequently).

[0097] In some embodiments, when the source / drain structure 124 is formed of undoped or doped silicon germanium and the dopant is gallium, as the concentration of germanium in the silicon germanium increases, the solid solubility of gallium will increase accordingly. Different from gallium, the solid solubility of boron will decrease as the concentration of germanium in the silicon germanium increases. If the source / drain structure 124 is only doped with boron, due to its low solid solubility, the doping concentration of boron will be limited. Therefore, compared with boron, due to the higher solid solubility of gallium, the doping amount of gallium doped into the source / drain structure 124 is higher.

[0098] The doped region 210 in this specification is doped with gallium. Since gallium is heavier than boron, the diffusion of gallium is slower than that of boron, which can avoid the short channel effect caused by the dopant diffusing into the channel region. The channel region is directly under the gate structure and between the source structure and the drain structure.

[0099] In some embodiments, the source / drain structure 124 is made of silicon germanium (Si x Gey ) formed, where the range of x is from about 5% to about 50%, and the range of y is from about 50% to about 95%. The compressive stress in the channel region of the P-type fin field effect transistor device is improved by increasing the concentration of germanium. If the germanium concentration is less than 50%, the performance of the P-type fin field effect transistor device will be reduced. When the germanium concentration is within the above range, the performance of the P-type fin field effect transistor device can be improved.

[0100] In some embodiments, the source / drain structure 124 is doped using a gallium source / drain structure pair. Therefore, the doped region 210 is formed of gallium-doped silicon germanium (SiGeGa). The concentration of gallium ranges from about 1E19 atoms / cm³ to about 4E20 atoms / cm³. In some embodiments, the doping depth of the doped region 210 ranges from about 5 nm to about 15 nm. The energy of the ion implantation process 11 ranges from about 2 KeV to about 6 KeV.

[0101] In some other embodiments, the source / drain structure 124 is doped using gallium and boron. Therefore, the doped region 210 is formed of gallium and boron-doped silicon germanium (SiGeGaB). In some embodiments, the concentration of gallium ranges from about 1E19 atoms / cm³ to about 4E20 atoms / cm³, and the concentration of boron ranges from about 1E19 atoms / cm³ to about 1E21 atoms / cm³.

[0102] When both gallium and boron are co-doped into the source / drain structure 124, the doping order is important. In some embodiments, a first doping process is performed on the source / drain structure 124, and the first ion implantation process includes using a first dopant, and this first dopant is gallium. Then, a second doping process is performed on the source / drain structure 124, and the second ion implantation process includes using a second dopant, and this second dopant is boron.

[0103] Gallium is doped first, and then boron is doped. Boron is lighter than gallium and boron easily diffuses into the channel region. If boron is doped before gallium, boron may easily diffuse into the channel region, causing an unwanted short channel effect. Therefore, the doping order in this specification is used to reduce and avoid the diffusion of boron into the channel region. In this way, the risk of short channel effect and leakage current can be reduced.

[0104] Note that, in addition to the source / drain structure 124, gallium (Ga) and gallium / boron (Ga / B) can also be used to dope the interlayer dielectric layer 128. In some embodiments, gallium is also used to dope the interlayer dielectric layer 128, and the interlayer dielectric layer 128 includes a gallium dopant. The gallium doping concentration of the interlayer dielectric layer 128 gradually decreases from the top surface to the bottom surface. In some other embodiments, gallium and boron are also used to dope the interlayer dielectric layer 128, and the interlayer dielectric layer 128 includes a gallium dopant and a boron dopant.

[0105] After that, according to some embodiments, as Figure 2D shown, a metal layer 212 and a metal nitride layer 214 are formed on the doped region 210. The metal layer 212 and the metal nitride layer 214 are formed on the isolation structure 214. The metal layer 212 is used to reduce the contact resistance of the source / drain contact structure. The metal nitride layer 214 is used as a diffusion barrier layer to prevent the metal in the metal layer 212 from being oxidized.

[0106] The metal layer 212 is formed of nickel (Ni), titanium (Ti), cobalt (Co), tantalum (Ta), or platinum (Pt) or other suitable materials. The metal nitride layer 214 is formed of nickel nitride (NiN), titanium nitride (TiN), cobalt nitride (CoN), tantalum nitride (TaN), or platinum nitride (PtN) or other suitable materials. In some embodiments, the metal layer 212 is formed of titanium, and the metal nitride layer 214 is formed of titanium nitride. The metal layer 212 and the metal nitride layer 214 can be formed by a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or other suitable processes. In some embodiments, the thickness of the metal layer 212 ranges from about 5 nm to about 7 nm. In some embodiments, the thickness of the metal nitride layer 214 ranges from about 1 nm to about 2 nm.

[0107] After that, according to some embodiments, as Figure 2E shown, an annealing process is performed on the metal layer 212 and the metal nitride layer 214 to form a metal silicide layer 216 on the doped region 210, and the remaining contact openings 151 are filled with a conductive material to form a source / drain contact structure 220. The metal silicide layer 216 is formed on the doped region 210 and directly contacts the doped region 210. The annealing process is used to activate the dopants located in the source / drain structure 124.

[0108] By performing the annealing process, the metal layer 212 reacts with the silicon in the source / drain structure 124 to form the metal silicide layer 216. In some embodiments, the metal layer 212 is formed of titanium, and the metal silicide layer 216 is formed of titanium silicide (TiSi x) is formed. In some embodiments, the metal layer 212 is formed of tantalum, and the metal silicide layer 216 is formed of tantalum silicide (TaSi x ) is formed. The unreacted metal layer 212 and the metal nitride layer 214 remain on the isolation structure 214.

[0109] The annealing process can be a thermal soaking process, a spike annealing process, a flash annealing process, or a laser annealing process. In some embodiments, the annealing process is carried out in a temperature range of about 500°C to about 700°C. In some embodiments, the duration of the annealing process ranges from about 5 seconds to about 30 seconds.

[0110] It should be noted that when the doped region 210 is formed of silicon germanium doped with gallium and boron, and the metal silicide layer 216 is formed of titanium silicide, titanium and boron will react to form a compound. In this way, boron in the doped region 210 may diffuse into the channel region.

[0111] The source / drain contact structure 220 can be formed of tungsten, tungsten alloy, aluminum, aluminum alloy, copper, or copper alloy. The source / drain contact structure 220 is electrically connected to the source / drain structure 124 through the metal silicide layer 216.

[0112] It should be noted that the source / drain structure 124 is formed of a semiconductor material, and the metal silicide layer 216 is formed of a metal material. Therefore, there is a barrier between the semiconductor material and the metal material. If there is no interface layer between the metal silicide layer 216 and the source / drain structure 124, there will be a junction. The doped region 210 is used as the interface layer to reduce the contact resistance (Rcsd) between the metal silicide layer 216 and the source / drain structure 124.

[0113] Figure 2E’ A cross-sectional view of a fin field-effect transistor device structure 100' according to some embodiments of the present invention is shown. Figure 2E’ The structure is similar to Figure 2E the structure, except that the metal layer 212 does not completely react with the silicon in the source / drain structure 124, and the unreacted metal layer 212 remains on Figure 2E’ the metal silicide layer 216 of Figure 2E’As shown. In addition, the portion of the metal layer 212 located above the isolation structure 114 is thicker than the remaining metal layer 212 located above the metal silicide layer 216.

[0114] Figures 3A to 3E The cross-sectional views of various process stages of the fin field-effect transistor device structure 100 according to some embodiments of the present invention after forming the structure as Figure 1J shown. Figure 3A The cross-sectional view shows along Figure 1J the II-II' cross-section line of the fin field-effect transistor device structure 100.

[0115] According to some embodiments, as Figure 3A shown, the gate spacer layer 122 is formed on the sidewall surfaces of the opposite sides of the gate structure 140. The contact etch stop layer 126 is formed on the source / drain structure 124, and the interlayer dielectric layer 128 is formed on the contact etch stop layer 126.

[0116] After that, according to some embodiments, as Figure 3B shown, a part of the interlayer dielectric layer 128 and a part of the contact etch stop layer 126 are removed to form the contact opening 151. In this way, the top portion of the source / drain structure 124 is exposed.

[0117] After that, according to some embodiments, as Figure 3C shown, a part of the source / drain structure 124 is doped to form the doped region 210 in the source / drain structure 124. The source / drain structure 124 is doped by performing the ion implantation process 11. More specifically, the outer part of the source / drain structure 124 is doped to form the doped region 210.

[0118] After that, according to some embodiments, as Figure 3D shown, the metal layer 212 and the metal nitride layer 214 are formed on the doped region 210.

[0119] After that, according to some embodiments, as Figure 3E shown, the annealing process is performed on the metal layer 212 and the metal nitride layer 214 to form the metal silicide layer 216, and the source / drain contact structure 220 is formed on the metal silicide layer 216. The metal silicide layer 216 is formed on the doped region 210 and directly contacts the doped region 210. The annealing process is used to activate the dopants in the source / drain structure 124. In some embodiments, the silicon in the source / drain structure 124 reacts with titanium to form titanium silicide as the metal silicide layer 216.

[0120] Figure 3E’A cross-sectional view of a fin field-effect transistor device structure 100' according to some embodiments of the present invention is shown. Figure 3E’ The structure of Figure 3E is similar to that of Figure 2E’ , except that the metal layer 212 does not fully react with the silicon in the source / drain structure 124, and the unreacted metal layer 212 remains on Figure 3E’ the silicide layer 216 of

[0121] Figures 4A to 4D A cross-sectional view of each process stage of a fin field-effect transistor device structure 200 according to some embodiments of the present invention is shown. Some of the processes and materials used to form the fin field-effect transistor device structure 200 are similar to or the same as those used to form the fin field-effect transistor device structure 100, and thus will not be described in detail.

[0122] According to some embodiments, as shown in Figure 4A , a portion of the interlayer dielectric layer 128 and a portion of the contact etch stop layer 126 are removed to form a contact opening 151. More specifically, the upward crystal plane 124A and the downward crystal plane 124B of the source / drain structure 124 are exposed. There is an angle θ between the upward crystal plane 124A and the downward crystal plane 124B. In some embodiments, this angle θ is about 80 degrees to about 150 degrees.

[0123] After that, according to some embodiments, as shown in Figure 4B , a portion of the source / drain structure 124 is doped to form a doped region 210 in the source / drain structure 124. The doped region 210 is formed by performing an ion implantation process 11. In some embodiments, due to the shadow effect, a portion of the source / drain structure 124 is not doped. Therefore, the doped region 210 is formed above the upward crystal plane 124A, but not above the downward crystal plane 124B.

[0124] After that, according to some embodiments, as shown in Figure 4C , a metal layer 212 and a metal nitride layer 214 are formed on the doped region 210.

[0125] After that, according to some embodiments, as shown in Figure 4D , an annealing process is performed on the metal layer 212 and the metal nitride layer 214 to form a silicide layer 216, and a source / drain contact structure 220 is formed on the silicide layer 216. It should be noted that the doped region 210 is interposed between the source / drain structure 124 and the silicide layer 216 to reduce the contact resistance between the source / drain structure 124 and the silicide layer 216.

[0126] Figure 4D’ A cross-sectional view of a fin field-effect transistor device structure 200' in accordance with some embodiments of the present invention is shown. Figure 4D’ The structure of... is similar to Figure 4D the structure of..., with the difference that the metal layer 212 does not fully react with the silicon in the source / drain structure 124, and the unreacted metal layer 212 remains on Figure 2E’ the silicide layer 216 of..., as Figure 4D’ shown. Thus, the silicide layer 216 is between the doped region 210 and the metal layer 212, and the metal layer 212 is between the silicide layer 216 and the source / drain contact structure 220. In addition, the portion of the metal layer 212 above the isolation structure 114 is thicker than the remaining metal layer 212 above the silicide layer 216.

[0127] Figures 5A to 5D Cross-sectional views of various process stages of a fin field-effect transistor device structure 300 in accordance with some embodiments of the present invention are shown.

[0128] According to some embodiments, as Figure 5A shown, a merged source / drain structure 134 is formed over the first fin structure 110a and the second fin structure 110b. The merged source / drain structure 134 has a recessed portion 135, where the recessed portion 135 is located at the center of the merged source / drain structure 134. Due to the recessed portion 135, the merged source / drain structure 134 can provide a larger surface area for the source / drain contact structure 220 to sit on.

[0129] After that, according to some embodiments, as Figure 5B shown, the upper portion of the merged source / drain structure 134 is doped to form a doped region 210. The doped region 210 extends from a first position to a second position. The first position is formed over the first fin structure 110a, and the second position is formed over the second fin structure 110b. The doped region 210 is formed over the upward crystal plane 134A, but not over the downward crystal plane 134B.

[0130] After that, according to some embodiments, as Figure 5C shown, a metal layer 212 and a metal nitride layer 214 are formed over the doped region 210.

[0131] After that, according to some embodiments, as Figure 5DAs shown, an annealing process is performed on the metal layer 212 and the metal nitride layer 214 to form a metal silicide layer 216 over the doped region 210, and the remaining contact openings 151 are filled with a conductive material to form a source / drain contact structure 220.

[0132] The doped region 210 is interposed between the merged source / drain structure 134 and the metal silicide layer 216 to reduce the contact resistance between the merged source / drain structure 134 and the metal silicide layer 216. The doped region 210 is formed along the shape of the merged source / drain structure 134. Thus, the doped region 210 has a wave-shaped structure.

[0133] Figure 5D’ A cross-sectional view of a fin field-effect transistor device structure 300' according to some embodiments of the present invention is shown. Figure 5D’ The structure is similar to Figure 5D the structure, except that the metal layer 212 does not completely react with the silicon in the merged source / drain structure 134, and the unreacted metal layer 212 remains on Figure 2E’ the metal silicide layer 216 of Figure 5D’ as shown. Thus, the metal silicide layer 216 is interposed between the doped region 210 and the metal layer 212, and the metal layer 212 is interposed between the metal silicide layer 216 and the source / drain contact structure 220.

[0134] It should be noted that the doped region 210 includes gallium. In some embodiments, the outer portion of the source / drain structure 124 is doped with gallium to form the gallium-doped region 210. The use of gallium in the gallium-doped region 210 provides many advantages. The solid solubility of gallium increases as the germanium concentration in the silicon germanium of the source / drain structure 124 increases. Thus, when the doped region 210 includes gallium, due to the higher concentration of gallium in the doped region 210, it can provide high stress to the fin field-effect transistor device structure, thereby improving the performance of the fin field-effect transistor device structure. Since gallium is heavier than boron, the diffusion of gallium is slower than that of boron, which can avoid the short-channel effect caused by dopant diffusion into the channel region. The channel region is directly under the gate structure and is interposed between the source structure and the drain structure. The solid solubility of gallium is greater than that of boron, and gallium is heavier than boron. Thus, when the doped region 210 in the source / drain structure 124 or the merged source / drain structure 134 includes gallium, the performance of the fin field-effect transistor device structure can be improved.

[0135] In some embodiments, when doping the doped region 210 with gallium and boron, gallium is doped first, and boron is doped later. Boron is lighter than gallium and is prone to diffusion into the channel region. If boron is doped before gallium, boron may easily diffuse into the channel region, resulting in an unwanted short-channel effect. Therefore, the doping sequence in this specification is used to reduce and avoid the diffusion of boron into the channel region. In this way, the risks of short-channel effect and leakage current can be reduced.

[0136] Some embodiments of a fin field-effect transistor device structure and a manufacturing method thereof are provided herein. The fin field-effect transistor device structure includes a fin structure formed on a substrate, and a gate structure formed on the fin structure. Source / drain structures are formed adjacent to the gate structure. Dopants are used to dope the outer portions of the source / drain structures to form doped regions. The doped regions include gallium or gallium / boron. A metal silicide layer is formed on and in direct contact with the doped regions. The doped regions are used to reduce the contact resistance between the source / drain structures formed of semiconductor materials and the metal silicide layers formed of metal layers. Therefore, the performance of the fin field-effect transistor device structure can be improved.

[0137] In some embodiments of the present invention, a fin field-effect transistor device structure is provided. The fin field-effect transistor device structure includes a fin structure extending on a substrate, and a gate structure formed on an intermediate portion of the fin structure. The intermediate portion of the fin structure is covered by the gate structure. The fin field-effect transistor device structure includes source / drain structures adjacent to the gate structure, and the source / drain structures include doped regions located in outer portions of the source / drain structures, and the doped regions include gallium. The fin field-effect transistor device structure includes a metal silicide layer formed on the doped regions of the source / drain structures, and the metal silicide layer is in direct contact with the doped regions of the source / drain structures.

[0138] The fin field-effect transistor device structure as described in some embodiments of the present invention. The fin field-effect transistor device structure further includes a source / drain contact structure formed on the metal silicide layer, wherein the source / drain contact structure is electrically connected to the source / drain structures through the metal silicide layer.

[0139] The fin field-effect transistor device structure as described in some embodiments of the present invention, wherein the source / drain structures are formed of silicon germanium, and the doped regions of the source / drain structures are formed of silicon germanium doped with gallium or silicon germanium doped with gallium and boron.

[0140] The fin field-effect transistor device structure as described in some embodiments of the present invention. The above fin field-effect transistor device structure further includes a metal layer formed on the above metal silicide layer; a metal nitride layer formed on the above metal layer; and a source / drain contact structure formed on the above metal nitride layer, wherein the above metal nitride layer is in direct contact with the above metal layer and the above source / drain contact structure.

[0141] The fin field-effect transistor device structure as described in some embodiments of the present invention. The above fin field-effect transistor device structure further includes an interlayer dielectric layer, which is formed on the above fin structure and adjacent to the above gate structure, wherein the above interlayer dielectric layer is doped with gallium, and the gallium concentration of the above interlayer dielectric layer gradually increases from the bottom to the top.

[0142] The fin field-effect transistor device structure as described in some embodiments of the present invention. The above fin field-effect transistor device structure further includes an isolation structure formed on the above substrate, wherein the above gate structure and the above source / drain structure are both formed on the above isolation structure, and the above doped region is higher than the above isolation structure.

[0143] In some other embodiments of the present invention, a fin field-effect transistor device structure is provided. The above fin field-effect transistor device structure includes a fin structure extending on a substrate, and a gate structure formed on the middle part of the above fin structure. The above fin field-effect transistor device structure includes a source / drain structure formed on one side of the above gate structure, wherein the above source / drain structure includes a doped region doped with gallium. The above fin field-effect transistor device structure also includes an interlayer dielectric layer surrounding the above source / drain structure, wherein the above interlayer dielectric layer is doped with gallium. The above fin field-effect transistor device structure further includes a metal silicide layer formed on the above doped region doped with gallium; and a source / drain contact structure formed on the above metal silicide layer.

[0144] The fin field-effect transistor device structure as described in some other embodiments of the present invention, wherein the above source / drain structure is formed of silicon germanium (Si x Ge y ), where x ranges from about 5% to about 50%, and y ranges from about 50% to about 95%.

[0145] The fin field-effect transistor device structure as described in some other embodiments of the present invention, wherein the above doped region doped with gallium is formed of silicon germanium doped with gallium or silicon germanium doped with gallium and boron.

[0146] The fin field-effect transistor device structure as described in some other embodiments of the present invention, wherein the gallium concentration of the above interlayer dielectric layer gradually increases from the bottom to the top.

[0147] A fin field-effect transistor device structure as described in some other embodiments of the present invention, wherein the metal silicide layer directly contacts the doped gallium doped region.

[0148] A fin field-effect transistor device structure as described in some other embodiments of the present invention. The fin field-effect transistor device structure further includes another fin structure extending above the substrate, wherein the source / drain structure is formed on the another fin structure, and the doped gallium doped region extends from a first position to a second position, and the first position is higher than the fin structure, the second position is higher than the another fin structure, and the doped gallium doped region has a waveform structure.

[0149] A fin field-effect transistor device structure as described in some other embodiments of the present invention, wherein the source / drain structure includes a plurality of upward crystal planes and a plurality of downward crystal planes, and the doped gallium doped region is formed on the upward crystal planes, but not formed on the downward crystal planes.

[0150] A fin field-effect transistor device structure as described in some other embodiments of the present invention. The fin field-effect transistor device structure further includes a metal layer formed on the metal silicide layer, wherein the metal layer is between the metal silicide layer and the source / drain contact structure.

[0151] In still some other embodiments of the present invention, a method for forming a fin field-effect transistor device structure is provided. The method includes forming a fin structure, wherein the fin structure extends above the substrate; and forming a gate structure, wherein the gate structure is formed on the middle part of the fin structure. The method also includes forming a source / drain structure on the fin structure, wherein the source / drain structure is adjacent to the gate structure. The method further includes doping an outer part of the source / drain structure to form a doped region, wherein the doped region includes gallium. The method includes forming a metal silicide layer on the doped region; and forming a source / drain contact structure on the metal silicide layer.

[0152] A fin field-effect transistor device structure as described in some other embodiments of the present invention. The method further includes forming a metal layer on the doped region; forming a metal nitride layer on the metal layer; and annealing the metal nitride layer and the metal layer to form the metal silicide layer on the doped region.

[0153] A fin field-effect transistor device structure as described in some other embodiments of the present invention, wherein forming the above source / drain structure on the above fin structure includes: removing a part of the above fin structure to form a notch adjacent to the above gate structure; and epitaxially forming a stress material in the above notch and on the above fin structure to form the above source / drain structure.

[0154] A fin field-effect transistor device structure as described in some other embodiments of the present invention, wherein the above source / drain structure is formed of silicon germanium, and the above doped region is formed of gallium-doped silicon germanium or gallium- and boron-doped silicon germanium.

[0155] A fin field-effect transistor device structure as described in some other embodiments of the present invention, wherein forming the above doped region on the above source / drain structure includes: performing a first ion implantation process on the above source / drain structure, and the above first ion implantation process includes using a first dopant, and the above first dopant includes gallium.

[0156] A fin field-effect transistor device structure as described in some other embodiments of the present invention. The above method further includes, after performing the above first ion implantation process, performing a second ion implantation process on the above source / drain structure, wherein the above second ion implantation process includes using a second dopant, and the above second dopant includes boron.

[0157] The foregoing text outlines the components of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Various changes, substitutions, or modifications can be made to the present invention without departing from the spirit and scope of the present invention.

[0158] Although the present invention has been disclosed above with several preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the claims.

Claims

1. A fin field effect transistor device structure, comprising: A fin structure extends over a substrate; A gate structure is formed over an intermediate portion of the fin structure, wherein the intermediate portion of the fin structure is covered by the gate structure; An interlayer dielectric layer is formed over the fin structure and adjacent to the gate structure, wherein the interlayer dielectric layer is doped with gallium and the gallium concentration of the interlayer dielectric layer gradually increases from bottom to top; A source / drain structure is adjacent to the gate structure, wherein the source / drain structure includes a doped region located at an outer portion of the source / drain structure, and the doped region includes gallium; and A metal silicide layer is formed over the doped region of the source / drain structure, wherein the metal silicide layer directly contacts the doped region of the source / drain structure.

2. The fin field effect transistor device structure according to claim 1, further comprising: A source / drain contact structure is formed on the metal silicide layer, wherein the source / drain contact structure is electrically connected to the source / drain structure through the metal silicide layer.

3. The fin field effect transistor device structure according to claim 1, wherein the source / drain structure is formed of silicon germanium, and the doped region of the source / drain structure is formed of gallium-doped silicon germanium or gallium- and boron-doped silicon germanium.

4. The fin field effect transistor device structure according to claim 1, further comprising: A metal layer is formed over the metal silicide layer; A metal nitride layer is formed over the metal layer; And A source / drain contact structure is formed over the metal nitride layer, wherein the metal nitride layer directly contacts the metal layer and the source / drain contact structure.

5. The fin field effect transistor device structure according to claim 1, further comprising: An isolation structure is formed over the substrate, wherein the gate structure and the source / drain structure are both formed over the isolation structure, and the doped region is higher than the isolation structure.

6. A fin field effect transistor device structure, comprising: A fin structure extends over a substrate; A gate structure is formed over an intermediate portion of the fin structure; A source / drain structure is formed on one side of the gate structure, wherein the source / drain structure includes a doped region doped with gallium; An interlayer dielectric layer surrounds the source / drain structure, wherein the interlayer dielectric layer is doped with gallium and the gallium concentration of the interlayer dielectric layer gradually increases from bottom to top; A metal silicide layer is formed over the doped region doped with gallium; And A source / drain contact structure is formed over the metal silicide layer.

7. The fin field effect transistor device structure according to claim 6, wherein the source / drain structure is formed of Si x Ge y where x ranges from 5% to 50% and y ranges from 50% to 95%.

8. The fin field effect transistor device structure according to claim 6, wherein the gallium-doped region is formed of gallium-doped silicon germanium or gallium- and boron-doped silicon germanium.

9. The fin field effect transistor device structure according to claim 6, wherein the metal silicide layer is in direct contact with the gallium-doped region.

10. The fin field effect transistor device structure according to claim 6, further comprising: Another fin structure extends over the substrate, wherein the source / drain structure is formed over the another fin structure, and the doped region doped with gallium extends from a first position to a second position, and the first position is higher than the fin structure, the second position is higher than the another fin structure, and the doped region doped with gallium has a waveform structure.

11. The fin field-effect transistor device structure according to claim 6, wherein the source / drain structure includes a plurality of upward crystal planes and a plurality of downward crystal planes, and the gallium-doped region is formed on the plurality of upward crystal planes but not on the plurality of downward crystal planes.

12. The fin field-effect transistor device structure according to claim 6, further comprising: A metal layer is formed over the metal silicide layer, wherein the metal layer is between the metal silicide layer and the source / drain contact structure.

13. A fin field-effect transistor device structure, comprising: A fin structure extends over a substrate; A gate structure is formed over an intermediate portion of the fin structure; An interlayer dielectric layer is formed over the fin structure and adjacent to the gate structure, wherein the interlayer dielectric layer is doped with gallium and the gallium concentration of the interlayer dielectric layer gradually increases from bottom to top; A source / drain structure is adjacent to the gate structure; A gallium interface layer is located over the source / drain structure; And A metal silicide layer is formed over the gallium interface layer.

14. The fin field-effect transistor device structure according to claim 13, wherein the source / drain structure includes a plurality of upward crystal planes and a plurality of downward crystal planes, and the gallium interface layer has a first portion located on the plurality of upward crystal planes and a second portion located on the plurality of downward crystal planes.

15. The fin field-effect transistor device structure according to claim 14, wherein the doping concentration of the first portion is greater than that of the second portion.

16. The fin field-effect transistor device structure according to claim 13, wherein the source / drain structure includes a plurality of upward crystal planes and a plurality of downward crystal planes, and the gallium interface layer is formed on the plurality of upward crystal planes but not on the plurality of downward crystal planes.

17. The fin field-effect transistor device structure according to claim 16, wherein the metal silicide layer is in direct contact with the gallium interface layer and the source / drain contact structure.

18. The fin field-effect transistor device structure according to claim 13, wherein the source / drain structure is formed of silicon germanium, and the gallium interface layer is formed of gallium-doped silicon germanium or gallium- and boron-doped silicon germanium.

19. A method for forming a fin field-effect transistor device structure, comprising: Form a fin structure extending over a substrate; Form a gate structure, the gate structure is formed over a part of the fin structure; Form a source / drain structure on the fin structure, wherein the source / drain structure is adjacent to the gate structure; Form an interlayer dielectric layer surrounding the source / drain structure, wherein the interlayer dielectric layer is doped with gallium and the gallium concentration of the interlayer dielectric layer gradually increases from bottom to top; Dope an outer portion of the source / drain structure to form a doped region, wherein the doped region includes gallium; Form a metal silicide layer on the doped region; And Form a source / drain contact structure on the metal silicide layer.

20. The method for forming the fin field effect transistor device structure according to claim 19 further includes: Form a metal layer on the doped region; Form a metal nitride layer on the metal layer; And Perform an annealing process on the metal nitride layer and the metal layer to form the metal silicide layer on the doped region.

21. The method for forming the fin field effect transistor device structure according to claim 19, wherein forming the source / drain structure on the fin structure includes: Remove a portion of the fin structure to form a notch adjacent to the gate structure; And Epitaxially grow a stress material in the notch and on the fin structure to form the source / drain structure.

22. The method for forming the fin field effect transistor device structure according to claim 19, wherein the source / drain structure is formed of silicon germanium, and the doped region is formed of silicon germanium doped with gallium or silicon germanium doped with gallium and boron.

23. The method for forming the fin field effect transistor device structure according to claim 19, wherein the operation of forming the doped region on the source / drain structure includes: Perform a first ion implantation process on the source / drain structure, and the first ion implantation process includes using a first impurity, and the first impurity includes gallium.

24. The method for forming the fin field effect transistor device structure according to claim 23, the above method further includes: After performing the first ion implantation process, perform a second ion implantation process on the source / drain structure, wherein the second ion implantation process includes using a second impurity, and the second impurity includes boron.

25. The method for forming the fin field effect transistor device structure according to claim 19, wherein the source / drain structure includes a first sidewall and a second sidewall on the substrate, and the metal silicide layer directly contacts the doped region of the source / drain structure on the first sidewall, and the metal silicide layer directly contacts a non-doped region of the source / drain structure on the second sidewall.

26. A method for forming a fin field effect transistor device structure, including: Form a fin structure extending on a substrate; Form a gate structure, and the gate structure is formed on the fin structure; Form a source / drain structure on the fin structure, wherein the source / drain structure is adjacent to the gate structure; And Form an interlayer dielectric layer surrounding the source / drain structure, wherein the interlayer dielectric layer is doped with gallium and the gallium concentration of the interlayer dielectric layer gradually increases from bottom to top.

27. The method for forming the fin field effect transistor device structure according to claim 26 further includes: Form a metal silicide layer on the source / drain structure; And Form a source / drain contact structure on the metal silicide layer.

28. The method for forming a fin field effect transistor device structure as claimed in claim 27, wherein forming the metal silicide layer further comprises: Form a metal layer on the source / drain structure; Form a metal nitride layer on the metal layer; And Perform an annealing process on the metal nitride layer and the metal layer to form the metal silicide layer.

29. The method for forming a fin field effect transistor device structure as claimed in claim 28, wherein the annealing process is carried out at a temperature ranging from 500 degrees to 700 degrees.

30. The method for forming a fin field effect transistor device structure as claimed in claim 28, wherein the annealing process is carried out for a time ranging from 5 seconds to 30 seconds.

31. The method for forming a fin field effect transistor device structure as claimed in claim 28, wherein the thickness of the metal layer is greater than the thickness of the metal nitride layer.

32. The method for forming a fin field effect transistor device structure as claimed in claim 26, further comprising doping an outer portion of the source / drain structure to form a doped region, wherein the doped region comprises gallium.

33. The method for forming a fin field effect transistor device structure as claimed in claim 32, wherein a single ion implantation process is used to dope the interlayer dielectric layer and the outer portion of the source / drain structure.

34. A method for forming a fin field effect transistor device structure, comprising: Form a fin structure extending on a substrate; Form a gate structure, and the gate structure is formed on the fin structure; Form a source / drain structure on the fin structure, wherein the source / drain structure is adjacent to the gate structure; Form an interlayer dielectric layer on the fin structure and adjacent to the gate structure; Perform a first ion implantation process on the source / drain structure using a first impurity, wherein the first impurity includes gallium and the doping concentration of the interlayer dielectric layer gradually increases from bottom to top; And After performing the first ion implantation process, perform a second ion implantation process on the source / drain structure using a second impurity, wherein the second impurity includes boron.

35. The method for forming a fin field effect transistor device structure as claimed in claim 34, wherein the energy of the first ion implantation process or the second ion implantation process is in the range of 2 keV to 6 keV.

36. The method for forming a fin field effect transistor device structure as claimed in claim 34, further comprising using the second ion implantation process to dope the interlayer dielectric layer with the second impurity.

37. The method for forming a fin field effect transistor device structure as claimed in claim 34, further comprising forming a metal silicide layer on the doped source / drain structure.

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