A method for manufacturing a spatial GaInP / GaAs / CuInGaSe triple junction cell epitaxial wafer

Abstract

The present invention discloses a method for manufacturing a spatial GaInP / GaAs / CuInGaSe triple junction cell epitaxial wafer, which comprises a double-sided polished n-type GaAs substrate, on which a GaAs ohmic contact layer, a GaInP subcell, a GaInP / AlGaAs tunneling junction layer, a GaAs subcell, a GaAs tunneling junction layer, and a GaAs buffer layer are deposited. A CuInGaSe subcell is sputtered on the lower surface of the GaAs substrate, and the band gap combination of the GaInP / GaAs / CuInGaSe triple junction cell is 1.9eV / 1.42eV / 1.1eV. The present invention further improves the utilization rate of the solar spectrum of the triple junction cell through a more optimized band gap combination, thereby improving the photoelectric conversion efficiency of the cell.

Description

Technical Field

[0001] The invention relates to the technical field of spacecraft batteries, and in particular to a method for manufacturing a space GaInP / GaAs / CuInGaSe triple-junction battery epitaxial wafer. Background Art

[0002] Conventional space GaInP / GaInAs / Ge triple-junction solar cells have the advantages of high photoelectric conversion efficiency, strong radiation resistance, good temperature characteristics, and lattice matching for easy large-scale production, and have become the main power source for spacecraft. The conventional lattice-matched three-junction GaInP / GaInAs / Ge structure has a low dislocation density during epitaxial growth due to lattice matching, and the photoelectric conversion efficiency can reach about 30%. However, due to the small band gap width of the Ge subcell in the GaInP (1.90eV) / GaInAs (1.42eV) / Ge (0.67eV) cell and the wide range of the solar spectrum covered, the current density generated is much greater than that of the GaInP and GaInAs subcells, resulting in spectrum loss, which limits the improvement of the photoelectric conversion efficiency of this structure cell. In order to further improve the photoelectric conversion efficiency of batteries, a variety of structures have been developed in recent years, such as mismatched GaInP / GaInAs / Ge structure, inverted GaAs structure and more junction cells. Although these structures can achieve the purpose of improving the photoelectric conversion efficiency of batteries, due to lattice mismatch, they all require the growth of thicker buffer layers, which greatly increases the cost of the battery. This is also the reason why they have not yet replaced conventional space GaInP / GaInAs / Ge lattice-matched batteries.

[0003] Theoretical studies have shown that triple-junction solar cells with a bandgap combination of 1.9eV / 1.42eV / 1.0eV can achieve better current matching, and the theoretical conversion efficiency under AM0 spectrum can reach 38%. GaInP / GaAs can achieve a bandgap combination of 1.9eV / 1.42eV and lattice matching. Currently, the 1eV material has Ga 0.7 In 0.3 As, GaInNAs and other materials. 0.7 In 0.3 As material has a serious lattice mismatch with GaInP (1.9eV), and GaInNAs has poor crystal quality and short minority carrier diffusion length, so they are not ideal materials. Finding available materials with a band gap of about 1.0eV is still one of the current hot topics. Summary of the invention

[0004] The purpose of the present invention is to provide a spatially available triple-junction solar cell composed of sub-cells with a bandgap width of about 1.0eV. The cell with a bandgap combination of 1.9eV / 1.42eV / 1.0eV is more compatible with the solar spectrum, can increase the open circuit voltage of the cell, and ultimately improve the photoelectric conversion efficiency of the cell.

[0005] To achieve the above-mentioned purpose, the present invention proposes a method for manufacturing a spatial GaInP / GaAs / CuInGaSe triple-junction cell epitaxial wafer, comprising a GaAs substrate, wherein the GaAs substrate is a double-sided polished n-type GaAs substrate single crystal wafer, a GaInP sub-cell, a GaAs sub-cell and a GaAs buffer layer are deposited on the upper surface of the GaAs substrate, a CuInGaSe sub-cell is sputtered on the lower surface of the GaAs substrate, the GaInP sub-cell and the GaAs sub-cell are connected by a first tunnel junction, and the GaAs sub-cell and the GaAs buffer layer are connected by a second tunnel junction.

[0006] Preferably, the CuInGaSe subcell is a pn structure CuInGaSe / CdS cell, which includes, from top to bottom, a TCO layer (Al-ZnO), an i-ZnO layer, a CdS buffer layer, a CuInGaSe layer, a Mo layer, and a MoNa layer.

[0007] Preferably, the GaInP sub-cell and the CuInGaSe sub-cell are respectively provided with electrodes.

[0008] Preferably, the band gap combination of the GaInP / GaAs / CuInGaSe triple junction cell is 1.9eV / 1.42eV / 1.1eV.

[0009] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0010] By utilizing a GaAs double-sided growth substrate and combining the characteristics of the CuInGaSe sub-cell, a GaInP sub-cell and a GaAs sub-cell are arranged on the upper surface of the GaAs substrate, and a CuInGaSe sub-cell with a band gap of about 1.1eV is arranged on the lower surface. Finally, a triple-junction solar cell with a band gap combination of about 1.9eV / 1.42eV / 1.1eV is obtained, achieving a better band gap combination for the triple-junction cell, making more effective segmentation and utilization of the solar spectrum, improving the utilization rate of the solar spectrum by the cell, and thus significantly improving the photoelectric conversion efficiency of the cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram of the structure of a triple-junction solar cell of the present invention;

[0012] The accompanying drawings are marked as follows:

[0013] 100: MoNa layer; 101: Mo layer;

[0014] 102: CuInGaSe layer; 103: CdS buffer layer;

[0015] 104: i-ZnO layer; 105: TCO layer;

[0016] 106: GaAs substrate; 107: GaAs buffer layer;

[0017] 108: GaAs tunneling junction layer; 109: AlGaAs / AlGaInAs (DBR) reflection layer;

[0018] 110: GaInP back field layer; 111: GaAs base layer;

[0019] 112: GaAs emitter layer; 113: AlInP window layer;

[0020] 114: GaInP / AlGaAs tunneling junction layer; 115: AlGaInP back field layer;

[0021] 116: GaInP base layer; 117: GaInP emitter layer;

[0022] 118: AlInP window layer; 119: GaAs ohmic contact layer. DETAILED DESCRIPTION

[0023] The present invention is further described in detail below with reference to examples and accompanying drawings.

[0024] like Figure 1 As shown, a method for manufacturing a spatial GaInP / GaAs / CuInGaSe triple-junction cell epitaxial wafer described in this embodiment includes a GaAs substrate 106, which is a double-sided polished n-type GaAs single crystal wafer, and an n-type GaAs ohmic contact layer 119, a GaInP sub-cell, a GaInP / AlGaAs tunnel junction layer 114, a GaAs sub-cell, a GaAs tunnel junction layer 108, and a GaAs buffer layer 107 are deposited on the upper surface of the GaAs substrate 106 from top to bottom.

[0025] The GaInP subcell includes, from top to bottom, an n-type AlInP window layer 118 , an n-type GaInP emitter layer 117 , a p-type GaInP base layer 116 , and a p-type AlGaInP back field layer 115 .

[0026] The GaAs subcell includes, from top to bottom, an n-type AlInP window layer 113 , an n-type GaAs emitter layer 112 , a p-type GaAs base layer 111 , a p-type GaInP back field layer 110 , and a p-type AlGaAs / AlGaInAs (DBR) reflective layer 109 .

[0027] A GuInGaSe subcell is sputtered on the lower surface of the GaAs substrate 106 , and a TCO layer 105 , an i-ZnO layer 104 , a CdS buffer layer 103 , a CuInGaSe layer 102 , a Mo layer 101 , and a MoNa layer 100 are sputtered in sequence from top to bottom.

[0028] The GaInP subcell is connected to the GaAs subcell via a GaInP / AlGaAs tunneling junction layer 114, and the GaAs subcell is connected to the GaAs buffer layer 107 via a GaAs tunneling junction layer 108. The band gap combination of the GaInP / GaAs / CuInGaSe triple junction solar cell is 1.9eV / 1.42eV / 1.1eV.

[0029] The following is a specific preparation process of the above-mentioned triple-junction solar cell in this embodiment, and the situation is as follows:

[0030] First, a 4-inch double-sided polished n-type GaAs single crystal wafer is used as a substrate, and then a GaAs buffer layer 107, a GaAs tunneling junction layer 108, a p-type AlGaAs / AlGaInAs (DBR) reflective layer 109, a p-type GaInP back field layer 110, a p-type GaAs base layer 111, an n-type GaAs emitter layer 112, an n-type AlInP window layer 113, a GaInP / AlGaAs tunneling junction layer 114, a p-type AlGaInP back field layer 115, p-type GaInP base layer 116, n-type GaInP emitter layer 117, n-type AlInP window layer 118, n-type GaAs ohmic contact layer 119, finally the GaAs substrate is turned 180°, and the TCO layer 105, i-ZnO layer 104, CdS buffer layer 103, CuInGaSe layer 102, Mo layer 101, and MoNa layer 100 are sputtered in sequence on the surface of the GaAs substrate using a magnetron sputtering (PVD) method to complete the preparation of the spatial GaInP / GaAs / CuInGaSe triple-junction battery epitaxial wafer.

[0031] In summary, the present invention utilizes an n-type GaAs double-sided polished substrate, and deposits GaInP sub-cells and GaAs sub-cells with a band gap combination of 1.9 eV / 1.42 eV on the upper surface of the GaAs by an MOCVD method, and sputters CuInGaSe sub-cells with a band gap width of 1.1 eV on the lower surface by a magnetron sputtering method, and finally obtains a spatial triple-junction solar cell with a band gap combination of 1.9 eV / 1.42 eV / 1.1 eV, achieving a better band gap combination under the solar spectrum, making the solar spectrum more effectively segmented and utilized, improving the utilization rate of the solar spectrum by the battery, and thus significantly improving the photoelectric conversion efficiency of the battery.

[0032] It should be noted that although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that several improvements and modifications may be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a spatial GaInP / GaAs / CuInGaSe triple junction cell epitaxial wafer, characterized in that: The GaAs substrate is a double-sided polished n-type GaAs single crystal wafer, on the upper surface of the GaAs substrate are deposited an n-type GaAs ohmic contact layer, a GaInP subcell, a GaInP / AlGaAs tunneling junction layer, a GaAs subcell, a GaAs tunneling junction layer, and a GaAs buffer layer in sequence from top to bottom, and a CuInGaSe subcell is sputtered on the lower surface of the GaAs substrate, wherein the GaInP subcell is composed of an n-type AlInP window layer, an n-type GaInP emitter layer, a p-type GaInP base layer, and a p-type AlGaInP back field layer, and the GaAs subcell is composed of an n-type AlInP window layer, an n-type GaAs emitter layer, a p-type GaAs base layer, a p-type GaInP back field layer, and a p-type AlGaAs / AlGaInAs reflective layer; The CuInGaSe subcell is sputtered with a TCO layer, an i-ZnO layer, a CdS buffer layer, a CuInGaSe layer, a Mo layer, and a MoNa layer from top to bottom; The band gap combination of the spatial GaInP / GaAs / CuInGaSe triple junction battery is 1.9eV / 1.42eV / 1.1eV.

2. A method for manufacturing a spatial GaInP / GaAs / CuInGaSe triple junction cell epitaxial wafer according to claim 1, characterized in that: The GaInP subcell and the GaAs subcell are deposited on the upper surface of the double-sided polished n-type GaAs substrate by metal organic compound chemical vapor deposition or molecular beam epitaxial growth technology, and the CuInGaSe subcell is sputtered on the lower surface of the GaAs substrate by magnetron sputtering.

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