Semiconductor structures and related operations and manufacturing methods

Abstract

The present invention discloses a semiconductor structure and related operation and manufacturing methods. The semiconductor structure includes: a substrate; a magnetic layer located above the substrate; a magnetic tunneling junction MTJ unit located above the magnetic layer; and a non-magnetic conductive layer located between the magnetic layer and the MTJ unit. The present invention also discloses a related method for manufacturing the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and related operations and manufacturing methods. Background Art

[0002] Previous efforts to implement electromagnetic devices that utilize magnetoresistance phenomena to achieve two information states (i.e., a single bit of information), such as magnetic tunneling junctions (MTJs), have been primarily directed to using current to generate magnetic fields to manipulate the device and / or directly applying torque to magnetic domains to manipulate the device. However, the required current is typically quite large, especially in cases where the MTJ is used in an MRAM configuration. Indeed, the requirement for relatively large currents makes the implementation of devices that rely on MTJs commercially unfeasible in applications that require low power operation. Summary of the invention

[0003] According to one embodiment of the present invention, a semiconductor structure for storing data includes: a first terminal, a second terminal and a third terminal, wherein the data is written into the semiconductor structure through the first terminal and the second terminal, and the data is read out from the semiconductor structure through the second terminal and the third terminal; a substrate; a magnetic layer located above the substrate, a first end of the magnetic layer is in physical contact with the first terminal, and a second end of the magnetic layer opposite to the first end is in physical contact with the second terminal; a magnetic tunneling junction (MTJ) unit located above the magnetic layer, wherein the first end and the second end of the magnetic layer protrude laterally from the sidewall of the MTJ unit, and the MTJ unit is located between the first end and the second end of the magnetic layer, and the MTJ unit includes a free layer, a barrier layer located above the free layer, and a reference layer located above the barrier layer; a nonmagnetic conductive layer located between the magnetic layer and the MTJ unit; and a top electrode located above the MTJ unit, the top electrode being in physical contact with the third terminal.

[0004] According to one embodiment of the present invention, a method for writing a magnetic tunneling junction (MTJ) unit includes: providing a magnetic layer adjacent to the MTJ unit, the magnetic layer having a first magnetization direction; providing a non-magnetic conductive layer between the MTJ unit and the magnetic layer; and flipping the magnetization direction of the magnetic layer from the first direction to a second direction opposite to the first direction.

[0005] According to one embodiment of the present invention, a method for manufacturing a semiconductor structure includes: providing a semiconductor substrate; depositing a magnetic layer above the semiconductor substrate; depositing a non-magnetic conductive layer above the magnetic layer; depositing a free layer above the non-magnetic conductive layer; depositing a barrier layer above the free layer; depositing a reference layer above the barrier layer; depositing a top electrode above the reference layer; patterning the non-magnetic conductive layer, the free layer, the reference layer and the top electrode; and removing a portion of the magnetic layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a cross-sectional view of a semiconductor structure according to various embodiments of the present disclosure;

[0008] Figure 2 is a top view of a semiconductor structure according to various embodiments of the present disclosure;

[0009] Figure 3 is a top view of a semiconductor structure according to various embodiments of the present disclosure;

[0010] Figures 4 to 7 Describes switching operations with respect to a free layer using a Bloch wall according to various embodiments of the present disclosure; and

[0011] Figures 8 to 12 are cross-sectional views of semiconductor devices fabricated at various stages according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The following disclosed embodiments provide many different embodiments or examples for implementing the different features of the present disclosure. The specific examples of components and arrangements will be described below to simplify the present disclosure embodiments. Of course, these are only examples and are not intended to be limiting. For example, in the following description, "forming a first component above or on a second component" may include embodiments in which the first component and the second component are directly contacted, and may also include embodiments in which additional components may be formed between the first component and the second component so that the first component and the second component may not be directly contacted. In addition, the present disclosure may repeat element symbols and / or letters in various examples. This repetition is intended to simplify and clarify and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for convenience of description, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to describe the relationship of one element or component to another element or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] Although the numerical ranges and parameters describing the broad scope of the embodiments of the present disclosure are approximate, the numerical values ​​described in the specific examples should be reported as accurately as possible. However, any numerical value inherently contains certain errors that are necessarily caused by the standard deviation found in the respective test measurements. In addition, as used herein, the term "about" generally means within 10%, 5%, 1% or 0.5% of a given value or range. Alternatively, as considered by ordinary technicians, the term "about" means within the acceptable standard error of the mean. Except in the operating or working examples, or unless otherwise clearly stated, all numerical ranges, quantities, values ​​and percentages (such as the numerical ranges, quantities, values ​​and percentages of the material quantities, durations, temperatures, operating conditions, quantity ratios, etc. of the embodiments disclosed herein) should be understood as being modified by the term "about" in all examples. Accordingly, unless otherwise indicated, the numerical parameters described in the embodiments of the present disclosure and the accompanying claims are approximate values ​​that can be varied as desired. At least, each numerical parameter should be interpreted at least in view of the number of significant figures reported and by applying general rounding techniques. Herein, ranges may be expressed as from one endpoint to another endpoint or between two endpoints.Unless otherwise stated, all ranges of the embodiments disclosed herein include the endpoints.

[0015] Figure 11 is a cross-sectional view of a semiconductor structure 100 according to various embodiments of the present disclosure. The semiconductor structure 100 includes a magnetoresistive random access memory (MRAM) device 117 formed on a semiconductor substrate 101. In the present embodiment, the semiconductor substrate 101 is a p-type semiconductor substrate (P-type substrate) or an n-type semiconductor substrate (N-type substrate) composed of silicon. Alternatively, the semiconductor substrate 101 includes: another element semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. In many examples, the semiconductor substrate 101 is a semiconductor on insulator (SOI). In other alternatives, the semiconductor substrate 101 may include a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer overlying another semiconductor layer of a different type, such as a silicon layer on a silicon germanium layer. In various examples, the semiconductor substrate 101 may include a doped region, such as a p-type well, an n-type well, or a combination thereof.

[0016] The semiconductor substrate 101 further includes heavily doped regions at least partially located in the semiconductor substrate 101, such as a source 103 and a drain 105. A gate 102 is positioned above the top surface of the semiconductor substrate 101 and between the source 103 and the drain 105 to form a transistor structure 121 together. Figure 1 A planar transistor having a doped region in the semiconductor substrate 101 is shown. However, the disclosed embodiments are not limited thereto. Any non-planar transistor, such as a fin FET structure, may have a raised doped region. The contact plug 107 may be formed in an interlayer dielectric (ILD) 111 adjacent to the top surface of the semiconductor substrate 101 and may be electrically coupled to the transistor structure 121. The ILD 111 above the semiconductor substrate 101 may be formed of a variety of dielectric materials and may be, for example, an oxide (e.g., germanium oxide), an oxynitride (e.g., gallium oxynitride), silicon dioxide (SiO2), a nitrogen-containing oxide (e.g., nitrogen-containing SiO2), a nitrogen-doped oxide (e.g., SiO2 implanted with N2), a silicon oxynitride (SiO2), or a dielectric layer (e.g., a dielectric layer containing silicon dioxide). x O y N z )etc.

[0017] In many examples, shallow trench isolation (STI) structures 109 are provided to define and electrically isolate adjacent transistors. The STI structures 109 are formed in a semiconductor substrate 101. The STI 109 may be formed by etching or otherwise forming a recess in the substrate 101 and then filling the recess with silicon dioxide and / or another dielectric material, which may be followed by chemical mechanical polishing (CMP) or other planarization steps.

[0018] In many examples, the MRAM device 117 is embedded in a metallization layer prepared in a back-end-of-line (BEOL) operation, while the transistor structure 121 is prepared in a front-end process operation. The MRAM device 117 may be embedded in any position of the metallization layer above the transistor structure 121, for example, between adjacent metal layers horizontally distributed parallel to the surface of the semiconductor substrate 101. Throughout the description, the term "metal layer" refers to a collection of metal lines in the same layer. For example, the embedded MRAM device 117 may be positioned between the 4th metal layer and the 5th metal layer. The number of metal layers provided herein is not limiting. Generally speaking, a person of ordinary skill in the art should understand that the MRAM is positioned between the Nth metal layer and the (N+1)th metal layer, where N is an integer greater than or equal to 1. Since the Nth metal layer may not be the first metal layer above the transistor structure 121, the Figure 1 The dots in the figure indicate that a portion of the metallization structure is omitted.

[0019] refer to Figure 1 , the MRAM device 117 includes a first terminal 118, a second terminal 120, and a third terminal 122. For many examples, the first terminal 118 is configured as a write terminal and is coupled to a first end (e.g., a left end) of the magnetic layer 104; the second terminal 120 is configured as a read / write terminal and is coupled to a second end (e.g., a right end) of the magnetic layer 104 opposite to the first side; and the third terminal 122 is configured as a read terminal and is coupled to the top electrode 114. The first terminal 118 and the second terminal 120 may be metal wires disposed in the Nth metal layer. The third terminal 122 may be a metal wire disposed in the (N+1)th metal layer. In some embodiments, the configurations of the first terminal 118 and the second terminal 120 may be interchangeable. For example, the first terminal 118 may be a read / write terminal and the second terminal 120 may be a write terminal. In many examples, the metal wires 118, 120, and 122 may be formed of W, and more preferably formed of copper (Cu) (which includes AlCu) (collectively referred to as Cu). Metal layers M1 to M N The IMD 113 is formed in an intermetallic dielectric (IMD) 113, which may include a low dielectric constant (k value) material or an ultra-low dielectric constant (ELK) material. Generally speaking, the low-k dielectric material has a dielectric constant of less than about 3.5, and the ELK dielectric material has a dielectric constant of less than about 2.8. The ELK material includes, for example, carbon-doped silicon dioxide and porous silicon dioxide.

[0020] The MRAM device 117 includes a top electrode 114, a magnetic tunneling junction (MTJ) unit 115, a spacer layer 106, and a magnetic layer 104. The top electrode 114 is electrically coupled to the MTJ unit 115 to convey a signal / bias. In numerous examples, the top electrode 114 may include Ta, Ta / TaN, Ta / TiN, TiN, TaN, TaN / TiN, etc. The top electrode 114 may have a thickness of about 50 nm to about 90 nm. According to the example provided previously, the top electrode is further connected to the (N+1)th metal layer through the (N+1)th metal line 122. On the other hand, the magnetic layer 104 is coupled to the Nth metal layer through the Nth metal lines 118 and 120. The magnetic layer 104 may include a ferromagnetic material, which may be composed of a metal or metal alloy such as Fe, Co, Ni, NiFe, CoFeB, FeB, CoFe, FePt, FePd, CoPt, CoPd, CoNi, TbFeCo, CrNi, etc.

[0021] In some embodiments, the sidewalls of the MTJ cell 115 may be protected by a protective or barrier layer 119. In many examples, the protective or barrier layer 119 may be formed around the edges and sides of the MTJ device 117. For example, the protective or barrier layer 119 may also encapsulate the spacer layer 106 and the magnetic layer 104. In many examples, the protective or barrier layer 119 further covers the top surface of the top electrode 114 and / or the magnetic layer 104. The protective or barrier layer 119 may include silicon nitride (SiN), SiO2, Al2O3, etc. In many examples, the protective or barrier layer 119 may have a thickness of about 15nm to about 35nm. The dielectric layer 116 is further disposed above the IMD 113 and surrounds the protective or barrier layer 119. In many examples, the dielectric layer 116 includes SiO2, TEOS / SRO, SiC, etc.

[0022] The spacer layer 106 is formed between the MTJ unit 115 and the magnetic layer 104 to prevent the MTJ unit 115 from directly adjoining the magnetic layer 104. Specifically, the upper side of the spacer layer 106 directly adjoins the MTJ unit 115 and the lower side of the spacer layer 106 directly adjoins the magnetic layer 104. The spacer layer 106 is composed of a non-magnetic conductive material including a metal such as Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, etc. It is obvious that the thickness of the spacer layer 106 should not be greater than the spin diffusion length of the non-magnetic conductive material. In many examples, the spacer layer 106 may have a thickness of about 0.5 nm to about 3 nm.

[0023] The MTJ unit 115 is deposited on the spacer layer 106 in the form of a plurality of material stacks. Figure 1, the MTJ cell 115 includes a reference layer 112, a barrier layer 110, and a free layer 108. The barrier layer 110 is composed of a non-magnetic material interposed between the reference layer 112 and the free layer 108. In some embodiments, the barrier layer 110 is an insulator, such as a tunneling barrier. In these embodiments, the barrier layer 110 may include a dielectric oxide, such as magnesium oxide (MgO), having a thickness of (but not limited to) about 0.6 nm to 2 nm. Alternatively, the barrier layer 110 may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), tantalum oxide (TaO), ruthenium oxide (RuO), or other suitable non-magnetic materials. The barrier layer 110 may enhance the tunneling magnetoresistance (TMR) and spin transfer efficiency of the MTJ cell 115.

[0024] The free layer 108 and the reference layer 112 may include ferromagnetic materials, which may be composed of metals or metal alloys such as Fe, Co, Ni, NiFe, CoFeB, FeB, CoFe, FePt, FePd, CoPt, CoPd, CoNi, TbFeCo, CrNi, etc. In some embodiments, the free layer 108 and / or the reference layer 112 may further include multiple layers. For example, Figure 1 , the reference layer 112 may include ferromagnetic layers 1122 and 1126 interleaved with a nonmagnetic layer 1124. In these embodiments, the ferromagnetic layers 1122 and 1126 may be antiferromagnetically aligned. Thus, the reference layer 112 may be a synthetic antiferromagnet (SAF). The magnetic moments (i.e., magnetization directions) of the reference layer 112 and the free layer 108 may be perpendicular to the plane (i.e., "out of plane", e.g., along the z-axis, the reference layer 112 ... Figure 1 ).

[0025] Particular components are described as magnetic, ferromagnetic, or ferrimagnetic. As used herein, the term "magnetic" in the disclosed embodiments may include ferromagnetic, ferrimagnetic, or similar structures. Therefore, as used herein, the term "magnetic" or "ferromagnetic" includes (but is not limited to) ferromagnets and ferrimagnets. In addition, as used herein, "out-of-plane" corresponds to a direction that is substantially perpendicular to one or more layers of the MTJ device 117. Conversely, "in-plane" is substantially within the plane of one or more layers of the MTJ device 117 or parallel to the plane.

[0026] It is desirable that the magnetic moment of the reference layer 112 is substantially fixed or pinned in place during operation of the semiconductor structure 100. In contrast, the magnetization direction of the free layer 108 rotates freely and represents a logic value written into the MTJ cell 115. In other words, the magnetic moment of the free layer 108 can be switched by controlling the magnetic layer 104, as will be described in detail below. The resistance of the MTJ cell 115 will change depending on the orientation of the magnetic moments of the free layer 108 and the reference layer 112. Therefore, the logic value can be read by determining the resistance of the MTJ cell 115. When the magnetizations of the free layer 108 and the reference layer 112 are parallel and the magnetic moments have the same polarity, the resistance of the MTJ cell 115 is low. Typically, this specifies a logic value of "0". When the magnetizations of the free layer 108 and the reference layer 112 are antiparallel (i.e., the magnetic moments have opposite polarities), the resistance of the MTJ cell 115 is high. Typically, this specifies a logic value of "1".

[0027] Spin-orbit transfer (SOT), also known as the spin Hall effect, is an existing technology for writing to a memory element through a spin-orbit interaction. Materials that exhibit the spin Hall effect typically include heavy metals or materials doped with heavy metals. Normally, a heavy metal layer resides adjacent to a free layer. The heavy metal layer is configured to apply a spin-orbit torque to the free layer due to a current passing through the heavy metal layer in a direction substantially perpendicular to the direction between the heavy metal layer and the free layer. However, when the magnetization directions of the reference layer and the free layer are perpendicular to the plane, the efficiency of the spin-orbit torque is not particularly ideal. Since the efficiency of the spin-orbit torque is proportional to the current passing through the heavy metal layer, power consumption increases when write time is the most prioritized factor.

[0028] The disclosed embodiments skip the existing SOT technology and provide an alternative technology to switch the magnetic moment of the free layer 108 by means of a Bloch wall disposed in the magnetic layer 104 below the MTJ unit 115. A wall is a boundary between domains where magnetization is in different directions. There are at least two types of walls in a thin magnetic film: one is a Bloch wall and the other is a Neel wall. The field of the Bloch wall affects the magnetization direction of the free layer 108. In addition, a portion of the current passing through the magnetic layer 104 may be spin-polarized by the field of the Bloch wall and thus pass through the free layer 108. As with spin torque transfer (STT), electrons may be repolarized based on the directional vector of the magnetic moment of the free layer 108. The repolarization of the electrons causes the free layer 108 to experience a torque associated with the change in the angular momentum of the electrons when they are repolarized. Therefore, this torque also contributes to the switching of the magnetization direction of the free layer 108. The current required to move the domain wall and thereby switch the free layer 108 is about 40 times smaller than the threshold current required by the existing SOT technology. Thus, an improved power solution is obtained without affecting write time.

[0029] The disclosed embodiments are described in the context of the current understanding of Bloch walls, STT, SOT, spin transfer phenomena, magnetic anisotropy, and other physical phenomena. Thus, one of ordinary skill will readily recognize that theoretical explanations of the behavior of the methods and systems are based on this current understanding of Bloch walls, STT, SOT, spin transfer phenomena, magnetic anisotropy, and other physical phenomena. However, the disclosed embodiments described herein do not rely on a particular physical explanation.

[0030] Figure 2 FIG. 1 is a top view of a semiconductor structure 100 according to various embodiments of the present disclosure. Specifically, the arrangement of the magnetic layer 104, the MTJ unit 115, the semiconductor substrate 101, the Nth metal lines 118 and 120, and the (N+1)th metal line 122 are depicted. Figure 2 omitted in Figure 1 104 is generally in the shape of an elongated rectangle. The shape of the MTJ unit 115 may be selected based on the desired magnetic polarization orientation. In an exemplary embodiment, it is desirable that the magnetic anisotropy has an "out-of-plane" directional component, so the shape of the MTJ unit 115 may be symmetrical, such as circular, when viewed from a top-down perspective. In this case, although there may still be a tendency for the magnetization to remain in the plane, it is unlikely to have a preferred directionality in the plane of the layer, so as long as there is an anisotropic tendency in the plane of the layer, the layer may define an easy plane even though there is no preferred magnetization axis in the plane.

[0031] It is apparent that the type of domain walls exhibited in the magnetic layer 104 is highly dependent on its size. Bloch walls preferably occur in films having a width of about 40 nm to about 200 nm and a thickness of about 10 nm to about 40 nm. In view of the above, the width W of the magnetic layer 104 may be in a range from about 40 nm to about 200 nm; and the thickness of the magnetic layer 104 may be in a range from about 10 nm to about 40 nm. In many examples, the magnetic layer 104 may be configured to have a length L that is approximately 3 to 5 times the width W, such that this shape anisotropy will result in a magnetization direction of the magnetic layer 104 along the major dimension of the magnetic layer 104 (in this example, the length L). In many examples, the diameter D of the MTJ unit 115 may be substantially 0.6 to 0.9 times the width W of the magnetic layer 104. In many examples, Figure 2 The magnetic layer 104 may be replaced by other contours that are substantially smooth and have no corners. For example, Figure 3 FIG. 1 is a top view of a semiconductor structure 100 according to various embodiments of the present disclosure. Figure 3 The magnetic layer 104 is elliptical in shape, which makes the injection of current more efficient because there is no obstruction from the four corners.

[0032] Figures 4 to 7The switching operation with respect to the free layer 108 by using the Bloch wall according to various embodiments of the present disclosure is depicted. Figure 4 , the MTJ cell 115 starts in a condition where a first type of logic value (e.g., logic value "0") is stored therein. In the described situation, the magnetizations of the free layer 108 and the reference layer 112 are parallel and the magnetic moments have the same polarity. The magnetic layer 104 has a magnetic polarization that is in a plane and depicted in the drawing as from a first terminal to a second end opposite the first terminal, such as (but not limited to) from the right terminal to the left terminal. When it is desired to rewrite the MTJ cell 115 with a second type of logic value (e.g., logic value "1"), all that is required is the opposite configuration of the magnetization of the free layer 108. To achieve switching of the free layer 108, current is injected from the second terminal to the first terminal, such as (but not limited to) from the left metal line 118 directly through the magnetic layer 104 to the right metal line 120.

[0033] When current is injected from the left metal wire 118 to the right metal wire 120, magnetic polarization from left to right is gradually formed and the Bloch wall 501 appears at the interface between the two opposite magnetic moments. After the Bloch wall 501 is generated at the left side of the magnetic layer 104, the Bloch wall 501 passes through the magnetic layer 104 and moves to the right side of the magnetic layer 104. Figure 5 It can be seen that the switching process of the magnetic polarization is shown in the region of the Bloch wall 501. The region of the Bloch wall 501 includes a -z direction magnetic field component for influencing the magnetic polarization of the free layer 108, that is, a magnetic field having a direction opposite to that of the free layer 108. As mentioned above, a portion of the current passing through the magnetic layer 104 can be spin-polarized by the magnetic field of the Bloch wall 501 and thus pass through the free layer 108 in a direction antiparallel to the reference layer 112 to apply a torque to the free layer 108 to promote the switching of the magnetization direction of the free layer 108. At the end of the write process, the magnetic moments in the magnetic layer 104 have the same polarity, that is, the +x direction, as shown in FIG. Figure 6 As shown in .

[0034] The magnetic moment in the free layer 108 is antiparallel to the reference layer 112 , indicating that a logic value of “1” has been stored. On the other hand, when the MTJ cell 115 needs to be rewritten with a logic value of “0”, current is injected from the right metal line 120 directly through the magnetic layer 104 to the left metal line 118 .

[0035] When current is injected from the right metal wire 120 to the left metal wire 118, magnetic polarization from right to left is gradually formed and the Bloch wall 701 appears at the interface between the two opposite magnetic moments. After the Bloch wall 701 is generated at the right side of the magnetic layer 104, the Bloch wall 701 passes through the magnetic layer 104 and moves to the left side of the magnetic layer 104. Figure 7It can be seen that the switching process of the magnetic polarization is shown in the region of the Bloch wall 701. The magnetization of the region of the Bloch wall 701 includes a +z-direction field component for influencing the magnetic polarization of the free layer 108, that is, a field having a direction opposite to that of the free layer 108. As mentioned above, a portion of the current passing through the magnetic layer 104 can be spin-polarized by the field of the Bloch wall 701 and thus pass through the free layer 108 in a direction parallel to the reference layer 112 to apply a torque to the free layer 108 to promote the switching of the magnetization direction of the free layer 108. At the end of the write process, the magnetic moments in the magnetic layer 104 have the same polarity, that is, the -x direction, as shown in FIG. Figure 4 As shown in .

[0036] Figures 8 to 12 is a cross-sectional view of a semiconductor device fabricated at various stages according to various embodiments of the present disclosure. Figure 8 In the embodiment, a semiconductor substrate 101 has a transistor structure 121 fabricated in a front-end process operation and covered by an ILD 111. A metallization layer is fabricated over the semiconductor substrate 101 in a back-end of line (BEOL) process operation. Layers associated with an MTJ device 117 are formed between an Nth metal layer and an (N+1)th metal layer, where N is an integer greater than or equal to 1. The layers associated with the MTJ device 117 include, from bottom to top, a magnetic layer 104, a spacer layer 106, a free layer 108, a barrier layer 110, a reference layer 112, and a top electrode 114, each of which is formed by any process known in the art, for example, by an atomic layer deposition (ALD) operation or a physical vapor deposition (PVD) operation.

[0037] exist Fig. 9 In the embodiment, a mask layer (not shown) is formed over the top electrode 114 to pattern the spacer layer 106, the free layer 108, the barrier layer 110, the reference layer 112, and the top electrode 114 into a cylindrical structure by reactive ion etching (RIE). In many examples, the patterned layers 106, 108, 110, 112, and 114 may have an elongated rectangular or trapezoidal shape when viewed in cross section.

[0038] exist Fig.10 In the embodiment of the present invention, a protective or barrier layer 119 may be conformally formed over the magnetic layer 104 and the patterned layers 106, 108, 110, 112, and 114. Fig.11 As shown in FIG. 1 , a portion of the protective or barrier layer 119 and the magnetic layer 104 are patterned to expose the underlying IMD 113. Fig.12In the embodiment, a dielectric layer 116 is deposited over a semiconductor substrate 101. In many examples, the thickness of the dielectric layer 116 can be configured to be greater than the height of the MTJ device 117. Therefore, the top surface of the dielectric layer 116 is higher than the top surface of the top electrode 114. Next, the dielectric layer 116 and the protective or barrier layer 119 are patterned to form a trench 901 to expose the top surface of the top electrode 114.

[0039] Finally, the conductive metal fills the trench 901 by, for example, a conventional dual damascene operation, and an excess portion of the conductive metal is removed from the surface using a chemical mechanical polishing (CMP) operation, an etching operation, or a combination thereof, such as Figure 1 As shown in .

[0040] Some embodiments of the present disclosure provide a semiconductor structure for storing data. The semiconductor structure includes: a first terminal, a second terminal, and a third terminal, wherein data is written into the semiconductor structure through the first terminal and the second terminal, and the data is read out from the semiconductor structure through the second terminal and the third terminal; a substrate; a magnetic layer located above the substrate, a first end of the magnetic layer being in physical contact with the first terminal, and a second end of the magnetic layer opposite to the first end being in physical contact with the second terminal; a magnetic tunneling junction (MTJ) unit located above the magnetic layer, wherein the first end and the second end of the magnetic layer protrude laterally from a sidewall of the MTJ unit, and the MTJ unit is located between the first end and the second end of the magnetic layer, and the MTJ unit includes a free layer, a barrier layer located above the free layer, and a reference layer located above the barrier layer; a nonmagnetic conductive layer located between the magnetic layer and the MTJ unit; and a top electrode located above the MTJ unit, the top electrode being in physical contact with the third terminal.

[0041] Some embodiments of the present disclosure provide a method for writing a magnetic tunnel junction (MTJ) cell. The method includes: providing a magnetic layer adjacent to the MTJ cell, the magnetic layer having a first magnetization direction; providing a nonmagnetic conductive layer between the MTJ cell and the magnetic layer; and flipping the magnetization direction of the magnetic layer from the first direction to a second direction opposite to the first direction.

[0042] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes: providing a semiconductor substrate; depositing a magnetic layer on the semiconductor substrate; depositing a non-magnetic conductive layer on the magnetic layer; depositing a free layer on the non-magnetic conductive layer; depositing a barrier layer on the free layer; depositing a reference layer on the barrier layer; depositing a top electrode on the reference layer; patterning the non-magnetic conductive layer, the free layer, the reference layer, and the top electrode; and removing a portion of the magnetic layer.

[0043] The foregoing has summarized the features of several embodiments so that a person of ordinary skill in the art may preferably understand aspects of the disclosed embodiments. A person of ordinary skill in the art should appreciate that he or she may readily use the disclosed embodiments as a basis for designing or modifying other programs and structures to implement the same purposes and / or achieve the same advantages of the embodiments introduced herein. A person of ordinary skill in the art should also recognize that these equivalent constructions should not depart from the spirit and scope of the disclosed embodiments, and that he or she may make various changes, substitutions, and modifications to the present disclosure without departing from the spirit and scope of the disclosed embodiments.

[0044] Explanation of symbols

[0045] 100 Semiconductor Structure

[0046] 101 Semiconductor Substrate

[0047] 102 Gate

[0048] 103 Source

[0049] 104 Magnetic layer

[0050] 105 Drain

[0051] 106 Spacer Layer

[0052] 107 Contact plug

[0053] 108 Free Layer

[0054] 109 Shallow Trench Isolation (STI) Structure

[0055] 110 Barrier layer

[0056] 111 Interlayer Dielectric (ILD)

[0057] 112 Reference Layer

[0058] 113 Intermetallic Dielectric (IMD)

[0059] 114 Top electrode

[0060] 115 Magnetic Tunnel Junction (MTJ) Cell

[0061] 116 Dielectric layer

[0062] 117 Magnetoresistive Random Access Memory (MRAM) Device

[0063] 118 First terminal

[0064] 119 Protective layer / barrier layer

[0065] 120 Second terminal

[0066] 121 Transistor Structure

[0067] 122 Third terminal

[0068] 501 Bloch Wall

[0069] 701 Bloch Wall

[0070] 901 Groove

[0071] 1122 Ferromagnetic layer

[0072] 1124 Non-magnetic layer

[0073] 1126 Ferromagnetic layer

[0074] D Diameter

[0075] L Length

[0076] W Thickness

Claims

1. A semiconductor structure for storing data, the semiconductor structure comprising: a first terminal, a second terminal, and a third terminal, wherein the data is written into the semiconductor structure through the first terminal and the second terminal, and the data is read out from the semiconductor structure through the second terminal and the third terminal; substrate; a magnetic layer located above the substrate, a first end of the magnetic layer being in physical contact with the first terminal, and a second end of the magnetic layer opposite to the first end being in physical contact with the second terminal; A magnetic tunneling junction MTJ unit, which is located above the magnetic layer, wherein the magnetic layer is continuously arranged when viewed from the top, and the entire area surrounded by the outline of the MTJ unit overlaps a portion within the range of the magnetic layer, and the MTJ unit is located between the first end and the second end of the magnetic layer, and the MTJ unit comprises: Free layer; a barrier layer located above the free layer; and a reference layer located above the barrier layer; a protection layer, which is located above the magnetic layer and aligned with the side of the magnetic layer and covers the outline of the MTJ unit; a non-magnetic conductive layer, located between the magnetic layer and the MTJ unit; and A top electrode is located above the MTJ unit, the top electrode being in physical contact with the third terminal. 2 . The semiconductor structure of claim 1 , wherein the magnetic layer is elongated and the MTJ unit is circular when viewed from the top. The semiconductor structure of claim 1 , wherein the magnetic layer comprises a ferromagnetic material.

4. The semiconductor structure of claim 1, wherein dimensions of the magnetic layer permit Bloch walls to form when current is passed through the magnetic layer along a major dimension of the magnetic layer. 5 . The semiconductor structure of claim 4 , wherein a thickness of the magnetic layer is about 10 nm to about 40 nm, and a width of the magnetic layer is about 40 nm to about 200 nm. The semiconductor structure of claim 2 , wherein the magnetic layer is elliptical in shape when viewed from the top.

7. The semiconductor structure of claim 1, wherein the magnetic anisotropy of the MTJ cell has an out-of-plane direction. 8 . The semiconductor structure according to claim 1 , wherein a thickness of the nonmagnetic conductive layer is not greater than a spin diffusion length of the nonmagnetic conductive layer.

9. A method for writing a magnetic tunnel junction (MTJ) unit, the method comprising: Providing a magnetic layer adjacent to the MTJ unit, the magnetic layer having a first direction; providing a nonmagnetic conductive layer between the MTJ unit and the magnetic layer; and flipping the magnetization direction of the magnetic layer from the first direction to a second direction opposite to the first direction to apply a torque to the free layer of the MTJ unit to help the magnetization direction of the free layer switch between upward from the magnetic layer and downward to the magnetic layer to write to the MTJ unit, The MTJ unit is located above the magnetic layer. When viewed from the top, the magnetic layer is continuously arranged. The entire area surrounded by the outline of the MTJ unit overlaps with a part within the range of the magnetic layer. A protective layer is located above the magnetic layer and aligned with the side of the magnetic layer, and covers the outline of the MTJ unit.

10. The method according to claim 9, wherein: The first direction and the second direction are in horizontal directions; and The magnetization direction of the free layer is freely rotated and represents a logic value stored in the MTJ cell, and the magnetization direction of the free layer of the MTJ cell is perpendicular to the first direction and the second direction.

11. The method of claim 9, wherein providing the magnetic layer comprises: The magnetic layer is provided with a thickness of about 10 nm to about 40 nm and a width of about 40 nm to about 200 nm.

12. The method of claim 9, wherein providing the nonmagnetic conductive layer comprises: The nonmagnetic conductive layer is provided with a thickness not greater than a spin diffusion length of the nonmagnetic conductive layer.

13. The method of claim 10, wherein the flipping the magnetization of the magnetic layer from the first direction to the second direction opposite to the first direction comprises: A Bloch wall is created at the first end of the magnetic layer.

14. The method of claim 13, wherein said generating the Bloch wall at the first end of the magnetic layer comprises: The magnetization direction of the magnetic layer is gradually changed from the first direction to the second direction at the first end.

15. The method according to claim 14, wherein the causing the magnetization direction of the magnetic layer to gradually change from the first direction to the second direction at the first end comprises: A current is injected from the first end of the magnetic layer through the magnetic layer to a second end.

16. The method of claim 14, wherein the Bloch wall comprises a magnetic moment perpendicular to the first direction and the second direction.

17. The method of claim 16, wherein said flipping the magnetization of the magnetic layer from the first direction to the second direction opposite to the first direction further comprises: The Bloch wall is moved across the magnetic layer from the first end to a second end of the magnetic layer opposite the first end, wherein the MTJ cell is located between the first end and the second end.

18. The method of claim 17, wherein said flipping the magnetization of the magnetic layer from the first direction to the second direction opposite to the first direction further comprises: The direction of the magnetization of the free layer of the MTJ cell is influenced by the magnetic moment of the Bloch wall that is perpendicular to the first direction and the second direction.

19. A method of manufacturing a semiconductor structure, comprising: providing a semiconductor substrate; depositing a magnetic layer over the semiconductor substrate; depositing a non-magnetic conductive layer over the magnetic layer; depositing a free layer over the nonmagnetic conductive layer; depositing a barrier layer over the free layer; depositing a reference layer over the barrier layer; depositing a top electrode over the free layer; patterning the nonmagnetic conductive layer, the free layer, the barrier layer, the reference layer, and the top electrode to form a patterned nonmagnetic conductive layer, a patterned free layer, a patterned barrier layer, a patterned reference layer, and a patterned top electrode; removing a portion of the magnetic layer; depositing a metallization layer over the semiconductor substrate, the metallization layer having a first terminal and a second terminal; depositing a protective layer to cover the patterned nonmagnetic conductive layer, the patterned free layer, the patterned barrier layer, the patterned reference layer, the patterned top electrode, and exposed portions of the magnetic layer; removing a portion of the protective layer to expose a portion of the patterned top electrode; and forming a third terminal in physical contact with the patterned top electrode; Wherein, the magnetic layer is continuously arranged when viewed from the top, and the entire area surrounded by the outline of the free layer overlaps a part of the range of the magnetic layer, and the protective layer is located above the magnetic layer and aligned with the side of the magnetic layer, and covers the side of the patterned free layer, the patterned barrier layer, and the patterned reference layer.

20. The method of claim 19, wherein depositing a magnetic layer over the semiconductor substrate comprises: The magnetic layer is deposited over the semiconductor substrate to allow the magnetic layer to be in physical contact with the first terminal and the second terminal.

21. A semiconductor structure for storing data, the semiconductor structure comprising: a first terminal, a second terminal, and a third terminal, wherein the data is written into the semiconductor structure through the first terminal and the second terminal, and the data is read out from the semiconductor structure through the second terminal and the third terminal; substrate; a magnetic layer located above the substrate, a first end of the magnetic layer coupled to the first terminal, and a second end of the magnetic layer opposite to the first end coupled to the second terminal; A magnetic tunneling junction MTJ unit, which is located above the magnetic layer, wherein the magnetic layer is continuously arranged when viewed from the top, and the entire area surrounded by the outline of the MTJ unit overlaps a portion within the range of the magnetic layer, and the MTJ unit is located between the first end and the second end of the magnetic layer, and the MTJ unit comprises: Free layer; a barrier layer located above the free layer; and a reference layer located above the barrier layer; a protection layer, which is located above the magnetic layer and aligned with the side of the magnetic layer and covers the outline of the MTJ unit; and A top electrode is located above the MTJ unit, wherein the top electrode is in direct contact with the third terminal.

22. The semiconductor structure of claim 21, wherein the magnetic layer is elongated and the MTJ cell is circular when viewed from the top.

23. The semiconductor structure of claim 21, wherein the magnetic layer comprises a ferromagnetic material.

24. The semiconductor structure of claim 21, wherein the dimensions of the magnetic layer permit Bloch walls to form when current is passed through the magnetic layer along a major dimension of the magnetic layer.

25. The semiconductor structure of claim 24, wherein a thickness of the magnetic layer is about 10 nm to about 40 nm, and a width of the magnetic layer is about 40 nm to about 200 nm.

26. The semiconductor structure of claim 22, wherein the magnetic layer is elliptical when viewed from the top.

27. The semiconductor structure of claim 21, wherein the magnetic anisotropy of the MTJ cell has an out-of-plane direction.

28. The semiconductor structure of claim 21, further comprising a nonmagnetic conductive layer between the magnetic layer and the MTJ unit, wherein a thickness of the nonmagnetic conductive layer is no greater than a spin diffusion length of the nonmagnetic conductive layer.

29. A method for writing a magnetic tunnel junction (MTJ) unit, the method comprising: Providing a magnetic layer adjacent to the MTJ unit, the magnetic layer having a first direction; and flipping the magnetization direction of the magnetic layer from the first direction to a second direction opposite to the first direction to apply a torque to the free layer of the MTJ unit to help the magnetization direction of the free layer switch between upward from the magnetic layer and downward to the magnetic layer to write to the MTJ unit, The MTJ unit is located above the magnetic layer. When viewed from the top, the magnetic layer is continuously arranged. The entire area surrounded by the outline of the MTJ unit overlaps with a part within the range of the magnetic layer. A protective layer is located above the magnetic layer and aligned with the side of the magnetic layer, and covers the outline of the MTJ unit.

30. The method of claim 29, wherein: The first direction and the second direction are in horizontal directions; and The magnetization direction of the free layer is freely rotated and represents a logic value stored in the MTJ cell, and the magnetization direction of the free layer of the MTJ cell is perpendicular to the first direction and the second direction.

31. The method of claim 29, wherein providing the magnetic layer comprises: The magnetic layer is provided with a thickness of about 10 nm to about 40 nm and a width of about 40 nm to about 200 nm.

32. The method of claim 29, further comprising: The nonmagnetic conductive layer is provided with a thickness no greater than a spin diffusion length of the nonmagnetic conductive layer.

33. The method of claim 30, wherein the flipping the magnetization of the magnetic layer from the first direction to the second direction opposite to the first direction comprises: A Bloch wall is created at the first end of the magnetic layer.

34. The method of claim 33, wherein said generating said Bloch wall at said first end of said magnetic layer comprises: The magnetization direction of the magnetic layer is gradually changed from the first direction to the second direction at the first end.

35. The method of claim 34, wherein the causing the magnetization direction of the magnetic layer to gradually change from the first direction to the second direction at the first end comprises: A current is injected from the first end of the magnetic layer through the magnetic layer to a second end.

36. The method of claim 34, wherein the Bloch wall comprises a magnetic moment perpendicular to the first direction and the second direction.

37. The method of claim 36, wherein said flipping the magnetization of the magnetic layer from the first direction to the second direction opposite to the first direction further comprises: The Bloch wall is moved across the magnetic layer from the first end to a second end of the magnetic layer opposite the first end, wherein the MTJ cell is located between the first end and the second end.

38. The method of claim 37, wherein said flipping the magnetization of the magnetic layer from the first direction to the second direction opposite to the first direction further comprises: The direction of the magnetization of the free layer of the MTJ cell is influenced by the magnetic moment of the Bloch wall that is perpendicular to the first direction and the second direction.

39. A method of manufacturing a semiconductor structure, comprising: providing a semiconductor substrate; depositing a magnetic layer over the semiconductor substrate; depositing a free layer over the magnetic layer; depositing a barrier layer over the free layer; depositing a reference layer over the barrier layer; depositing a top electrode over the free layer; patterning the free layer, the barrier layer, the reference layer, and the top electrode to form a patterned free layer, a patterned barrier layer, a patterned reference layer, and a patterned top electrode; removing a portion of the magnetic layer; depositing a metallization layer over the semiconductor substrate, the metallization layer having a first terminal and a second terminal; depositing a protective layer to cover the patterned free layer, the patterned barrier layer, the patterned reference layer, the patterned top electrode, and exposed portions of the magnetic layer; removing a portion of the protective layer to expose a portion of the patterned top electrode; and forming a third terminal in physical contact with the patterned top electrode; Wherein, the magnetic layer is continuously arranged when viewed from the top, and the entire area surrounded by the outline of the free layer overlaps a part within the range of the magnetic layer, and the protective layer is located above the magnetic layer and aligned with the side of the magnetic layer, and covers the side of the patterned free layer, the patterned barrier layer, and the patterned reference layer.

40. The method of claim 39, wherein depositing a magnetic layer over the semiconductor substrate comprises: The magnetic layer is deposited over the semiconductor substrate to allow the magnetic layer to be in physical contact with the first terminal and the second terminal.

41. A semiconductor structure comprising: Magnetic layer; A magnetic tunnel junction MTJ unit is located above the magnetic layer, wherein the magnetic layer is continuously arranged when viewed from the top, and the entire area surrounded by the outline of the MTJ unit overlaps a portion within the range of the magnetic layer, and the MTJ unit comprises: Free layer; a barrier layer located above the free layer; and a reference layer located above the barrier layer; and A protection layer is located above the magnetic layer and aligned with the side of the magnetic layer, and covers the outline of the MTJ unit.

42. The semiconductor structure of claim 41, wherein the magnetic layer is elongated and the MTJ cell is circular when viewed from the top.

43. The semiconductor structure of claim 41, wherein the magnetic layer comprises a ferromagnetic material.

44. The semiconductor structure of claim 41, wherein dimensions of the magnetic layer permit Bloch wall formation when current is passed through the magnetic layer along a major dimension of the magnetic layer.

45. The semiconductor structure of claim 44, wherein a thickness of the magnetic layer is about 10 nm to about 40 nm, and a width of the magnetic layer is about 40 nm to about 200 nm.

46. ​​The semiconductor structure of claim 42, wherein the magnetic layer is elliptical when viewed from the top.

47. The semiconductor structure of claim 41, wherein the magnetic anisotropy of the MTJ cell has an out-of-plane direction.

48. The semiconductor structure of claim 41, further comprising a nonmagnetic conductive layer between the magnetic layer and the MTJ unit, wherein a thickness of the nonmagnetic conductive layer is no greater than a spin diffusion length of the nonmagnetic conductive layer.

49. A semiconductor structure comprising: Magnetic layer; and A magnetic tunnel junction MTJ unit, which is located above the magnetic layer; The direction of the magnetic field of the magnetic layer is switched from a first direction to a second direction to apply a torque to the free layer of the MTJ unit to help the magnetization direction of the free layer switch between upward and downward from the magnetic layer to write to the MTJ unit, wherein the first direction is opposite to the second direction, wherein the magnetic layer is continuously arranged when viewed from the top, the entire area surrounded by the outline of the MTJ unit overlaps a part of the magnetic layer, and a protective layer is located above the magnetic layer and aligned with the side of the magnetic layer and covers the outline of the MTJ unit.

50. The semiconductor structure of claim 49, wherein: The first direction and the second direction are in horizontal directions; and The magnetization direction of the free layer is freely rotated and represents a logic value stored in the MTJ cell, and the magnetization direction of the free layer of the MTJ cell is perpendicular to the first direction and the second direction.

51. The semiconductor structure of claim 50, wherein the magnetic layer has a thickness of about 10 nm to about 40 nm and a width of about 40 nm to about 200 nm.

52. The semiconductor structure of claim 49, further comprising a nonmagnetic conductive layer between the magnetic layer and the MTJ unit, wherein a thickness of the nonmagnetic conductive layer is no greater than a spin diffusion length of the nonmagnetic conductive layer.

53. The semiconductor structure of claim 51, wherein when the direction of the magnetic field of the magnetic layer is switched from the first direction to the second direction, a Bloch wall is formed at a first end of the magnetic layer.

54. The semiconductor structure of claim 53, wherein the Bloch wall is formed at the first end of the magnetic layer when the magnetization direction of the magnetic layer gradually changes from the first direction to the second direction at the first end.

55. The semiconductor structure of claim 54, wherein when current is injected from the first end to the second end of the magnetic layer through the magnetic layer, the magnetization direction of the magnetic layer gradually changes from the first direction to the second direction at the first end.

56. The semiconductor structure of claim 54, wherein the Bloch wall comprises a magnetic moment perpendicular to the first direction and the second direction.

57. The semiconductor structure of claim 56, wherein the Bloch wall moves across the magnetic layer from the first end to a second end of the magnetic layer opposite the first end, wherein the MTJ unit is located between the first end and the second end.

58. The semiconductor structure of claim 57, wherein the direction of the magnetization of the free layer of the MTJ cell is affected by the magnetic moment of the Bloch wall that is perpendicular to the first direction and the second direction.

59. A semiconductor structure comprising: A magnetoresistive random access memory (MRAM) device embedded in a metallization layer coupled to a first terminal, a second terminal, and a third terminal, wherein the MRAM device comprises: Magnetic layer; A magnetic tunnel junction MTJ unit is located above the magnetic layer, wherein the magnetic layer is continuously arranged when viewed from the top, and the entire area surrounded by the outline of the MTJ unit overlaps a portion within the range of the magnetic layer, and the MTJ unit comprises: Free layer; a barrier layer located above the free layer; and a reference layer located above the barrier layer; and A protection layer is located above the magnetic layer and aligned with the side of the magnetic layer, and covers the outline of the MTJ unit.

60. The semiconductor structure of claim 59, wherein the first terminal is configured as a write terminal of the MRAM device, the second terminal is configured as a read or write terminal of the MRAM device, and the third terminal is configured as a read terminal of the MRAM device.

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