An analog-to-digital conversion circuit and method for capacitive fingerprint sampling

Abstract

This invention discloses an analog-to-digital converter (ADC) circuit and method for capacitive fingerprint sampling, belonging to the field of electronics. The ADC circuit and method for capacitive fingerprint sampling of this invention include a first voltage output unit, a sampling unit, a post-amplifier unit, a first comparator, and an arithmetic logic unit. The first voltage output unit outputs several reference voltages VREFA and VREFB. The sampling unit processes the sampled signal VIN to obtain data DATAA and a difference signal. The post-amplifier unit amplifies the difference signal to obtain an amplified signal. The first comparator compares the amplified signal with the reference voltages VREFA and VREFB respectively, and encodes the comparison results to obtain data DATAB. The arithmetic logic unit calculates DATAA and DATAB to obtain data DATA, and outputs data DATA. This allows the capacitive fingerprint sampling ADC circuit to achieve a smaller area and lower power consumption while meeting sampling rate requirements.

Description

Technical Field

[0001] This invention relates to the field of electronics, and more specifically, to an analog-to-digital conversion circuit and method for capacitive fingerprint sampling. Background Technology

[0002] An analog-to-digital converter (A / D converter), or simply ADC, is an electronic component that converts analog signals into digital signals. A typical A / D converter converts an input voltage signal into an output digital signal. Since digital signals themselves do not have inherent meaning and only represent a relative magnitude, any A / D converter needs a reference analog signal as a standard for conversion. A common reference standard is the maximum convertible signal size, while the output digital signal represents the magnitude of the input signal relative to the reference signal.

[0003] Currently, the mainstream ADC sampling technologies include flash ADC, pipeline ADC, SAR ADC, and Σ-Δ architectures, each with its own characteristics and advantages. Flash ADC achieves the fastest conversion rate among all ADC architectures and is widely used in high-speed fields such as hard disk read circuits and image processing circuit chips. Pipeline ADC has high sampling rate and high accuracy, but it has high power consumption and high price. The SAR ADC architecture is a complete, effective, and easy-to-understand architecture, very suitable for modern fine-line CMOS processes, and features low power consumption, small package size, and low latency. Σ-Δ ADC has a simple structure, can achieve high frequency resolution, and has a low cost; Σ-Δ ADCs have been widely used in industrial and audio applications.

[0004] For analog-to-digital converters (ADCs) used in capacitive fingerprint sampling, an 8-bit ADC is generally sufficient to meet fingerprint recognition requirements. However, when meeting requirements for area, speed, and power consumption, and maintaining the same sampling rate: a flash ADC architecture typically requires 256 comparators, resulting in a larger area; a pipeline ADC requires 8 stages and an 8-fold increase in clock frequency, resulting in a smaller area but higher power consumption; while a SAR ADC has the smallest area, its clock frequency is still eight times higher, increasing the power consumption of the digital circuit by eight times and increasing wiring complexity. Therefore, achieving a smaller area and lower power consumption for capacitive fingerprint sampling ADCs is a pressing issue that needs to be addressed in current technology. Summary of the Invention

[0005] 1. The problem to be solved

[0006] The purpose of this invention is to overcome the shortcomings of high power consumption and large area of ​​analog-to-digital conversion circuits in capacitive fingerprint sampling, and to provide an analog-to-digital conversion circuit and method for capacitive fingerprint sampling, so that the area of ​​the analog-to-digital conversion circuit can be smaller and the power consumption can be lower while meeting the sampling rate requirements.

[0007] 2. Technical Solution

[0008] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0009] The present invention discloses an analog-to-digital converter circuit for capacitive fingerprint sampling, comprising: a first voltage output unit for outputting a plurality of reference voltages VREFA and VREFB; a sampling unit electrically connected to the first voltage output unit, which processes the sampled signal VIN to obtain data DATAA and a difference signal; a post-amplifier unit electrically connected to both the sampling unit and the first voltage output unit, which amplifies the difference signal to obtain an amplified signal; a first comparator electrically connected to both the first voltage output unit and the post-amplifier unit, which compares the amplified signal with the reference voltages VREFA and VREFB, and encodes the comparison result to obtain data DATAB; and an arithmetic logic unit electrically connected to both the first comparator and the sampling unit, which calculates data DATA based on DATAA and DATAB and outputs the data DATA.

[0010] Preferably, the sampling unit includes an operational amplifier A, which enhances the sampled signal VIN into a signal VINA; a second comparator, which is electrically connected to the operational amplifier A and the first voltage output unit, and is used to compare the signal VINA with a reference voltage VREFA to obtain a quantized value, and encode the comparison result to obtain data DATAA; a second voltage output unit, which is electrically connected to the second comparator and the first voltage output unit, and is used to obtain a reference voltage VREFB-n based on the quantized value; and a subtraction unit, which is electrically connected to the operational amplifier A and the second voltage output unit, and is used to subtract the signal VINA from the reference voltage VREFB-n to obtain a difference signal.

[0011] Preferably, the post-amplifier unit includes capacitors C1 and C2 and operational amplifier B. Capacitors C1 and C2 are electrically connected to operational amplifier B. Furthermore, capacitor C1 is electrically connected to both the subtraction unit and capacitor C2, and operational amplifier B is electrically connected to both the first voltage output unit and the first comparator.

[0012] The present invention provides an analog-to-digital conversion method for capacitive fingerprint sampling, employing the aforementioned analog-to-digital conversion circuit for capacitive fingerprint sampling, comprising the following steps: S100, enhancing the sampling signal: the sampling unit enhances the sampling signal VIN into a signal VINA; S200, acquiring data DATAA: the sampling unit compares the signal VINA with a reference voltage VREFA to obtain a quantized value, and simultaneously encodes the comparison result to obtain data DATAA; then, based on the quantized value, the reference voltage VREFB-n is obtained, and the sampling unit subtracts the signal VINA from the reference voltage VREFB-n to obtain a difference signal; S300, acquiring data D ATAB: The sampling unit transmits the difference signal to the subsequent amplifier unit, which amplifies the difference signal to obtain the amplified signal. The subsequent amplifier unit then transmits the amplified signal to the first comparator, which compares the amplified signal with the reference voltage VREFA and the reference voltage VREFB respectively, and encodes the comparison result to obtain data DATAB. S400, Acquire data DATA: The sampling unit and the first comparator transmit data DATAA and DATAB to the arithmetic logic unit respectively. The arithmetic logic unit calculates data DATAA and DATAB to obtain data DATA, and outputs data DATA.

[0013] Preferably, the specific steps of S200 and acquiring data DATAA are as follows: the second comparator of the sampling unit compares the signal VINA with the reference voltage VREFA, and then encodes the comparison result to obtain data DATAA; at the same time, the reference voltages less than VINA in the comparison result are subjected to priority logic processing to obtain the largest reference voltage VREFA-n; the second comparator and the first voltage output unit transmit the reference voltage VREFA-n and the reference voltage VREFB to the second voltage output unit of the sampling unit, respectively, and the second voltage output unit selects the reference voltage VREFB-n according to the reference voltage VREFA-n; then the subtraction unit of the sampling unit subtracts the signal VINA from the reference voltage VREFB-n to obtain the difference signal.

[0014] Preferably, there are 16 reference voltages VREFA and VREFB, where the 16 reference voltages VREFA are VREFB-0 to VREFB-15; and the 16 reference voltages VREFB are VREFB-0 to VREFB-15.

[0015] Preferably, the specific steps of S200 and acquiring data DATAA are as follows: the second comparator of the sampling unit compares the signal VINA with the reference voltages VREFA-1 to VREFB-15 respectively to obtain 15 comparison results, and then encodes the 15 comparison results to obtain the high 4 bits of data DATAA<3:0>; at the same time, the reference voltages less than VINA in the comparison results are subjected to priority logic processing to obtain the largest reference voltage VREFA-n; the second comparator and the first voltage output unit transmit the reference voltage VREFA-n and the reference voltages VREFB-1 to VREFB-15 to the second voltage output unit of the sampling unit respectively, and the second voltage output unit selects the reference voltage VREFB-n according to the reference voltage VREFA-n; then the subtraction unit of the sampling unit subtracts the signal VINA from the reference voltage VREFB-n to obtain the difference signal.

[0016] Preferably, the specific steps of S300 and acquiring data DATAB are as follows: the subtraction unit transmits the difference signal to the subsequent amplifier unit, the subsequent amplifier unit amplifies the difference signal to obtain an amplified signal; the subsequent amplifier unit then transmits the amplified signal to the first comparator, the first comparator compares the amplified signal with the reference voltages VREFA-1~VREFB-15 and VREFB-0~VREFB-15 respectively, and encodes the comparison results to obtain the lower 5 bits of data DATAB<4:0>.

[0017] Preferably, in step S400, the specific steps for acquiring data DATA are as follows: the sampling unit and the first comparator transmit data DATAA<3:0> and DATAB<4:0> to the arithmetic logic unit, respectively; the arithmetic logic unit calculates data DATAA<3:0> and DATAB<4:0> to obtain data DATA<7:0>, and outputs data DATA<7:0>; wherein, the calculation formula is as follows:

[0018] DATA<7:0>=DATAB<4:0>*16+DATAA<3:0>-4.

[0019] Preferably, the ratio of the capacitance value C1 of the capacitor C1 in the subsequent amplifier unit to the capacitance value C2 of the capacitor C2 in the subsequent amplifier unit is: C1:C2 = 8.

[0020] 3. Beneficial effects

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] (1) The analog-to-digital converter circuit for capacitive fingerprint sampling of the present invention adopts a two-stage pipeline structure, thereby reducing the number of stages of the analog-to-digital converter circuit and keeping the clock frequency constant, thereby making the power consumption of the analog-to-digital converter circuit of the present invention relatively small.

[0023] (2) The analog-to-digital converter circuit for capacitive fingerprint sampling of the present invention adopts a two-stage pipeline structure. The front stage is a four-bit flash ADC structure and the back stage is a five-bit flash ADC structure, using a total of 48 comparators. This reduces the area of ​​the analog-to-digital converter circuit and the number of stages, thereby reducing the power consumption of the circuit and keeping the clock frequency constant.

[0024] (3) The analog-to-digital conversion method for capacitive fingerprint sampling of the present invention can reduce the power consumption of analog-to-digital conversion and keep the clock frequency unchanged at the same sampling rate. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an analog-to-digital conversion circuit for capacitive fingerprint sampling according to the present invention;

[0026] Figure 2 This is a flowchart of an analog-to-digital conversion method for capacitive fingerprint sampling according to the present invention.

[0027] Explanation of the labels in the diagram:

[0028] 100. First voltage output unit;

[0029] 200. Sampling unit; 210. Operational amplifier A; 220. Second comparator; 230. Second voltage output unit; 240. Subtraction unit;

[0030] 300. Power amplifier unit; 310. Capacitor C1; 320. Capacitor C2; 330. Operational amplifier B;

[0031] 400. First comparator;

[0032] 500. Arithmetic Logic Unit. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention; moreover, the various embodiments are not relatively independent and can be combined with each other as needed to achieve better results. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0034] To further understand the content of this invention, a detailed description of the invention will be provided in conjunction with the accompanying drawings and embodiments.

[0035] Example 1

[0036] Combination Figure 1 As shown, an analog-to-digital converter circuit for capacitive fingerprint sampling according to the present invention includes a first voltage output unit 100, a sampling unit 200, a post-amplifier unit 300, a first comparator 400, and an operational logic unit 500. The first voltage output unit 100 outputs several reference voltages VREFA and VREFB. The sampling unit 200 is electrically connected to the first voltage output unit 100 and processes the sampled signal VIN to obtain data DATAA and a difference signal. Specifically, the sampling unit 200 includes an operational amplifier A210, a second comparator 220, a second voltage output unit 230, and a subtraction unit 240. The operational amplifier A210 processes the sampled signal VIN to obtain data DATAA and a difference signal. The sample signal VIN is amplified into the signal VINA. The second comparator 220 is electrically connected to the operational amplifier A210 and the first voltage output unit 100. The operational amplifier A210 transmits the signal VINA to the second comparator 220. The first voltage output unit 100 transmits several reference voltages VREFA generated to the second comparator 220. The second comparator 220 compares the signal VINA with several reference voltages VREFA to obtain the quantized value. At the same time, the comparison result is encoded to obtain the data DATAA. It is worth noting that the second comparator 220 performs priority logic processing on the reference voltages in the comparison result that are less than VINA to obtain the largest reference voltage VREFA-n, which is the quantized value.

[0037] Furthermore, the second voltage output unit 230 is electrically connected to the second comparator 220 and the first voltage output unit 100, respectively. The second voltage output unit 230 obtains the reference voltage VREFB-n according to the quantized value. Specifically, the second comparator 220 transmits the reference voltage VREFA-n to the second voltage output unit 230, and the first voltage output unit 100 transmits several reference voltages VREFB to the second voltage output unit 230. The second comparator 220 selects the reference voltage VREFB-n according to the reference voltage VREFA-n. The operational amplifier A210 and the second voltage output unit 230 are electrically connected to the subtraction unit 240, respectively. The operational amplifier A210 transmits the signal VINA to the subtraction unit 240, and the second voltage output unit 230 transmits the reference voltage VREFB-n to the subtraction unit 240. The subtraction unit 240 subtracts the signal VINA from the reference voltage VREFB-n to obtain the difference signal.

[0038] Furthermore, the post-amplifier unit 300 is electrically connected to the sampling unit 200 and the first voltage output unit 100, respectively. The post-amplifier unit 300 amplifies the difference signal to obtain an amplified signal. Specifically, the post-amplifier unit 300 includes capacitor C1310, capacitor C2320, and operational amplifier B330. Capacitors C1310 and C2320 are electrically connected to operational amplifier B330. Capacitor C1310 is electrically connected to subtraction unit 240 and capacitor C2320, respectively. The input terminal of operational amplifier B330 is electrically connected to the first voltage output unit 100, and the output terminal of operational amplifier B330 is electrically connected to the first comparator 400. Capacitors C1310, C2320, and operational amplifier B330 form an amplification circuit that can amplify the difference signal to obtain an amplified signal. Operational amplifier B330 outputs the amplified signal to the first comparator 400.

[0039] The first comparator 400 is electrically connected to the operational amplifier B330 and the first voltage output unit 100 respectively. The first voltage output unit 100 transmits several reference voltages VREFA and VREFB to the first comparator 400. The first comparator 400 compares the amplified signal with the reference voltages VREFA and VREFB respectively, and encodes the comparison result to obtain data DATAB.

[0040] The first comparator 400 and the sampling unit 200 are electrically connected to the arithmetic logic unit 500. The first comparator 400 transmits data DATAB to the arithmetic logic unit 500, and the second comparator 220 of the sampling unit 200 transmits data DATAA to the arithmetic logic unit 500. The arithmetic logic unit 500 calculates data DATAA and DATAB to obtain data DATA and outputs data DATA. This invention provides a capacitive fingerprint sampling analog-to-digital converter circuit that employs a two-stage pipeline structure, thereby reducing the number of stages in the analog-to-digital converter circuit and maintaining a constant clock frequency, thus resulting in lower power consumption.

[0041] Combination Figure 2 As shown, the analog-to-digital conversion method for capacitive fingerprint sampling of the present invention employs the aforementioned analog-to-digital conversion circuit for capacitive fingerprint sampling, and includes the following steps:

[0042] S100, Enhanced Sampling Signal

[0043] The sampling unit 200 amplifies the sampled signal VIN into the signal VINA; specifically, the operational amplifier A210 of the sampling unit 200 amplifies the sampled signal VIN into the signal VINA.

[0044] S200, Obtain Data DATAA

[0045] The sampling unit 200 compares the signal VINA with the reference voltage VREFA to obtain a quantized value, and encodes the comparison result to obtain data DATAA. Then, based on the quantized value, it obtains the reference voltage VREFB-n. The sampling unit 200 then subtracts the signal VINA from the reference voltage VREFB-n to obtain a difference signal. Specifically, the second comparator 220 of the sampling unit 200 compares the signal VINA with the reference voltage VREFA, and then encodes the comparison result to obtain data DATAA. At the same time, the reference voltages less than VINA in the comparison result are processed by priority logic to obtain the largest reference voltage VREFA-n. The second comparator 220 and the first voltage output unit 100 transmit the reference voltage VREFA-n and the reference voltage VREFB to the second voltage output unit 230 of the sampling unit 200, respectively. The second voltage output unit 230 selects the reference voltage VREFB-n based on the reference voltage VREFA-n. Then, the subtraction unit 240 of the sampling unit 200 subtracts the signal VINA from the reference voltage VREFB-n to obtain a difference signal.

[0046] S300, Get Data DATAB

[0047] The sampling unit 200 transmits the difference signal to the subsequent amplifier unit 300, which amplifies the difference signal to obtain an amplified signal. The subsequent amplifier unit 300 then transmits the amplified signal to the first comparator 400, which compares the amplified signal with the reference voltage VREFA and the reference voltage VREFB respectively, and encodes the comparison result to obtain data DATAB. The first voltage output unit 100 transmits the reference voltage VREFA and the reference voltage VREFB to the first comparator 400. The capacitors C1310 and C2320 of the subsequent amplifier unit 300 and the operational amplifier B330 cooperate to form a C1 / C2 multiple amplification circuit, and then the amplified signal is transmitted to the first comparator 400 through the operational amplifier B330.

[0048] S400, Get Data

[0049] The sampling unit 200 and the first comparator 400 transmit data DATAA and DATAB to the arithmetic logic unit 500, respectively. The arithmetic logic unit 500 calculates data DATAA and DATAB to obtain data DATA and outputs data DATA.

[0050] The present invention provides an analog-to-digital conversion circuit and method for capacitive fingerprint sampling, which enables the ADC circuit to achieve a smaller area and lower power consumption while meeting the sampling rate requirements.

[0051] Example 2

[0052] This embodiment is basically the same as Embodiment 1, except that: in this embodiment, the analog-to-digital conversion circuit for capacitive fingerprint sampling has 16 reference voltages VREFA and VREFB. The 16 reference voltages VREFA are VREFA-0 to VREFA-15, i.e., VREFA-0, VREFA-1, VREFA-2, VREFA-3…VREFA-15 respectively; the 16 reference voltages VREFB are VREFB-0 to VREFB-15, i.e., VREFB-0, VREFB-1, VREFB-2, VREFB-3…VREFB-15 respectively. It is worth noting that the reference voltage range in this embodiment is 2 to 4V, meaning the first voltage output unit 100 generates 32 equally spaced reference voltages between 2V and 4V (including 2V, excluding 4V). Furthermore, in this embodiment, the ratio of the capacitance value C1 of capacitor C1310 to the capacitance value C2 of capacitor C2320 of the post-amplifier unit 300 is C1:C2 = 8, thus obtaining 8-bit ADC data, meaning that the ADC circuit can meet the requirements of fingerprint recognition. Furthermore, in this embodiment, the second comparator 220 is a 15-bit comparator, meaning it has 15 data bits, and the first comparator 400 is a 31-bit comparator, meaning it has 31 data bits.

[0053] The specific steps of the analog-to-digital conversion method for capacitive fingerprint sampling in this embodiment are as follows:

[0054] S100, Enhanced Sampling Signal

[0055] The sampling unit 200 amplifies the sampled signal VIN into the signal VINA; specifically, the operational amplifier A210 of the sampling unit 200 amplifies the sampled signal VIN into the signal VINA.

[0056] S200, Obtain Data DATAA

[0057] The second comparator 220 of the sampling unit 200 compares the signal VINA with the reference voltages VREFA-1 to VREFB-15 respectively to obtain 15 comparison results, and then encodes the 15 comparison results to obtain the high 4 bits of data DATAA<3:0>; at the same time, the reference voltages less than VINA in the comparison results are processed by priority logic to obtain the largest reference voltage VREFA-n; the second comparator 220 and the first voltage output unit 100 transmit the reference voltages VREFA-n and VREFB-1 to VREFB-15 to the second voltage output unit 230 of the sampling unit 200 respectively, and the second voltage output unit 230 selects the reference voltage VREFB-n according to the reference voltage VREFA-n; then the subtraction unit 240 of the sampling unit 200 subtracts the signal VINA from the reference voltage VREFB-n to obtain the difference signal.

[0058] S300, Obtain Data DATAB

[0059] The subtraction unit 240 transmits the difference signal to the subsequent amplifier unit 300, which amplifies the difference signal to obtain an amplified signal. The subsequent amplifier unit 300 then transmits the amplified signal to the first comparator 400, which compares the amplified signal with the reference voltages VREFA-1 to VREFB-15 and VREFB-0 to VREFB-15 respectively, and encodes the comparison results to obtain the lower 5 bits of data DATAB<4:0>.

[0060] It is worth noting that this embodiment adopts a two-stage pipeline structure. The front stage is a 4-bit flash ADC, which uses a second comparator 220 with 15 data bits and 15 reference voltages VREFA-1 to VREFB-15. The 15 comparison results are encoded to obtain the high 4 bits of data DATAA<3:0>. Furthermore, the front stage can be multiplexed with the rear stage. The rear stage is a 5-bit flash ADC, which uses a first comparator 400 with 31 data bits and 31 reference voltages, including VREFA-1 to VREFB-15 and VREFB-0 to VREFB-15. At the same time, the rear amplifier unit 300 requires a reference voltage VREFA-0, that is, a total of 32 reference voltages.

[0061] S400, Get Data

[0062] The sampling unit 200 and the first comparator 400 transmit data DATAA<3:0> and DATAB<4:0> to the arithmetic logic unit 500, respectively. The arithmetic logic unit 500 calculates data DATAA<3:0> and DATAB<4:0> to obtain data DATA<7:0>, and outputs data DATA<7:0>. The calculation formula is as follows:

[0063] DATA<7:0>=DATAB<4:0>*16+DATAA<3:0>-4, and the 8-bit ADC data can be obtained through this formula.

[0064] This embodiment of an analog-to-digital converter (ADC) circuit and method for capacitive fingerprint sampling employs a two-stage pipeline structure: a four-bit flash ADC in the front stage and a five-bit flash ADC in the back stage, using a total of 48 comparators. Compared to existing capacitive fingerprint sampling ADC circuits, this embodiment reduces the area and the number of stages, resulting in lower power consumption and a constant clock frequency. Furthermore, this embodiment features a simple and rationally designed ADC circuit structure.

[0065] The present invention has been described in detail above with reference to specific exemplary embodiments. However, it should be understood that various modifications and variations can be made without departing from the scope of the invention as defined by the appended claims. The detailed description and drawings should be considered illustrative only and not restrictive, and any such modifications and variations shall fall within the scope of the invention described herein. Furthermore, the background art is intended to illustrate the current state of development and significance of the technology and is not intended to limit the present invention or the scope of application of the present application.

Claims

1. An analog-to-digital converter circuit for capacitive fingerprint sampling, characterized in that: include A first voltage output unit (100) is used to output several reference voltages VREFA and several reference voltages VREFB; The sampling unit (200) is electrically connected to the first voltage output unit (100). The sampling unit (200) processes the sampled signal VIN to obtain data DATAA and a difference signal. The post-amplifier unit (300) is electrically connected to the sampling unit (200) and the first voltage output unit (100) respectively. The post-amplifier unit (300) amplifies the difference signal to obtain the amplified signal. The first comparator (400) is electrically connected to the first voltage output unit (100) and the subsequent amplifier unit (300). The first comparator (400) compares the amplified signal with the reference voltage VREFA and the reference voltage VREFB respectively, and encodes the comparison result to obtain data DATAB. An arithmetic logic unit (500) is electrically connected to a first comparator (400) and a sampling unit (200). The arithmetic logic unit (500) calculates data DATA from DATAA and DATAB and outputs the data DATA. It adopts a two-stage pipeline structure, with the front stage being a four-bit flash ADC structure and the rear stage being a five-bit flash ADC structure, using a total of 48 comparators; The analog-to-digital conversion circuit for capacitive fingerprint sampling is implemented through the following steps: S100, Enhanced Sampling Signal The sampling unit (200) amplifies the sampled signal VIN into the signal VINA; S200, Obtain Data DATAA The sampling unit (200) compares the signal VINA with the reference voltage VREFA to obtain a quantized value, and encodes the comparison result to obtain data DATAA. Then, the reference voltage VREFB-n is obtained based on the quantized value, and the sampling unit (200) subtracts the signal VINA from the reference voltage VREFB-n to obtain the difference signal. S300, Get Data DATAB The sampling unit (200) transmits the difference signal to the subsequent amplifier unit (300), which amplifies the difference signal to obtain an amplified signal. The subsequent amplifier unit (300) then transmits the amplified signal to the first comparator (400), which compares the amplified signal with the reference voltage VREFA and the reference voltage VREFB respectively, and encodes the comparison result to obtain data DATAB. S400, Get Data The sampling unit (200) and the first comparator (400) transmit data DATAA and DATAB to the arithmetic logic unit (500) respectively. The arithmetic logic unit (500) calculates data DATAA and DATAB to obtain data DATA and outputs data DATA. There are 16 reference voltages VREFA and VREFB, with the 16 reference voltages VREFA ranging from VREFB-0 to VREFB-15; and the 16 reference voltages VREFB ranging from VREFB-0 to VREFB-15. S200, The specific steps to obtain data DATAA are as follows: The second comparator (220) of the sampling unit (200) compares the signal VINA with the reference voltages VREFA-1 to VREFB-15 respectively to obtain 15 comparison results, and then encodes the 15 comparison results to obtain the high 4 bits of data DATAA<3:0>; at the same time, the reference voltages less than VINA in the comparison results are processed by priority logic to obtain the largest reference voltage VREFA-n; the second comparator (220) and the first voltage output unit (100) transmit the reference voltages VREFA-n and VREFB-1 to VREFB-15 to the second voltage output unit (230) of the sampling unit (200) respectively, and the second voltage output unit (230) selects the reference voltage VREFB-n according to the reference voltage VREFA-n; then the subtraction unit (240) of the sampling unit (200) subtracts the signal VINA from the reference voltage VREFB-n to obtain the difference signal; S300, the specific steps for obtaining data DATAB are as follows: The subtraction unit (240) transmits the difference signal to the subsequent amplifier unit (300), which amplifies the difference signal to obtain an amplified signal. The subsequent amplifier unit (300) then transmits the amplified signal to the first comparator (400), which compares the amplified signal with the reference voltages VREFA-1 to VREFB-15 and VREFB-0 to VREFB-15 respectively, and encodes the comparison results to obtain the lower 5 bits of data DATAB<4:0>. S400, the specific steps to obtain data DATA are as follows: The sampling unit (200) and the first comparator (400) transmit data DATAA<3:0> and DATAB<4:0> to the arithmetic logic unit (500) respectively. The arithmetic logic unit (500) calculates data DATAA<3:0> and DATAB<4:0> to obtain data DATA<7:0>, and outputs data DATA<7:0>. The calculation formula is as follows: DATA<7:0>=DATAB<4:0>*16+DATAA<3:0>-4.

2. The analog-to-digital conversion circuit for capacitive fingerprint sampling according to claim 1, characterized in that: The sampling unit (200) includes Operational amplifier A (210) is used to amplify the sampled signal VIN into signal VINA; The second comparator (220) is electrically connected to the operational amplifier A (210) and the first voltage output unit (100) respectively. The second comparator (220) is used to compare the signal VINA with the reference voltage VREFA to obtain a quantized value, and encode the comparison result to obtain data DATAA. The second voltage output unit (230) is electrically connected to the second comparator (220) and the first voltage output unit (100) respectively. The second voltage output unit (230) obtains the reference voltage VREFB-n according to the quantized value. The subtraction unit (240) is electrically connected to the operational amplifier A (210) and the second voltage output unit (230). The subtraction unit (240) subtracts the signal VINA from the reference voltage VREFB-n to obtain the difference signal.

3. The analog-to-digital conversion circuit for capacitive fingerprint sampling according to claim 1, characterized in that: The post-amplifier unit (300) includes capacitor C1 (310), capacitor C2 (320) and operational amplifier B (330). Capacitors C1 (310) and C2 (320) are electrically connected to operational amplifier B (330), respectively. Capacitor C1 (310) is electrically connected to subtraction unit (240) and capacitor C2 (320), respectively. Operational amplifier B (330) is electrically connected to first voltage output unit (100) and first comparator (400), respectively.

4. The analog-to-digital conversion circuit for capacitive fingerprint sampling according to claim 1, characterized in that: S200, The specific steps to obtain data DATAA are as follows: The second comparator (220) of the sampling unit (200) compares the signal VINA with the reference voltage VREFA, and then encodes the comparison result to obtain data DATAA; at the same time, the reference voltages less than VINA in the comparison result are processed by priority logic to obtain the largest reference voltage VREFA-n; the second comparator (220) and the first voltage output unit (100) transmit the reference voltage VREFA-n and the reference voltage VREFB to the second voltage output unit (230) of the sampling unit (200) respectively, and the second voltage output unit (230) selects the reference voltage VREFB-n according to the reference voltage VREFA-n; then the subtraction unit (240) of the sampling unit (200) subtracts the signal VINA from the reference voltage VREFB-n to obtain the difference signal.

5. The analog-to-digital conversion circuit for capacitive fingerprint sampling according to claim 1, characterized in that: The ratio of the capacitance value C1 of capacitor C1 (310) of the power amplifier unit (300) to the capacitance value C2 of capacitor C2 (320) of the power amplifier unit (300) is: C1:C2 = 8.

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