Semiconductor structure

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source / drain structure, a contact structure, an adhesive layer, and a barrier layer. The gate structure is located on a fin structure. The gate spacer is located on the fin structure and on the sidewall surface of the gate structure. The source / drain structure is located in the fin structure and adjacent to the gate spacer. The contact structure is located on the source / drain structure. The adhesive layer covers the lower surface and the sidewall surface of the contact structure. The barrier layer surrounds the sidewall surface of the contact structure. The lower surface of the adhesive layer is exposed to the barrier layer.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to semiconductor structures, and more particularly to fluorine-doped barrier layers. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of the processes and methods of forming integrated circuits. To achieve these advances, similar developments in integrated circuit processes and methods of forming integrated circuits have been required. In the evolution of integrated circuits, functional density (the number of interconnect devices per unit chip area) has generally increased as geometry size (the smallest component that can be produced by the manufacturing process) has decreased.

[0003] In addition to breakthroughs in materials and fabrication methods, scaling down planar devices such as MOSFETs has proven challenging. Circuit designers have sought new structures to improve performance to overcome these challenges, resulting in the development of three-dimensional designs such as finFETs. FinFETs have thin fins or fin-like structures that extend upward from a substrate. The channel of a finFET is formed in this vertical fin. A gate is located on the fin to control the channel from multiple sides. Advantages of finFETs may include reduced short channel effects, lower leakage current, and increased current.

[0004] However, as the size of structures continues to shrink, the manufacturing process becomes increasingly difficult, making it challenging to form reliable semiconductor structures containing fin field-effect transistors. Summary of the invention

[0005] A semiconductor structure provided by one embodiment of the present invention includes: a gate structure located on a fin structure; a gate spacer located on the fin structure and on the side wall surface of the gate structure; a source / drain structure located in the fin structure and adjacent to the gate spacer; a contact structure located on the source / drain structure; an adhesion layer covering the lower surface and side wall surface of the contact structure; and a barrier layer surrounding the side wall surface of the contact structure, wherein the lower surface of the adhesion layer is exposed to the barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a three-dimensional diagram of a simplified fin field effect transistor in some embodiments.

[0007] Figures 2A to 2F is a cross-sectional view of various stages of a process for forming a semiconductor device structure in some embodiments, along Figure 1 Section A-A'.

[0008] Figure 3is a cross-sectional view of a semiconductor device structure in some embodiments.

[0009] Figure 4 is a cross-sectional view of a semiconductor device structure in some embodiments.

[0010] Figure 5 is a cross-sectional view of a semiconductor device structure in some embodiments.

[0011] Figures 6A to 6C are cross-sectional views of various stages of a process for forming a semiconductor device structure in some embodiments.

[0012] Figure 7 is a cross-sectional view of a semiconductor device structure in some embodiments.

[0013] Reference numerals list

[0014] A' section

[0015] D1, D2, D3 distance

[0016] 200 substrates

[0017] 204 Fin Structure

[0018] 205, 208, 320A, 320B, 320C upper surface

[0019] 206 Quarantine Zone

[0020] 210, 243A, 243B, 243C, 246A, 246B, 246C, 246D, 321A, 321B, 321C, 331A, 331B, 331C, 343A, 343B, 343C, 346A, 346B, 346C, 356A, 356B, 356C lower surface

[0021] 215A, 215B, 412 Dummy gate structure

[0022] 218A, 218B Gate spacer

[0023] 220, 220A, 220B, 220C Source / Drain Structure

[0024] 221 Contact Etch Stop Layer

[0025] 222, 226 Dielectric layer

[0026] 230 Mask layer

[0027] 232A, 232B, 232C, 239A, 239B, 332A, 332B, 332C, 339A, 339B opening

[0028] 233A, 233B, 233C, 237A, 237B, 248A, 248B, 248C, 248D, 255A, 255B side wall surface

[0029] 234, 234A, 234C, 235B, 236A, 236B, 236C, 334A, 334C, 335B Barrier layer

[0030] 238 Fluorine

[0031] 240A, 240B, 240C Source / drain silicide layer

[0032] 242A, 242B, 242C, 242D, 342A, 342B, 342C, 342D Adhesive layer

[0033] 244A, 244B, 244C, 244D, 344A, 344B, 344C, 344D Contact Structure

[0034] 252, 252A, 252B gate dielectric layer

[0035] 254, 254A, 254B Gate layer

[0036] 256A, 256B Metal Gate Structure

[0037] 336A, 336B, 336C Barrier layer structure

[0038] 337A, 337B side wall

[0039] 360, 361, 460 Etching Process

[0040] 362 Pre-cleaning process

[0041] 500, 500A, 500B FinFET

[0042] 600A, 600B, 600C, 600D, 600E, 600F Semiconductor device structure DETAILED DESCRIPTION

[0043] The following disclosure provides many different embodiments or examples to implement different structures of the present invention. The following specific components and arrangement embodiments are used to simplify the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes direct contact between the two, or there are other additional components between the two instead of direct contact. In addition, multiple embodiments of the present invention may use repeated numbers and / or symbols to simplify and clarify the description, but these repetitions do not mean that the same corresponding relationship between the components with the same number in multiple embodiments.

[0044] In addition, spatially relative terms such as "below," "beneath," "below," "above," "above," or similar terms may be used to simplify the description of the relative relationship of one element to another element in a diagram. Spatially relative terms may be extended to elements used in other orientations, not limited to the orientation shown in the diagram. Elements may also be rotated 90 degrees or other angles, so directional terms are only used to describe the orientation shown in the diagram.

[0045] Some embodiments of the present invention are described below. Additional steps may be performed before, during, or after the stages described in these embodiments. Other embodiments may replace or omit some of the stages described below. Additional structures may be added to the semiconductor device structure. Other embodiments may replace or omit some of the structures described below. Although the steps in the embodiments are described in a specific order, these steps may be performed in other logical orders.

[0046] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more lithography processes, such as a double patterning or multiple patterning process. Generally, the double patterning or multiple patterning process combines lithography with a self-alignment process, and the pattern spacing produced may be smaller than the pattern spacing formed using a single direct lithography process. For example, some embodiments form a sacrificial layer on a substrate and pattern the sacrificial layer using a lithography process. A self-alignment process may be used to form spacers along the patterned sacrificial layer. The sacrificial layer is then removed, and the retained spacers can then be used to pattern the fins.

[0047] Figure 1 is a three-dimensional diagram of a simplified FinFET 500 in some embodiments. Figure 1 Other aspects not shown or described can be known from the subsequent figures and descriptions. The fin field effect transistor 500 includes a fin structure 204 and a substrate 200. The substrate 200 includes an isolation region 206, and the fin structure 204 protrudes above the upper surface 208 of the isolation region 206. In addition, the fin structure 204 can be formed between adjacent isolation regions 206. The gate structure 256 includes a gate dielectric layer 252 and a gate layer 254, and is located on the fin structure 204. The gate dielectric layer 252 is along the sidewall of the fin structure 204 and is located on the fin structure 204, and the gate layer 254 is located on the gate dielectric layer 252. The source / drain structure 220 is located in the two side regions of the fin structure 204 relative to the gate dielectric layer 252 and the gate layer 254. Figure 1 Reference cross section AA′ is also shown for subsequent figures. Cross section AA′ may be along a plane of a channel in the fin structure 204 between opposing source / drain structures 220 .

[0048] For example, the source / drain structure 220 may be shared between multiple transistors. In some examples, the source / drain structure 220 may be connected or coupled to other fin field effect transistors so that multiple fin field effect transistors are implemented as one functional transistor. For example, if adjacent (as opposed to opposite) source / drain regions are electrically connected, such as merged via epitaxial growth, then one functional transistor may be implemented. Other configurations in other examples may implement other numbers of functional transistors.

[0049] Figures 2A to 2F 6 is a cross-sectional view of various stages of a process for forming a semiconductor device structure 600A in some embodiments, along the Figure 1 It should be noted that the cross-sectional view of the semiconductor structure is along the longitudinal direction (eg, the channel length direction of the fin field effect transistor) of the fin structure (eg, the fin structure 204) of the semiconductor device structure.

[0050] In some embodiments, a gate replacement process (ie, a gate-last process) is used to fabricate the semiconductor device structure 600A, such as a FinFET (eg, FinFETs 500A and 500B).

[0051] like Figure 2A As shown, a substrate 200 containing a fin structure 204 is received. In some embodiments, the substrate 200 may be a semiconductor substrate such as a bulk semiconductor substrate, a semiconductor-on-insulator substrate, or the like, which may be doped (p-type dopant or n-type dopant) or undoped. The substrate 200 may be a wafer such as a silicon wafer. Generally speaking, a semiconductor-on-insulator substrate includes a semiconductor layer formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, generally a silicon substrate or a glass substrate. Other substrates such as multilayer or compositionally graded substrates may also be used. In some embodiments, the semiconductor material of the substrate 200 may include silicon, germanium, a semiconductor compound (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or a combination thereof.

[0052] In some embodiments, the fin structure 204 is formed by performing a patterning process on the substrate 200. The grooves (eg, Figure 1 The isolation region 206 in the example may surround the fin structure 204. Figure 1 An isolation region 206 (STI) in the trench may be formed on the lower surface 210 of the trench. The isolation structure surrounds the lower portion of the fin structure 204, and the upper portion of the fin structure 204 protrudes from the upper surface 208 of each isolation structure.

[0053] After forming the isolation region, a dummy gate structure (not shown) is formed on the upper surface 205 of the fin structure 204. In addition, a hard mask layer is formed on the dummy gate structure 412. In some embodiments, the dummy gate structure covers the respective channel regions of the final fin field effect transistors (such as fin field effect transistors 500A and 500B) on the fin structure 204. In some embodiments, the dummy gate structure covers the upper surface 205 and sidewalls of the fin structure 204 and extends to the isolation region outside the fin structure 204 and the substrate 200. In some embodiments, each dummy gate structure includes a gate dielectric layer (not shown) and a gate (not shown) formed on the gate dielectric layer.

[0054] like Figure 2A In some embodiments shown, gate spacers 218A and 218B are formed on the sidewalls of both sides of the dummy gate structure and are located on the fin structure 204. Gate spacers 218A and 218B may include a single-layer structure or a multi-layer structure. Gate spacers 218A and 218B may be composed of a material with a low dielectric constant (e.g., less than 5), such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, another suitable material, or a combination thereof. In some embodiments, the gate spacers 218A and 218B are formed by a deposition process and a subsequent etching process. The deposition process may include a chemical vapor deposition process, a physical vapor deposition process, a spin coating process, another feasible process, or a combination thereof. The etching process may include a dry etching process.

[0055] like Figure 2A In some embodiments shown, after forming the gate spacers 218A and 218B, source / drain structures 220A, 220B, and 220C are formed in the portions of the fin structure 204 not covered by the dummy gate structure and the gate spacers 218A and 218B. The source / drain structures 220A, 220B, and 220C may be formed in the fin structure 204 and adjacent to the gate spacers 218A and 218B.

[0056] In some embodiments, the source / drain structures 220A, 220B, and 220C may include strained materials or stressed materials to apply stress to the channel region. For example, the source / drain structures 220A, 220B, and 220C are composed of germanium, silicon germanium, indium arsenide, indium gallium arsenide, indium antimonide, gallium arsenide, gallium antimonide, indium aluminum phosphide, indium phosphide, or the like. In some embodiments, the lattice constant of the source / drain structures 220A, 220B, and 220C is different from the lattice constant of the fin structure 204. In some embodiments, the source / drain structures 220A, 220B, and 220C have a diamond shape.

[0057] The source / drain structures 220A, 220B, and 220C may be formed by an etching process followed by a filling process. An etching process is performed to form a recess (not shown) adjacent to the gate spacers 218A and 218B in the fin structure 204. In some embodiments, the etching process is a dry etching process. In some embodiments, a filling process (not shown) is performed to fill one or more strained or stressed semiconductor materials to form the source / drain structures 220A, 220B, and 220C. In some embodiments, the filling process includes an epitaxial process such as a selective epitaxial growth process, a chemical vapor deposition technique (such as vapor phase epitaxy and / or super-vapor chemical vapor deposition), a molecular beam epitaxy, or another suitable epitaxial process.

[0058] like Figure 2A In some embodiments shown, after forming the source / drain structures 220A, 220B, and 220C, a contact etch stop layer 221 is conformally deposited on the source / drain structures 220A, 220B, and 220C and the gate spacers 218A and 218B by a thin film deposition process. The contact etch stop layer 221 can be used as an etch stop layer for a subsequent etching process (configured to form source / drain contact holes (not shown)). In some embodiments, the contact etch stop layer 221 can be a single layer or multiple layers. The composition of the contact etch stop layer 221 can be silicon carbide, silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, silicon oxide, or another feasible material. In some embodiments, the contact etch stop layer 221 has a double-layer structure of different materials, such as a silicon oxide layer formed on a silicon carbide layer. In some embodiments, the contact etch stop layer 221 is formed by a plasma enhanced chemical vapor deposition process, a low pressure chemical vapor deposition process, an atomic layer deposition process, or another feasible process.

[0059] like Figure 2A In some embodiments shown, after forming the contact etch stop layer 221, a dielectric layer 222 (e.g., an interlayer dielectric layer) is formed on the fin structure 204, the dummy gate structure, the gate spacers 218A and 218B, and the source / drain structures 220A, 220B, and 220C. The dielectric layer 222 may be formed on the contact etch stop layer 221 and fill the gap between the dummy gate structures 215A and 215B. In some embodiments, the dielectric layer 222 surrounds the dummy gate structures 215A and 215B.

[0060] In some embodiments, a deposition process is performed to form a dielectric layer 222 on the contact etch stop layer 221. A planarization process is then performed to make the upper surfaces of the contact etch stop layer 221, the dielectric layer 222, the gate spacers 218A and 218B, and the dummy gate structure flush.

[0061] In some embodiments, the dielectric layer 222 is composed of a dielectric material such as silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, carbon-doped silicate glass, silicon nitride, or silicon oxynitride. In some embodiments, the dielectric layer 222 is composed of a dielectric material with an extremely low dielectric constant, whose dielectric constant is less than about 2.5. As the geometry size progresses to 30nm or less in the technology node, the dielectric material with an extremely low dielectric constant is used to minimize the capacitance-resistance delay of the device. In some embodiments, the dielectric material with an extremely low dielectric constant includes carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, benzodibutylene, polytetrafluoroethylene, or carbon oxide silicon polymer. In some embodiments, the dielectric material with an extremely low dielectric constant includes a porous existing dielectric material, such as porous hydrogen silsesquioxane, porous methyl silsesquioxane, porous polyarylether, porous SiLK, or porous silicon oxide. In some embodiments, the deposition method of the very low dielectric constant dielectric material is a plasma enhanced chemical vapor deposition process or a spin coating process.

[0062] In some embodiments, the deposition process of the dielectric layer 222 includes a plasma enhanced chemical vapor deposition process, a low pressure chemical vapor deposition process, an atomic layer deposition process, a flowable chemical vapor deposition process, a spin coating process, or another possible process. In some embodiments, the planarization process includes a chemical mechanical polishing process, a polishing process, an etching process, another possible process, or a combination thereof.

[0063] like Figure 2A In some embodiments shown, after forming the dielectric layer 222, a removal process, a deposition process, and a subsequent planarization process are performed to form metal gate structures 256A and 256B to replace the dummy gate structure. In some embodiments, the metal gate structure 256A surrounded by the gate spacer 218A includes a gate dielectric layer 252A and a gate 254A on the gate dielectric layer 252A. Similarly, the metal gate structure 256B surrounded by the gate spacer 218B may include a gate dielectric layer 252B and a gate layer 254B on the gate dielectric layer 252B. In some embodiments, the gate spacer 218A is located on the sidewall surfaces 255A on both sides of the metal gate structure 256A, and the gate spacer 218B is located on the sidewall surfaces 255B on both sides of the metal gate structure 256B.

[0064] In some embodiments, the gate dielectric layers 252A and 252B include a single layer or multiple layers. In some embodiments, the gate dielectric layers 252A and 252B include a U-shape (cross-sectional view) or a rectangular shape (plan view). In some embodiments, the gate dielectric layers 252A and 252B are composed of silicon oxide, silicon nitride, or a dielectric material with a high dielectric constant (greater than 7.0) (such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or a combination thereof). The gate dielectric layers 252A and 252B may be formed by molecular beam deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, or the like.

[0065] In some embodiments, the gate layers 254A and 254B are composed of metal-containing materials such as titanium nitride, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, combinations thereof, or multilayers thereof, and the formation method thereof may be a deposition process such as electroplating, electroless plating, or another suitable method.

[0066] In some embodiments, a work function layer (not shown) may be formed in the metal gate structures 256A and 256B. The work function layer may include an n-type work function metal or a p-type work function metal. The p-type work function layer may include titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, another suitable p-type work function material, or a combination thereof. The n-type work function layer may include titanium, silver, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, another suitable n-type work function material, or a combination thereof.

[0067] like Figure 2A In some embodiments shown, a dielectric layer 226 (e.g., an intermetallic dielectric layer) is then formed on the dielectric layer 222 and the metal gate structures 256A and 256B. For example, the dielectric layer 226 can be a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, the dielectric layer 226 is composed of a dielectric material such as phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, undoped silicate glass, or the like, and the deposition method thereof can be any suitable method such as chemical vapor deposition or plasma enhanced chemical vapor deposition.

[0068] like Figure 2BIn some embodiments shown, after the dielectric layer 226 is formed, a mask layer 230 is formed on the dielectric layer 226. The mask layer 230 may have openings directly located at the locations of the source / drain structures 220A, 220B, and 220C. The mask layer 230 may be a photosensitive layer such as a photoresist, which may cover a portion of the dielectric layer 226, and the formation method thereof may adopt a deposition process (such as chemical vapor deposition, physical vapor deposition, or spin coating), a photolithography process, and a patterning process. The photolithography process may include coating the photoresist (such as spin coating), soft baking, aligning the mask, exposing, post-exposure baking, developing the photoresist, rinsing, and drying (such as hard baking).

[0069] like Figure 2B In some embodiments shown, an etching process 360 is then performed to form openings 232A, 232B, and 232C in the dielectric layers 222 and 226 to expose the source / drain structures 220A, 220B, and 220C. The etching process 360 is performed to remove portions of the dielectric layers 222 and 226 and the contact etch stop layer 221 to form the openings 232A, 232B, and 232C, and the etching process stops on the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C to expose the upper surfaces 320A, 320B, and 320C. Therefore, the openings 232A, 232B, and 232C pass through the dielectric layers 222 and 226 and the contact etch stop layer 221, but do not pass through a portion of the source / drain structures 220A, 220B, and 220C. In some embodiments, the etching process 360 is a dry etching process. In addition, the etching gas used in the etching process 360 includes a fluorine-containing gas. After the openings 232A, 232B, and 232C are formed, the mask layer 230 may be removed by etching or any other suitable method.

[0070] like Figure 2C In some embodiments shown, a barrier layer 234 is then deposited to line the sidewall surfaces 233A of the opening 232A, the sidewall surfaces 233B of the opening 232B, the sidewall surfaces 233C of the opening 232C, the upper surface 320A of the source / drain structure 220A, the upper surface 320B of the source / drain structure 220B, and the upper surface 320C of the source / drain structure 220C. The barrier layer 234 may be conformally formed on the dielectric layers 222 and 226 and the source / drain structures 220A, 220B, and 220C.

[0071] In some embodiments, the energy bandgap of the barrier layer 234 is between about 4 eV and about 9 eV. Therefore, the barrier layer 234 with a larger energy bandgap may have excellent insulation capability. For example, the material composition of the barrier layer 234 includes silicon nitride (such as SiN, Si2N3, or Si3N4), aluminum oxide, aluminum fluoride, aluminum oxyfluoride, silicon-doped zirconium oxide, silicon-doped hafnium oxide, hafnium oxide, zirconium oxide, silicon oxide, or a combination thereof. In some embodiments, the energy bandgap of the barrier layer 234 is greater than the energy bandgap of the gate spacers 218A and 218B and the contact etch stop layer 221. For example, the energy bandgap of the gate spacers 218A and 218B and the contact etch stop layer 221 may be between about 3 eV and about 6 eV. Therefore, the barrier layer 234 may have better insulation capability than the gate spacers 218A and 218B, the contact etch stop layer 221, and the dielectric layers 222 and 226.

[0072] In some embodiments, the barrier layer 234 is formed by a deposition process (such as a chemical vapor deposition process or an atomic layer deposition process) or a thermal oxidation process. The deposition process is performed using a precursor such as dichlorosilane, ammonia, silane, nitrous oxide, trimethylaluminum, water, ozone, oxygen, fluorine, or nitrogen trifluoride. The radio frequency power during the deposition process is between about 100 W and about 1000 W. The pressure of the deposition process is between about 2 Torr and about 9 Torr. The temperature of the deposition process is between about 300° C. and about 800° C.

[0073] like Figure 2D In some embodiments shown, an etching process 361 is then performed to etch the barrier layer 234 (see Figure 2C ) to expose the source / drain structures 220A, 220B, and 220C. An etching process 361 is performed to remove a portion of the barrier layer 234 on the upper surface of the dielectric layer 226 and the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C, and the etching process stops on the source / drain structures 220A, 220B, and 220C. For example, when the barrier layer 234 is composed of silicon nitride, the etching process 361 can adjust the etching selectivity of silicon nitride to silicon (or silicon oxide) to partially remove the barrier layer 234 and stop on the source / drain structures 220A, 220B, and 220C. The etching process 361 may form a barrier layer 234A on the sidewall surface 233A of the opening 232A, and a barrier layer 234B on the sidewall surface 233B of the opening 232B. In addition, a barrier layer 234C is formed on the sidewall surface 233C of the opening 232C. In addition, after the etching process 361 is performed, the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C in the openings 232A, 232B, and 232C may be exposed.

[0074] In some embodiments, the etching process 361 includes a dry etching process or other feasible processes. In some embodiments, the etching gas used in the etching process 361 includes argon, hydrofluorocarbon, hydrogen, or carbon fluoride. The temperature of the etching process 361 can be between about 30° C. and about 100° C. In addition, the RF power of the etching process 361 is between about 100 W and about 1000 W.

[0075] like Figure 2E In some embodiments shown in FIG. 1 , barrier layers 234A, 234B, and 234C (see FIG. 234A and FIG. 234C) are provided. Figure 2D ) is subjected to a pre-cleaning process 362. In some embodiments, the pre-cleaning process 362 is performed to clean (remove) the sidewalls of the barrier layers 234A, 234B, and 234C and the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C (see Figure 2D ) on the native oxide (not shown). In addition, a pre-cleaning process 362 is performed to dope fluorine 238 to the sidewalls of the barrier layers 234A, 234B, and 234C in the openings 232A, 232B, and 232C (see Figure 2D ). For example, when the barrier layers 234A, 234B, and 234C are composed of silicon nitride and the process gas used in the pre-cleaning process 362 includes hydrofluoric acid, fluorinated silicon nitride can be formed on the sidewalls of the barrier layers 234A, 234B, and 234C. For example, the concentration of fluorine 238 in the barrier layers 234A, 234B, and 234C is between about 2 atomic % and about 4 atomic %. Doping the barrier layers 234A, 234B, and 234C with fluorine 238 helps improve some parameters of wafer acceptance testing of the fin field effect transistor, such as off-state current (leakage current) and breakdown voltage. After performing the pre-cleaning process 362, the barrier layers 234A, 234B, and 234C contain fluorine 238 therein.

[0076] In some embodiments, the pre-cleaning process 362 includes a plasma pre-cleaning process. The pre-cleaning process 362 may use a process gas including hydrofluoric acid, nitrogen trifluoride, ammonia, and helium. The temperature of the pre-cleaning process 362 may be between about 30° C. and about 300° C. In addition, the RF power during the etching process 361 may be between about 100 W and about 1000 W.

[0077] like Figure 2EIn some embodiments shown, a patterning process is then performed to remove portions of the dielectric layer 226 on the metal gate structures 256A and 256B to form openings 239A and 239B. The opening 239A may pass through the dielectric layer 226 and expose the metal gate structure 256A. In addition, the patterning process may remove a portion of the barrier layer 234B and a portion of the dielectric layer 226 on the metal gate structure 256B. Thus, the patterning process may enlarge the opening 232B (see FIG. Figure 2D ), an opening 239B may be formed. A barrier layer 235B may be formed on a portion of a sidewall surface 237B of the opening 239B. In addition, the opening 239B passes through the dielectric layer 226 and exposes the upper surface 320B of the source / drain structure 220B and the metal gate structure 256B. It should be noted that the barrier layer does not cover the sidewall surface 237A of the opening 239A directly on the metal gate structure 256A, and a portion of the sidewall surface 237B of the opening 239B directly on the metal gate structure 256B.

[0078] In some embodiments, the patterning process includes a photolithography process and a subsequent etching process. The photolithography process may include applying photoresist (such as spin coating), soft baking, aligning mask, exposing, post-exposure baking, developing photoresist, rinsing, and drying (such as hard baking). The etching process may include a dry etching process or a wet etching process.

[0079] like Figure 2F In some embodiments shown, source / drain silicide layers 240A, 240B, and 240C are then formed on the source / drain structures 220A, 220B, and 220C by a silicide process. In some embodiments, the silicide process includes sequentially performing a metal deposition process and an annealing process. In some embodiments, the deposition process of the silicide process includes a physical vapor deposition process, an atomic layer deposition process, or another feasible process. In some embodiments, the annealing process temperature of the silicide process is between about 300° C. and about 800° C. After the annealing process, the unreacted metal material is removed.

[0080] In some embodiments, the source / drain silicide layers 240A, 240B, and 240C are composed of cobalt silicide (such as CoSi, CoSi2, Co2Si, or Co3Si), titanium silicide (such as Ti5Si3, TiSi, TiSi2, TiSi3, or Ti6Si4), nickel silicide (such as Ni3Si, Ni 31 Si 12 , Ni2Si, Ni3Si2, NiSi, or NiSi2), copper silicide (such as Cu 17 Si3、Cu 56 Si 11 、Cu5Si、Cu 33 Si7, Cu4Si, Cu19 Si6, Cu3Si, or Cu 87 Si 13 ), one or more of tungsten silicide (such as W5Si3 or WSi2), and molybdenum silicide (such as Mo3Si, Mo5Si3, or MoSi2).

[0081] Adhesive layers 242A, 242B, 242C, and 242D are then formed to cover the sidewall surfaces of the openings 232A, 239B, 232C, and 239A. Figure 2F In some embodiments shown, adhesive layers 242A, 242B, 242C, and 242D cover the source / drain structures 220A, 220B, and 220C in the openings 232A, 239B, and 232C. In addition, contact structures 244A, 244B, 244C, and 244D are formed to fill the openings 232A, 239B, 239A, and 232C. The contact structures 244A, 244B, and 244C pass through the dielectric layers 222 and 226, and the contact structure 244D passes through the dielectric layer 226.

[0082] like Figure 2F As shown, an adhesion layer 242A may be conformally formed on the source / drain silicide layer 240A and line the sidewall surface 233A and the bottom of the opening 232A. An adhesion layer 242B may be conformally formed on the source / drain silicide layer 240B and line the sidewall surface 237A and the bottom of the opening 239B. An adhesion layer 242C may be conformally formed on the source / drain silicide layer 240C and the metal gate structure 256B and line the sidewall surface 233C and the bottom of the opening 232C. An adhesion layer 242D may be conformally formed on the metal gate structure 256A and line the sidewall surface 237A and the bottom of the opening 239B. In some embodiments, the lower surfaces 243A, 243B, and 243C of the adhesion layers 242A, 242B, and 242C are exposed to the barrier layers 234A, 234B, and 234C, respectively. In addition, the barrier layers 234A, 234B, and 234C do not cover the lower surfaces 243A, 243B, and 243C of the adhesion layers 242A, 242B, and 242C. The lower surfaces 243A, 243B, and 243C of the adhesion layers 242A, 242B, and 242C directly contact the source / drain silicide layers 240A, 240B, and 240C, respectively. In addition, the lower surfaces 243A, 243B, and 243C of the adhesive layers 242A, 242B, and 242C are flush with the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C, respectively.

[0083] like Figure 2FAs shown, adhesive layers 242A, 242B, 242C, and 242D surround contact structures 244A, 244B, 244C, and 244D, respectively. Dielectric layers 222 and 226 surround contact structures 244A, 244B, 244C, and 244D. Dielectric layer 226 surrounds contact structure 224D. Adhesive layer 242A covers lower surface 246A and sidewall surface 248A of contact structure 244A. Adhesive layer 242B covers lower surface 246B and sidewall surface 248B of contact structure 244B. Adhesive layer 242C covers lower surface 246C and sidewall surface 248C of contact structure 244C. Adhesive layer 242D covers lower surface 246D and sidewall surface 248D of contact structure 244D. In addition, the contact structure 244A is formed on the source / drain structure 220A. The contact structure 244B is formed on the source / drain structure 220B and the metal gate structure 256B. The contact structure 244C is formed on the source / drain structure 220C. The contact structure 244D is formed on the metal gate structure 256A. In addition, the lower surfaces 246A, 246B, and 246C of the contact structures 244A, 244B, and 244C can be electrically connected to the source / drain structures 220A, 220B, and 220C via the adhesive layers 242A, 242B, and 242C, respectively. The lower surface 246D of the contact structure 244D can be electrically connected to the metal gate structure 256A. It is noteworthy that the barrier layers 234A, 235B, and 234C are not sandwiched between the lower surfaces 246A, 246B, and 246C of the contact structures 244A, 244B, and 244C and the source / drain structures 220A, 220B, and 220C.

[0084] like Figure 2F As shown, contact structures 244A and 244C can be used as source / drain contact structures. Contact structure 244B can be used as a slot contact structure, which is formed by combining the source / drain contact structure and the gate contact structure. In addition, contact structure 244D can be used as a gate contact structure.

[0085] In some embodiments, a deposition process and a subsequent planarization process such as chemical mechanical polishing are performed to form adhesion layers 242A, 242B, 242C, and 242D and contact structures 244A, 244B, 244C, and 244D. Adhesion layers 242A, 242B, 242C, and 242D may include conductive materials such as titanium, titanium nitride, tantalum, tantalum nitride, or the like, and may be formed by a chemical vapor deposition process (such as plasma enhanced chemical vapor deposition). However, other processes such as sputtering, metal organic chemical vapor deposition, physical vapor deposition, or atomic layer deposition may also be used. The contact structures 244A, 244B, 244C, and 244D may be made of a conductive material, such as copper, aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, or another feasible material, and may be formed by any suitable deposition method such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or plating (such as electroplating).

[0086] After the above process is performed, the fin field effect transistor 500A and the fin field effect transistor 500B are formed on the fin structure 204. In addition, Figure 2F Some embodiments shown form a semiconductor device structure 600A including a FinFET 500A and a FinFET 500B.

[0087] In some embodiments, the semiconductor device structure 600A includes barrier layers 234A, 234C, and 235B surrounding sidewall surfaces 248A, 248B, and 248C of contact structures 244A, 244B, and 244C, and the contact structures 244A, 244B, and 244C are electrically connected to the source / drain structures 220A, 220B, and 220C. In some embodiments, the barrier layers 234A, 234C, and 235B have an energy band gap between about 4 eV and about 9 eV, which is greater than the energy band gaps of the gate spacers 218A and 218B, the contact etch stop layer 221, and the dielectric layers 222 and 226. Therefore, the barrier layers 234A, 234C, and 235B can provide preferred insulation properties to the FinFETs 500A and 500B between the source / drain structures 220A, 220B, and 220C and the metal gate structures 256A and 256B. In some embodiments, a pre-cleaning process can be performed before forming the contact structure to dope fluorine into the barrier layer. Therefore, the leakage current problem between the source / drain contact structure and the metal gate structure in the FinFET can be eliminated. Some parameters of the wafer acceptance test of the FinFET can be improved, such as the off-state current (leakage current) and the breakdown voltage.

[0088] Figure 36 is a cross-sectional view of a semiconductor device structure 600B in some embodiments. The material, configuration, structure, and / or formation process of the semiconductor device structure 600B may be similar or identical to the material, configuration, structure, and / or formation process of the semiconductor device structure 600A, and the relevant details are not repeated here. One of the differences between the semiconductor device structure 600A and the semiconductor device structure 600B is that the semiconductor device structure 600B further includes additional barrier layers 236A, 236B, and 236C. Specifically, the barrier layer structures 336A, 336B, and 336C are located between the dielectric layer 222 (or the dielectric layer 226) and the adhesive layers 242A, 242B, and 242C, and surround the sidewalls of the corresponding contact structures 244A, 244B, and 244C. In some embodiments, barrier layer structures 336A, 336B, and 336C are multi-layer structures, each of which surrounds the sidewalls of corresponding contact structures 244A, 244B, and 244C. For example, barrier layer structure 336A may include barrier layer 234A and barrier layer 236A surrounding barrier layer 234A. Barrier layer structure 336B may include barrier layer 234B and barrier layer 236B surrounding barrier layer 234B. In addition, barrier layer structure 336C may include barrier layer 234C and barrier layer 236C surrounding barrier layer 234C. In some embodiments, the material, configuration, structure, and / or formation process of barrier layers 236A, 236B, and 236C may be similar to or the same as the material, configuration, structure, and / or formation process of barrier layers 234A, 235B, and 234C. For example, the energy band gap of the material of the barrier layers 236A, 236B, and 236C may be between about 4 eV and about 9 eV. In some embodiments, the energy band gap of the barrier layers 236A, 236B, and 236C may be the same as or similar to the energy band gap of the gate spacers 218A and 218B, the contact etch stop layer 221, and the dielectric layers 222 and 226. In some embodiments, fluorine 238 may be doped into the barrier layers 236A, 236B, and 236C.

[0089] Figure 46 is a cross-sectional view of a semiconductor device structure 600C in some embodiments. The material, configuration, structure, and / or formation process of the semiconductor device structure 600C may be similar or identical to the material, configuration, structure, and / or formation process of the semiconductor device structure 600A, and the relevant details are not repeated here. One of the differences between the semiconductor device structure 600A and the semiconductor device structure 600C is that the lower surface of the adhesion layer of the semiconductor device structure 600C is lower than the upper surface of the source / drain structure. Specifically, the source / drain structure is connected to the adhesion layer via a source / drain silicide layer. The lower surface of the adhesion layer of the semiconductor device structure 600C is located between the upper surface and the lower surface of the source / drain structure, or is buried in the source / drain structure. Therefore, the corresponding source / drain structure surrounds a portion of the lower surface and the sidewall surface of the adhesion layer.

[0090] For example, the lower surface 243A of the adhesive layer 242A is located between the upper surface 320A and the lower surface 321A of the source / drain structure 220A connected to the adhesive layer 242A. The lower surface 243B of the adhesive layer 242B is located between the upper surface 320B and the lower surface 321B of the source / drain structure 220B connected to the adhesive layer 242B. The lower surface 243C of the adhesive layer 242C is located between the upper surface 320C and the lower surface 321C of the source / drain structure 220C connected to the adhesive layer 242C. In addition, the lower surfaces 243A, 243B, and 243C of the adhesive layers 242A, 242B, and 242C may be buried in the source / drain structures 220A, 220B, and 220C. In some embodiments, the lower surfaces 243A, 243B, and 243C of the adhesive layers 242A, 242B, and 242C are lower than the source / drain structures 220A, 220B, and 220C by a distance D1. Figure 4 In some embodiments, the lower surfaces 243A, 243B, and 243C of the adhesion layers 242A, 242B, and 242C are lower than the lower surfaces of the barrier layers 236A, 236B, and 236C, while the lower surfaces of the barrier layers 236A, 236B, and 236C are flush with the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C.

[0091] Figure 56 is a cross-sectional view of a semiconductor device structure 600D in some embodiments. The material, configuration, structure, and / or formation process of the semiconductor device structure 600D may be similar or identical to the material, configuration, structure, and / or formation process of the semiconductor device structure 600C, and the relevant details are not repeated here. One of the differences between the semiconductor device structure 600C and the semiconductor device structure 600D is that the lower surface of the contact structure of the semiconductor device structure 600C is lower than the upper surface of the source / drain structure. Specifically, the lower surface of the contact structure of the semiconductor device structure 600D is located between the upper surface and the lower surface of the source / drain structure (or buried in the source / drain structure). The source / drain structure is connected to the adhesive layer via the source / drain silicide layer. In this way, the corresponding source / drain structure can surround a portion of the sidewall surface and the lower surface of the contact structure.

[0092] For example, the lower surface 246A of the contact structure 244A is located between the upper surface 320A and the lower surface 321A of the source / drain structure 220A. The lower surface 246B of the contact structure 244B is located between the upper surface 320B and the lower surface 321B of the source / drain structure 220B. The lower surface 246C of the contact structure 244C is located between the upper surface 320C and the lower surface 321C of the source / drain structure 220C. In addition, the contact structures 244A, 244B, and 244C can be buried in the source / drain structures 220A, 220B, and 220C. In some embodiments, the lower surfaces 246A, 246B, and 246C of the contact structures 244A, 244B, and 244C are lower than the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C by a distance D2, and the distance D2 is less than Figure 5 The distance D1 is shown.

[0093] The semiconductor device structures 600B, 600C, and 600D include barrier layers 234A, 234C, and 235B surrounding the contact structures 244A, 244B, and 244C. In addition, the barrier layers 234A, 234C, and 235B are located between the contact structures 244A, 244B, and 244C and the metal gate structures 256A and 256B along the longitudinal direction of the fin structure 204 of the semiconductor device structures 600B, 600C, and 600D (i.e., the channel length direction of the fin field effect transistors 500A and 500B). In some embodiments, the energy band gap of the barrier layers 234A, 234C, and 235B is between about 4 eV and about 9 eV to provide preferred insulation characteristics to the FinFETs 500A and 500B, between the source / drain structures 220A, 220B, and 220C and the metal gate structures 256A and 256B. In some embodiments, a pre-cleaning process may be performed to dope fluorine into the barrier layer before forming the contact structure. Some parameters of the wafer acceptance test of the FinFETs, such as the off-state current (leakage current) and the breakdown voltage, may be improved.

[0094] Figures 6A to 6C In some embodiments, Figure 2A The cross-sectional view of various stages of the process for forming the semiconductor device structure 600E after the stage shown. The materials, configurations, structures, and / or formation processes of the semiconductor device structure 600E may be similar or identical to the materials, configurations, structures, and / or formation processes of the semiconductor device structure 600A, and the relevant details will not be repeated here.

[0095] like Fig. 6A In some embodiments shown, after the dielectric layer 226 is formed, a mask layer 230 is formed on the dielectric layer 226 . Fig. 6A The material, configuration, structure, and / or formation process of the mask layer 230 shown in the figure may be different from Figure 2B The material, configuration, structure, and / or formation process of the mask layer 230 are similar or identical, and the relevant details are not repeated here.

[0096] like Fig. 6AIn some embodiments shown, an etching process 460 is then performed to form openings 332A, 332B, and 332C in the dielectric layers 222 and 226 and a portion of the source / drain structures 220A, 220B, and 220C. The etching process 460 is performed to remove portions of the dielectric layers 222 and 226, the contact etch stop layer 221, and the source / drain structures 220A, 220B, and 220C to form the openings 332A, 332B, and 332C. Thus, the openings 332A, 332B, and 332C may pass through the dielectric layers 222 and 226 and the contact etch stop layer 221. In addition, the bottom surfaces 331A, 331B, and 331C of the openings 332A, 332B, and 332C may be lower than the source / drain structures 220A, 220B, and 220C by a distance D3, as shown in FIG. Fig. 6A In some embodiments, the etching gas used in the etching process 460 includes a fluorine-containing gas.

[0097] A barrier layer (not shown) may then be deposited to line the sidewall surfaces and lower surfaces of the openings 332A, 332B, and 332C. The barrier layer may be conformally formed on the dielectric layers 222 and 226 and the source / drain structures 220A, 220B, and 220C. The material, configuration, structure, and / or formation process of the barrier layer may be different from the material, configuration, structure, and / or formation process of the barrier layer. Figure 2C The material, configuration, structure, and / or formation process of the barrier layer 234 are similar or identical, and thus the related details are not repeated.

[0098] Then, a portion of the barrier layer is etched by an etching process to expose the source / drain structures 220A, 220B, and 220C. The etching process removes a portion of the barrier layer on the upper surface of the dielectric layer 226 and the portions of the source / drain structures 220A, 220B, and 220C in the openings 332A, 332B, and 332C, and stops on the source / drain structures 220A, 220B, and 220C. The method and / or conditions of the etching process may be the same as those of Figure 2D The etching process 361 is similar or the same as that shown, and the relevant details are not repeated here. After the etching process is performed, the source / drain structures 220A, 220B, and 220C in the openings 332A, 332B, and 332C are exposed.

[0099] A pre-cleaning process 362 is then performed on the barrier layers 334A and 334C in the openings 332A and 332C. Figure 6B In some embodiments shown, a pre-cleaning process 362 is performed on the barrier layer on the source / drain structure 220B. In some embodiments, the pre-cleaning process 362 is performed to dope fluorine 238 into the openings 332A, 332B, and 332C (see FIG. Fig. 6A ) on the sidewall of the barrier layer. Figure 6BThe method and / or conditions of the pre-cleaning process 362 shown may be similar to Figure 2E The method and / or conditions of the pre-cleaning process 362 are similar or identical, and therefore the relevant details are not repeated. After the pre-cleaning process 362 is performed, the barrier layers 334A and 334C on the source / drain structure 220B contain fluorine 238 therein.

[0100] like Figure 6B In some embodiments shown, a patterning process is then used to remove portions of the dielectric layer 226 on the metal gate structures 256A and 256B to form openings 339A and 339B. The opening 339A can pass through the dielectric layer 226 and expose the metal gate structure 256A. In addition, a patterning process is performed to remove a portion of the barrier layer 334B and a portion of the dielectric layer 226 on the metal gate structure 256B. Thus, the patterning process can be used to enlarge the opening 332B (see Fig. 6A ) to form an opening 339B. Therefore, the barrier layer 335B is formed on a portion of the sidewall 337B of the opening 339B. In addition, the opening 339B passes through the dielectric layer 226 and exposes the upper surface of the source / drain structure 220B and the metal gate structure 256B. It is worth noting that the barrier layer does not cover the sidewall 337A of the opening 339A directly on the metal gate structure 256A, and the portion of the sidewall 337B of the opening 339B directly on the metal gate structure 256B.

[0101] Then, source / drain silicide layers 240A, 240B, and 240C are formed on the source / drain structures 220A, 220B, and 220C. Adhesion layers 342A, 342B, 342C, and 342D cover the openings 332A, 339A, 339B, and 332C, and the source / drain structures 220A, 220B, and 220C in the openings 332A, 339B, and 332C (see FIG. 2 ). Figure 6B ). In addition, Figure 6C In some embodiments shown, contact structures 344A, 344B, 344C, and 344D are formed to fill openings 332A, 339A, 339B, and 332C through dielectric layers 222 and 226 . Figure 6C The materials, configurations, structures, and / or formation processes of the source / drain silicide layers 240A, 240B, and 240C, the adhesion layers 342A, 342B, 342C, and 342D, and the contact structures 344A, 344B, 344C, and 344D shown may be similar to those of the embodiment of the present invention. Figure 2FThe materials, settings, structures, and / or formation processes of the source / drain silicide layers 240A, 240B, and 240C, adhesion layers 242A, 242B, 242C, and 242D, and contact structures 244A, 244B, 244C, and 244D shown are similar or identical, so the relevant details are not repeated.

[0102] In some embodiments, portions of the barrier layers 334A, 335B, and 334C, portions of the adhesion layers 342A, 3422B, and 342C, and portions of the contact structures 344A, 344B, and 344C are buried in the source / drain structures 220A, 220B, and 220C. The lower surfaces 343A, 343B, and 343C of the adhesion layers 342A, 342B, and 342C are lower than the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C by a distance D1. The lower surfaces 346A, 346B, and 346C of the contact structures 344A, 344B, and 344C are lower than the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C by a distance D2. In addition, the lower surfaces 356A, 356B, and 356C of the barrier layers 334A, 335B, and 334C are lower than the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C by a distance D3. The lower surfaces 356A, 356B, and 356C of the barrier layers 334A, 335B, and 334C may be buried in the source / drain structures 220A, 220B, and 220C. Figure 6C In some embodiments shown, distance D1 is equal to distance D3 and greater than distance D2. Lower surfaces 356A, 356B, and 356C of barrier layers 334A, 335B, and 334C are aligned with lower surfaces 343A, 343B, and 343C of adhesive layers 342A, 342B, and 342C.

[0103] After performing the above processes, some embodiments form a semiconductor device structure 600E including the fin field effect transistor 500A and the fin field effect transistor 500B. Figure 6C shown.

[0104] Figure 76 is a cross-sectional view of a semiconductor device structure 600F in some embodiments. The material, configuration, structure, and / or formation process of the semiconductor device structure 600F may be similar or identical to the material, configuration, structure, and / or formation process of the semiconductor device structure 600E, and the relevant details are not repeated here. One of the differences between the semiconductor device structure 600E and the semiconductor device structure 600F is that the lower surface of the adhesive layer of the semiconductor device structure 600F is located between the lower surface of the barrier layer and the lower surface of the source / drain structure connected to the adhesive layer. Therefore, the corresponding source / drain structure surrounds a portion of the sidewall surface and the lower surface of the adhesive layer. For example, the lower surface 343A of the adhesive layer 342A is located between the lower surface 356A of the barrier layer 334A and the lower surface 321A of the source / drain structure 220A connected to the adhesive layer 342A. The lower surface 343B of the adhesion layer 342B is located between the lower surface 356B of the barrier layer 334B and the lower surface 321B of the source / drain structure 220B connected to the adhesion layer 342B. The lower surface 343C of the adhesion layer 342C is located between the lower surface 356C of the barrier layer 334C and the lower surface 321C of the source / drain structure 220C connected to the adhesion layer 342C. Figure 7 In some of the embodiments shown, distance D1 (the distance between the lower surface of the adhesion layer and the upper surface of the source / drain structure connected to the adhesion layer) is greater than distance D3 (the distance between the lower surface of the barrier layer and the upper surface of the source / drain structure) and greater than distance D2 (the distance between the lower surface of the contact structure and the upper surface of the source / drain structure).

[0105] The semiconductor device structures 600E and 600F include barrier layers 334A, 334C, and 335B surrounding the contact structures 344A, 344B, and 344C. In addition, the lower surfaces 356A, 356B, and 356C of the barrier layers 334A, 335B, and 334C are lower than the upper surfaces 320A, 320B, and 320C of the source / drain structures 220A, 220B, and 220C. In some embodiments, the barrier layers 334A, 334C, and 335B may provide preferred insulation properties to the fin field effect transistors 500A and 500B between the source / drain structures 220A, 220B, and 220C and the metal gate structures 256A and 256B. In some embodiments, the barrier layers may be doped with fluorine. Some parameters of wafer acceptance testing of FinFETs, such as off-state current (leakage current) and breakdown voltage, can be improved.

[0106] As described above, the semiconductor device structure (e.g., semiconductor device structures 600A, 600B, 600C, 600D, 600E, and 600F) includes a barrier layer (e.g., barrier layers 234A, 234C, and 235B) surrounding sidewall surfaces (e.g., sidewall surfaces 248A, 248B, and 248C) of contact structures (e.g., contact structures 244A, 244B, and 244C) that are electrically connected to source / drain structures (e.g., source / drain structures 220A, 220B, and 220C). In some embodiments, the barrier layer has an energy bandgap between about 4 eV and about 9 eV, which is greater than the energy bandgap of the gate spacer (e.g., gate spacers 218A and 218B), the contact etch stop layer (e.g., contact etch stop layer 221), and the dielectric layer (e.g., dielectric layers 222 and 226). Therefore, the barrier layer can provide preferred insulation properties between the source / drain structure and the metal gate structure in the fin field effect transistor (such as the fin field effect transistors 500A and 500B). In some embodiments, a pre-cleaning process (such as the pre-cleaning process 362) can be performed before forming the contact structure to dope fluorine into the barrier layer. Therefore, the leakage current problem between the source / drain contact structure and the metal gate structure in the fin field effect transistor can be eliminated. Some parameters of the wafer acceptance test of the fin field effect transistor can be improved, such as the off-state current (leakage current) and the breakdown voltage.

[0107] The present invention provides an embodiment of a semiconductor device structure and a method for forming the same. The semiconductor device structure includes a gate structure, a source / drain structure, a contact structure, an adhesive layer, and a barrier layer. The gate spacer is located on the fin structure and on the sidewall surface of the gate structure. The source / drain structure is located in the fin structure and adjacent to the gate spacer. The contact structure is located on the source / drain structure. The adhesive layer covers the lower surface and the sidewall surface of the contact structure. The barrier layer surrounds the sidewall surface of the contact structure. The lower surface of the adhesive layer is exposed to the barrier layer. The barrier layer surrounding the contact structure has better insulation between the source / drain structure and the metal gate structure than the gate spacer, the contact etch stop layer, and the dielectric layer.

[0108] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a gate structure, a gate spacer, a source / drain structure, a contact structure, an adhesive layer, and a barrier layer. The gate structure is located on a fin structure. The gate spacer is located on the fin structure and on a sidewall surface of the gate structure. The source / drain structure is located in the fin structure and adjacent to the gate spacer. The contact structure is located on the source / drain structure. The adhesive layer covers the lower surface and the sidewall surface of the contact structure. The barrier layer surrounds the sidewall surface of the contact structure. The lower surface of the adhesive layer is exposed to the barrier layer.

[0109] In some embodiments, a lower surface of the adhesive layer directly contacts the source / drain silicide layer on the source / drain structure.

[0110] In some embodiments, a lower surface of the adhesive layer is flush with an upper surface of the source / drain structure.

[0111] In some embodiments, a lower surface of the barrier layer is buried in the source / drain structure.

[0112] In some embodiments, the energy band gap of the adhesion layer is smaller than the energy band gap of the barrier layer.

[0113] In some embodiments, the barrier layer has a bandgap between about 4 eV and about 9 eV.

[0114] In some embodiments, the barrier layer includes silicon nitride, aluminum oxide, aluminum fluoride, aluminum fluoride oxyfluoride, silicon-doped zirconium oxide, silicon-doped hafnium oxide, hafnium oxide, zirconium oxide, silicon oxide, or a combination thereof.

[0115] In some embodiments, the barrier layer includes fluorine therein.

[0116] In some embodiments, the fluorine concentration in the barrier layer is between about 2 atomic % and about 4 atomic %.

[0117] In some embodiments, the semiconductor structure includes a contact etch stop layer on the source / drain structure and the gate spacer; and a dielectric layer on the gate structure and surrounding the contact structure, wherein the energy band gaps of the contact etch stop layer and the dielectric layer are smaller than the energy band gap of the barrier layer.

[0118] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a gate structure, a source / drain structure, a dielectric layer, a contact structure, an adhesive layer, and a barrier layer. The gate structure is located on a fin structure. The source / drain structure is located in the fin structure and is adjacent to the gate structure. The dielectric layer is located on the gate structure and the source / drain structure. The contact structure passes through the dielectric layer. The adhesive layer covers the lower surface and sidewall surface of the contact structure. The barrier layer is located between the dielectric layer and the adhesive layer. Part of the barrier layer and part of the contact structure are buried in the source / drain structure.

[0119] In some embodiments, a distance between a lower surface of the barrier layer and an upper surface of the source / drain structure is less than or equal to a distance between a lower surface of the contact structure and an upper surface of the source / drain structure.

[0120] In some embodiments, a lower surface of the contact structure is located between a lower surface of the barrier layer and a lower surface of the source / drain structure.

[0121] In some embodiments, the bottom surface of the contact structure is electrically connected to the source / drain structure via an adhesive layer.

[0122] In some embodiments, the barrier layer has a bandgap between about 4 eV and about 9 eV.

[0123] In some embodiments, the barrier layer includes silicon nitride, aluminum oxide, aluminum fluoride, aluminum fluoride oxyfluoride, silicon-doped zirconium oxide, silicon-doped hafnium oxide, hafnium oxide, zirconium oxide, silicon oxide, or a combination thereof.

[0124] In some embodiments, the semiconductor structure includes: a gate spacer located on the fin structure and on the sidewall surface of the gate structure; and a contact etch stop layer located on the source / drain structure and the gate spacer, wherein a barrier layer is provided between the gate spacer, the contact etch stop layer and the contact structure, and wherein the energy band gaps of the gate spacer, the contact etch stop layer and the adhesion layer are all smaller than the energy band gap of the barrier layer.

[0125] In some embodiments, a method for forming a semiconductor structure is provided. The method includes forming a gate structure on a fin structure. The method also includes forming a source / drain structure in the fin structure, and the source / drain structure is adjacent to the gate structure. The method also includes forming a dielectric layer on the gate structure and the source / drain structure. The method includes forming an opening in the dielectric layer to expose the source / drain structure. The method also includes depositing a barrier layer to pad the sidewall surface of the opening and the upper surface of the source / drain structure. The method also includes etching a portion of the barrier layer to expose the source / drain structure. The method also includes depositing an adhesion layer to cover the sidewall surface of the opening and the source / drain structure in the opening. The method also includes forming a contact structure to fill the opening in the dielectric layer. The adhesion layer surrounds the contact structure.

[0126] In some embodiments, the method includes removing a portion of the dielectric layer and a portion of the source / drain structure when forming the opening.

[0127] In some embodiments, the method includes: performing a pre-cleaning process on the barrier layer before filling the contact structure into the opening, wherein the pre-cleaning process dopes fluorine into the barrier layer.

[0128] The present invention has been disclosed as above with several embodiments to facilitate those skilled in the art to understand the present invention. Those skilled in the art can use the embodiments of the present invention as a basis to design or adjust other processes and structures to implement the same purpose of the embodiments and / or achieve the same advantages of the embodiments. Those skilled in the art should understand that the above equivalent substitutions do not deviate from the concept and scope of the present invention, and can make these different changes, substitutions, and adjustments without deviating from the concept and scope of the present invention.

Claims

1. A semiconductor structure comprising: a gate structure located on a fin structure; a gate spacer located on the fin structure and on the sidewall surface of the gate structure; a source / drain structure located in the fin structure and adjacent to the gate spacer; a contact structure located on the source / drain structure; an adhesive layer covering the lower surface and the sidewall surface of the contact structure, wherein a portion of the adhesive layer is buried in the source / drain structure, and wherein an extended portion of the adhesive layer directly contacts the gate structure; as well as A barrier layer surrounds the sidewall surface of the contact structure, wherein the upper surface of the barrier layer is flush with the upper surface of the gate structure. 2 . The semiconductor structure of claim 1 , wherein a lower surface of the adhesive layer directly contacts a source / drain silicide layer on the source / drain structure. 3 . The semiconductor structure of claim 1 , wherein a lower surface of the barrier layer is buried in the source / drain structure. 4 . The semiconductor structure of claim 1 , wherein an energy band gap of the adhesion layer is smaller than an energy band gap of the barrier layer. The semiconductor structure of claim 1 , wherein the energy band gap of the barrier layer is between 4 eV and 9 eV.

6. The semiconductor structure of claim 1, wherein the barrier layer comprises silicon nitride, aluminum oxide, aluminum fluoride, aluminum oxyfluoride, silicon-doped zirconium oxide, silicon-doped hafnium oxide, hafnium oxide, zirconium oxide, silicon oxide, or a combination thereof.

7. The semiconductor structure of claim 1, wherein the barrier layer comprises fluorine therein.

8. The semiconductor structure of claim 7, wherein the fluorine concentration in the barrier layer is between 2 atomic % and 4 atomic %.

9. The semiconductor structure of claim 1, further comprising: a contact etch stop layer located on the source / drain structure and the gate spacer; as well as A dielectric layer is located on the gate structure and surrounds the contact structure, wherein the energy band gaps of the contact etching stop layer and the dielectric layer are both smaller than the energy band gap of the barrier layer.

10. A semiconductor structure comprising: a gate structure located on a fin structure; a source / drain structure located in the fin structure and adjacent to the gate structure; a dielectric layer located on the gate structure and the source / drain structure; a contact structure passing through the dielectric layer; an adhesive layer covering the lower surface and sidewall surface of the contact structure; as well as A barrier layer is located between the dielectric layer and the adhesive layer, wherein a portion of the barrier layer and a portion of the contact structure are buried in the source / drain structure, wherein the adhesive layer covers an interface between the barrier layer and the dielectric layer.

11. The semiconductor structure of claim 10, wherein a distance between a lower surface of the barrier layer and an upper surface of the source / drain structure is less than or equal to a distance between a lower surface of the contact structure and an upper surface of the source / drain structure. 12 . The semiconductor structure of claim 11 , wherein a lower surface of the contact structure is located between a lower surface of the barrier layer and a lower surface of the source / drain structure. 13 . The semiconductor structure of claim 10 , wherein a lower surface of the contact structure is electrically connected to the source / drain structure via the adhesive layer.

14. The semiconductor structure of claim 10, wherein the energy band gap of the barrier layer is between 4 eV and 9 eV.

15. The semiconductor structure of claim 10, wherein the barrier layer comprises silicon nitride, aluminum oxide, aluminum fluoride, aluminum oxyfluoride, silicon-doped zirconium oxide, silicon-doped hafnium oxide, hafnium oxide, zirconium oxide, silicon oxide, or a combination thereof.

16. The semiconductor structure of claim 10, further comprising: a gate spacer located on the fin structure and on the sidewall surface of the gate structure; as well as a contact etch stop layer located on the source / drain structure and the gate spacer, The barrier layer is located between the gate spacer, the contact etching stop layer and the contact structure, and The energy band gaps of the gate spacer, the contact etching stop layer, and the adhesive layer are all smaller than the energy band gap of the barrier layer.

17. A semiconductor structure comprising: a gate structure located on a fin structure; a source / drain structure located in the fin structure and adjacent to the gate structure; a dielectric layer located on the gate structure and the source / drain structure; a contact structure passing through the dielectric layer; an adhesive layer covering the lower surface and the sidewall surface of the contact structure, wherein the adhesive layer has an extended portion to directly contact the gate structure; as well as A barrier layer is located between the dielectric layer and the adhesive layer, wherein the lower surface of the adhesive layer is located between the upper surface of the source / drain structure and the lower surface of the source / drain structure.

18. The semiconductor structure of claim 17, wherein a lower surface of the barrier layer is higher than a lower surface of the adhesive layer.

19. The semiconductor structure of claim 17, wherein the contact structure is electrically connected to the gate structure and the source / drain structure.

20. A method for forming a semiconductor structure, comprising: forming a gate structure on a fin structure; forming a source / drain structure in the fin structure, wherein the source / drain structure is adjacent to the gate structure; forming a dielectric layer on the gate structure and the source / drain structure; forming an opening in the dielectric layer to expose the source / drain structure; Depositing a barrier layer to line the sidewall surface of the opening and the upper surface of the source / drain structure; etching a portion of the barrier layer to expose the source / drain structure; Depositing an adhesion layer to cover the sidewall surface of the opening and the source / drain structure in the opening, wherein an extended portion of the adhesion layer directly contacts the gate structure; as well as A contact structure is formed to fill the opening in the dielectric layer, wherein the adhesive layer surrounds the contact structure.

21. The method for forming a semiconductor structure according to claim 20, further comprising: When forming the opening, a portion of the dielectric layer and a portion of the source / drain structure are removed.

22. The method for forming a semiconductor structure according to claim 20, further comprising: Before filling the contact structure into the opening, a pre-cleaning process is performed on the barrier layer, wherein the pre-cleaning process dopes fluorine into the barrier layer. 23 . The method for forming a semiconductor structure according to claim 20 , wherein a lower surface of the adhesive layer is flush with an upper surface of the source / drain structure. 24 . The method for forming a semiconductor structure according to claim 20 , wherein an upper surface of the barrier layer is flush with an upper surface of the gate structure. 25 . The method for forming a semiconductor structure according to claim 20 , wherein the adhesive layer covers an interface between the barrier layer and the dielectric layer.

26. The method for forming a semiconductor structure according to claim 20, further comprising: A silicidation process is performed to form a source / drain silicide layer on the source / drain structure.

27. The method for forming a semiconductor structure according to claim 20, further comprising: An additional barrier layer is deposited, wherein the barrier layer and the additional barrier layer form a multi-layer barrier layer structure between the dielectric layer and the adhesive layer and surround the sidewall of the contact structure.

28. A method for forming a semiconductor structure, comprising: forming a gate structure on a fin structure; forming a source / drain structure in the fin structure, wherein the source / drain structure is adjacent to the gate structure; forming a dielectric layer on the gate structure and the source / drain structure; forming an opening in the dielectric layer to expose the source / drain structure; Depositing a barrier layer to line the sidewall surface of the opening and the upper surface of the source / drain structure; etching a portion of the barrier layer to expose the source / drain structure, The energy band gap of the barrier layer is 4eV to 9eV; as well as An adhesion layer is deposited to cover the sidewall surface of the opening and the source / drain structure in the opening, wherein an extended portion of the adhesion layer directly contacts the gate structure.

29. The method for forming a semiconductor structure according to claim 28, further comprising: A contact structure is formed to fill the opening in the dielectric layer, wherein the adhesive layer surrounds the contact structure. 30 . The method for forming a semiconductor structure according to claim 29 , wherein a lower surface of the adhesive layer is flush with an upper surface of the source / drain structure.

31. The method for forming a semiconductor structure according to claim 29, wherein a lower surface of the adhesive layer is lower than an upper surface of the source / drain structure. 32 . The method for forming a semiconductor structure according to claim 31 , wherein a lower surface of the adhesive layer is located between an upper surface and a lower surface of the source / drain structure.

33. The method for forming a semiconductor structure according to claim 29, further comprising: Before forming the contact structure to fill the opening, a pre-cleaning process is performed on the barrier layer, wherein the pre-cleaning process dopes fluorine into the barrier layer.

34. A method for forming a semiconductor structure, comprising: forming a gate structure on a fin structure; forming a source / drain structure in the fin structure, wherein the source / drain structure is adjacent to the gate structure; forming a dielectric layer on the gate structure and the source / drain structure; forming an opening in the dielectric layer to expose the source / drain structure; Depositing a barrier layer to line the sidewall surface of the opening and the upper surface of the source / drain structure; etching a portion of the barrier layer to expose the source / drain structure; performing a pre-cleaning process on the barrier layer, wherein the pre-cleaning process dopes fluorine into the barrier layer; Depositing an adhesion layer to cover the sidewall surface of the opening and the source / drain structure in the opening, wherein an extended portion of the adhesion layer directly contacts the gate structure; as well as A contact structure is formed to fill the opening in the dielectric layer.

35. The method for forming a semiconductor structure according to claim 34, wherein the barrier layer comprises silicon nitride, aluminum oxide, aluminum fluoride, aluminum oxyfluoride, silicon-doped zirconium oxide, silicon-doped hafnium oxide, hafnium oxide, zirconium oxide, silicon oxide, or a combination thereof.

36. The method for forming a semiconductor structure according to claim 34, wherein a fluorine concentration in the barrier layer is between 2 atomic % and 4 atomic %.

37. The method for forming a semiconductor structure according to claim 34, wherein a lower surface of the contact structure is lower than an upper surface of the source / drain structure.

38. The method for forming a semiconductor structure according to claim 37, wherein a lower surface of the contact structure is located between an upper surface and a lower surface of the source / drain structure.

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