Non-volatile memory cell and method of forming the same

Abstract

An embodiment of the present invention discloses a non-volatile memory cell. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer located on the substrate; a floating gate located on the first oxide layer; a second oxide layer located on the floating gate; and a control gate located at least partially on the second oxide layer. At least one of the first oxide layer and the second oxide layer contains fluorine.

Description

Technical Field

[0001] Embodiments of the present invention relate to a non-volatile memory cell and a method for forming the same. Background Art

[0002] Memory devices for storing information non-volatilely are widely used in many applications. Several examples of non-volatile semiconductor memories include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash memory.

[0003] Flash memory is a non-volatile computer storage medium that can be electrically erased and reprogrammed. Flash is a type of electrically erasable programmable read-only memory that is erased and programmed in large blocks. The cost of flash memory is much lower than byte-programmable EEPROM. Flash memory is often used in computers, phones, personal digital assistants, Global Positioning System (GPS) receivers, cameras, and various other electronic devices.

[0004] A flash memory cell is similar to a standard metal oxide semiconductor field effect transistor (MOSFET), except that the transistor has two gates: a top control gate and a floating gate below the top control gate, which is insulated on all sides by an oxide layer. The floating gate is located between the control gate and the channel and is electrically isolated by the oxide layer. Any electrons placed on the floating gate are trapped there. When the floating gate holds charge, the charge reduces the electric field from the control gate, changing the threshold voltage (V T During readout, an intermediate voltage between the possible threshold voltages is applied to the control gate, and based on the charge in the floating gate, the actual V T Depending on the current flowing through the MOSFET channel, the MOSFET channel becomes conductive or remains insulated. The current flowing through the MOSFET channel is sensed to reproduce the stored data.

[0005] A single-level flash cell in its default state is logically equivalent to a binary "1" value because current will flow through the channel under the condition that the appropriate voltage is applied to the control gate, causing the bit line voltage to be pulled low. Typically, a flash memory cell is programmed or set to a binary "0" value by applying a voltage to the floating gate transistor in the flash memory cell so that electrons are trapped in the floating gate of the transistor. Hot carrier injection (HCI) is the basis of operation of several non-volatile memory technologies, such as erasable programmable read-only memory cells and flash cells. Flash memory utilizes the principle of hot carrier injection to charge the floating gate by carefully injecting carriers across the gate oxide. This charging changes the threshold voltage to represent a binary "0" value. Typically, a flash memory cell is erased by applying a voltage to the floating gate transistor to remove any charge trapped in the floating gate of the floating gate transistor.

[0006] Hot carrier injection induces floating gate oxide trapping where fixed charge or carriers are trapped in the gate oxide. This is called hot carrier injection damage (HCI damage) and is one of the factors that limits the number of write-erase cycles. Floating gate oxide trapping can cause an increase in threshold voltage during erase and a decrease in threshold voltage during write, both of which affect the ability of the memory cell to have distinct "1" and "0" charge states. Thus, hot carrier injection damage causes cell current degradation and causes the non-volatile memory logic margin window to close over time. The number of write-erase cycles where "1" and "0" can no longer be distinguished defines the endurance of the non-volatile memory. In view of the adverse effects of hot carrier injection, there is no satisfactory method for enhancing the endurance of non-volatile memory cells. Summary of the invention

[0007] According to some embodiments of the present invention, a nonvolatile memory cell includes: a substrate; a first oxide layer located on the substrate; a floating gate located on the first oxide layer; a second oxide layer located on the floating gate; and a control gate located at least partially on the second oxide layer. At least one of the first oxide layer and the second oxide layer contains fluorine. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the size and geometry of the various features may be arbitrarily increased or reduced for clarity of discussion. Throughout the specification and in all drawings, the same reference numerals represent the same features.

[0009] Figure 1 An exemplary structure of a flash memory cell according to some embodiments of the present invention is shown in which floating gate oxide trapping occurs.

[0010] Figure 2 Exemplary threshold voltage changes of flash memory cells with increasing write / erase cycles according to some embodiments of the present invention are shown.

[0011] Figure 3 An exemplary fluorine implant in a flash memory cell according to some embodiments of the present invention is shown.

[0012] Figure 4 An endurance performance comparison between a standard flash memory cell and a fluorine-doped flash memory cell according to some embodiments of the present invention is shown.

[0013] Figure 5 An exemplary structure of a stacked gate flash memory cell according to some embodiments of the present invention is shown.

[0014] Figure 6 An exemplary structure of a split-gate flash memory cell according to some embodiments of the present invention is shown.

[0015] Figure 7 An exemplary method for fluorine implantation in a flash memory cell according to some embodiments of the present invention is shown.

[0016] Figure 8 Another exemplary method for fluorine implantation in a flash memory cell according to some embodiments of the present invention is shown.

[0017] Fig. 9 Yet another exemplary method for fluorine implantation in a flash memory cell according to some embodiments of the present invention is shown.

[0018] Fig.10 is a flow chart illustrating an exemplary method for fluorine implantation in a flash memory cell according to some embodiments of the present invention.

[0019] Fig.11 is a flow chart illustrating another exemplary method for fluorine implantation in a flash memory cell according to some embodiments of the present invention. DETAILED DESCRIPTION

[0020] The following disclosure sets forth various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and configurations are set forth below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than itself representing the relationship between the various embodiments and / or configurations discussed.

[0021] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another element or features. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless otherwise expressly stated, terms such as "attached", "affixed", "connected", and "interconnected" refer to a relationship in which structures are fastened or attached to each other directly or indirectly through intermediate structures and refer to removable or rigid attachments or relationships.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It should be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and should not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0023] Reference will now be made in detail to various embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and description to refer to the same or similar components. In the present invention, the terms "memory cell" and "cell" are used interchangeably.

[0024] Hot carrier injection (HCI) is the basis of operation of several non-volatile memory technologies, such as erasable programmable read-only memory cells and flash cells. Flash memory utilizes the principle of hot carrier injection to charge the floating gate by carefully injecting carriers across the gate oxide. Hot carrier injection induces floating gate oxide trapping where fixed charge or carriers are trapped in the gate oxide and can increase the threshold voltage, degrade the cell current, and cause the memory to have poor endurance due to the degradation of the memory's ability to have distinct "1" and "0" charge states.

[0025] The present invention is directed to improving the endurance of non-volatile memory cells (e.g., flash memory cells) by fluorine doping. The present invention provides various embodiments of non-volatile memory cells including a fluorine-doped gate oxide layer. In one embodiment, the fluorine-doped gate oxide layer is located between the floating gate and the substrate of the memory cell. In another embodiment, the fluorine-doped gate oxide layer is located between the floating gate and the control gate of the memory cell. In yet another embodiment, the memory cell has two fluorine-doped gate oxide layers, one located between the floating gate and the substrate and the other located between the floating gate and the control gate.

[0026] Fluorine doping in the gate oxide layer can reduce the fixed charge trapped in the gate oxide layer by activating the silicon-fluorine (Si-F) bond. The Si-F bond can be made to have a strong bonding strength by furnace annealing and rapid thermal annealing (RTA). Strong bonding strength can resist hot carrier injection damage and reduce floating gate oxide trapping, thereby improving the durability of the memory cell.

[0027] The present invention further provides a method for forming a non-volatile memory cell including a fluorine-doped gate oxide layer. According to various embodiments, the method may include doping fluorine ions into a first oxide layer between a floating gate and a substrate or into a second oxide layer between a floating gate and a control gate or into both oxide layers. The fluorine ions may come from any gas commercially available in the semiconductor industry, such as fluorides including: boron fluoride (BF x ), Nitrogen fluoride (NF x ) or silicon fluoride (SiF x ).

[0028] The present invention is applicable to the durability enhancement of all kinds of non-volatile memory cells (including flash memory cells, multiple time programmable (MTP) memory cells, etc.) in which hot carrier injection is used for writing and erasing. The flash memory cells can be stacked gate flash cells or split gate flash cells. As described in detail below, by fluorine doping, the current degradation and durability of the memory cells can be improved.

[0029] Figure 1 FIG. 1 shows an exemplary structure of a flash memory cell 110 according to some embodiments of the present invention, in which floating gate oxide trapping occurs. Figure 1 As shown in FIG. 1 , a flash memory cell 110 includes a drain 101 connected to a bit line, a source 102 (source line), a substrate 103 , a floating gate oxide layer 104 , a floating gate 105 , an inter-gate oxide layer 106 , and a control gate 107 .

[0030] In one embodiment, substrate 103 is a semiconductor substrate including silicon, and floating gate oxide layer 104 includes silicon dioxide. Both floating gate 105 and control gate 107 may include polysilicon. Therefore, inter-gate oxide layer 106 may be referred to as an inter-poly oxide layer. During a programming operation of flash memory cell 110, an elevated voltage is applied to control gate 107 to allow electrons to flow from source 102 to drain 101. When the source-drain current is high enough, some high-energy electrons jump from substrate 103 through floating gate oxide layer 104 onto floating gate 105. Equivalently, some high-energy carriers (i.e., hot carriers) in floating gate 105 move across floating gate oxide layer 104 to substrate 103. This induces floating gate oxide trapping where one or more fixed charges or carriers 120 are trapped in the floating gate oxide layer 104 and can increase the threshold voltage, degrade the cell current, and cause the flash memory cell 110 to have poor endurance due to the degradation of the ability of the flash memory cell 110 to have distinctly different "1" and "0" charge states.

[0031] Figure 2 2 is a graph 200 showing exemplary threshold voltage changes of a flash memory cell as write / erase cycles increase according to some embodiments of the present invention. Figure 2As shown in , due to floating gate oxide trapping, the threshold voltage during erase increases with increasing write / erase cycles; and the threshold voltage during programming decreases with increasing write / erase cycles. This will cause the logic margin window of the flash memory cell to close over time.

[0032] Figure 3 FIG. 3 shows an exemplary fluorine implant in a flash memory cell 300 according to some embodiments of the present invention. Figure 3 As shown in FIG. 1 , a flash memory cell 300 includes a p-type substrate 303, a gate oxide layer 304 located on the p-type substrate 303, and a polysilicon floating gate 305 located on the gate oxide layer 304. Fluorine ions 310 may be implanted into the gate oxide layer 304 to form dangling bonds with Si surface charges trapped in the gate oxide layer 304. In one embodiment, the fluorine ions 310 may be implanted immediately after the polysilicon floating gate 305 is formed. By furnace annealing or rapid thermal annealing, Si-F bonds may be activated to neutralize the charges trapped in the gate oxide layer 304. This will improve the endurance of the flash memory cell 300 by avoiding or delaying the closing of the logic margin window of the flash memory cell 300.

[0033] Figure 4 FIG. 4 is a graph 400 showing an endurance performance comparison between a standard flash memory cell and a fluorine-doped flash memory cell according to some embodiments of the present invention. Figure 4 As shown in FIG. 4 , the fluorine-doped flash memory cells 410 , 420 have better endurance due to a smaller threshold voltage shift under a given stress time compared to a standard flash memory cell 430 without fluorine implantation. 15 cm -2 ) has a higher fluorine doping density than that of (2×10 13 cm -2 )The lower fluorine-doped flash memory cell 420 has even better endurance.

[0034] Figure 5 FIG. 5 shows an exemplary structure of a stacked gate flash memory cell 500 according to some embodiments of the present invention. Figure 5As shown in , the stacked gate flash memory cell 500 in this example includes a drain 501, a source 502, a substrate 503, a floating gate oxide layer 504, a floating gate 505, an inter-gate oxide layer 506, and a control gate 507. The floating gate oxide layer 504 is formed over the substrate 503; and the floating gate 505 is formed over the floating gate oxide layer 504. The control gate 507 is formed over the floating gate 505, and the floating gate 505 is insulated from the control gate 507 on all sides by the inter-gate oxide layer 506. The floating gate 505 and the control gate 507 may include polysilicon, so that the inter-gate oxide layer 506 may be referred to as an inter-poly oxide layer.

[0035] In this example, at least one of the floating gate oxide layer 504 and the inter-gate oxide layer 506 includes fluoride ions to reduce gate oxide trapping. The fluoride ions can come from any gas commercially available in the semiconductor industry or from any fluoride including: BF x NF x or SiF x .

[0036] In one embodiment, the stacked gate flash memory cell 500 further includes an oxide-nitride-oxide (ONO) layer (not shown) located on the floating gate 505. The oxide-nitride-oxide layer includes two oxide layers and a nitride layer located between the two oxide layers. The oxide-nitride-oxide layer can be formed above or below the inter-gate oxide layer 506. In another embodiment, the stacked gate flash memory cell 500 can further include a select gate 508 located above the floating gate oxide layer 504.

[0037] Figure 6 FIG. 6 shows an exemplary structure of a split-gate flash memory cell 600 according to some embodiments of the present invention. Figure 6 As shown in FIG. 6 , the split gate flash memory cell 600 in this example includes two drains 601, a source line 602, a substrate 603, a floating gate oxide layer 604, two floating gates 605, an inter-gate oxide layer 606, and two control gates 607. The floating gate oxide layer 604 is formed on the substrate 603; and the two floating gates 605 are formed on the floating gate oxide layer 604. The source line 602 is a common source diffusion region in the substrate between the two floating gates 605.

[0038] The two control gates 607 may serve as coupling gates and are formed at least partially over the two floating gates 605. The two floating gates 605 are insulated from the two control gates 607 on all sides by an inter-gate oxide layer 606. The two floating gates 605 and the two control gates 607 may include polysilicon, so that the inter-gate oxide layer 606 may be referred to as an inter-poly oxide layer.

[0039] The two drains 601 are a pair of drain diffusion regions in the substrate 603. A pair of word lines can be connected to the two control gates 607 and are located over a region of the substrate 603 between the drains 601. The split-gate flash memory cell 600 can also include an isolation layer 608 located between the two floating gates 605 and the inter-gate oxide layer 606. In one embodiment, the isolation layer 608 includes two oxide layers and a nitride layer located between the two oxide layers.

[0040] In this example, at least one of the floating gate oxide layer 604 and the inter-gate oxide layer 606 includes fluoride ions to reduce gate oxide trapping. The fluoride ions can come from any gas commercially available in the semiconductor industry or from any fluoride including: BF x NF x or SiF x .

[0041] Figure 7 An exemplary method for performing fluorine implantation during fabrication of a flash memory cell 710 according to some embodiments of the present invention is shown. Figure 7 As shown in FIG. 7 , the manufactured flash memory cell 710 includes an active region 713, an isolation region 711 around the active region 713, a floating gate oxide layer 714 located above the active region 713, a floating gate 715 deposited on the isolation region 711 and the floating gate oxide layer 714, and one or more ion masks 719 formed on the floating gate 715. The ion mask 719 is formed on the floating gate 715 to create a masking pattern for ion implantation. After the floating gate 715 is deposited and the ion mask 719 is formed, fluorine ions 716 are doped or implanted into the floating gate oxide layer 714 to reduce floating gate oxide trapping and improve the durability of the flash memory cell 710. By performing energy control during ion implantation, the fluorine ions 716 can be doped and implanted into the floating gate oxide layer 714 at an appropriate rate.

[0042] Figure 7Also shown is a detailed view 720 of a flash memory cell 710 after fluorine ions 716 are doped. The active region 713 may include a drain 721, a source line 722, and a substrate 723. The fluorine ions 716 are doped into a floating gate oxide layer 724 between the substrate 723 and the floating gate 725. An ion mask 729 may help block ions at the isolation region and focus the ion implantation on the floating gate oxide layer 724. Figure 7 As shown in , the ion implantation in this example is performed before the control gate or word line is formed. After the word line is formed, some of the implanted fluorine ions 716' will be located between the substrate 723 and the word line. In one embodiment, an annealing process is performed to activate the silicon-fluorine bonds in the floating gate oxide layer 724 based on at least one of the following: furnace annealing and rapid thermal annealing. The fluorine ions 716 can come from any gas commercially available in the semiconductor industry or from any fluoride including the following: BF x NF x or SiF x In one embodiment, pure fluorine ions are implanted into the floating gate oxide layer 724 rather than fluoride.

[0043] Figure 8 Another exemplary method for performing fluorine implantation during fabrication of a flash memory cell 810 according to some embodiments of the present invention is shown. Figure 8 As shown in FIG. 8 , the manufactured flash memory cell 810 includes an active region 813, a floating gate oxide layer 814 located above the active region 813, a floating gate 815 deposited on the floating gate oxide layer 814, an inter-gate oxide layer 816 formed on and around the floating gate 815, and a control gate 817 deposited on the inter-gate oxide layer 816, and one or more ion masks 819 formed above the control gate 817. The ion mask 819 is formed above the control gate 817 to create a masking pattern for ion implantation. After the control gate 817 is deposited and the ion mask 819 is formed, fluorine ions 818 are doped or implanted into the inter-gate oxide layer 816 to reduce floating gate oxide trapping and improve the durability of the flash memory cell 810. By performing energy control during ion implantation, the fluorine ions 818 can be doped and implanted into the inter-gate oxide layer 816 at an appropriate rate.

[0044] Figure 8 Also shown is a detailed view 820 of a flash memory cell 810 after fluorine ions 818 are doped. The active region 813 may include a drain 821, a source line 822, and a substrate 823. The fluorine ions 818 are doped into an inter-gate oxide layer 826. An ion mask 829 may help block ions at the isolation region and focus the ion implantation on the inter-gate oxide layer 826. Figure 8As shown in , the ion implantation in this example is performed after the control gate and / or word line are formed.

[0045] The inter-gate oxide layer 826 has an overlap region with the floating gate oxide layer 824 around the floating gate 825. The overlap region is located between the substrate 823 and the control gate 827. After ion implantation, while some of the implanted fluorine ions 818 are doped into the region between the floating gate 825 and the control gate 827, other implanted fluorine ions 818′ are doped into the overlap region between the substrate 823 and the control gate 827 or into the sidewall region of the floating gate 825. Therefore, fluorine doping into the inter-gate oxide layer 826 can also reduce floating gate oxide trapping and improve the endurance of the flash memory cell 810.

[0046] In one embodiment, both the floating gate 825 and the control gate 827 include polysilicon. In one embodiment, an annealing process is performed to activate silicon-fluorine bonds in the inter-gate oxide layer 826 based on at least one of the following: furnace annealing and rapid thermal annealing. The fluorine ions 818 can come from any commercially available gas in the semiconductor industry or from any fluoride including: BF x NF x or SiF x In one embodiment, pure fluorine ions are implanted into the inter-gate oxide layer 826 rather than fluoride.

[0047] Fig. 9 Still another exemplary method for performing fluorine implantation during fabrication of a flash memory cell 910 according to some embodiments of the present invention is shown. Fig. 9 As shown in FIG. 1 , fluorine ions are implanted into the fabricated flash memory cell 910 twice, once as shown in FIG. Figure 7 After the floating gate is deposited and another time as Figure 8 After the control gate is deposited. Fig. 9 A detailed view 920 of the flash memory cell 910 is shown after the fluorine ions 716, 818 have been doped. Figure 8 The flash memory cell 810 shown, the active region of the flash memory cell 910 may include a drain 821, a source line 822, and a substrate 823. Before forming a control gate 827 (word line), fluorine ions 716 are doped into the floating gate oxide layer 824 according to a masking pattern generated by an ion mask 729. After forming the control gate 827 (word line), fluorine ions 818 are doped into the inter-gate oxide layer 826 according to a masking pattern generated by an ion mask 829.

[0048] By performing energy control during ion implantation, each of the two groups of fluorine ions 716, 818 is doped at an appropriate rate and implanted into the floating gate oxide layer 824 and the inter-gate oxide layer 826. The inter-gate oxide layer 826 has an overlapping region with the floating gate oxide layer 824 around the floating gate 825. The overlapping region is located between the substrate 823 and the control gate 827. While some of the implanted fluorine ions 818 are doped into the region between the floating gate 825 and the control gate 827, other implanted fluorine ions 818' are doped into the overlapping region between the substrate 823 and the control gate 827 or into the sidewall region of the floating gate 825. Therefore, fluorine doping into the floating gate oxide layer 824 and the inter-gate oxide layer 826 can reduce floating gate oxide trapping and improve the durability of the flash memory cell 910.

[0049] In one embodiment, an annealing process is performed to activate silicon-fluorine bonds in the floating gate oxide layer 824 and the inter-gate oxide layer 826 based on at least one of the following: furnace annealing and rapid thermal annealing. The fluorine ions 716, 818 can come from any commercially available gas in the semiconductor industry or from any fluoride including: BF x NF x or SiF x In one embodiment, pure fluorine ions are implanted into the floating gate oxide layer 824 and the inter-gate oxide layer 826 instead of fluoride.

[0050] In one embodiment, by fluorine doping in a flash memory cell, the flash cell current degradation is improved by about 22% from 6.1 μA degradation to 4.8 μA degradation in a 1K cycle test. Therefore, the predicted endurance for the flash memory cell is increased from 20K cycles to 50K cycles. In some embodiments, during ion implantation, fluorine ions may be replaced by deuterium (D) ions to form Si-D bonds in the gate oxide layer, thereby reducing hot carrier damage and enhancing the endurance of the flash memory cell.

[0051] Fig.10 1 is a flow chart illustrating an exemplary method 1000 for fluorine implantation in a flash memory cell according to some embodiments of the present invention. At operation 1002, a semiconductor substrate is formed. At operation 1004, a first oxide layer is formed over the substrate. At operation 1006, a floating gate is formed over the first oxide layer. At operation 1008, fluorine ions are doped into the first oxide layer. At operation 1010, a second oxide layer is formed over the floating gate. At operation 1012, a control gate is formed at least partially over the second oxide layer.

[0052] Fig.111 is a flow chart illustrating another exemplary method 1100 for fluorine implantation in a flash memory cell according to some embodiments of the present invention. At operation 1102, a semiconductor substrate is formed. At operation 1104, a first oxide layer is formed over the substrate. At operation 1106, a floating gate is formed over the first oxide layer. At operation 1108, a second oxide layer is formed over the floating gate. At operation 1110, a control gate is formed at least partially over the second oxide layer. At operation 1112, fluorine ions are doped into the second oxide layer. It should be understood that the method may vary according to different embodiments of the present invention. Fig.10 and Fig.11 The order of the steps shown in each.

[0053] In one embodiment, a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes: a substrate; a first oxide layer located on the substrate; a floating gate located on the first oxide layer; a second oxide layer located on the floating gate; and a control gate located at least partially on the second oxide layer. At least one of the first oxide layer and the second oxide layer contains fluorine.

[0054] In the nonvolatile memory cell, at least one of the floating gate and the control gate includes polysilicon.

[0055] The nonvolatile memory cell further includes an oxide-nitride-oxide layer on the floating gate, wherein the oxide-nitride-oxide layer includes two oxide layers and a nitride layer between the two oxide layers.

[0056] In the nonvolatile memory cell, the oxide-nitride-oxide layer is located above the second oxide layer.

[0057] In the nonvolatile memory cell, the oxide-nitride-oxide layer is located below the second oxide layer.

[0058] The nonvolatile memory cell further includes: an additional floating gate located on the first oxide layer; and a common source diffusion region located in the substrate between the floating gate and the additional floating gate.

[0059] In the nonvolatile memory cell, at least one of the first oxide layer and the second oxide layer includes at least one of the following fluorides: boron fluoride, nitrogen fluoride, and silicon fluoride.

[0060] In another embodiment, a method for forming a nonvolatile memory cell is disclosed. The method includes: forming a substrate; forming a first oxide layer over the substrate; forming a floating gate over the first oxide layer; doping fluorine ions into the first oxide layer; forming a second oxide layer over the floating gate; and forming a control gate at least partially over the second oxide layer.

[0061] In the method, the fluorine ions are doped into the first oxide layer through the floating gate by ion implantation.

[0062] In the method, doping the fluorine ions further includes: forming a first ion mask over the floating gate to create a masking pattern for the ion implantation.

[0063] In the method, after forming the control gate, the method further includes doping additional fluorine ions into the second oxide layer.

[0064] In the method, the additional fluorine ions are doped into the second oxide layer through the control gate by ion implantation.

[0065] In the method, doping the additional fluorine ions further includes forming a second ion mask over the control gate to create a masking pattern for the ion implantation.

[0066] In the method, at least one of the floating gate and the control gate comprises polysilicon.

[0067] The method further includes forming an oxide-nitride-oxide layer on the floating gate, wherein the oxide-nitride-oxide layer includes two oxide layers and a nitride layer located between the two oxide layers.

[0068] In the method, further comprising: forming an additional floating gate over the first oxide layer; and forming a common source diffusion region in the substrate between the floating gate and the additional floating gate.

[0069] In the method, doping the fluorine ions includes doping at least one of the following fluorides: boron fluoride, nitrogen fluoride, and silicon fluoride.

[0070] In the method, further comprising performing an annealing process to activate silicon-fluorine bonds in the first oxide layer based on at least one of the following: furnace annealing and rapid thermal annealing.

[0071] In yet another embodiment, a method for forming a nonvolatile memory cell is disclosed. The method includes: forming a substrate; forming a first oxide layer over the substrate; forming a floating gate over the first oxide layer; forming a second oxide layer over the floating gate; forming a control gate at least partially over the second oxide layer; and doping fluorine ions into the second oxide layer.

[0072] In the nonvolatile memory cell, the fluorine ions are doped into the second oxide layer through the control gate by ion implantation.

[0073] The above content summarizes the features of several embodiments so that those of ordinary skill in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures to implement the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications to this article without departing from the spirit and scope of the present invention.

Claims

1. A non-volatile memory cell, characterized in that: include: substrate; A first oxide layer, located on the substrate; A floating gate, located on the first oxide layer; a second oxide layer located on the floating gate; as well as a control gate at least partially located on the second oxide layer, wherein the second oxide layer contains fluorine ions, and the fluorine ions are doped into the second oxide layer through the control gate, The first portion of the control gate laterally extends beyond the sidewall of the second oxide layer and extends onto the substrate, and the fluorine ions are doped into an overlapping region between the first portion of the control gate and the substrate.

2. The nonvolatile memory cell according to claim 1, wherein: At least one of the floating gate and the control gate includes polysilicon.

3. The nonvolatile memory cell according to claim 1, wherein: The invention further comprises an oxide-nitride-oxide layer located on the floating gate, wherein the oxide-nitride-oxide layer comprises two oxide layers and a nitride layer located between the two oxide layers.

4. The non-volatile memory cell according to claim 3, characterized in that: The oxide-nitride-oxide layer is located over the second oxide layer.

5. The non-volatile memory cell according to claim 3, wherein: The oxide-nitride-oxide layer is located below the second oxide layer.

6. The nonvolatile memory cell according to claim 1, wherein: Further including: an additional floating gate disposed above the first oxide layer; as well as A common source diffusion region is located in the substrate between the floating gate and the additional floating gate.

7. The nonvolatile memory cell according to claim 1, wherein: The second oxide layer includes at least one of the following fluorides: boron fluoride, nitrogen fluoride, and silicon fluoride.

8. A method for forming a non-volatile memory cell, characterized in that: include: forming a substrate; forming a first oxide layer on the substrate; forming a floating gate on the first oxide layer; doping fluoride ions into the first oxide layer; forming a second oxide layer over the floating gate; forming a control gate; as well as After forming the control gate, additional fluorine ions are doped into the second oxide layer, The first portion of the control gate laterally extends beyond the sidewall of the second oxide layer and extends onto the substrate, and the additional fluorine ions are doped into an overlapping region between the first portion of the control gate and the substrate.

9. The method for forming a non-volatile memory cell according to claim 8, wherein: The fluorine ions are doped into the first oxide layer through the floating gate by ion implantation.

10. The method for forming a non-volatile memory cell according to claim 9, wherein: Doping the fluorine ions into the first oxide layer further comprises: A first ion mask is formed over the floating gate to create a masking pattern for the ion implantation.

11. The method for forming a non-volatile memory cell according to claim 8, wherein: The control gate is at least partially formed over the second oxide layer.

12. The method for forming a non-volatile memory cell according to claim 11, wherein: The additional fluorine ions are doped into the second oxide layer through the control gate by ion implantation.

13. The method for forming a non-volatile memory cell according to claim 12, wherein: Doping the additional fluorine ions into the second oxide layer further comprises: A second ion mask is formed over the control gate to create a masking pattern for the ion implantation.

14. The method for forming a non-volatile memory cell according to claim 11, wherein: At least one of the floating gate and the control gate includes polysilicon.

15. The method for forming a non-volatile memory cell according to claim 8, wherein: The method further includes forming an oxide-nitride-oxide layer on the floating gate, wherein the oxide-nitride-oxide layer includes two oxide layers and a nitride layer located between the two oxide layers.

16. The method for forming a non-volatile memory cell according to claim 8, wherein: Further including: forming an additional floating gate over the first oxide layer; as well as A common source diffusion region is formed in the substrate between the floating gate and the additional floating gate.

17. The method for forming a non-volatile memory cell according to claim 8, wherein: Doping the fluorine ions includes doping at least one of the following fluorides: boron fluoride, nitrogen fluoride, and silicon fluoride.

18. The method for forming a non-volatile memory cell according to claim 8, wherein: The method further includes performing an annealing process based on at least one of the following to activate silicon-fluorine bonds in the first oxide layer: furnace annealing and rapid thermal annealing.

19. A method for forming a non-volatile memory cell, characterized in that: include: forming a substrate; forming a first oxide layer on the substrate; forming a floating gate on the first oxide layer; forming a second oxide layer over the floating gate; forming a control gate at least partially over the second oxide layer; as well as doping fluorine ions into the second oxide layer through the control gate, The first portion of the control gate laterally extends beyond the sidewall of the second oxide layer and extends onto the substrate, and the fluorine ions are doped into an overlapping region between the first portion of the control gate and the substrate.

20. The method for forming a non-volatile memory cell according to claim 19, wherein: The fluorine ions are doped into the second oxide layer through the control gate by ion implantation.

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