Storage system, power management device, and power management method

Abstract

The present invention provides a power management device. A power management device includes a secondary power device, the secondary power device includes at least one capacitor. The power management device includes a charging circuit, the charging circuit includes a direct current (DC)-to-DC converter and is configured to supply power to the secondary power device. In addition, the power management device includes a measuring circuit, the measuring circuit is configured to measure the switching distribution of the DC-to-DC converter, and determine the state of the secondary power device by comparing at least one time period of the switching distribution with a reference time. The present invention also provides a related storage system and a power management method.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims the benefit of Korean Patent Application No. 10-2017-0161005 filed on November 28, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a power supply device, and more particularly, to a secondary power supply device that secondarily supplies power and a storage system including the secondary power supply device. Background Art

[0004] Generally speaking, a storage system including a storage device and a storage controller operates by receiving power from an external source. In this regard, a sudden power off (SPO) situation may occur in which a power source (e.g., a main / primary power source) is suddenly terminated while the storage system is running. In this case, since the storage controller may utilize a volatile memory to store data, the data stored in the volatile memory may be at risk of being lost and / or the storage device may be at risk of failing to complete an operation of the storage device (e.g., an erase operation, a write operation, etc.). Therefore, in response to a sudden power off situation, the storage system may utilize a secondary power supply device to attempt to complete an ongoing operation, and / or may perform an operation to back up the data. In addition, it may be desirable to verify the health of the secondary power supply device to ensure that the secondary power supply device is able to provide sufficient power. Summary of the invention

[0005] The inventive concept may provide a monitoring device and a method for monitoring a secondary power device, and a storage system including the monitoring device so as to efficiently monitor the status of the secondary power device.

[0006] According to some embodiments of the inventive concept, a power management device is provided. The power management device may include a secondary power device, the secondary power device including at least one capacitor. The power management device may include a charging circuit, the charging circuit including a direct current (DC)-to-DC converter and configured to supply power to the secondary power device. In addition, the power management device may include a measurement circuit, the measurement circuit configured to measure a switching profile of the DC-to-DC converter, and determine a state of the secondary power device by comparing at least one time period of the switching profile with a reference time.

[0007] According to some embodiments of the inventive concept, a power management device may include a secondary power device, the secondary power device including a plurality of capacitors connected in parallel. The power management device may include a direct current (DC)-to-DC converter, the DC-to-DC converter including a field effect transistor (FET) as a switching device and configured to supply power to the secondary power device. The power management device may include a measurement circuit configured to measure a switching profile of the DC-to-DC converter and determine a state of the secondary power device by comparing at least one time period of the switching profile with a reference time. In addition, the power management device may include a control circuit configured to control the DC-to-DC converter.

[0008] According to some embodiments of the inventive concept, a storage system may include: a power loss protection (PLP) system, including a secondary power supply device and a direct current (DC)-to-DC converter, the secondary power supply device including a plurality of capacitors connected in parallel, the DC-to-DC converter being configured to supply power to the secondary power supply device. The storage system may include a main system, the main system including a control circuit and at least one memory chip. In addition, the storage system may include a power supply circuit, the power supply circuit being located between the power loss protection system and the main system and being configured to supply power to the main system. One of the power loss protection system or the main system may include a measurement circuit, the measurement circuit monitoring the secondary power supply device based on a switching distribution of the DC-to-DC converter.

[0009] According to some embodiments of the inventive concept, a method for power management of a secondary power supply device may include charging the secondary power supply device by supplying power to the secondary power supply device via a direct current (DC)-to-DC converter. The method may include measuring a switching profile of the DC-to-DC converter. In addition, the method may include determining a state of the secondary power supply device by comparing at least one time period of the switching profile with a reference time. Through the determination, the state of the secondary power supply device may be monitored in real time without discharging all of the plurality of capacitors or changing an operation mode of a storage system that is a power supply target of the secondary power supply device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the inventive concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a structure of a monitoring apparatus configured to monitor a secondary power supply device according to some embodiments.

[0012] Figure 2A and Figure 2B is a diagram showing some embodiments of the present invention. Figure 1 Circuit diagram of a direct current (DC)-to-DC converter of a charging circuit in the monitoring device shown.

[0013] Figure 3A and Figure 3B is a diagram showing some embodiments of the present invention. Figure 1 Circuit diagram showing the structure of the secondary power supply device in the monitoring device.

[0014] Figure 4A and Figure 4B It is further shown that according to some embodiments Figure 1 A block diagram of a measuring device of the measuring circuit in the monitoring device is shown.

[0015] Figure 5A A graph showing a voltage distribution of a secondary power supply device and an on-off distribution of a field effect transistor (FET) when the state of the secondary power supply device is normal.

[0016] FIG. 5B to FIG. 5D Graphs showing voltage distribution of a secondary power supply device and on-off distribution of a field effect transistor when the state of the secondary power supply device is abnormal.

[0017] Fig. 6A and Figure 6B is a block diagram showing the structure of a monitoring device according to some embodiments.

[0018] Figure 7 is a block diagram showing the structure of a storage system including a monitoring device according to some embodiments.

[0019] Fig. 8A and Figure 8B It is shown Figure 7 Diagram of the power supply process in the storage system shown.

[0020] Fig. 9 is a flow chart of a method of monitoring a secondary power device according to some embodiments.

[0021] Fig.10 and Fig.11 yes Fig. 9 Detailed flow chart of the method for measuring the switching profile and determining the status of the secondary power supply device.

[0022] [Explanation of Symbols]

[0023] 100: charging circuit;

[0024] 100a, 100b: buck converter / DC-DC converter;

[0025] 101: Power supply;

[0026] 110: switch;

[0027] 110a: switch / first switch / field effect transistor;

[0028] 110b: switch / second switch;

[0029] 1110, 1120, 1122, 1124, 1126, 1127, 1130, 1131, 1131a, 1132, 1133, 1134, 1136: blocks;

[0030] 120: Inductor;

[0031] 130: diode;

[0032] 140, 210: capacitors;

[0033] 200, 200a, 200b: secondary power supply device;

[0034] 300: measurement circuit;

[0035] 310, 310a: measuring device;

[0036] 312: voltage detector;

[0037] 314: timer;

[0038] 314a: tick counter;

[0039] 330: determiner;

[0040] 400, 400a: control circuit;

[0041] 500: event generating circuit;

[0042] 1000: Monitoring device / monitoring system / device / system;

[0043] 1000a: monitoring device;

[0044] 1500: Anti-power-off integrated circuit / anti-power-off system / anti-power-off block;

[0045] 2000: Main system integrated circuit / main system block;

[0046] 2000a: Main system integrated circuit;

[0047] 2100: a first memory chip;

[0048] 2200: a second memory chip;

[0049] 2500: Power block;

[0050] 10000: storage system;

[0051] A: Marking / second voltage;

[0052] B: Marking / first voltage;

[0053] C: third voltage;

[0054] Ext: external power supply;

[0055] PWM_A, PWM_B: pulse width modulation signal;

[0056] Rn: reference number;

[0057] Tn: number of ticks / number of tick counts;

[0058] Vc: voltage;

[0059] Vo: output voltage;

[0060] △T: time;

[0061] △Toff-O1: first open circuit off time;

[0062] △Toff-O2: Second open circuit off time;

[0063] △Toff-R: Turn-off reference time / reference time;

[0064] △Toff-S: short circuit off time;

[0065] △Ton-R: connection reference time / reference time;

[0066] △TR: reference time. DETAILED DESCRIPTION

[0067] Hereinafter, the inventive concept will be described in detail by explaining embodiments of the inventive concept with reference to the accompanying drawings. The same reference numerals in the accompanying drawings denote the same elements, and repeated explanation of the same elements may be omitted.

[0068] Figure 1 is a block diagram illustrating a structure of a monitoring apparatus 1000 configured to monitor a secondary power supply device 200 according to some embodiments.

[0069] Reference Figure 1According to some embodiments, a monitoring device (or monitoring system) 1000 may include a charging circuit 100, a secondary power device 200, a measurement circuit 300, and a control ("CTRL") circuit 400. Although the term "monitoring" is used herein to describe an example of the device / system 1000, the device / system 1000 is not limited thereto, but may also be a "power management" device / system, a "power control" device / system, or a "backup power" device / system.

[0070] The charging circuit 100 includes a direct current (DC)-to-DC converter and can supply power to the secondary power supply device 200. In more detail, as shown in the figure, the secondary power supply device 200 may have a structure in which at least two capacitors 210 are connected in parallel. The charging circuit 100 can charge the capacitor 210 by supplying power to the secondary power supply device 200. When the charge is stored in the capacitor 210 due to the charging by the charging circuit 100 and thus the voltage of the capacitor 210 reaches a set (e.g., predetermined) second voltage, the charging by the charging circuit 100 is stopped. When the charging is stopped, self-discharge that reduces the charge in the capacitor 210 occurs, so that the voltage of the capacitor 210 gradually decreases. When the voltage of the capacitor 210 gradually decreases and then reaches a set (e.g., predetermined) first voltage, the charging operation of the charging circuit 100 is resumed and the capacitor 210 of the secondary power supply device 200 can be charged again.

[0071] When the state of the secondary power supply device 200 is normal, the charging operation of the charging circuit 100 can be repeatedly performed at regular intervals. However, when the state of the secondary power supply device 200 is abnormal (for example, when a short circuit defect or an open circuit defect has occurred in some of the capacitors 210 of the secondary power supply device 200), the charging operation of the charging circuit 100 may become different compared to the charging operation when the state of the secondary power supply device 200 is normal. Therefore, the state of the secondary power supply device 200 can be determined by measuring and analyzing the charging operation of the charging circuit 100. The charging operation of the charging circuit 100 can be represented as a switching distribution of a DC-DC converter. Therefore, the state of the secondary power supply device 200 can be determined by measuring and analyzing the switching distribution of the DC-DC converter. The detailed structure of the charging circuit 100 will be referred to. Figure 2A and Figure 2B The switching profile of the DC-DC converter will be measured and analyzed with reference to FIG. 5A to FIG. 5D To elaborate.

[0072] As described above, the secondary power supply device 200 may include at least two capacitors 210 connected in parallel. However, the structure of the secondary power supply device 200 is not limited thereto. For example, in some embodiments, the reference Figure 3A and Figure 3B The structure of the secondary power supply device 200 is described in detail. As shown in the figure, the secondary power supply device 200 may include only the capacitor 210 and may not include a separate load. Therefore, when a defect occurs in one of the capacitors 210, a ripple change in the voltage of each capacitor 210 (hereinafter referred to as the capacitor 210) due to the load may not occur.

[0073] The capacitor 210 may be classified into an electrolytic capacitor, a film capacitor, a tantalum capacitor, a ceramic capacitor, etc. based on a dielectric material.

[0074] An electrolytic capacitor may include a thin oxide film as a dielectric and aluminum as an electrode, and is thus referred to as an aluminum (Al) capacitor. An electrolytic capacitor has good low frequency characteristics and may be implemented with a high capacitance of tens of thousands of microfarads (μF). A tantalum capacitor may have an electrode formed of tantalum (Ta) and may have excellent temperature and frequency characteristics compared to those of an electrolytic capacitor.

[0075] The film capacitor may have a structure in which a film dielectric (for example, polypropylene, polystyrol / polystyrene, or Teflon) is stacked between electrodes formed of Al or copper. The capacity and use of the film capacitor may vary based on the material and manufacturing process. The capacitor may be a relatively inexpensive film capacitor, which may be made by inserting a polyester film into a metal and then winding the polyester film and the metal into a cylindrical shape, and may be mainly used in high-frequency circuits, oscillation circuits, and the like.

[0076] Ceramic capacitors may include a high dielectric constant material (e.g., titanium-barium) as a dielectric. Ceramic capacitors have good high frequency characteristics and may be configured to pass noise to ground. A multilayer ceramic capacitor (MLCC), which is a type of ceramic capacitor, may include a multilayer high dielectric constant ceramic structure as a dielectric between electrodes. Since multilayer ceramic capacitors have excellent temperature and frequency characteristics and are small, multilayer ceramic capacitors may be mainly used as by-pass.

[0077] In the monitoring device 1000, the capacitor 210 included in the secondary power device 200 may be implemented as a tantalum capacitor, an Al capacitor, or a multilayer ceramic capacitor having a low equivalent series resistance (ESR). However, the material of the capacitor 210 of the secondary power device 200 is not limited to the above materials.

[0078] When a sudden power outage (SPO) occurs in which power supply from an external source to an electronic system (e.g., a storage system) as a power supply target is suspended, the secondary power supply device 200 can enable the storage system to complete ongoing operations and perform data backup operations by supplying energy stored in the secondary power supply device 200 as power to the storage system. However, in a case in which a defect occurs in the secondary power supply device 200, the secondary power supply device 200 may not be able to supply sufficient / appropriate power to the storage system in the sudden power outage, so that serious data loss may occur in the storage system. Therefore, in order to suppress / prevent data loss in the storage system in the sudden power outage, it may be beneficial to periodically or in real time monitor the secondary power supply device 200 and check the status of the secondary power supply device 200, and in the case of detecting a defect, it may be beneficial to repair or replace the secondary power supply device 200.

[0079] The measuring circuit 300 can determine the state of the secondary power device 200 by measuring and analyzing the charging operation of the charging circuit 100. For example, the charging operation of the charging circuit 100 can be represented as a switching distribution of a DC-DC converter, and the measuring circuit 300 can determine the state of the secondary power device 200 by measuring and analyzing the switching distribution of the DC-DC converter. The measuring circuit 300 may include a measurer ("Mea.") 310 and a determiner ("Det.") 330. The measurer 310 can measure the switching distribution of the DC-DC converter. The determiner 330 can determine the state of the secondary power device 200 by analyzing the measured switching distribution of the DC-DC converter. The configuration of the measurer 310 will refer to Figure 4A and Figure 4B Detailed description will be given below, and the operation of the determiner 330 will be referred to FIG. 5A to FIG. 5D To elaborate.

[0080] The control circuit 400 may control the charging circuit 100 based on the result received from the determiner 330. In this regard, the control of the charging circuit 100 may indicate that when a defect occurs in the secondary power device 200, the charging condition of the charging circuit 100 may be changed to maintain the state of the secondary power device 200 to a state close to a normal state. In addition, when a defect occurs in the secondary power device 200, the control circuit 400 may change the memory write operation mode of the electronic system (e.g., the storage system) as the power supply target, so that data can be stored in the main memory in real time. For example, in the monitoring device 1000, when a defect occurs in the secondary power device 200, the control circuit 400 may change the write-back (write-behind) mode of the storage system to the direct write mode.

[0081] In this regard, the memory write operation mode may include a write-back mode and a write-through mode. In the write-back mode, data is first written to the cache, and the data stored in the cache is written to the main memory only when the data is needed. Therefore, the write-back mode may indicate a mode in which data is recorded in a background operation using the CPU wait state time of the central processing unit (CPU). The write-through mode may indicate a mode in which the cache and the main memory simultaneously perform data write operations in parallel, and the data write operation is performed immediately rather than in idle time. In the write-through mode, when a data read operation is requested to be performed on the cache during a data write operation on the cache, the data write operation is performed simultaneously with the data read operation. On the other hand, in the write-back mode, when a data read operation is requested during a data write operation, the data write operation is stopped and resumed after the data read operation ends.

[0082] When the state of the secondary power supply device 200 is normal, the write-back mode, which may be excellent in efficiency, can generally be used. However, when the secondary power supply device 200 is abnormal during the write-back mode, data loss may occur. Therefore, the control circuit 400 can reduce / minimize data loss by changing the memory write mode from the write-back mode to the direct write mode.

[0083] In addition, when a defect occurs in the secondary power supply device 200 , the control circuit 400 may notify the user of the defect by generating an alarm signal, thereby facilitating / promoting the user to repair or replace the secondary power supply device 200 .

[0084] The monitoring device 1000 according to some embodiments may monitor the state of the secondary power device 200 in real time by measuring and analyzing the charging operation of the charging circuit 100 in real time by the measuring circuit 300. In this regard, the charging operation of the charging circuit 100 may be represented as a switching profile of a DC-DC converter, and the measuring circuit 300 may measure the switching profile of the DC-DC converter.

[0085] The monitoring device 1000 according to some embodiments may monitor the state of the secondary power supply device 200 based on the charging operation of the charging circuit 100 that is naturally performed. Therefore, the monitoring device 1000 may not perform a forced discharge (e.g., irregular discharge) operation on the capacitor 210 (e.g., all capacitors 210) of the secondary power supply device 200. Therefore, the storage system that is the power supply target of the secondary power supply device 200 may be stably maintained unchanged. For example, in the case where a forced discharge operation is performed on the capacitor 210 to monitor the state of the secondary power supply device 200, if a sudden power failure occurs during the forced discharge operation, data loss may not be prevented.

[0086] In this regard, the memory write operation mode may be changed by taking into account the sudden power failure that occurs during the forced discharge operation. However, since the memory write operation mode is changed in advance regardless of the state of the secondary power supply device 200, the operation efficiency of the storage system may be deteriorated. However, the monitoring device 1000 according to some embodiments does not need to perform a forced discharge operation on the capacitor 210. Therefore, it is not necessary to change the memory write operation mode during the monitoring operation of the secondary power supply device 200, thereby suppressing / preventing the degradation of the operation efficiency of the storage system.

[0087] Figure 2A and Figure 2B It is shown Figure 1 A circuit diagram of a DC-DC converter of a charging circuit 100 in a monitoring device 1000 is shown. Figure 2A shows a simplified structure / representation of a buck converter, and Figure 2B The actual / detailed structure of the buck converter is shown in FIG. Figure 1 To provide explanation (i.e., to mention / elaborate Figure 1 components shown).

[0088] Reference Figure 2A and Figure 2B In the monitoring device 1000 according to some embodiments, the charging circuit 100 may be formed as a DC-DC converter. However, the charging circuit 100 is not limited to a DC-DC converter. For example, a buffer circuit including a switching device may be used as the charging circuit 100.

[0089] DC-DC converters can be generally classified as either boost converters or buck converters, and in this regard, a boost converter is a converter configured to step up input DC power and output increased power, and a buck converter is a converter configured to step down input DC power and output decreased power. Figure 2A As shown, in the monitoring device 1000 according to some embodiments, the charging circuit 100 may be formed as a buck converter 100a, and the buck converter 100a may include a switch 110, an inductor 120, a diode 130 and a capacitor 140. As shown in the figure, the capacitor 140 may be included in the buck converter 100a. Alternatively, the capacitor 140 may be a component of the secondary power supply device 200 to be charged. Briefly describing the operation of the buck converter 100a, when the switch 110 is as in Figure 2AWhen the top structure of the capacitor 140 is closed, current is applied from the power supply 101 to the inductor 120 so that the current flowing through the inductor 120 increases and thus energy is stored in the inductor 120, and then the energy is delivered to the output terminal, whereby the output voltage Vo (i.e., the voltage of the capacitor 140) increases. In this regard, the diode 130 is reverse biased so that the current does not flow to the diode 130. Next, as in Figure 2A As in the bottom structure of , when the switch 110 is opened, a closed circuit is formed by the inductor 120, the diode 130 and the capacitor 140. In this regard, the current flowing in the inductor 120 gradually decreases while flowing in the closed circuit, and thus, the output voltage Vo (i.e., the voltage of the capacitor 140) decreases. This may correspond to the self-discharge of the capacitor 140. The average voltage of the output voltage Vo may be controlled according to the ratio of the closed state to the open state of the switch 110. In addition, when the switch 110 is closed, the maximum output voltage may be obtained, and the output voltage Vo may always be equal to or less than the input voltage. The switch 110 may be formed as a field effect transistor (FET) that is easy to control. Now, the following description will be made with reference to FIG. Figure 2B The control of the switch 110 is explained in detail together with the description of the buck converter 100 b shown.

[0090] like Figure 2B As shown, the buck converter 100b may include a pair of switches 110a and 110b (also referred to as a first switch 110a and a second switch 110b), an inductor 120, and a capacitor 140. In this regard, the pair of switches 110a and 110b may be formed as the same n-type field effect transistor. However, the inventive concept is not limited thereto. For example, the pair of switches 110a and 110b may be formed as an n-type field effect transistor and a p-type field effect transistor, respectively, and in this case, the same pulse width modulation (PWM) signals PWM_A and PWM_B may be input to the pair of switches 110a and 110b, respectively.

[0091] Briefly describing the operation of the buck converter 100b, the buck converter 100b can operate in two modes according to the on state or off state of the switches 110a and 110b. For example, the first mode is an operation mode in which the first switch 110a is turned on and the second switch 110b is turned off, and during the first mode, a current is applied from the power source 101 to the inductor 120 so that the current flowing in the inductor 120 increases and thus energy is stored in the inductor 120, and then the energy is delivered to the output terminal, whereby the output voltage Vo (i.e., the voltage of the capacitor 140) increases. The second mode is an operation mode in which the first switch 110a is turned off and the second switch 110b is turned on, and during the second mode, a closed circuit is formed by the inductor 120 and the capacitor 140. In this regard, the current flowing in the inductor 120 gradually decreases while flowing in a closed circuit until the first switch 110 a is turned on in the next time period, thereby decreasing the output voltage Vo.

[0092] Based on this criterion, the control circuit ("CONTROLLER") 400a detects the output voltage Vo, and when the output voltage Vo is low, the control circuit 400a may increase the output voltage Vo by increasing the connection time of the first switch 110a and decreasing the connection time of the second switch 110b. In addition, when the output voltage Vo is high, the control circuit 400a may decrease the output voltage Vo by decreasing the connection time of the first switch 110a and increasing the connection time of the second switch 110b. For example, the control circuit 400a may maintain a constant level of the voltage of the capacitor 140 by adjusting the duty ratio of the pulse width modulation signals respectively output to the switches 110a and 110b based on the output voltage Vo.

[0093] Figure 3A and Figure 3B is a diagram showing some embodiments of the present invention. Figure 1 The circuit diagram of the structure of the secondary power device 200 in the monitoring device 1000 is shown. For ease of understanding, refer to Figure 1 To provide explanation (i.e., to mention / elaborate Figure 1 components shown).

[0094] Reference Figure 3AIn the monitoring device 1000 according to some embodiments, the secondary power supply device 200a may be formed by at least two capacitors 210 connected in series. Generally speaking, when the capacitors 210 are connected in series, the collective voltage / total voltage of the group of capacitors 210 may increase. Therefore, a secondary power supply device 200a having a high voltage may be implemented by connecting capacitors 210 each having a small capacity in series. When the capacitors 210 are connected in parallel, the capacity of the group of capacitors 210 may increase so that the amount of charge to be stored may increase.

[0095] Reference Figure 3B In the monitoring device 1000 according to some embodiments, the secondary power supply device 200b may be formed by a plurality of capacitors 210 connected in series and parallel. As described above, the voltage of the group of capacitors 210 may be increased by connecting the capacitors 210 in series, and the capacity of a group of capacitors 210 may be increased by connecting the capacitors 210 in parallel. Therefore, in the monitoring device 1000 according to some embodiments, the plurality of capacitors 210 are connected in series and parallel so that the voltage and capacity of the group of capacitors 210 may be increased. Figure 3B In the secondary power supply device 200b shown, two capacitors 210 are connected in series, but the present invention is not limited thereto, and thus at least three capacitors 210 may be connected in series. In addition, the secondary power supply device 200b is not limited to a structure in which the capacitors 210 connected in series are connected in parallel, and thus may have a structure in which the capacitors 210 connected in parallel are connected in series.

[0096] In the monitoring device 1000 according to some embodiments, the secondary power supply device 200, 200a or 200b may be applied to an electronic device (e.g., a storage module) using relatively high backup energy. Therefore, the secondary power supply device 200, 200a or 200b may have a structure in which a plurality of capacitors are connected in parallel and may have a high capacitor capacity. For example, the secondary power supply device 200, 200a or 200b may have a high capacitor capacity ranging from several hundred microfarads (μF) to several millifarads (mF). For example, the secondary power supply device 200, 200a or 200b may be applied to a solid state drive (SSD) module using at least 10 millijoules (mJ) of backup energy, and therefore, the monitoring device 1000 may be included in the solid state drive module and may monitor the secondary power supply device. However, the example of the electronic device to which the secondary power supply device 200, 200a or 200b is applied is not limited to the solid state drive module.

[0097] Figure 4A and Figure 4B It further shows Figure 1FIG. 1 is a block diagram of a measuring device 310 of a measuring circuit 300 in the monitoring device 1000. For ease of understanding, refer to FIG. Figure 1 To provide explanation (i.e., to mention / elaborate Figure 1 components shown).

[0098] Reference Figure 4A In the monitoring device 1000 according to some embodiments, the measurer 310 of the measuring circuit 300 may include a voltage ("Vol.") detector 312 and a timer 314. The voltage detector 312 may measure the output voltage of the charging circuit 100 or the voltage of the secondary power device 200. More specifically, the voltage detector 312 may detect a first voltage (refer to Figure 5A 'B' in the graph shown in FIG. 1 ) and a second voltage of the secondary power supply device 200 when charging of the secondary power supply device 200 is completed (refer to FIG. 1 ). Figure 5A 'A' in the graph shown).

[0099] The charging circuit 100 may automatically perform a charging operation based on the voltage level of the secondary power supply device 200. In other words, the charging circuit 100 may perform a charging operation on the secondary power supply device 200 based on a preset / predetermined voltage condition. For example, in a case where the first voltage of the secondary power supply device 200 is set as a charging start voltage and the second voltage of the secondary power supply device 200 is set as a charging end voltage, when the secondary power supply device 200 self-discharges and thus reaches the first voltage, the charging circuit 100 starts the charging operation of the secondary power supply device 200. Then, when the secondary power supply device 200 reaches the second voltage as the charging end voltage due to the charging operation of the charging circuit 100, the charging circuit 100 ends the charging operation. In a case where the state of the secondary power supply device 200 is normal, the charging operation of the charging circuit 100 may be periodically and repeatedly performed between the first voltage and the second voltage.

[0100] When the voltage detector 312 of the measurer 310 detects the first voltage and the second voltage of the secondary power device 200, the timer 314 can measure the time of the charging cycle and / or the discharging cycle of the charging circuit 100. In more detail, the charging cycle may refer to a time period in which the voltage of the secondary power device 200 increases from the first voltage to the second voltage, and may correspond to the field effect transistor of the DC-DC converter of the charging circuit 100 (refer to Figure 2BThe discharge period may refer to a time period in which the voltage of the secondary power supply device 200 decreases from the second voltage to the first voltage, and may correspond to an off period of the field effect transistor of the DC-DC converter of the charging circuit 100. In the following, for ease of explanation, the on period of the field effect transistor of the DC-DC converter is abbreviated as the on period of the field effect transistor, and the off period of the field effect transistor of the DC-DC converter is abbreviated as the off period of the field effect transistor.

[0101] When the timer 314 measures the time of the on-cycle of the field effect transistor and / or the off-cycle of the field effect transistor, the determiner 330 can determine whether the state of the secondary power supply device 200 is normal or abnormal. In other words, in the case where the state of the secondary power supply device 200 is normal, the charging operation of the charging circuit 100 can be performed periodically and repeatedly between the first voltage and the second voltage. Therefore, the time of the on-cycle of the field effect transistor corresponding to the charging cycle and the time of the off-cycle of the field effect transistor corresponding to the discharge cycle can have set / predetermined values ​​respectively. Therefore, the time of the on-cycle of the field effect transistor and / or the off-cycle of the field effect transistor is measured for the secondary power supply device 200 in a normal state, and then is set as a reference time, and the measured time of the on-cycle of the field effect transistor and / or the off-cycle of the field effect transistor is compared with the reference time so that it can be determined whether the state of the secondary power supply device 200 is normal. In some embodiments, the reference time can be input in advance without performing a separate setting process.

[0102] The determiner 330 may compare the measured time of the on-period of the field effect transistor and / or the off-period of the field effect transistor with the reference time, and then may determine that the state of the secondary power supply device 200 is normal when the difference between the measured time and the reference time is equal to or less than a set / predetermined range, and may determine that the state of the secondary power supply device 200 is abnormal when the difference between the measured time and the reference time is greater than a set / predetermined range. For example, the set / predetermined range of the difference between the measured time and the reference time may be ±5%. However, the set / predetermined range is not limited to the above values.

[0103] The reference time may be set for each of the on-reference time relative to the on-cycle of the field effect transistor and the off-reference time relative to the off-cycle of the field effect transistor, or may be set for one of the on-reference time and the off-reference time. The determination made by the determiner 330 as to whether the state of the secondary power supply device 200 is normal may be achieved by comparing the measured time of the on-cycle of the field effect transistor with the on-reference time or by comparing the measured time of the off-cycle of the field effect transistor with the off-reference time. In addition, in some embodiments, the determination may be achieved by performing two comparisons, a comparison between the measured time of the on-cycle of the field effect transistor and the on-reference time and a comparison between the measured time of the off-cycle of the field effect transistor and the off-reference time.

[0104] Reference Figure 4B In the monitoring device 1000 according to some embodiments, the measurer 310a of the measuring circuit 300 may include a voltage detector 312 and a tick counter 314a. The voltage detector 312 may measure the voltage of the secondary power device 200. More specifically, the voltage detector 312 may detect a first voltage (refer to Figure 5A B voltage in the figure) and the second voltage of the secondary power supply device 200 when the charging of the secondary power supply device 200 is completed (refer to Figure 5A A voltage in).

[0105] picture Figure 4A Like the timer 314 of the meter 310 in FIG. 1 , the tick counter 314 a can measure the time of the on period of the field effect transistor and / or the off period of the field effect transistor. Generally speaking, the operating system (OS) uses a time unit called a 'tick' during a process (e.g., scheduling). The interval between ticks is normally between about 1 millisecond (ms) and about 10 ms, and the time of the corresponding cycle can be measured by counting the number of ticks. For example, in the case where the interval between ticks is 1 ms and 20 ticks are counted within the cycle to be measured, the time of the cycle can be determined to be 20 ms.

[0106] Therefore, in the monitoring device 1000 according to some embodiments, the measurer 310a of the measuring circuit 300 can measure the time of the on-period of the field effect transistor and / or the off-period of the field effect transistor by counting the ticks in the on-period of the field effect transistor and / or the off-period of the field effect transistor using the tick counter 314a. Figure 4AIn a similar manner to the description of the measuring device 310 shown in FIG. 1 , the determiner 330 may compare the number of ticks counted by the tick counter 314 a with the reference data, thereby determining whether the state of the secondary power supply device 200 is normal or abnormal. The setting of the reference number and the setting / predetermined range of the difference between the number of counted ticks and the reference time may be the same as that described herein with respect to Figure 4A The contents described in the setting of the reference time and the set / predetermined range of the difference between the measured time and the reference time.

[0107] Figure 5A A graph showing a voltage distribution of the secondary power supply device 200 and an on-off distribution of the field effect transistor when the state of the secondary power supply device 200 is normal, and FIG. 5B to FIG. 5D A graph showing the voltage distribution of the secondary power device 200 and the on-off distribution of the field effect transistor when the state of the secondary power device 200 is abnormal. In the graph, the x-axis represents time, the y-axis represents voltage, and the unit can be any unit. The mark A on the y-axis refers to the second voltage of the secondary power device 200 when the charging by the charging circuit 100 is completed, and the mark B on the y-axis refers to the first voltage of the secondary power device 200 when the charging by the charging circuit 100 starts. For ease of understanding, refer to Figure 1 to provide instructions.

[0108] Reference Figure 5A , when the state of the secondary power supply device 200 is normal, the voltage of the secondary power supply device 200 may periodically repeat rising and falling between the first voltage B and the second voltage A. Therefore, based on each cycle, the time of the rising cycle and the time of the falling cycle may be constant / consistent. In this regard, the rising cycle may correspond to the charging cycle, and the falling cycle may correspond to the discharging cycle. In addition, the charging cycle may correspond to the field effect transistor (refer to Figure 2B The field effect transistor 110a) is shown as being on-period, and the discharge period may correspond to the off-period of the field effect transistor.

[0109] The voltage of the secondary power supply device 200 may correspond to the output voltage from the charging circuit 100. In addition, the voltage of the secondary power supply device 200 may correspond to the voltage of all capacitors 210. The switching distribution of the charging circuit 100 or the DC-DC converter may include an on-off distribution of the field effect transistor and a voltage distribution of the capacitor 210 (e.g., a total voltage distribution / collective voltage distribution taking all the plurality of capacitors 210 into account).

[0110] When the state of the secondary power supply device 200 is normal, as shown in the lower part of the graph of the field effect transistor, the time of the on-cycle of the field effect transistor may correspond to the on-reference time (ΔTon-R), and the time of the off-cycle of the field effect transistor may correspond to the off-reference time (ΔToff-R). The on-reference time (ΔTon-R) and the off-reference time (ΔToff-R) may be maintained constantly / consistently in each cycle.

[0111] In other words, in a case where the state of the secondary power supply device 200 is unknown, when the time of the on-period of the field effect transistor and / or the off-period of the field effect transistor measured by the measurer 310 of the measurement circuit 300 is substantially the same as the on-reference time (ΔTon-R) or the off-reference time (ΔToff-R), it can be determined that the state of the secondary power supply device 200 is normal.

[0112] Reference Figure 5B , when the state of the secondary power supply device 200 is abnormal, the voltage of the secondary power supply device 200 may deviate from the pattern in which the voltage periodically increases and decreases between the first voltage B and the second voltage A (eg, may be irregular). Figure 5B In the example, at the time point where the longer bold straight line starts, an open circuit defect has occurred in some of the capacitors 210 forming the secondary power supply device 200. In this regard, in some of the capacitors 210 in which the open circuit defect has occurred, the self-discharge may be slow or fast based on the surrounding environment, and Figure 5B The case of slow self-discharge is shown.

[0113] In the case of slow self-discharge, the time for the voltage of the secondary power supply device 200 to decrease to the first voltage B (i.e., the off period of the field effect transistor) increases. Therefore, the measurer 310 of the measurement circuit 300 can measure the time of the off period of the field effect transistor as the first open circuit off time (△Toff-O1). The first open circuit off time (△Toff-O1) may be different from the off reference time (△Toff-R). For example, when it is assumed that the set / predetermined range about the difference is 5%, the first open circuit off time (△Toff-O1) may increase by more than 5% compared with the off reference time (△Toff-R). Therefore, the determiner 330 can determine that the state of the secondary power supply device 200 is abnormal.

[0114] The time of the charging cycle may be fast when the self-discharge is slow due to open circuit defects in some of the capacitors 210. However, the time relationship between discharge and charge is not limited thereto.

[0115] Reference Figure 5C, the state of the secondary power supply device 200 is abnormal, and an open circuit defect has occurred in some of the capacitors 210. However, unlike Figure 5B The situation shown, Figure 5C A rapid self-discharge situation is shown.

[0116] In more detail, in the case of rapid self-discharge, the time (i.e., the off-cycle of the field effect transistor) for the voltage of the secondary power supply device 200 to decrease to the first voltage B is reduced. Therefore, the measurer 310 of the measurement circuit 300 can measure the time of the off-cycle of the field effect transistor as the second open circuit off-time (△Toff-O2). The second open circuit off-time (△Toff-O2) may be different from the off reference time (△Toff-R). For example, when it is assumed that the set / predetermined range of the difference is 5%, the second open circuit off-time (△Toff-O2) may be reduced by more than 5% compared with the off reference time (△Toff-R). Therefore, the determiner 330 can determine that the state of the secondary power supply device 200 is abnormal.

[0117] When the self-discharge is rapid due to open circuit defects in some of the capacitors 210, the time of the charging cycle may increase. However, the time relationship between the discharge and the charge is not limited thereto.

[0118] Reference Figure 5D , the state of the secondary power supply device 200 is abnormal, and a short circuit defect has occurred in some of the capacitors 210. When a short circuit defect occurs in some of the capacitors 210, the charge may not be stored in the capacitor 210, but may flow away and disappear. Therefore, the voltage of the capacitor 210 may continue to decrease and then may decrease to a ground state. Figure 1 As shown, in a case where the secondary power supply device 200 is composed of capacitors 210 connected in parallel, when a short circuit defect occurs in one of the capacitors 210, other capacitors 210 in the capacitors 210 may be affected, so that the overall voltage of the secondary power supply device 200 (e.g., the total voltage / collective voltage taking all the capacitors 210 into account) may decrease and then may decrease to a ground state.

[0119] The short circuit defect in capacitor 210 will now be described with respect to the on-cycle of the field effect transistor and the off-cycle of the field effect transistor. Figure 5DA short circuit defect has occurred in the capacitor 210 at the time point where the thick straight line starts. When a short circuit defect occurs in the capacitor 210, discharge can be quickly performed through the short circuit path. Therefore, the off period of the field effect transistor can become very short, and the measurer 310 of the measurement circuit 300 can measure the time of the off period of the field effect transistor as the short circuit off time (△Toff-S). The short circuit off time (△Toff-S) may be different from the off reference time (△Toff-R). For example, when it is assumed that the set / predetermined range of the difference is 5%, the short circuit off time (△Toff-S) can be reduced by more than 5% compared with the off reference time (△Toff-R). Therefore, the determiner 330 can determine that the state of the secondary power supply device 200 is abnormal.

[0120] The short-circuit off time (ΔToff-S) may represent the time period for the second voltage A to decrease to the first voltage B. Generally speaking, when the voltage of the secondary power supply device 200 reaches the first voltage B, the charging operation of the charging circuit 100 is performed again. That is, the on-cycle of the field effect transistor is generated again. However, even if the charging operation of the charging circuit 100 is performed as shown in the figure, the voltage of the secondary power supply device 200 continues to decrease. Therefore, the charging operation of the charging circuit 100 remains unchanged, and the on-cycle of the field effect transistor also remains unchanged.

[0121] Even when the determiner 330 determines that the state of the secondary power supply device 200 is abnormal, it is still difficult to identify whether an open circuit defect or a short circuit defect has occurred in the capacitor 210 of the secondary power supply device 200. This is because even if Figure 5C In the case of an open circuit defect in the capacitor 210 as in FIG. 1 , the second open circuit off time (ΔToff-O2) can still be shorter than the off reference time (ΔToff-R). Figure 5B As in the open defect in the capacitor 210 in FIG. 1 , in the case where the first open off time (ΔToff-O1) is longer than the off reference time (ΔToff-R), it can be determined that an open defect has occurred in the capacitor 210 .

[0122] In the case where a short circuit defect has occurred in capacitor 210, as Figure 5D As shown, the voltage of the secondary power supply device 200 may continue to decrease after the first voltage B. Therefore, when a third voltage C lower than the first voltage B is set and the measurer 310 of the measurement circuit 300 detects a voltage of the secondary power supply device 200 corresponding to the third voltage C, it can be determined that a short circuit defect has occurred in the capacitor 210 of the secondary power supply device 200. That is, by adding a detection mechanism for the third voltage C, the short circuit defect can be Figure 5C The open circuit defect in capacitor 210 is similar to that in Figure 5DThe short circuit defects in the same capacitor 210 are distinguished.

[0123] Therefore, the monitoring device 1000 according to some embodiments can distinguish all defective states of the capacitor 210 by adding a detection mechanism for the third voltage C. In addition, when a defect occurs in the secondary power supply device 200, detailed information about the type of the defect is sent to the control circuit 400, so that the control circuit 400 can be used to further efficiently control the charging circuit 100. For example, when an open circuit defect occurs in the capacitor 210, the switching cycle of the field effect transistor or the input voltage input to the field effect transistor can be adjusted to control the secondary power supply device 200 to substantially / maximally maintain the normal state of the secondary power supply device 200. In addition, when a short circuit defect occurs in the capacitor 210, the charging operation of the charging circuit 100 can be suspended so that unnecessary waste of power can be suppressed / prevented. In addition, the defective state of the capacitor 210 can be notified to the user through an alarm message or an alarm signal so that the secondary power supply device 200 can be quickly repaired or replaced.

[0124] Fig. 6A and Figure 6B is a block diagram showing the structure of a monitoring device according to some embodiments. Figures 1 to 4B Provide instructions.

[0125] Reference Fig. 6A In the monitoring device 1000 according to some embodiments, the measurement circuit ("Mea.Cir.") 300 and the control circuit 400 may be integrated together in a main system integrated circuit (IC) 2000 or a main system block. In some embodiments, the charging circuit 100 and the secondary power supply device 200 may be configured in an integrated circuit or block different from the main system integrated circuit 2000.

[0126] As reference Figure 1 As described above, the measurement circuit 300 may include a measurer 310 and a determiner 330. Fig. 6A In the example shown, the measurement circuit 300 is configured in the main system integrated circuit 2000, so the measurement circuit 300 can monitor the state of the secondary power device 200 and can directly send information about the state of the secondary power device 200 to the control circuit 400. Therefore, the control circuit 400 can be used to further quickly perform control of the charging circuit 100.

[0127] Reference Figure 6BIn the monitoring device 1000a according to some embodiments, the measuring circuit 300 may be configured together with the charging circuit ("Cha.Cir.") 100 in a power loss protection (PLP) integrated circuit 1500, which is also referred to as a power loss protection block / system 1500. The measuring circuit 300 may include a measurer 310 and a determiner 330.

[0128] In the case where the measurement circuit 300 is configured in the anti-power-off integrated circuit 1500, the anti-power-off integrated circuit 1500 may further include an event generating circuit ("Event Gen. Cir.") 500. In more detail, in the case where the measurement circuit 300 is configured in the anti-power-off integrated circuit 1500 and monitors the state of the secondary power supply device 200, the measurement circuit 300 may obtain (e.g., may have to obtain) information about the state of the secondary power supply device 200, and may send the information to the control circuit 400 configured in the main system integrated circuit 2000a. Therefore, the event generating circuit 500 may be configured in the anti-power-off integrated circuit 1500. The event generating circuit 500 may send the information about the state of the secondary power supply device 200 as an event signal (e.g., interrupt) to the control circuit 400 of the main system integrated circuit 2000a. For example, the event generating circuit 500 may periodically send a high signal to the control circuit 400 , and when a defect occurs in the secondary power supply device 200 , the event generating circuit 500 may send a low signal to the control circuit 400 , thereby sending information about the state of the secondary power supply device 200 to the control circuit 400 .

[0129] As mentioned above Figure 5D As described, in a case where various defect states of the secondary power supply device 200 are distinguished, the event generating circuit 500 may generate various signals corresponding to the various defect states and may send the various signals to the control circuit 400, thereby sending information about the detailed defect state of the secondary power supply device 200 to the control circuit 400.

[0130] Reference Figure 6B , the secondary power device 200 and the anti-power-off integrated circuit 1500 are configured separately, but in fact, the secondary power device 200 can be configured in the anti-power-off integrated circuit 1500 and thus can be a component included in the anti-power-off integrated circuit 1500. However, in some embodiments, the secondary power device 200 and the anti-power-off integrated circuit 1500 can be configured separately.

[0131] Figure 7 1 is a block diagram showing the structure of a storage system 10000 including a monitoring device according to some embodiments. Figures 1 to 6B Provide instructions.

[0132] Reference Figure 7 According to some embodiments, the storage system 10000 may include a power failure prevention block 1500 , a power supply block (“PWR”) 2500 , and a main system block 2000 .

[0133] The power-off prevention block 1500 may be configured to suppress / prevent power off of the power supplied to the main system block 2000. For example, the power-off prevention block 1500 may include the charging circuit 100 and the secondary power supply device 200 therein. Figure 7 , the secondary power supply device 200 and the anti-power-off block 1500 are configured separately, but this configuration may be for the convenience of reference Fig. 8A and Figure 8B As described above, the secondary power device 200 may be configured in the anti-power-off block 1500 and thus may be regarded as a component included in the anti-power-off block 1500. However, in some embodiments, the secondary power device 200 and the anti-power-off block 1500 may be configured separately.

[0134] The measurement circuit 300 and the event generation circuit 500 can be configured in the power-off prevention block 1500, such as Figure 6B In the case where the measurement circuit 300 and the event generation circuit 500 are configured in the power-off prevention block 1500 , the measurement circuit 300 may not be configured in the main system block 2000 .

[0135] The power block 2500 may be configured to supply power received via the power-off prevention block 1500 to the main system block 2000. For example, the power block 2500 may correspond to power input and output terminals of the main system block 2000.

[0136] The main system block 2000 may include a control circuit 400, a first memory chip 2100, and a second memory chip 2200. One of the first memory chip 2100 and the second memory chip 2200 may be a cache memory, and the other may be a main memory. In some embodiments, the chip corresponding to the main memory may have a multi-layer structure. Depending on the type of the main memory, the storage system 10000 may correspond to one of a solid-state drive module, a dynamic random access memory (DRAM) module, and a flash memory module. In the solid-state drive module, a dynamic random access memory may be used as a cache memory and a non-flash memory may be used as a main memory.

[0137] In the storage system 10000 according to some embodiments, the main system block 2000 may use relatively high energy as backup energy. For example, the main system block 2000 may use at least 10 megajoules (mJ) of energy as energy supplied from the secondary power supply device 200. In more detail, the storage system 10000 may be a solid state drive module in which the main system block 2000 uses at least 10 mJ of energy as backup energy. However, the type of the storage system 10000 is not limited to the solid state drive module.

[0138] The control circuit 400 may control data read operation, data write operation, data erase operation, etc. of the main system block 2000. In addition, the control circuit 400 may receive information on the state of the secondary power supply device 200 to control the charging circuit 100 of the power failure prevention block 1500.

[0139] like Fig. 6A As shown in , the measurement circuit 300 may be configured in the main system block 2000. In the case where the measurement circuit 300 is configured in the main system block 2000, the control circuit 400 may directly receive information about the state of the secondary power supply device 200 from the measurement circuit 300. In the case where the measurement circuit 300 is configured in the main system block 2000, both the measurement circuit 300 and the event generation circuit 500 may not be configured in the power-off prevention block 1500.

[0140] Fig. 8A and Figure 8B It is shown Figure 7 A diagram showing a power supply process in storage system 10000.

[0141] Reference Fig. 8A and Figure 8B In the absence of an error in the external (eg, main / primary) power supply Ext, the Fig. 8A As shown by the thick arrows, power from the external power source Ext is supplied to the main system block 2000 via the power failure prevention block 1500 and the power supply block 2500. In addition, power from the external power source Ext can be supplied to the charging circuit 100 in the power failure prevention block 1500, so that the charging operation of the charging circuit 100 can be periodically and repeatedly performed on the secondary power supply device 200.

[0142] In the event of a sudden power failure due to an error in the external power supply Ext, Figure 8BAs shown by the thick arrow in FIG. 1 , power is supplied from the secondary power supply device 200 to the main system block 2000 via the power failure prevention block 1500 and the power supply block (e.g., power supply circuit / system) 2500. Therefore, even in the case of a sudden power failure, the main system block 2000 can continue to perform operations using the power of the secondary power supply device 200, so that data loss can be suppressed / prevented. However, when the secondary power supply device 200 has a defect, the main system block 2000 may not be able to use the power of the secondary power supply device 200 when a sudden power failure occurs, and thus data loss may not be avoided.

[0143] According to some embodiments, the storage system 10000 may include a monitoring device 1000 (see Fig. 6A ) or monitoring device 1000a (refer to Figure 6B ). Therefore, the secondary power supply device 200 can be monitored in real time. Therefore, the user can repair or replace the secondary power supply device 200 in response to the occurrence of a defect in the secondary power supply device 200. Therefore, the storage system 10000 according to some embodiments can pre-suppress / prevent a data loss problem that may occur when the operation of the main system block 2000 is suspended due to a defect in the secondary power supply device 200 in a sudden power-off situation.

[0144] Fig. 9 2 is a flow chart of a method for monitoring a secondary power device 200 according to some embodiments. Figures 1 to 8B For easier understanding, please refer to Figures 1 to 4B to provide instructions.

[0145] Reference Fig. 9 , charging the secondary power device 200 via the charging circuit 100 (block 1110). The secondary power device 200 may include at least two capacitors 210 connected in series, series-parallel, or parallel. The charging circuit 100 may include a DC-DC converter 100a or 100b. In this regard, charging may mean charging the capacitor 210 in the secondary power device 200. In addition, charging may mean periodically and repeatedly charging the secondary power device 200.

[0146] Next, the switching profile of the DC-DC converter 100a or 100b is measured using the measuring device 310 of the measuring circuit 300 (block 1120). The switching profile of the DC-DC converter 100a or 100b may include a field effect transistor (refer to Figure 2BThe on-off distribution of the field effect transistor 110a) and the power distribution of the secondary power supply device 200 are shown. The power distribution of the secondary power supply device 200 may correspond to the output voltage distribution of the DC-DC converter 100a or 100b. For example, the voltage of the capacitor 210 is detected by the voltage detector 312 of the measuring device 310, and the on-cycle and / or off-cycle of the field effect transistor may be measured by the timer 314 or the tick counter 314a. Fig.10 The voltage detection and time measurement of the on-period and / or off-period of the field effect transistor will be described in detail in the description.

[0147] Then, the state of the secondary power device 200 is determined based on the measured switching distribution of the DC-DC converter 100a or 100b (block 1130). For example, the measured time / duration of the on-period and / or off-period of the field effect transistor is compared with a reference time, and in the case where the difference between the measured time and the reference time is within a set / predetermined range, the state of the secondary power device 200 is determined to be a normal state. On the other hand, in the case where the difference between the measured time and the reference time exceeds the set / predetermined range, the state of the secondary power device 200 is determined to be an abnormal state. In addition, the method of monitoring (and / or managing / controlling) the secondary power device 200 may include completing a read operation, a write operation, or an erase operation of the storage system 10000 after determining (block 1130) that the state of the secondary power device 200 is abnormal and while the secondary power device 200 supplies power to the storage system 10000. Therefore, since the secondary power device 200 is not forcibly discharged, the secondary power device 200 can complete a read operation, a write operation, or an erase operation before the secondary power device 200 is repaired or replaced, even though the secondary power device 200 is in an abnormal state. Fig.10 The determination of the state of the secondary power supply device 200 is explained in detail.

[0148] Fig.10 and Fig.11 Yes Fig. 9 A flow chart of details of the method of measuring a switching profile (block 1120) and determining a state of a secondary power device (block 1130).

[0149] Reference Fig.10 , the voltage detector 312 of the measuring device 310 detects the first voltage of the capacitor 210 (refer to Figure 5A In addition, the voltage detector 312 is used to detect the second voltage of the capacitor 210 (refer to Figure 5A The second voltage A shown) (block 1124). Fig.10, first the first voltage B is detected and then the second voltage A is detected, but the detection order is not limited thereto. Therefore, the second voltage A may be detected first and then the first voltage B may be detected. Alternatively, the first voltage B and the second voltage A may be detected almost / substantially simultaneously.

[0150] Then, the time ΔT of the on-period and / or off-period of the field effect transistor is measured using the timer 314 of the measurer 310 or the tick counter 314a of the measurer 310a (block 1126). The on-period of the field effect transistor may correspond to a charging period of the capacitor 210 in which the voltage of the capacitor 210 increases from the first voltage B to the second voltage A. The off-period of the field effect transistor may correspond to a discharging period of the capacitor 210 in which the voltage of the capacitor 210 decreases from the second voltage A to the first voltage B.

[0151] Detecting a first voltage (block 1122), detecting a second voltage (block 1124), and measuring a time ΔT of an on period and / or an off period of a field effect transistor (block 1126) may be included in the operation shown in block 1120 of measuring a switching profile of a DC-DC converter 100a or 100b.

[0152] Then, it is determined whether the time △T of the on-cycle and / or off-cycle of the field effect transistor is equal to the reference time △TR within the set / predetermined range (block 1131). In this regard, the symbol '≒' can represent the sameness within the set / predetermined range. For example, in the case where the set / predetermined range is ±5% and the difference between the time △T of the on-cycle and / or off-cycle of the field effect transistor and the reference time △TR is within ±5%, it can be determined that the time △T and the reference time △TR are equal to each other. On the other hand, in the case where the difference exceeds ±5%, it can be determined that the time △T and the reference time △TR are not equal to each other. In addition, the set / predetermined range is not limited to ±5%. For example, when precise determination is desired / needed, the set / predetermined range can be set to less than ±5%.

[0153] The time ΔT of the on-period and / or off-period of the field effect transistor may include the time ΔTon of the on-period of the field effect transistor and the time ΔToff of the off-period of the field effect transistor. In addition, the reference time ΔTR may include a reference time ΔTon-R (reference time) relative to the on-period of the field effect transistor. Figure 5A ) and the reference time △Toff-R (reference Figure 5A). Therefore, the time ΔTon of the on-period of the field effect transistor can be compared with the reference time ΔTon-R relative to the on-period of the field effect transistor, and the time ΔToff of the off-period of the field effect transistor can be compared with the reference time ΔToff-R relative to the off-period of the field effect transistor. In this regard, the determination of the normal state can be performed based on one of the two comparisons or based on both of the two comparisons.

[0154] When (e.g., in response to determining that) the time ΔT of the on-period and / or off-period of the field effect transistor is equal to the reference time ΔTR within a set / predetermined range (in the case of “yes”), the state of the secondary power supply device 200 is determined to be a normal state (block 1132).

[0155] When the time ΔT of the on-period and / or off-period of the field effect transistor is not equal to the reference time ΔTR within the set / predetermined range (in the case of "No"), that is, when the difference between the time ΔT of the on-period and / or off-period of the field effect transistor and the reference time ΔTR exceeds the set / predetermined range, it is determined whether the voltage Vc of the capacitor 210 is between the first voltage B and the second voltage A (block 1133). The voltage detector 312 of the measurer 310 can be used to detect the voltage Vc of the capacitor 210.

[0156] When the voltage Vc of the capacitor 210 is between the first voltage B and the second voltage A (in the case of “yes”), it is determined that the state of the secondary power supply device 200 is an abnormal state and open circuit defects have occurred in some capacitors 210 (one or more capacitors 210) among the capacitors 210 of the secondary power supply device 200 (block 1136).

[0157] When the voltage Vc of the capacitor 210 is not between the first voltage B and the second voltage A (in the case of "No"), for example, when a third voltage C lower than the first voltage B is detected in the voltage Vc of the capacitor 210 (refer to Figure 5D ), it is determined that the state of the secondary power supply device 200 is an abnormal state and a short circuit defect has occurred in some capacitors 210 (one or more capacitors 210) among the capacitors 210 of the secondary power supply device 200 (block 1134).

[0158] Determining whether the time ΔT of the on-period and / or off-period of the field effect transistor is equal to the reference time ΔTR within a set range (block 1131), the operation of block 1132, the operation of block 1133, the operation of block 1134 and / or the operation of determining an open circuit defect in the capacitor 210 (block 1136) may be included in the operation of determining the state of the secondary power supply device 200 (block 1130).

[0159] In some embodiments, the determination of whether the voltage Vc of the capacitor 210 is between the first voltage B and the second voltage A (block 1133) may be omitted. In this case, when the time ΔT of the on-period and / or off-period of the field effect transistor is not equal to the reference time ΔTR within the set / predetermined range (in the case of "No"), it may be simply determined that the state of the secondary power device 200 is abnormal. In some embodiments, in the case of determining that the state of the secondary power device 200 is in an abnormal state, the method may further include substantially / maximally maintaining the state of the secondary power device 200 as a normal state by adjusting the charging circuit 100, and / or notifying the user of the abnormal state to repair or replace the secondary power device 200.

[0160] Reference Fig.11 The method of monitoring the secondary power device 200 may be different from Fig.10 The method for monitoring the secondary power device 200 in the embodiment of the present invention is different in that the time of the on-period and / or off-period of the field effect transistor is measured by the tick timer 314a of the measurer 310a.

[0161] In more detail, after performing the detection of the first voltage (block 1122) and the detection of the second voltage (block 1124), the number of ticks Tn in the on-period and / or off-period of the field effect transistor is counted by the tick counter 314a of the measurer 310a (block 1127). The number of ticks Tn in the on-period and / or off-period of the field effect transistor may include the number of ticks Tn_on in the on-period of the field effect transistor and the number of ticks Tn_off in the off-period of the field effect transistor.

[0162] Then, it is determined whether the number of ticks Tn is equal to the reference number Rn in the set / predetermined range (block 1131a). For example, in the case where the set / predetermined range is ±5% and the reference number Rn is 50, when the count number Tn of the ticks is 51, it can be determined that the count number is equal to the reference number Rn, and when the count number Tn of the ticks is 55, the count number cannot be determined to be equal to the reference number Rn. The reference number Rn may include a reference number Rn_on relative to the on-period of the field effect transistor and a reference number Rn_off relative to the off-period of the field effect transistor. Therefore, the number of ticks Tn_on in the on-period of the field effect transistor may be compared with the reference number Rn_on relative to the on-period of the field effect transistor, and the number of ticks Tn_off in the off-period of the field effect transistor may be compared with the reference number Rn_off relative to the off-period of the field effect transistor. In this regard, the determination of the normal state may be performed based on one of the two comparisons or based on both of the two comparisons.

[0163] The subsequent process is the same as the above reference Fig.10 A method for monitoring a secondary power device 200 is provided.

[0164] Although the inventive concept has been specifically shown and described with reference to the exemplary embodiments of the inventive concept, it should be understood that various changes in form and details may be made herein without departing from the scope of the above claims. Therefore, the scope of the inventive concept is not defined by the detailed description of the inventive concept but by the appended claims and their equivalents, and should not be restricted or limited by the foregoing detailed description.

Claims

1. A power management device, characterized in that: include: a secondary power supply device including at least one capacitor; a charging circuit including a DC-DC converter and configured to supply power to the secondary power supply device; as well as a measuring circuit configured to measure a switching profile of the DC-DC converter and determine a state of the secondary power supply device by comparing at least one time period of the switching profile with a reference time, wherein the at least one time period of the switching profile is related to a duration of one of a charging cycle or a discharging cycle of the charging circuit, The power management device is in a storage system including at least one memory chip, and The power management device is configured to monitor the state of the secondary power device in real time without forcibly discharging the at least one capacitor or changing an operation mode of the storage system.

2. The power management device according to claim 1, characterized in that: The DC-DC converter includes a field effect transistor and an inductor. The switching profile includes an on-period and an off-period of the field effect transistor, and The measurement circuit is configured to determine the state of the secondary power supply device by comparing a duration of one of the on-period or the off-period with the reference time.

3. The power management device according to claim 2, characterized in that: The measuring circuit is further configured to: determining that the state of the secondary power supply device is normal in response to the voltage of the at least one capacitor periodically and repeatedly rising and falling between a first voltage and a second voltage higher than the first voltage, and in response to the voltage of the at least one capacitor exceeding the range between the first voltage and the second voltage or irregularly increasing and decreasing, determining that the state of the secondary power supply device is abnormal, and wherein the secondary power supply device is configured to supply power to the memory system to complete a read operation, a write operation, or an erase operation of the memory system after the measurement circuit determines that the state of the secondary power supply device is abnormal.

4. The power management device according to claim 3, characterized in that: wherein the measurement circuit is further configured to determine that a short circuit defect has occurred in the secondary power supply device in response to the voltage of the at least one capacitor being lower than a third voltage that is lower than the first voltage, and wherein the charging circuit is configured to suspend charging of the secondary power supply device in response to the measurement circuit determining that the short circuit defect has occurred.

5. The power management device according to claim 3, characterized in that: wherein the measurement circuit is further configured to determine that an open circuit defect has occurred in the secondary power supply device in response to the voltage of the at least one capacitor being maintained between the first voltage and the second voltage and a difference between the reference time and the duration of the one of the on-period or the off-period exceeding a predetermined range, and The charging circuit is configured to adjust the on-period and / or the off-period or the input voltage of the field effect transistor in response to the measurement circuit determining that the open circuit defect has occurred.

6. The power management device according to claim 1, characterized in that: The at least one capacitor of the secondary power supply device includes a plurality of capacitors connected in series, series-parallel, or parallel, and Each of the plurality of capacitors includes a tantalum capacitor, an aluminum capacitor, or a multilayer ceramic capacitor.

7. The power management device according to claim 1, characterized in that: The measurement circuit comprises a voltage detector configured to measure the voltage of the at least one capacitor and a timer or tick counter configured to measure the duration of each time period of the switching profile.

8. The power management device according to claim 1, characterized in that: Also includes a control circuit, the control circuit is configured to control the charging circuit, The measuring circuit and the control circuit are both in a main system that is a power supply target of the secondary power supply device, or the measuring circuit and the charging circuit are both in a power failure prevention system.

9. The power management device according to claim 8, characterized in that: The anti-power-off system includes the measuring circuit and the charging circuit. The main system includes the control circuit, The anti-power-off system also includes an event generating circuit, and The event generation circuit is configured to transmit information on the state of the secondary power supply device as an event signal to the control circuit of the main system.

10. A power management device, characterized in that: include: A secondary power supply device including a plurality of capacitors connected in parallel; a DC-DC converter including a field effect transistor as a switching device and configured to supply power to the secondary power supply device; a measurement circuit configured to measure a switching profile of the DC-DC converter and determine a state of the secondary power device by comparing at least one time period of the switching profile with a reference time, wherein the at least one time period of the switching profile is related to a duration of one of a charging cycle or a discharging cycle of the DC-DC converter; as well as a control circuit configured to control the DC-DC converter, The power management device is in a storage system including at least one memory chip, and The power management device is configured to monitor the state of the secondary power device in real time without forcibly discharging the at least one capacitor or changing an operation mode of the storage system.

11. The power management device according to claim 10, characterized in that: The switching profile includes an on-off profile of the field effect transistor and a total voltage profile of the plurality of capacitors, The measurement circuit comprises: a voltage detector configured to measure the total voltage of the plurality of capacitors; and a timer or tick counter configured to measure the duration of an on-period and / or an off-period of the field effect transistor, and The measurement circuit is further configured to determine the state of the secondary power supply device by comparing the on-period and / or the off-period of the field effect transistor with the reference time.

12. The power management device according to claim 11, characterized in that: The measurement circuit is further configured to: determining that the state of the secondary power supply device is normal in response to the total voltage distribution periodically and repeatedly rising and falling between a first voltage and a second voltage higher than the first voltage, and In response to the total voltage distribution exceeding the range between the first voltage and the second voltage or irregularly increasing and decreasing, it is determined that the state of the secondary power supply device is abnormal.

13. The power management device according to claim 10, characterized in that: The measuring circuit and the control circuit are in a main system that is a power supply target of the secondary power supply device, or the measuring circuit and the DC-DC converter are in a power failure prevention system, the power failure prevention system includes an event generation circuit, and The event generation circuit is configured to transmit information on the state of the secondary power supply device as an event signal to the control circuit of the main system.

14. A storage system, characterized in that: include: A power failure prevention system, comprising a secondary power supply device and a DC-DC converter, wherein the secondary power supply device comprises a plurality of capacitors connected in parallel, and the DC-DC converter is configured to supply power to the secondary power supply device; A main system, including a control circuit and at least one memory chip; as well as a power supply circuit, located between the power-off prevention system and the main system and configured to supply power to the main system, wherein one of the power-off prevention system or the main system further comprises a measurement circuit, wherein the measurement circuit monitors the secondary power supply device based on at least one time period of a switching profile of the DC-DC converter, wherein the at least one time period of the switching profile is related to a duration of one of a charging cycle or a discharging cycle of the DC-DC converter, and The measurement circuit is further configured to monitor the status of the secondary power supply device in real time without forcibly discharging at least one of the plurality of capacitors or changing an operation mode of the storage system.

15. The storage system according to claim 14, characterized in that: The DC-DC converter includes a field effect transistor and an inductor, and The measurement circuit is further configured to measure the switching profile and determine the state of the secondary power supply device by comparing at least one time period of the switching profile with a reference time.

16. The storage system according to claim 15, characterized in that: The switching profile includes an on-period and an off-period of the field effect transistor, The measurement circuit comprises: a voltage detector configured to measure the total voltage of the plurality of capacitors; and a timer or tick counter configured to measure the duration of the on-period and the duration of the off-period of the switching profile, and The measurement circuit is further configured to determine the state of the secondary power supply device by comparing the duration of one of the on-period or the off-period with the reference time.

17. The storage system according to claim 14, characterized in that: The anti-power-off system also includes the measurement circuit and the event generation circuit, and The event generation circuit is configured to transmit information on the state of the secondary power supply device as an event signal to the control circuit of the main system.

18. The storage system according to claim 14, characterized in that: wherein the storage system comprises one of a solid state drive, a dynamic random access memory, or a flash memory, and Wherein said one of the solid state drive, the dynamic random access memory, or the flash memory is configured to use at least 10 megajoules of backup energy from the secondary power supply device.

19. A method for power management of a secondary power device comprising a plurality of capacitors, characterized in that: The method comprises: charging the secondary power source device by supplying electric power to the secondary power source device via a DC-DC converter; measuring a switching profile of the DC-DC converter; and determining a state of the secondary power device by comparing at least one time period of the switching profile with a reference time, wherein the state of the secondary power supply device is monitored in real time by determination without discharging all of the plurality of capacitors or without changing an operation mode of a storage system that is a power supply target of the secondary power supply device.

20. The method according to claim 19, characterized in that: The DC-DC converter includes a switching device, wherein the switching device includes a field effect transistor, The switching profile includes an on-period and an off-period of the field effect transistor, and The determining includes determining the state of the secondary power supply device by comparing a duration of one of the on-period or the off-period with the reference time.

21. The method according to claim 20, characterized in that: The plurality of capacitors include a plurality of capacitors connected in parallel, The charging includes charging the plurality of capacitors connected in parallel from a first voltage to a second voltage higher than the first voltage using the DC-DC converter during the on-period, and stopping the charging during the off-period, The total voltage of the plurality of capacitors connected in parallel decreases from the second voltage to the first voltage due to self-discharge during the off period, and The measuring the switching profile is performed by a measurement circuit and includes using a voltage detector of the measurement circuit to detect the first voltage and the second voltage, and also includes using a timer or tick counter of the measurement circuit to detect the duration of the one of the on period or the off period.

22. The method according to claim 21, characterized in that The determination also includes: determining that the state of the secondary power supply device is normal in response to the total voltage of the plurality of capacitors connected in parallel periodically and repeatedly rising and falling between the first voltage and the second voltage, and in response to the total voltage of the plurality of capacitors connected in parallel exceeding the range between the first voltage and the second voltage or irregularly increasing and decreasing, determining that the state of the secondary power supply device is abnormal, and The method further includes completing a read operation, a write operation, or an erase operation of the storage system while the secondary power supply device supplies power to the storage system after determining that the state of the secondary power supply device is abnormal.

23. The method according to claim 19, characterized in that: said measuring said switching profile is performed by a measuring circuit, The measuring circuit is in a main system powered by the secondary power supply device, or the measuring circuit is in a power-off protection system including the DC-DC converter, and The method further includes sending the state of the secondary power supply device from the measurement circuit to a control circuit of the host system, and controlling the DC-DC converter by the control circuit.

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