Light emitting device including a light reflecting pattern and a wavelength conversion layer

Abstract

The light emitting device includes a light emitting chip having a first surface and a second surface. A first light reflecting pattern is formed on the second surface. A plurality of terminals are arranged to be connected to the light emitting chip by passing through the first light reflecting pattern. The second light reflecting pattern is formed on a side surface of the light emitting chip and a side surface of the first light reflecting pattern. A light-transmitting pattern is formed between the light emitting chip and the second light reflecting pattern and extends between the first light reflecting pattern and the second light reflecting pattern. A wavelength conversion layer is formed on the first surface of the light emitting chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2017-0167530 filed on December 7, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to a light emitting device including a light reflection pattern and a wavelength conversion layer, and a method of manufacturing the same. Background Art

[0004] Various studies are being conducted to improve the luminous flux of a light emitting device. The light emitting device includes a light emitting chip and a power supply terminal. When power is supplied through the power supply terminal, the light emitting chip emits light. When light emitted from the light emitting chip is concentrated in a desired direction, it is beneficial to improve the luminous flux of the light emitting device. A new technology is needed for simplifying the process and also improving the luminous flux of the light emitting device. Summary of the invention

[0005] Exemplary embodiments of the inventive concept relate to a light emitting device having improved luminous flux and facilitating high-density integration.

[0006] In addition, exemplary embodiments of the inventive concept relate to a method for manufacturing a light emitting device having improved luminous flux and facilitating high-density integration.

[0007] A light-emitting device according to an exemplary embodiment of the present invention may include a light-emitting chip having a first surface and a second surface opposite to the first surface. A first light-reflecting pattern may be formed on the second surface. A plurality of terminals may be arranged to be connected to the light-emitting chip by passing through the first light-reflecting pattern. The second light-reflecting pattern may be formed on a side surface of the light-emitting chip and on a side surface of the first light-reflecting pattern. A light-transmitting pattern may be formed between the light-emitting chip and the second light-reflecting pattern, and may extend between the first light-reflecting pattern and the second light-reflecting pattern. A wavelength conversion layer may be formed on the first surface of the light-emitting chip.

[0008] A light-emitting device according to an exemplary embodiment of the present invention may include a light-emitting chip having a first surface and a second surface opposite to the first surface. A first light reflecting pattern may be formed on the second surface. A plurality of terminals may be arranged to be connected to the light-emitting chip by passing through the first light reflecting pattern. The second light reflecting pattern may be formed on a side surface of the light-emitting chip and on a side surface of the first light reflecting pattern. A wavelength conversion layer may be formed on the first surface of the light-emitting chip. The surface of the first light reflecting pattern and the surfaces of the plurality of terminals may be substantially coplanar, the side surface of the light-emitting chip and the side surface of the first light reflecting pattern may be substantially coplanar, and the second light reflecting pattern may be in contact with the first light reflecting pattern.

[0009] A light emitting device according to an exemplary embodiment of the present invention may include a light emitting chip having a first surface and a second surface opposite to the first surface. A light reflecting pattern may be formed on the second surface. A plurality of terminals may be arranged to be connected to the light emitting chip by passing through the light reflecting pattern. A wavelength conversion layer may be arranged to cover the first surface of the light emitting chip and may contact the side surface of the light emitting chip and the side surface of the light reflecting pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 13 is a sectional view illustrating a light emitting device according to an exemplary embodiment of the inventive concept.

[0011] Figures 14 to 27 is a cross-sectional view illustrating a method of manufacturing a light emitting device according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0012] Various exemplary embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. On the contrary, these exemplary embodiments are provided so that the description will be thorough and complete and will fully convey the scope of the inventive concept to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0013] It should be understood that when an element or layer is referred to as being "above", "over", "on", "connected to" or "coupled to" another element or layer, the element or layer may be directly above, above, on, connected to or coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly above", "over", "on", "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. The same reference numerals always refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0014] It should be understood that, although the terms first, second, third, fourth, etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another region, layer or part. Therefore, the first element, first component, first region, first layer or first part discussed below can be referred to as the second element, second component, second region, second layer or second part, without departing from the teaching of the present invention.

[0015] For ease of description, spatially relative terms such as "below", "below", "down", "above", "above", "on", "top", "bottom", etc. may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the drawings. It will be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, the elements described as "below" or "below" other elements or features will be oriented to be "above" the other elements or features. Therefore, the term "below" can cover both the orientation of above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0016] The terms used herein are only for the purpose of describing specific exemplary embodiments and are not intended to limit the inventive concept. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof.

[0017] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized exemplary embodiments (and intermediate structures). Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the exemplary embodiments should not be interpreted as limited to the specific shapes of the regions shown herein, but rather to include shape deviations caused by, for example, manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and / or an implant concentration gradient at its edges, rather than having a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device, and are not intended to limit the scope of the inventive concept.

[0018] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the inventive concept belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be understood as an idealized or overly formal meaning unless explicitly defined as such herein.

[0019] Figures 1 to 13 is a sectional view illustrating a light emitting device according to an exemplary embodiment of the inventive concept.

[0020] Reference Figure 1 , a light emitting device according to an exemplary embodiment of the inventive concept may include a light emitting chip 20, a first terminal 43, a second terminal 44, a first light reflecting pattern 51, a light transmitting pattern 53, a second light reflecting pattern 55, and a wavelength conversion layer 57. The light emitting chip 20 may include a substrate 21, a buffer layer 23, a first semiconductor layer 25, an active layer 27, a second semiconductor layer 29, an upper electrode 31, a first insulating layer 33, a first interconnection 35, a second interconnection 37, and a second insulating layer 39. In the light emitting chip 20, a first surface 20S1 and a second surface 20S2 opposite to the first surface 20S1 may be defined. The first metal layer 41 may be formed between the first terminal 43 and the first interconnection 35. The second metal layer 42 may be formed between the second terminal 44 and the second interconnection 37.

[0021] The first light reflecting pattern 51, the first terminal 43, and the second terminal 44 may be disposed below the second surface 20S2 of the light emitting chip 20. The first terminal 43 may pass through the first light reflecting pattern 51 and may be connected to the first interconnect 35 via the first metal layer 41. The second terminal 44 may pass through the first light reflecting pattern 51 and may be connected to the second interconnect 37 via the second metal layer 42. The side surface of the light emitting chip 20 and the side surface of the first light reflecting pattern 51 may be substantially coplanar. The light emitting chip 20, the first light reflecting pattern 51, the first terminal 43, and the second terminal 44 may correspond to a chip scale package (CSP). The configuration of the light emitting chip 20, the first light reflecting pattern 51, the first terminal 43, and the second terminal 44 may be conducive to high-density integration and process simplification.

[0022] The light-transmitting pattern 53 may cover the first surface 20S1 and the side surface of the light-emitting chip 20, and may extend to the side surface of the first light-reflecting pattern 51. The side surface of the light-emitting chip 20 may be completely covered by the light-transmitting pattern 53. The light-transmitting pattern 53 may directly contact the side surface of the light-emitting chip 20 and the side surface of the first light-reflecting pattern 51. The lowermost end P1 of the light-transmitting pattern 53 may be formed at a lower level than at least some areas of the second surface 20S2. The lowermost end P1 of the light-transmitting pattern 53 may be formed at a higher level than the bottom surface 51S2 of the first light-reflecting pattern 51. The light-transmitting pattern 53 may have a width that decreases toward the lowermost end P1. The light-transmitting pattern 53 may include a side surface that is inclined inward.

[0023] In an exemplary embodiment, the lowermost end P1 of the light-transmitting pattern 53 may be interpreted as one end of the light-transmitting pattern 53. The one end of the light-transmitting pattern 53 may be disposed adjacent to the bottom surface 51S2 of the first light-reflecting pattern 51. In an exemplary embodiment, the light-transmitting pattern 53 may cover the side surface of the light-emitting chip 20 and the first surface 20S1, and may be disposed between the side surface of the first light-reflecting pattern 51 and the second light-reflecting pattern 55.

[0024] The second light reflecting pattern 55 may be formed at the outer side of the light transmitting pattern 53. The lower portion of the second light reflecting pattern 55 may be in direct contact with a portion of the side surface 51SW of the first light reflecting pattern 51. The bottom surface 55S2 of the second light reflecting pattern 55 and the bottom surface 51S2 of the first light reflecting pattern 51 may be substantially coplanar. The top surface 55S1 of the second light reflecting pattern 55 and the top surface 53S1 of the light transmitting pattern 53 may be substantially coplanar. The second light reflecting pattern 55 may be in direct contact with the light transmitting pattern 53.

[0025] The interface between the second light reflecting pattern 55 and the light transmitting pattern 53 may have various inclination angles. One surface of the second light reflecting pattern 55 may have a first angle θ1 relative to the side surface of the light emitting chip 20 or the side surface of the first light reflecting pattern 51. The first angle θ1 may be between 20 and 70 degrees. In an exemplary embodiment, the first angle θ1 may be between 45 and 70 degrees. For example, the first angle θ1 may be about 45 degrees or about 55 degrees. The bottom surface 51S2 of the first light reflecting pattern 51, the bottom surface 55S2 of the second light reflecting pattern 55, the bottom surface of the first terminal 43, and the bottom surface of the second terminal 44 may be exposed in substantially the same plane.

[0026] The wavelength conversion layer 57 may be formed on the second light reflecting pattern 55 and the light transmitting pattern 53. The wavelength conversion layer 57 may be in direct contact with the second light reflecting pattern 55 and the light transmitting pattern 53. The side surface 57SW of the wavelength conversion layer 57 and the side surface 55SW of the second light reflecting pattern 55 may be substantially coplanar. The wavelength conversion layer 57 may have a first thickness T1. The first thickness T1 may be between 30 μm and 300 μm. In an exemplary embodiment, the first thickness T1 may be about 90 μm.

[0027] In an exemplary embodiment, the top surface 55S1 of the second light reflective pattern 55 may have a first width W1. The horizontal distance between a point located directly above the side surface of the light emitting chip 20 at the top surface 53S1 of the light-transmitting pattern 53 and the outermost end of the light-transmitting pattern 53 may be a second width W2. The horizontal width of the light emitting chip 20 may be a third width W3. The light emitting chip 20 may be rectangular in a plan view. The third width W3 may correspond to the length of a single side of the light emitting chip 20. The total width Wt of the light emitting device according to an exemplary embodiment of the inventive concept may be defined as 2×first width W1+2×second width W2+third width W3. The horizontal width of the wavelength conversion layer 57 may be substantially the same as the total width Wt of the light emitting device. The ratio of the first width W1 to the second width W2 may be between 1:1 and 1:10. In an exemplary embodiment, the ratio of the first width W1 to the second width W2 may be 1:2. The ratio of the first width W1 to the second width W2 to the third width W3 may be between 1:1:10 and 1:10:26. In an exemplary embodiment, a ratio of the first width W1 to the second width W2 to the third width W3 may be 1:2:12.

[0028] The horizontal width of the light-transmitting pattern 53 adjacent to the side surface of the first light-reflecting pattern 51 may be defined as a fourth width W4. The fourth width W4 may be smaller than the second width W2. The light-transmitting pattern 53 may have a width that decreases toward the bottom surface 51S2 of the first light-reflecting pattern 51. The light-transmitting pattern 53 may have a width that increases toward the wavelength conversion layer 57. The lowermost end P1 of the light-transmitting pattern 53 may be arranged at a level that is higher than the bottom surface 51S2 of the first light-reflecting pattern 51 by a first height D1. The first height D1 may be between 10 μm and 30 μm.

[0029] The combination of the first light reflecting pattern 51 , the light transmitting pattern 53 , and the second light reflecting pattern 55 may maximize the efficiency of extracting light emitted from the light emitting chip 20 .

[0030] Reference Figure 2 , the lowermost end P1 of the light-transmitting pattern 53 may be formed adjacent to the lower end of the side surface of the first light-reflecting pattern 51. In an exemplary embodiment, the lowermost end P1 of the light-transmitting pattern 53 may be formed at substantially the same level as the bottom surface 51S2 of the first light-reflecting pattern 51.

[0031] Reference Figure 3 , the lowermost end P1 of the light-transmitting pattern 53 may be formed adjacent to the upper end of the side surface of the first light-reflecting pattern 51. In an exemplary embodiment, the lowermost end P1 of the light-transmitting pattern 53 may be formed at substantially the same level as the upper end of the side surface of the first light-reflecting pattern 51. The second light-reflecting pattern 55 may contact the side surface of the first light-reflecting pattern 51.

[0032] Reference Figure 4 , the bottom surface 55S2 of the second light reflecting pattern 55 may be formed at a higher level than the bottom surface 51S2 of the first light reflecting pattern 51. The step between the bottom surface 55S2 of the second light reflecting pattern 55 and the bottom surface 51S2 of the first light reflecting pattern 51 may be represented by a second height D2. The second height D2 may be between 5 μm and 500 μm. The step may be used as a reference for mounting the light emitting device in a specific pattern of a circuit board. In an exemplary embodiment, the second height D2 of the step may be between 10 μm and 100 μm.

[0033] Reference Figure 5, the top surface of the light-transmitting pattern 53 may be formed at substantially the same level as the first surface 20S1 of the light-emitting chip 20. The top surface of the second light-reflecting pattern 55, the top surface of the light-transmitting pattern 53, and the first surface 20S1 of the light-emitting chip 20 may be substantially coplanar. The bottom surface of the wavelength conversion layer 57 may be in direct contact with the top surface of the second light-reflecting pattern 55, the top surface of the light-transmitting pattern 53, and the first surface 20S1 of the light-emitting chip 20. The horizontal width of the wavelength conversion layer 57 may be greater than the horizontal width of the light-emitting chip 20. The wavelength conversion layer 57 may completely cover the first surface 20S1 of the light-emitting chip 20 and extend to the second light-reflecting pattern 55 and the light-transmitting pattern 53.

[0034] Reference Figure 6 , the lowermost end of the wavelength conversion layer 57 may be formed at a level lower than the first surface 20S1 of the light emitting chip 20. The wavelength conversion layer 57 may cover a portion of the side surface of the light emitting chip 20. The top surface of the light-transmitting pattern 53 may be formed at a level lower than the first surface 20S1 of the light emitting chip 20. This may prevent peeling of the wavelength conversion layer 57 by improving the bonding strength between the wavelength conversion layer 57 and the light emitting chip 20, and may also improve the effect of radiating the heat generated by the light emitting chip 20 through the wavelength conversion layer 57. The wavelength conversion layer 57 may be formed by applying pressure to a soft film or a soft material layer. The step between the first surface 20S1 of the light emitting chip 20 and the lowermost end of the wavelength conversion layer 57 may be represented by a third height D3, which may be between approximately 1 μm and 30 μm.

[0035] Reference Figure 7 , the interface between the light-transmitting pattern 53 and the second light-reflecting pattern 55 may have a curved shape. In an exemplary embodiment, a portion of the interface between the light-transmitting pattern 53 and the second light-reflecting pattern 55 may be formed in a circular shape. At least a portion of the second light-reflecting pattern 55 may have a concave shape relative to the side surface of the light-emitting chip 20 or relative to the side surface of the first light-reflecting pattern 51.

[0036] Reference Figure 8 The interface between the light-transmitting pattern 53 and the second light-reflecting pattern 55 may be formed in a circular shape. At least a portion of the second light-reflecting pattern 55 may have a convex shape relative to the side surface of the light-emitting chip 20 or relative to the side surface of the first light-reflecting pattern 51 .

[0037] Reference Fig. 9, the first wavelength conversion layer 57A may be formed on the first surface 20S1 of the light emitting chip 20, and the second wavelength conversion layer 57B may be formed adjacent to the side surface of the light emitting chip 20 and the side surface of the first light reflecting pattern 51. The second wavelength conversion layer 57B may be in direct contact with the side surface of the light emitting chip 20 and the side surface of the first light reflecting pattern 51. The bottom surface 57BS2 of the second wavelength conversion layer 57B, the bottom surface 51S2 of the first light reflecting pattern 51, the bottom surface of the first terminal 43, and the bottom surface of the second terminal 44 may be exposed in substantially the same plane.

[0038] The first wavelength conversion layer 57A may have a first thickness T1. The first thickness T1 may be between 30 μm and 300 μm. In an exemplary embodiment, the first thickness T1 may be about 90 μm. The horizontal width of the second wavelength conversion layer 57B may be defined as a second thickness T2. The ratio of the first thickness T1 to the second thickness T2 may be between 1:2 and 1:5.

[0039] The top surface of the second wavelength conversion layer 57B and the first surface 20S1 of the light emitting chip 20 may be substantially coplanar. The bottom surface of the first wavelength conversion layer 57A may be in contact with the top surface of the second wavelength conversion layer 57B and the first surface 20S1 of the light emitting chip 20. An interface may be formed between the bottom surface of the first wavelength conversion layer 57A and the top surface of the second wavelength conversion layer 57B. The interface between the bottom surface of the first wavelength conversion layer 57A and the top surface of the second wavelength conversion layer 57B may be substantially coplanar with the first surface 20S1. The side surface of the first wavelength conversion layer 57A and the side surface of the second wavelength conversion layer 57B may be substantially coplanar.

[0040] In an exemplary embodiment, the first light reflection pattern 51 may correspond to a light reflection pattern.

[0041] Reference Fig.10 , the first wavelength conversion layer 57A and the second wavelength conversion layer 57B may be formed integrally. The second wavelength conversion layer 57B may be a continuous structure of the first wavelength conversion layer 57A.

[0042] Reference Fig.11 , the bottom surface 57BS2 of the second wavelength conversion layer 57B may be formed at a higher level than the bottom surface 51S2 of the first light reflecting pattern 51. The step between the bottom surface 57BS2 of the second wavelength conversion layer 57B and the bottom surface 51S2 of the first light reflecting pattern 51 may be represented by a fourth height D4, which may be between 10 μm and 30 μm. The bottom surface 57BS2 of the second wavelength conversion layer 57B may be formed at a level between the top surface 51S1 and the bottom surface 51S2 of the first light reflecting pattern 51.

[0043] Reference Fig.12 , the upper corner of the wavelength conversion layer 57 may be formed into a round shape.

[0044] Reference Fig.13 , the lowermost end 57S2 of the wavelength conversion layer 57 may be formed at a level higher than the bottom surface 51S2 of the first light reflecting pattern 51. The step between the lowermost end 57S2 of the wavelength conversion layer 57 and the bottom surface 51S2 of the first light reflecting pattern 51 may be represented by a fifth height D5, which may be between 10 μm and 30 μm. The lowermost end 57S2 of the wavelength conversion layer 57 may be formed at a level between the bottom surface 51S2 and the top surface 51S1 of the first light reflecting pattern 51.

[0045] Figures 14 to 22 is a cross-sectional view illustrating a method of manufacturing a light emitting device according to an exemplary embodiment of the inventive concept.

[0046] Reference Fig.14 , a plurality of light emitting chips 20 may be formed. Each of the plurality of light emitting chips 20 may include a substrate 21, a buffer layer 23, a first semiconductor layer 25, an active layer 27, a second semiconductor layer 29, an upper electrode 31, a first insulating layer 33, a first interconnector 35, a second interconnector 37, and a second insulating layer 39. In each of the plurality of light emitting chips 20, a first surface 20S1 and a second surface 20S2 opposite to the first surface 20S1 may be defined.

[0047] According to an exemplary embodiment, the substrate 21 may include a material having excellent transmittance. The substrate 21 may include sapphire (Al 2 O 3 ), spinel (MgAl 2 O 4 ), GaN, SiC, ZnO, ZnS, GaP, SiO 2 , silicone resin, epoxy resin, polyimide resin, ceramic, AlN or a combination thereof. In an exemplary embodiment, the substrate 21 may include sapphire. The buffer layer 23 may be formed on the substrate 21. The buffer layer 23 may be used to relieve stress between the substrate 21 and the first semiconductor layer 25. The buffer layer 23 may be formed on the substrate 21 using an epitaxial growth method. The buffer layer 23 may be used to relieve crystal defects between the substrate 21 and the first semiconductor layer 25. The buffer layer 23 may include at least some of the materials of the substrate 21 and the first semiconductor layer 25. In an exemplary embodiment, the buffer layer 23 may include AlN. The buffer layer 23 may be omitted.

[0048] The first semiconductor layer 25 may be formed on the buffer layer 23. The first semiconductor layer 25 may include an n-type semiconductor layer. The first semiconductor layer 25 may include an Al a In bGa (1-a-b) The material represented by N (0≤a≤1, 0≤b≤1, and 0≤a+b≤1). In an exemplary embodiment, the first semiconductor layer 25 may include a GaN layer containing n-type impurities. The n-type impurities may include Si, Ge, Sn, Se, Te, or a combination thereof. The first semiconductor layer 25 may be formed on the buffer layer 23 using an epitaxial growth method.

[0049] The active layer 27 may be formed on the first semiconductor layer 25. The active layer 27 may include a single quantum well (SQW) structure, a multiple quantum well (MQW) structure, a nanorod structure, a quantum wire structure, a quantum dot structure, or a combination thereof. In an exemplary embodiment, the active layer 27 may include an MQW structure in which a quantum well layer and a quantum barrier layer are alternately stacked. The quantum well layer / quantum barrier layer may have one or more paired structures of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs, and GaP (InGaP) / AlGaP. The quantum well layer may include a material having a band gap lower than that of the quantum barrier layer. The active layer 27 may be formed on the first semiconductor layer 25 using an epitaxial growth method.

[0050] The second semiconductor layer 29 may be formed on the active layer 27. The second semiconductor layer 29 may include a p-type semiconductor layer. The second semiconductor layer 29 may include a a In b Ga (1-a-b) N (0≤a≤1, 0≤b≤1, 0≤a+b≤1). In an exemplary embodiment, the second semiconductor layer 29 may include a GaN layer containing p-type impurities. The p-type impurities may include Mg, Zn, Ca, Sr, Ba, or a combination thereof. The second semiconductor layer 29 may be formed on the active layer 27 using an epitaxial growth method. In an exemplary embodiment, the buffer layer 23, the first semiconductor layer 25, the active layer 27, and the second semiconductor layer 29 may be formed by an in-situ process.

[0051] The upper electrode 31 may cover the second semiconductor layer 29. The upper electrode 31 may be in direct contact with the second semiconductor layer 29. The upper electrode 31 may include a metal layer such as silver (Ag).

[0052] The first insulating layer 33 may cover the upper electrode 31 and surround side surfaces of the first interconnection 35 and the second interconnection 37. The first insulating layer 33 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0053] The first interconnect 35 and the second interconnect 37 may be formed on the insulating layer 33. The first interconnect 35 and the second interconnect 37 may include a plurality of contact plugs, a plurality of horizontal interconnects, and a plurality of pads. The first interconnect 35 and the second interconnect 37 may include metal, metal nitride, metal oxide, metal silicide, conductive carbon, or a combination thereof. The first interconnect 35 and the second interconnect 37 may include a plurality of different material layers.

[0054] The first interconnect 35 may pass through the first insulating layer 33, the upper electrode 31, the second semiconductor layer 29, and the active layer 27, and directly contact the first semiconductor layer 25. The lowermost end of the first interconnect 35 may be formed at a lower level than the uppermost end of the first semiconductor layer 25. The first insulating layer 33 may be interposed between the first interconnect 35 and the upper electrode 31, between the first interconnect 35 and the second semiconductor layer 29, and between the first interconnect 35 and the active layer 27. The second interconnect 37 may pass through the first insulating layer 33 and directly contact the upper electrode 31. The second interconnect 37 may be formed to be spaced apart from the first interconnect 35.

[0055] A second insulating layer 39 exposing a portion of the first interconnect 35 and a portion of the second interconnect 37 may be formed on the first insulating layer 33. The second insulating layer 39 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc. One surface of the substrate 21 may be exposed at the first surface 20S1. The second insulating layer 39, a portion of the first interconnect 35, and a portion of the second interconnect 37 may be exposed at the second surface 20S2.

[0056] Reference Fig.15 , a first metal layer 41, a second metal layer 42, a first terminal 43 and a second terminal 44 may be formed on the first interconnect 35 and the second interconnect 37. The first metal layer 41 and the second metal layer 42 may correspond to an under bump metal (UBM). In an exemplary embodiment, the first metal layer 41 and the second metal layer 42 may include Ti, Ni or a combination thereof. The first terminal 43 and the second terminal 44 may include a metal, a metal nitride, a metal oxide, a metal silicide, a conductive carbon, or a combination thereof. In an exemplary embodiment, the first terminal 43 and the second terminal 44 may include a solder bump. The first terminal 43 and the second terminal 44 may include tin-silver-copper (Sn-Ag-Cu).

[0057] The first metal layer 41 may be formed on the exposed surface of the first interconnection 35. The second metal layer 42 may be formed on the exposed surface of the second interconnection 37. The first terminal 43 may be formed on the first metal layer 41, and the second terminal 44 may be formed on the second metal layer 42. The first terminal 43 and the second terminal 44 may protrude to a higher level than the second insulating layer 39. The upper side of the first terminal 43 and the upper side of the second terminal 44 may be formed in a round shape.

[0058] Reference Fig.16 The first light reflecting layer 51L may be formed on the second surface 20S2 of the plurality of light emitting chips 20. The first light reflecting layer 51L may cover the second insulating layer 39, the first terminal 43, and the second terminal 44. According to an exemplary embodiment, the first light reflecting layer 51L may include TiO 2 、TaO 2 、ZrO 2 、SiO 2 、Al 2 O 3 、Al(OH) 3 MgCO 3 、ZnO 2 , Nb 2 O 5 、MgO、Mg(OH) 2 、SrO、In 2 O 3 、HFO、SeO、Y 2 O 3 、SiN、AlN、AlON、MgF 2 or a combination thereof.

[0059] In an exemplary embodiment, the first light reflecting layer 51L may include TiO 2 The process of forming the first light reflecting layer 51L may include a process of dispensing a liquid or a flexible material onto the second surface 20S2 and a process of curing the liquid or the flexible material. The first light reflecting layer 51L may have a reflectivity of 10% to 97%. For example, a material such as WR-3100, WR-3110, WR-3120 (Dow Chemical Company) or a combination thereof may be used as a material for forming the first light reflecting layer 51L.

[0060] Reference Fig.17 , a planarization process may be used to partially remove the first light reflecting layer 51L, the first terminal 43, and the second terminal 44. Top surfaces of the first light reflecting layer 51L, the first terminal 43, and the second terminal 44 may be exposed in substantially the same plane.

[0061] Reference Fig.18, a plurality of light emitting chips 20 may be separated from each other using a separation process. In the process of separating the plurality of light emitting chips 20 from each other, the first light reflecting layer 51L may also be segmented so that a first light reflecting pattern 51 may be formed. Each of the plurality of light emitting chips 20 may include a first surface 20S1 and a second surface 20S2. The first light reflecting pattern 51, the first terminal 43 and the second terminal 44 may be formed on the second surface 20S2. The top surface of the first light reflecting pattern 51, the top surface of the first terminal 43 and the top surface of the second terminal 44 may be exposed in substantially the same plane. The side surface of a selected one of the plurality of light emitting chips 20 and the side surface of the first light reflecting pattern 51 may be substantially coplanar. The process of separating the plurality of light emitting chips 20 may include a scribing process, a cutting process or a combination thereof.

[0062] Reference Fig.19 , each of the plurality of light emitting chips 20 may be mounted on the first auxiliary substrate 81. The top surface of the first light reflecting pattern 51, the top surface of the first terminal 43, and the top surface of the second terminal 44 may be bonded to the first auxiliary substrate 81. A light-transmitting material 53D may be formed on the second auxiliary substrate 83. The light-transmitting material 53D may include a material different from that of the first light reflecting pattern 51. In an exemplary embodiment, the light-transmitting material 53D may include SiO 2 MgF 2 The light-transmitting material 53D may be a liquid or a flexible material. The light-transmitting material 53D may have various shapes due to its viscosity, composition, and surface tension. In an exemplary embodiment, the light-transmitting material 53D may be formed in a hemispherical shape on the second auxiliary substrate 83. The light-transmitting material 53D may include silicone.

[0063] Reference Fig. 20 , the light-transmitting material 53D may be combined with the plurality of light-emitting chips 20 between the first auxiliary substrate 81 and the second auxiliary substrate 83, so that the light-transmitting pattern 53 may be formed. The first surface 20S1 may be buried in the light-transmitting pattern 53. The light-transmitting pattern 53 may cover the side surfaces of the plurality of light-emitting chips 20 and extend to the side surfaces of the first light-reflecting pattern 51. The side surfaces of the plurality of light-emitting chips 20 may be completely covered by the light-transmitting pattern 53. The light-transmitting pattern 53 may directly contact the side surfaces of the plurality of light-emitting chips 20 and the side surfaces of the first light-reflecting pattern 51. The uppermost end of the light-transmitting pattern 53 may be formed at a level higher than the second surface 20S2. The uppermost end of the light-transmitting pattern 53 may be formed between the second surface 20S2 and the first auxiliary substrate 81. The light-transmitting pattern 53 may have a width that increases toward the first surface 20S1. The light-transmitting pattern 53 may include a side surface that is inclined outward.

[0064] like Figures 1 to 8As shown, the light-transmitting pattern 53 may have various shapes. In an exemplary embodiment, due to the viscosity, composition and surface tension of the light-transmitting material 53D, the light-transmitting pattern 53 may have various shapes. In an exemplary embodiment, the light-transmitting pattern 53 may be formed using an injection molding method, and a detailed description of the injection molding method will be omitted for brevity.

[0065] Reference Fig.21 , the second auxiliary substrate 83 is removed, and a wavelength conversion layer 57 may be formed on the light-transmitting pattern 53. The first auxiliary substrate 81 is removed, and a second light-reflecting layer 55L may be formed on a side surface of the light-transmitting pattern 53. The second light-reflecting layer 55L may be in direct contact with a side surface of the first light-reflecting pattern 51. The second light-reflecting layer 55L may be in direct contact with a side surface of the light-transmitting pattern 53.

[0066] The second light reflective layer 55L may include a material different from that of the light-transmitting pattern 53. According to an exemplary embodiment, the second light reflective layer 55L may include TiO 2 、TaO 2 、ZrO 2 、SiO 2 、Al 2 O 3 、Al(OH) 3 MgCO 3 、ZnO 2 , Nb 2 O 5 、MgO、Mg(OH) 2 、SrO、In 2 O 3 、HFO、SeO、Y 2 O 3 、SiN、AlN、AlON、MgF 2 In an exemplary embodiment, the second light reflecting layer 55L may include TiO having a lower refractive index than the first light reflecting pattern 51. 2 The second light reflecting layer 55L may include a material layer having a reflectivity of 91% to 97%. The second light reflecting layer 55L may include a material having a higher reflectivity than the first light reflecting pattern 51. The second light reflecting layer 55L may include TiO having a lower intensity than the first light reflecting pattern 51. 2 . For example, a material such as WR-3100, WR-3110, WR-3120 (Dow Chemical Company) or a combination thereof may be used as a material for forming the second light reflecting layer 55L. The wavelength conversion layer 57 may be formed by mixing a light-transmitting material and a wavelength conversion material. The wavelength conversion layer 57 may include a fluorescent layer. In an exemplary embodiment, the wavelength conversion layer 57 may include phosphor (P). The wavelength conversion layer 57 may be attached in the form of a film.

[0067] Reference Fig. 22 , the second light reflecting layer 55L may be divided so that the second light reflecting pattern 55 may be formed. When the second light reflecting layer 55L is divided, the wavelength conversion layer 57 may also be divided. The divided wavelength conversion layer 57 may be in direct contact with the second light reflecting pattern 55 and the light-transmitting pattern 53. The side surface of the divided wavelength conversion layer 57 and the side surface of the second light reflecting pattern 55 may be substantially coplanar.

[0068] Figure 23 to Figure 25 is a cross-sectional view illustrating a method of manufacturing a light emitting device according to an exemplary embodiment of the inventive concept.

[0069] Reference Fig.23 , a plurality of light emitting chips 20 may be mounted on the third auxiliary substrate 85. The plurality of light emitting chips 20 may be spaced apart from each other. The first wavelength conversion layer 57A may be formed on the plurality of light emitting chips 20. Each of the plurality of light emitting chips 20 may be disposed between the third auxiliary substrate 85 and the first wavelength conversion layer 57A. The surface of the first light reflecting pattern 51, the surface of the first terminal 43, and the surface of the second terminal 44 may be bonded to the third auxiliary substrate 85. The first surface 20S1 may be in contact with the first wavelength conversion layer 57A. The first wavelength conversion layer 57A may be formed in a film shape.

[0070] Reference Fig.24 , the second wavelength conversion layer 57B may be formed on the side surfaces of the plurality of light emitting chips 20 and the side surfaces of the first light reflecting pattern 51. The second wavelength conversion layer 57B may be used to completely fill the gaps between the plurality of light emitting chips 20. The second wavelength conversion layer 57B may be in contact with the first wavelength conversion layer 57A. An interface 57S may be formed between the first wavelength conversion layer 57A and the second wavelength conversion layer 57B. The interface 57S and the first surface 20S1 may be substantially coplanar. The second wavelength conversion layer 57B may be in direct contact with the side surfaces of the plurality of light emitting chips 20 and the side surfaces of the first light reflecting pattern 51.

[0071] Reference Fig.25 , each of the first wavelength conversion layer 57A and the second wavelength conversion layer 57B may be segmented. When the first wavelength conversion layer 57A and the second wavelength conversion layer 57B are segmented, the third auxiliary substrate 85 may also be segmented. The side surfaces of the segmented first wavelength conversion layer 57A and the side surfaces of the segmented second wavelength conversion layer 57B may be substantially coplanar. The third auxiliary substrate 85 is removed so that the bottom surfaces of the segmented second wavelength conversion layer 57B, the bottom surfaces of the first light reflecting patterns 51, the bottom surfaces of the first terminals 43, and the bottom surfaces of the second terminals 44 may be exposed in substantially the same plane.

[0072] Fig.26 and Fig. 27 is a cross-sectional view illustrating a method of manufacturing a light emitting device according to an exemplary embodiment of the inventive concept.

[0073] Reference Fig.26 , a plurality of light emitting chips 20 may be mounted on the fourth auxiliary substrate 87. The plurality of light emitting chips 20 may be spaced apart from each other. A surface of the first light reflecting pattern 51, a surface of the first terminal 43, and a surface of the second terminal 44 may be bonded to the fourth auxiliary substrate 87. The wavelength conversion layer 57 may be formed on a side surface of the first light reflecting pattern 51, on the first surface 20S1, and on a side surface of the plurality of light emitting chips 20. The wavelength conversion layer 57 may be in direct contact with a side surface of the first light reflecting pattern 51, the first surface 20S1, and a side surface of the plurality of light emitting chips 20.

[0074] Reference Fig. 27 , the wavelength conversion layer 57 may be divided. While the wavelength conversion layer 57 is divided, the fourth auxiliary substrate 87 may also be divided. The fourth auxiliary substrate 87 is removed so that the bottom surface of the wavelength conversion layer 57, the bottom surface of the first light reflecting pattern 51, the bottom surface of the first terminal 43, and the bottom surface of the second terminal 44 may be exposed in substantially the same plane.

[0075] According to an exemplary embodiment of the present invention, a first light reflecting pattern, a light transmitting pattern, and a second light reflecting pattern are provided. The light transmitting pattern is formed between each side surface of the light emitting chip and the second light reflecting pattern, and extends between the first light reflecting pattern and the second light reflecting pattern. The combination of the first light reflecting pattern, the light transmitting pattern, and the second light reflecting pattern can maximize the reflection efficiency of the light emitted from the light emitting chip. A light emitting device that is conducive to high-density integration and also has an improved luminous flux can be realized.

[0076] Although the embodiments of the present invention have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the present invention and without changing its essential features. Therefore, the above embodiments should be considered to be illustrative only and not for the purpose of limitation.

Claims

1. A light emitting device, comprising: A light emitting chip comprising a first surface and a second surface opposite to the first surface; a first light reflecting pattern formed on the second surface; a plurality of terminals connected to the light emitting chip by passing through the first light reflecting pattern; a second light reflecting pattern disposed on an outer side surface of the first light reflecting pattern; a light-transmitting pattern formed between the light-emitting chip and the second light-reflecting pattern and extending between the first light-reflecting pattern and the second light-reflecting pattern; as well as a wavelength conversion layer formed on a first surface of the light emitting chip, Wherein, the outer surface of the light emitting chip and the outer surface of the first light reflecting pattern are substantially coplanar.

2. The light emitting device according to claim 1, wherein: The second light reflecting pattern is in direct contact with the first light reflecting pattern.

3. The light emitting device according to claim 1, wherein: One end of the light-transmitting pattern is located between the outer side surface of the first light-reflecting pattern and the second light-reflecting pattern, and is formed at a level between the second surface of the light-emitting chip and a bottom surface of the first light-reflecting pattern.

4. The light emitting device according to claim 1, wherein: One end of the light-transmitting pattern is adjacent to a lower end of the outer side surface of the first light-reflecting pattern.

5. The light emitting device according to claim 1, wherein: A bottom surface of the first light reflecting pattern, bottom surfaces of the plurality of terminals, and a bottom surface of the second light reflecting pattern are substantially coplanar.

6. The light emitting device according to claim 1, wherein: The lowermost end of the second light reflecting pattern is formed at a level lower than the second surface of the light emitting chip, and The uppermost end of the second light reflecting pattern is formed at a level higher than or equal to a level of the first surface of the light emitting chip.

7. The light emitting device according to claim 1, wherein: The second light reflecting pattern includes a material having a higher reflectivity than the first light reflecting pattern.

8. The light emitting device according to claim 1, wherein: The second light reflecting pattern includes a material having a lower intensity than that of the first light reflecting pattern.

9. The light emitting device according to claim 1, wherein: An interface between the light-transmitting pattern and the second light-reflecting pattern is inclined at 45 to 70 degrees with respect to an outer side surface of the first light-reflecting pattern.

10. A light emitting device, comprising: A light emitting chip comprising a first surface and a second surface opposite to the first surface; a first light reflecting pattern formed on the second surface; a plurality of terminals connected to the light emitting chip by passing through the first light reflecting pattern; a second light reflecting pattern disposed on an outer side surface of the first light reflecting pattern; as well as a wavelength conversion layer formed on the first surface of the light emitting chip, wherein the bottom surface of the first light reflecting pattern and the bottom surfaces of the plurality of terminals are substantially coplanar, The outer surface of the light emitting chip and the outer surface of the first light reflecting pattern are substantially coplanar, and The second light reflecting pattern includes at least a portion that contacts an outer surface of the first light reflecting pattern and extends on the outer surface of the first light reflecting pattern.

11. The light emitting device according to claim 10, further comprising a light-transmitting pattern formed between the second light-reflecting pattern and the light-emitting chip and extending between the first light-reflecting pattern and the second light-reflecting pattern, in, The wavelength conversion layer extends onto the second light-reflective pattern and the light-transmitting pattern.

12. The light emitting device according to claim 10, wherein: The second light reflecting pattern includes TiO 2 having a higher reflectivity than the first light reflecting pattern.

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