Voltage Controlled Oscillator Circuit

Abstract

The present disclosure relates to a voltage-controlled oscillator circuit, which includes: a charge pump configured to generate a tuning voltage having a minimum operating voltage; an offset voltage source configured to generate an offset voltage based on the minimum operating voltage; and a voltage-controlled oscillator (VCO) configured to provide an oscillator frequency based on the tuning voltage and the offset voltage.

Description

Technical Field

[0001] The present disclosure relates to a voltage controlled oscillator circuit, and more particularly but not exclusively to a voltage controlled oscillator circuit for a phase locked loop system in a radar transceiver. Background Art

[0002] Radar transceivers are widely used in automotive applications such as impact detection and driver assistance systems. In some applications, it is required to provide a radar transceiver that operates in multiple frequency bands. For example, a dual-band radar transceiver can operate at 76 to 77 GHz and 77 to 81 GHz. Dedicated voltage controlled oscillators (VCOs) can be provided to implement each of the operating frequency bands of the radar transceiver through a phase-locked loop (PLL)-based frequency synthesizer.

[0003] In some applications, it is desirable to be able to switch from one operating frequency band to another in real time. Due to timing and frequency alignment issues, it is difficult or infeasible to use two VCOs. Summary of the Invention

[0004] According to a first aspect of the present disclosure, there is provided a voltage controlled oscillator circuit, the voltage controlled oscillator circuit comprising:

[0005] A charge pump configured to generate a tuning voltage having a minimum operating voltage;

[0006] An offset voltage source configured to generate an offset voltage based on the minimum operating voltage; and

[0007] A voltage controlled oscillator, VCO, configured to provide an oscillator frequency based on the tuning voltage and the offset voltage.

[0008] The present disclosure solves the above problems by compensating for the minimum operating voltage of the charge pump within the VCO. In this way, the operating constraints of the charge pump are alleviated, which would otherwise limit the operating frequency range of the VCO. As a result, the operating range of the VCO can be extended, so that a single VCO can be used to cover multiple operating frequency bands. For example, the VCO can be used to cover the frequency ranges of both 76 to 77 GHz and 77 to 81 GHz. That is to say, the voltage controlled oscillator circuit can enable a radar transceiver to have a single PLL and / or a single VCO for selecting an operating frequency. In this way, the complexity and bill of materials (BOM) of the radar transceiver can be reduced by implementing the voltage controlled oscillator circuit.

[0009] In one or more embodiments, a voltage controlled oscillator includes at least one variable reactor unit. A variable reactor voltage based on an offset voltage may be applied across the variable reactor of the at least one variable reactor unit.

[0010] In one or more embodiments, the variable reactor voltage is based on a difference between a tuning voltage and an offset voltage.

[0011] In one or more embodiments, each of the at least one variable reactor unit includes a pair of variable reactors of opposite polarities.

[0012] In one or more embodiments, the voltage controlled oscillator has a minimum VCO voltage. The offset voltage may be based on a difference between the minimum VCO voltage and a minimum operating voltage of the tuning voltage.

[0013] In one or more embodiments, the voltage controlled oscillator has a maximum VCO voltage. The voltage controlled oscillator circuit may include a high voltage supply configured to provide a high voltage to a charge pump. The high voltage may be based on a sum of the maximum VCO voltage and the offset voltage.

[0014] In one or more embodiments, the high voltage is greater than a sum of the maximum VCO voltage and the offset voltage. The offset voltage may be greater than a difference between the minimum operating voltage and the minimum VCO voltage.

[0015] In one or more embodiments, the offset voltage source includes a low noise regulator.

[0016] In one or more embodiments, it further includes a temperature compensation circuit configured to provide a temperature compensation voltage to the voltage controlled oscillator.

[0017] In one or more embodiments, the temperature compensation voltage is provided to different variable reactor units to achieve the tuning voltage.

[0018] In one or more embodiments, the offset voltage is a first offset voltage. The offset voltage source may be further configured to generate a second offset voltage according to a temperature compensation minimum operating voltage of the temperature compensation circuit. The offset voltage source may be configured to provide the first offset voltage to different variable reactor units to achieve the second offset voltage.

[0019] In one or more embodiments, the first offset voltage and the second offset voltage are fixed DC voltages.

[0020] According to another aspect, a phase-locked loop (PLL) system is provided, which includes:

[0021] A phase comparator; and

[0022] Voltage-controlled oscillator circuit. The charge pump can be configured to provide a tuning voltage based on an input voltage received by the charge pump. The input voltage can be based on an output signal from a phase comparator.

[0023] According to another aspect, a radar transceiver including a PLL system is provided. The radar transceiver can have a single VCO for operating within a first frequency band or a second frequency band.

[0024] In one or more embodiments, the VCO has an oscillator frequency range of 5 GHz or greater.

[0025] While the present disclosure admits of various modifications and alternative forms, specific examples thereof have been shown by way of illustration in the drawings and will be described in detail. It should be understood, however, that other embodiments beyond the specific embodiments described are also possible. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0026] The foregoing discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim sets. The drawings and the following detailed description also illustrate various example embodiments. The various example embodiments can be more fully understood by considering the following detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0028] Figure 1 An example embodiment of a phase-locked loop (PLL) system including a voltage-controlled oscillator circuit is shown;

[0029] Figure 2a A schematic block diagram of an example embodiment of a voltage-controlled oscillator circuit for a PLL system is shown;

[0030] Figure 2b A schematic block diagram of an example embodiment of a voltage-controlled oscillator circuit for a PLL system is shown;

[0031] Figure 2c Shows for Figure 2b A circuit diagram of a variable reactance unit in the VCO shown in;

[0032] Figure 3 An analog curve of the VCO oscillator frequency versus the charge pump tuning voltage is shown;

[0033] Figure 4 Curves of phase noise versus oscillator frequency for various VCO circuits are shown; and

[0034] Figure 5A flowchart showing a voltage generation method before calibrating a phase-locked loop in an extended tuning range. DETAILED DESCRIPTION

[0035] NXP's 'Eagle' dual-band (76 - 77 GHz and 77 - 81 GHz) automotive radar transceiver uses two voltage-controlled oscillators (VCOs) in its main phase-locked loop (PLL) system to achieve operation across two frequency bands. The two dedicated VCOs allow the tuning range and phase noise requirements to meet the application range. The two VCOs are independently laser-trimmed to cover the corresponding frequency bands. As will be further described below, referring to Figure 2b , the implementation of the charge pump for providing the tuning voltage Vtune results in an operating constraint where the tuning voltage Vtune has a minimum operating voltage below which the charge pump (and PLL) may not operate properly. In some examples, the minimum operating voltage is approximately 0.6 V. The minimum operating voltage constraint imposed on the tuning voltage during laser trimming has several disadvantages:

[0036] · It results in productivity loss at the probe level;

[0037] · It limits the operating range of each corresponding frequency band due to the loss at the 0.6 V minimum (which results in a reduction of the PLL bandwidth by ~1.8 GHz) and

[0038] · The undershoot of the PLL, especially at low tuning voltages (before calibration), may cause interruptions.

[0039] Some aspects of the present disclosure address problems encountered in a phase-locked loop (PLL) system of a radar transceiver including a phase comparator and a charge pump for driving a voltage-controlled oscillator (VCO). The charge pump is configured to provide a tuning voltage to the VCO based on an output signal from the phase comparator. The minimum operating voltage of the tuning voltage is a practical limitation for providing the correct functionality of the circuit in some embodiments. In Figure 1 , 2a and the example embodiments of 2b, an offset voltage is applied within the VCO to compensate for the minimum operating voltage.

[0040] Figure 1A phase locked loop (PLL) system 100 including a VCO circuit is shown. The VCO circuit includes a voltage controlled oscillator (VCO) 102, a charge pump 104, an offset voltage source 106, a temperature compensation circuit 108, and others.

[0041] The offset voltage source 106 and the temperature compensation circuit 108 provide inputs to the VCO 102. The charge pump 104 is provided within the loop of the PLL system 100. The charge pump is configured to convert an input voltage Vb associated with the phase difference of the PLL system into a tuning voltage Vtune. The tuning voltage is provided to the VCO 202 via a low pass filter 105. The low pass filter 105 can also be regarded as a component of the charge pump 104.

[0042] The operation of the VCO circuit is further described with reference to FIG. 2 below.

[0043] In addition to the voltage controlled oscillator circuit described previously, the PLL system 100 further includes standard PLL components 160. The standard PLL components 160 include other components within the PLL loop between the output of the VCO 102 and the input of the charge pump 104. Such components include a first amplifier 162, a static frequency divider (SFD) 164, a second amplifier 166, a programmable frequency divider 168, and a PFD 170 serially arranged between the VCO 102 and the charge pump 104. The output of the programmable frequency divider 168 is also provided to the ECL of the CMOS converter unit 172 to drive a digital controller. The ECL of the CMOS converter unit provides a signal to a sigma delta modulator 174 and a ramp generator 176. The sigma delta modulator 174 is also controlled by the output of the ramp generator 176. The output of the sigma delta modulator 174 is fed back to the programmable frequency divider 168.

[0044] A reference oscillator signal is also fed from a reference oscillator 180 to the PFD 170. The reference oscillator 180 also receives a control signal from the digital controller via an ALC unit 182. The signal from the reference oscillator 180 is also fed back to the digital controller through a differential signal unit 184 to generate timing.

[0045] Figure 2aA schematic block diagram showing a voltage-controlled oscillator circuit 200' for a phase-locked-loop (PLL) system is presented. The voltage-controlled oscillator circuit 200' includes a voltage-controlled oscillator (VCO) 202', a charge pump 204', and an offset voltage source 206'.

[0046] The charge pump 204' is configured to generate a tuning voltage Vtune. The tuning voltage Vtune has a minimum operating voltage, which is an actual limitation of the charge pump 204'.

[0047] The offset voltage source 206' is configured to generate an offset voltage Voffset based on the minimum operating voltage. For example, the offset voltage Voffset can be set to the same magnitude as the minimum operating voltage.

[0048] The VCO 202' has a minimum VCO voltage and a maximum VCO voltage that define a tuning range Vrange. The tuning voltage Vtune is selected to take a value between the minimum VCO voltage and the maximum VCO voltage. The maximum VCO voltage is managed by fine-tuning the supply voltage VCC_HV in the charge pump 204', while preventing avalanche noise multiplication by tuning the input voltage Vb during calibration. In practice, depending on the Vtune voltage, the input voltage Vb of the charge pump is adjusted to reduce the VCE of the last stage of the charge pump 204'.

[0049] The oscillator frequency of a typical VCO is based on the tuning voltage Vtune. However, the minimum operating voltage is usually greater than the minimum VCO voltage, which results in a loss of the operating range. In the current situation, the VCO 202' is configured to provide the oscillator frequency based on the offset voltage Voffset in addition to the tuning voltage Vtune. In this way, the offset voltage Voffset provided by the offset voltage source 206' can be used to compensate for the minimum operating voltage of the charge pump 204', thereby increasing the operating range of the oscillator frequency Ofreq provided by the VCO 202'.

[0050] The tuning range of a given PLL system is increased by solving for the low and high Vtune limits: the lower limit is generally specified by the charge pump, and the upper limit is specified by the required maximum Vtune voltage generated. The technique is based on shifting the Vtune range to higher values, where the lower limit is the minimum charge pump limit (Vcp) and the maximum Vtune generated by the power supply. For maximum Vtune generation, the charge pump is adapted to prevent avalanche noise multiplication by tuning the input voltage Vb during calibration. In practice, depending on the Vtune voltage, the input voltage Vb of the charge pump is adjusted to reduce the VCE of the last stage of the charge pump 204'. This proposal allows elimination of the yield loss associated with the minimum Vtune constraint of the PLL to be reduced.

[0051] The following reference Figure 2b shows an example of the operation of a voltage-controlled oscillator circuit and shows the curves of the performance of this circuit in Figure 3 and 4

[0052] Figure 2b A circuit diagram showing a specific example of a voltage-controlled oscillator circuit 200 for a phase-locked loop (PLL) system. The voltage-controlled oscillator circuit 200 includes a voltage-controlled oscillator (VCO) 202, a charge pump 204, an offset voltage source 206, and a temperature compensation circuit 208.

[0053] The VCO 202 includes four variable reactor units 209a-d. Each variable reactor unit 209a-d includes four terminals.

[0054] Figure 2c Shows for Figure 2b the variable reactor unit 209 in the VCO shown in. A first capacitor 269 is serially disposed between a first terminal 265 and a second terminal 266 of the variable reactor unit 209 and a first variable reactor 270. A second capacitor 271 is serially disposed between the first terminal 265 and a third terminal 267 of the variable reactor unit 209 and a second variable reactor 272. The polarity of the first variable reactor 270 is opposite to the polarity of the second variable reactor 272. In this example, the respective cathodes of the first variable reactor 270 and the second variable reactor 272 are directly connected to the first terminal 265. The node between the first capacitor 269 and the first variable reactor 270 is coupled to the fourth terminal 268 via a first load 273. The node between the second capacitor 271 and the second variable reactor 272 is coupled to the fourth terminal 268 via a second load 274.

[0055] Returning to Figure 2b , the second and third terminals of the first variable reactor unit 209a and the second variable reactor unit 209b are indirectly coupled to the power supply.

[0056] ​In this example, a voltage divider circuit is provided between VCC and ground. The voltage divider circuit includes a conductive channel of an enable / disable transistor 214, a first splitter load 210, a second splitter load 212, and a forward-biased diode 216 arranged in series. The enable / disable transistor 214 provides a way to start or stop the VCO 202. A node 211 of the voltage divider circuit between the first splitter load 210 and the second splitter load 212 is coupled to the second ends of the first variable reactor unit 209a and the second variable reactor unit 209b via a first transmission line 218. The node 211 is also coupled to the third ends of the first variable reactor unit 209a and the second variable reactor unit 209b via a second transmission line 220.

[0057] A first output (O+) of the VCO 202 is provided according to a signal at the second ends of the variable reactor units 209a-d. In this example, signals from the variable reactor units 209a-d are combined on a first output path, including a first output transistor 222. A capacitor is provided between the base and the emitter of the first output transistor 222. The base of the first output transistor 222 is connected to the second ends of the first variable reactor unit 209a and the second variable reactor unit 209b via a third transmission line 224 that is serially coupled with a first variable transmission line 226 for laser trimming and re-aligning the frequency of the VCO. The collector of the first output transistor 222 is coupled to VCC via a fourth transmission line 227 and a fifth transmission line 228. The first output signal is obtained at a node between the fourth transmission line 227 and the fifth transmission line 228. A sixth transmission line couples the emitter of a first output transistor 229 to ground via a ground load 230. The second ends of the third variable reactor unit 209c and the fourth variable reactor unit 209d are connected to the emitter of the first output transistor 222.

[0058] Provide a second output (O-) of the VCO 202 according to the signals at the third terminals of the variable reactor units 209a-d. In this example, the signals from the variable reactor units 208a-d are combined on a second output path, including the second output transistor 232. A capacitor is provided between the base and the emitter of the second output transistor 232. The base of the second output transistor 232 is connected to the third terminals of the first variable reactor unit 209a and the second variable reactor unit 209b via a seventh transmission line 234 that is serially coupled to a second variable transmission line 236 used for laser trimming and re-aligning the frequency of the VCO. The collector of the second output transistor 232 is coupled to VCC via an eighth transmission line 237 and a ninth transmission line 238. The second output signal is obtained at the node between the eighth transmission line 237 and the ninth transmission line 238. A tenth transmission line couples the emitter of the second output transistor 239 to ground via a ground load 230. The third terminals of the third variable reactor unit 209c and the fourth variable reactor unit 209d are connected to the emitter of the second output transistor 232.

[0059] The charge pump is configured to convert an input voltage Vb that can be associated with the phase difference of the PLL system into a tuning voltage Vtune. The tuning voltage Vtune is provided to the first ends of the first variable reactor unit 209a and the third variable reactor unit 209c of the 202.

[0060] In this example, the charge pump 204 includes a first charge pump transistor 242 and a second charge pump transistor 244. The first charge pump transistor 242 and the second charge pump transistor 244 provide a transistor differential pair. The base of the first charge pump transistor 242 is configured to receive the input voltage Vb. The input voltage Vb can vary, which simultaneously shifts the emitter voltage Ve. In fact, the PLL integrates a calibration mechanism that measures Vtune and adjusts the input voltage Vb. When Vtune is high, Vb is shifted up and thus Ve reduces the voltage VCE of the xHBT.

[0061] The collector of the first charge pump transistor 242 is connected to a 'high voltage' VCC_HV (e.g., it can have about 5V) via a first charge pump current source 246. The tuning voltage Vtune is provided as the output of the charge pump 204 through a low-pass filter 205 connected to the collector of the first charge pump transistor 242.

[0062] The emitter of the first charge pump transistor 242 is connected to the emitter of the second charge pump transistor 244. The emitters of the first charge pump transistor 242 and the second charge pump transistor 244 are coupled to ground via a second charge pump current source 248.

[0063] In this example, an offset voltage source 206 is provided by a low noise regulator (LNR). The offset voltage source 206 is configured to provide a first offset voltage Voffset1 and a second offset voltage Voffset2. The LNR can provide the first offset voltage Voffset1 and the second offset voltage Voffset2, which have an output noise level in a relatively small nVs (nanovolt) range, such as less than 10 or 20 nVs. The first offset voltage Voffset1 can be equal to or different from the second offset voltage Voffset2.

[0064] The minimum VCO voltage is typically 0V. In the case where the minimum VCO voltage is 0V for the illustrated example, the first offset voltage Voffset1 is selected to be equal to the minimum operating voltage of the tuning voltage Vtune. In the case where the minimum VCO voltage is not 0V for the illustrated example, the first offset voltage Voffset1 is selected to be equal to the difference between the minimum operating voltage of the tuning voltage Vtune and the minimum VCO voltage.

[0065] The high voltage VCC_HV can be based on the sum of the maximum VCO voltage and the offset voltage. For example, the high voltage VCC_HV can be greater than or equal to (maximum VCO voltage - minimum VCO voltage + first offset voltage Voffset1).

[0066] The first offset voltage Voffset1 is provided to the fourth terminal of the first variable reactor unit 209a and the third variable reactor unit 209c. The first offset voltage Voffset1 and the tuning voltage Vtune are provided to the same variable reactor unit. A respective variable reactor voltage is provided across each of the variable reactors in the first variable reactor unit 209a and the third variable reactor unit 209c. These variable reactor voltages are based on the difference between the tuning voltage and the offset voltage. Thus, the effect of applying the offset voltage is to compensate the variable reactor voltage for the minimum operating voltage of the tuning voltage. This compensation results in an increase in the dynamic range of the VCO, as discussed further below with reference to Figure 3 and 4 discussed further.

[0067] In Figure 2bIn the example shown, the VCO circuit 200 further includes a temperature compensation circuit 208, which includes a current source 250 connected between a high voltage VCC_HV and ground via a temperature compensation resistor 252. VCO temperature compensation can compensate for any temperature variations in the voltage, capacitance, and / or oscillation frequency of the VCO circuit 200. A temperature compensation voltage Vtemp is provided at a node between the current source 250 and the temperature compensation resistor 252. The temperature compensation voltage Vtemp is provided to the first ends of the second variable reactor unit 209b and the fourth variable reactor unit 209d. In this way, the temperature compensation circuit 208 is configured to provide a temperature compensation voltage to the voltage-controlled oscillator 202.

[0068] The offset voltage source 206 is configured to generate a second offset voltage Voffset2 based on the temperature compensation minimum operating voltage of the temperature compensation circuit. The second offset voltage can be a fixed DC voltage. The second offset voltage Voffset2 is provided to the fourth ends of the second variable reactor unit 209b and the fourth variable reactor unit 209d. That is, the second offset voltage Voffset2 and the temperature compensation voltage Vtemp are provided to the same variable reactor unit.

[0069] For safety reasons, to ensure the normal operation of the PLL, a minimum safe Vtune (set to the minimum voltage of the charge pump) can be defined. During calibration, the tuning voltage Vtune is measured and the result is compared with the minimum safe Vtune. If Vtune <= minimum safe Vtune, then an interrupt is generated, indicating the presence of a safety fault. At the system level, the microcontroller unit can then reset the circuit considering the received data to be invalid.

[0070] Figure 3 Simulated curves of the VCO oscillator frequency Ofreq versus the charge pump tuning voltage Vtune are shown for: (i) the VCO circuit without the variable reactor bias 380 (i.e., without compensation for the minimum operating voltage 384 of the charge pump); and (ii) the VCO circuit with the variable reactor bias 382 (i.e., the offset voltage source provides an offset voltage to the VCO to compensate for the minimum operating voltage 384 of the charge pump), as in the VCO circuits, for example, those described above with respect to Figure 1 、 2a and 2b.

[0071] At approximately 0.62V, the minimum operating voltage 384 is indicated by the vertical line. The VCO circuit without the variable inductor bias 380 has a minimum tuning voltage Vtune_min defined by the minimum operating voltage 384 (i.e., 0.62V). The minimum tuning voltage Vtune_min corresponds to an oscillator frequency of 47.1GHz. The maximum tuning voltage Vtune-max is defined by the maximum VCO voltage, which is approximately 4.4V in this example. The maximum tuning voltage Vtune_max corresponds to an oscillator frequency of 49GHz. The minimum tuning voltage Vtune_min and the maximum tuning voltage Vtune_max thus correspond to an oscillator frequency range of 47.1GHz to 49GHz (~1.9GHz).

[0072] Due to the presence of the offset voltage Voffset, for the VCO circuit with the variable inductor bias 382, the relationship between the VCO oscillator frequency Ofreq and the tuning voltage Vtune is shifted relative to the variable inductor without the bias 380. In this example, the offset voltage Voffset is equal to the minimum operating voltage 384 of the charge pump. The VCO circuit with the variable inductor bias 382 still has a minimum tuning voltage Vtune_min defined by the minimum operating voltage 384, i.e., 0.62V. However, the variable inductor voltage based on the difference between the tuning voltage Vtune and the offset voltage Voffset can determine the oscillator frequency Ofreq. The minimum tuning voltage Vtune_min now corresponds to an oscillator frequency of 46.2GHz (shown at point B in the figure). The maximum tuning voltage Vtune_max is based on the sum of the maximum VCO voltage (4.4V) and the offset voltage Voffset (0.6V), i.e., 5V. In this way, the maximum tuning voltage Vtune still corresponds to an oscillator frequency of 49GHz (shown at point C in the figure). The minimum tuning voltage Vtune_min and the maximum tuning voltage Vtune_max thus correspond to an oscillator frequency range of 46.2GHz to 49GHz (~2.8GHz).

[0073] The VCO circuit without the variable inductor bias 380 cannot obtain the oscillation bandwidth A corresponding to the tuning voltage less than the minimum operating voltage 384 of the charge pump. Due to the use of the offset voltage source, the VCO circuit with the variable inductor bias 382 has obtained this bandwidth. Figure 3Point B in shows how the oscillator frequency dependence of the minimum tuning voltage Vtune is converted (using the offset voltage Voffset) to allow the minimum operating voltage 384 of the charge pump. In other words, the tuning range is increased due to the Vtune conversion (Vtune_min > V_charge_pump_min). In this example, the bandwidth gain is approximately 0.9 GHz (from 2.8 GHz to 1.9 GHz). An 1.8 GHz bandwidth gain can be obtained at an oscillation frequency of 77 GHz.

[0074] Figure 4 Shows the simulated curves of phase noise versus oscillator frequency for: (i) a typical VCO 486 (internal VCO phase noise); (ii) a VCO with an offset voltage provided by an offset voltage source 488; and (iii) a VCO with an offset voltage provided by an offset voltage source, where the simulated output noise of the offset voltage source has been reduced by 10 dB 490. The three curves are almost indistinguishable, showing that there is no VCO phase noise degradation due to the presence of the offset voltage provided by the offset voltage source. The offset voltage source can thus have relaxed noise requirements, enabling the die size to be reduced.

[0075] Figure 5 Shows for example see Figure 1 Flowchart describing a voltage generation method 500 before calibrating a phase-locked loop in an extended tuning range. This defines 502 the tuning range Vrange for the VCO. The tuning range Vrange is defined between the limits of the minimum VCO voltage and the maximum VCO voltage. The minimum VCO voltage is set 504 to the minimum operating voltage of the charge pump of the VCO.

[0076] Fine-tune 508 the linear voltage regulator to provide an offset voltage equal to the minimum operating voltage of the charge pump of the VCO. Fine-tune 510 the power supply to generate a high voltage VCC_HV equal to the maximum VCO voltage plus the offset voltage. Then conventionally calibrate 512 the PLL and the PLL is subsequently available for normal operation 514.

[0077] The oscillator frequency of a typical VCO is based on the tuning voltage Vtune. However, the minimum operating voltage is usually greater than the minimum VCO voltage, resulting in a loss of the operating range. In the current situation, the VCO 202' is configured to provide the oscillator frequency in accordance with an offset voltage Voffset in addition to the tuning voltage Vtune. In this way, the offset voltage Voffset provided by the offset voltage source 206' can be used to compensate for the minimum operating voltage of the charge pump 204', thereby causing an increase in the operating range of the oscillator frequency Ofreq provided by the VCO 202'.

[0078] Can be provided including Figure 1a phase-locked-loop (PLL) system or Figure 2a a radar transceiver with a voltage-controlled oscillator circuit such as 2a or 2b. In these examples, the charge pump of the voltage-controlled oscillator circuit is configured to provide a tuning voltage based on an output signal from a phase comparator of the PLL. This radar transceiver can have a single VCO for operating within a first frequency band or a second frequency band. The single VCO can have an oscillator frequency range greater than 3 GHz or even 5 GHz.

[0079] Thus, according to some examples of the present disclosure, the voltage-controlled oscillator overcomes the minimum Vtune limitation of the charge pump and handles the high Vtune operation of the charge pump, thereby preventing collapse noise multiplication. This enables a single VCO to cover the radar frequency bands (76 - 77 GHz, 77 - 81 GHz). In addition, the full VCO tuning range can be used to lock the PLL. Therefore, the yield at the probe level can be improved and fast and stable switching between frequency bands can be achieved using a single VCO.

[0080] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the above schema can be executed in any order. Moreover, those skilled in the art will recognize that although one example instruction set / method has been discussed, the materials in this specification can be combined in various ways to yield other examples as well, and should be understood within the context provided in this detailed description.

[0081] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied as an executable instruction set, which is implemented on a computer or a machine programmed and controlled by the executable instructions. Such instructions are loaded to be executed on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor can refer to a single component or multiple components.

[0082] In other examples, the instruction set / method shown herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture can refer to any manufactured single component or multiple components. As defined herein, non-transitory machine or computer-usable media do not include signals, but such media may be capable of receiving and processing information from signals and / or other transient media.

[0083] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via a network, computer, or data-based device and / or service. These may include the cloud, the Internet, an intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. As used herein and in the claims, the following non-exclusive definitions are provided.

[0084] In one example, one or more of the instructions or steps discussed herein are automated. The term automated or automatic (and its similar variants) means the use of a computer and / or mechanical / electrical device to control the operation of a device, system, and / or process without human intervention, observation, effort, and / or decision-making.

[0085] It should be understood that any components that are alleged to be coupled may be directly or indirectly coupled or connected. In the case of indirect coupling, additional components may be disposed between the two components that are alleged to be coupled.

[0086] In this specification, example embodiments have been presented in accordance with a selected set of details. However, those of ordinary skill in the art will understand that many other example embodiments may be practiced that include different selected sets of these details. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A voltage-controlled oscillator circuit, characterized in that, comprising: a charge pump configured to generate a tuning voltage having a minimum operating voltage; an offset voltage source configured to generate an offset voltage based on the minimum operating voltage; and a voltage-controlled oscillator VCO configured to provide an oscillator frequency based on the tuning voltage and the offset voltage, the voltage-controlled oscillator having a minimum VCO voltage, and wherein the offset voltage is based on a difference between the minimum VCO voltage and the minimum operating voltage of the tuning voltage.

2. The voltage-controlled oscillator circuit according to claim 1, characterized in that, the voltage-controlled oscillator includes at least one variable reactor unit, wherein a variable reactor voltage based on the offset voltage is applied across the variable reactor of the at least one variable reactor unit.

3. The voltage-controlled oscillator circuit according to claim 2, characterized in that, the variable reactor voltage is based on a difference between the tuning voltage and the offset voltage.

4. The voltage-controlled oscillator circuit according to claim 2 or claim 3, characterized in that, each of the at least one variable reactor units includes a pair of variable reactors.

5. The voltage-controlled oscillator circuit according to any one of claims 1-3, characterized in that, the voltage-controlled oscillator has a maximum VCO voltage, and the voltage-controlled oscillator circuit includes a high voltage supply configured to provide a high voltage to the charge pump, wherein the high voltage is greater than or equal to a sum of the maximum VCO voltage and the offset voltage.

6. The voltage-controlled oscillator circuit according to claim 5, characterized in that, the high voltage is greater than the sum of the maximum VCO voltage and the offset voltage.

7. The voltage-controlled oscillator circuit according to any one of claims 1-3, characterized in that, further comprising a temperature compensation circuit configured to provide a temperature compensation voltage to the voltage-controlled oscillator.

8. A phase-locked loop (PLL) system, characterized in that, comprising: a phase comparator; and the voltage-controlled oscillator circuit according to any one of the preceding claims, wherein the charge pump is configured to provide a tuning voltage based on an input voltage received by the charge pump, and wherein the input voltage is based on an output signal from the phase comparator.

9. A radar transceiver including the phase-locked loop (PLL) system according to claim 8, characterized in that, the radar transceiver has a single VCO for operating within a first frequency band or a second frequency band.

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