Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing the semiconductor device, wherein the semiconductor device is provided with a diode region on a semiconductor substrate, the diode region comprising: a base region of a first conductivity type, provided in a manner exposed on the upper surface of the semiconductor substrate; a cathode region of a second conductivity type, provided in a manner exposed on the lower surface of the semiconductor substrate; an inter-cathode region of the first conductivity type, provided in a manner exposed on the lower surface of the semiconductor substrate and alternately arranged with the cathode region in a predetermined direction; and a floating region of the second conductivity type, provided above the cathode region and above the inter-cathode region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, it is known that a P-type buried layer is provided in a diode (for example, see Patent Document 1). Also, it is known that in a semiconductor device having an SJ-MOSFET (Super Junction-Metal Oxide Semiconductor Field Effect Transistor) portion and an IGBT (Insulated Gate Bipolar Transistor) portion in one semiconductor chip, a P-type floating region is provided in the SJ-MOSFET portion (for example, see Patent Document 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2014 / 156849

[0006] Patent Document 2: International Publication No. 2016 / 063683 Summary of the invention

[0007] Technical issues

[0008] In a diode, it is desired to be able to adjust the amount of carriers injected from the cathode with high accuracy.

[0009] Technical Solution

[0010] In a first aspect of the present invention, a semiconductor device is provided in which a diode region is provided on a semiconductor substrate. The diode region may have a base region of a first conductivity type provided in a manner exposed on the upper surface of the semiconductor substrate. The diode region may have a cathode region of a second conductivity type provided in a manner exposed on the lower surface of the semiconductor substrate. The diode region may have an inter-cathode region of a first conductivity type provided in a manner exposed on the lower surface of the semiconductor substrate and arranged alternately with the cathode region in a predetermined direction. The diode region may have a floating region of a second conductivity type provided above the cathode region and above the inter-cathode region.

[0011] The semiconductor device may include a transistor region provided on a semiconductor substrate and arranged to be aligned with a diode region when the semiconductor substrate is viewed from above.

[0012] The inter-cathode region and the floating region may be arranged separately in the depth direction of the semiconductor substrate.

[0013] The diode region may include a dummy trench portion extending along an extension direction on an upper surface of the semiconductor substrate. The cathode region and the inter-cathode region may be alternately arranged in the extension direction.

[0014] In the diode region, the cathode region may be provided to reach a position deeper than the inter-cathode region with respect to the lower surface of the semiconductor substrate.

[0015] In a depth direction of the semiconductor substrate, a distance between an upper end of the cathode region and a lower end of the floating region may be smaller than a distance between an upper end of the inter-cathode region and a lower end of the floating region.

[0016] When looking down at the semiconductor substrate, the area of ​​the floating region provided in the diode region may be larger than the area of ​​the cathode region provided in the diode region. When looking down at the semiconductor substrate, the area of ​​the inter-cathode region provided in the diode region may be larger than the area of ​​the cathode region provided in the diode region.

[0017] In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. The semiconductor device may have a transistor region and a diode region on a semiconductor substrate. The method for manufacturing a semiconductor device may include: an injection step for a collector region, an injection step for a cathode region, and an injection step for a floating region. In the injection step for the collector region, a first conductive type dopant may be injected into the lower surface of the semiconductor substrate to form a collector region in the transistor region. In the injection step for the cathode region, a second conductive type dopant may be injected into the lower surface of the semiconductor substrate to form a cathode region in the diode region. The injection step for the floating region may be after the injection step for the cathode region. In the injection step for the floating region, a first conductive type dopant may be injected into the lower surface of the semiconductor substrate to form a first conductive type floating region provided in the diode region.

[0018] The cathode region injection step may be performed after the collector region injection step. Alternatively, the collector region injection step may be performed after the cathode region injection step, and the floating region injection step may be performed after the collector region injection step. Further alternatively, the collector region injection step may be performed after the floating region injection step.

[0019] In a third aspect of the present invention, another method for manufacturing a semiconductor device is provided. The semiconductor device may have a transistor region and a diode region on a semiconductor substrate. Another method for manufacturing a semiconductor device may include: an injection step for the collector region, an injection step for the floating region, and an injection step for the cathode region. In the injection step for the collector region, a first conductivity type dopant may be injected into the lower surface of the semiconductor substrate to form a collector region in the transistor region. In the injection step for the floating region, a first conductivity type dopant may be injected into the lower surface of the semiconductor substrate to form a first conductivity type floating region provided in the diode region. The injection step for the cathode region may be performed after the injection step for the floating region. In the injection step for the cathode region, a second conductivity type dopant may be injected into the lower surface of the semiconductor substrate to form a cathode region in the diode region.

[0020] The floating region injection step may be performed after the collector region injection step. Alternatively, the collector region injection step may be performed after the floating region injection step, and the cathode region injection step may be performed after the collector region injection step. Further alternatively, the collector region injection step may be performed after the cathode region injection step.

[0021] After the collector region injection step, the cathode region injection step, and the floating region injection step, the end of the floating region may not reach the boundary between the collector region and the cathode region. The end of the floating region may be the end of the floating region closest to the boundary between the collector region and the cathode region. The end of the floating region may not reach the boundary between the collector region and the cathode region in a direction parallel to the arrangement direction of the cathode region and the collector region from the cathode region toward the collector region. The floating region may be located in the diode region.

[0022] Alternatively, after the collector region injection step, the cathode region injection step, and the floating region injection step, the end of the floating region may be located at the boundary between the collector region and the cathode region. The end of the floating region may be the end of the floating region closest to the boundary between the collector region and the cathode region. The end of the floating region may be located at the boundary between the collector region and the cathode region in a direction parallel to the arrangement direction of the cathode region and the collector region from the cathode region toward the collector region.

[0023] A lower end of the floating region may be closer to the upper surface of the semiconductor substrate than an upper end of the collector region.

[0024] After the collector region implantation step, the cathode region implantation step, and the floating region implantation step, at least a portion of the floating region may be located in the cathode region.

[0025] The cathode region may have at least two electron concentration peaks at different positions in the depth direction from the lower surface toward the upper surface, and the peak position of the hole concentration in the floating region may be located between two of the at least two electron concentration peaks in the cathode region in the depth direction.

[0026] A lower end of the floating region may be separated from an upper end of the cathode region.

[0027] After the collector region implantation step, the cathode region implantation step, and the floating region implantation step, an upper end of the cathode region may be closer to the upper surface of the semiconductor substrate than an upper end of the collector region.

[0028] In the cathode region implantation step, the second conductivity type dopant may be implanted into a local region of the lower surface of the semiconductor substrate in the diode region to form cathode regions and first conductivity type inter-cathode regions alternately arranged with the cathode regions in a predetermined direction.

[0029] It should be noted that the above summary of the invention does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a top view of a semiconductor device 100 according to one embodiment of the present invention.

[0031] Figure 2 It is shown Figure 1 Figure 2. AA section of the image.

[0032] Figure 3 yes Figure 1 Magnified view of area B.

[0033] Figure 4A 1 is a flowchart showing a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0034] Figure 4B The diagrams show the steps of the method for manufacturing the semiconductor device 100 according to the first embodiment.

[0035] Figure 5A 1 is a flowchart showing a method for manufacturing the semiconductor device 120 according to the first modification of the first embodiment.

[0036] Figure 5B 1 and 2 are diagrams showing the steps of a method for manufacturing the semiconductor device 120 according to the first modification of the first embodiment.

[0037] Fig. 6A 1 is a flowchart showing a method for manufacturing the semiconductor device 140 according to the second modification of the first embodiment.

[0038] Figure 6B1 and 2 are diagrams showing the steps of a method for manufacturing a semiconductor device 140 according to a second modification of the first embodiment.

[0039] Figure 7 3 is a diagram showing the concentration distribution of electrons and holes near the boundary 72 according to the first embodiment.

[0040] Figure 8 1 and 2 are diagrams showing steps of a method for manufacturing a semiconductor device 160 according to a third modification of the first embodiment.

[0041] Fig. 9 1 and 2 are diagrams showing steps of a method for manufacturing a semiconductor device 180 according to a fourth modification of the first embodiment.

[0042] Fig. 10A 1 is a flowchart showing a method for manufacturing the semiconductor device 200 according to the second embodiment.

[0043] Fig. 10B It is a diagram showing each step of the method for manufacturing the semiconductor device 200 according to the second embodiment.

[0044] Fig.11A : is a flowchart showing a method for manufacturing the semiconductor device 220 according to the first modification example of the second embodiment.

[0045] Fig. 11B It is a diagram showing each step of a method for manufacturing a semiconductor device 220 according to a first modification of the second embodiment.

[0046] Fig. 12A : is a flowchart showing a method for manufacturing a semiconductor device 240 according to a second modification of the second embodiment.

[0047] Fig. 12B It is a diagram showing each step of a method for manufacturing a semiconductor device 240 according to a second modification of the second embodiment.

[0048] Fig.13A 1 is a flowchart showing a method for manufacturing the semiconductor device 300 according to the third embodiment.

[0049] Fig. 13B 1 and 2 are diagrams showing the steps of a method for manufacturing the semiconductor device 300 according to the third embodiment.

[0050] Fig. 13C 3 is a diagram showing the concentration distribution of electrons and holes in the vicinity of the boundary 72 according to the third embodiment.

[0051] Fig.13D 1 is a diagram showing the concentration distribution of electrons and holes in the vicinity of the boundary 72 according to the first modification example of the third embodiment.

[0052] Fig.13E1 is a diagram showing the concentration distribution of electrons and holes in the vicinity of the boundary 72 according to the second modification of the third embodiment.

[0053] Fig.14 It is a top view of the FWD region 80 according to the fourth embodiment.

[0054] Fig.15 Yes Fig.14 Stereoscopic cross-sectional view of the KK section and the LL section.

[0055] Fig.16 It is an enlarged plan view for explaining an example of arrangement of the floating region 84 , the cathode region 82 , and the inter-cathode region 81 .

[0056] Fig.17 1 is a diagram showing the cathode region 82 and the inter-cathode region 81 on the YZ plane.

[0057] Fig.18 It is a plan view of the FWD region 80 according to the first modified example of the fourth embodiment.

[0058] Fig.19 It is a plan view of the FWD region 80 according to the second modified example of the fourth embodiment.

[0059] Fig. 20 It is a plan view of the FWD region 80 according to the third modified example of the fourth embodiment.

[0060] Fig.21 It is a plan view of the FWD region 80 according to the third modified example of the fourth embodiment.

[0061] Fig. 22 It is shown Fig.21 A diagram showing an example of an MM cross section in FIG.

[0062] Fig.23 This is a flowchart showing an example of a method for manufacturing a semiconductor device according to the fourth embodiment.

[0063] Fig.24 Yes Description Fig.23 FIG. 5 shows a collector region implantation step S620, a cathode region implantation step S632 and a floating region implantation step S640.

[0064] Fig.25 This is a flowchart showing another example of the method for manufacturing the semiconductor device according to the fourth embodiment.

[0065] Fig.26 Yes Description Fig.25 FIG. 5 shows a collector region implantation step S620, a floating region implantation step S642, and a cathode region implantation step S634.

[0066] Fig.27AThis is a flowchart showing another example of the method for manufacturing the semiconductor device according to the fourth embodiment.

[0067] Fig.27B This is a flowchart showing another example of the method for manufacturing the semiconductor device according to the fourth embodiment.

[0068] Fig.28A This is a flowchart showing another example of the method for manufacturing the semiconductor device according to the fourth embodiment.

[0069] Fig.28B This is a flowchart showing another example of the method for manufacturing the semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION

[0070] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0071] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, region, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the mounting direction when the semiconductor device is mounted on a wiring substrate, etc.

[0072] In this specification, the rectangular coordinate axes of the X-axis, Y-axis, and Z-axis are sometimes used to explain technical matters. In this specification, the X-axis, Y-axis, and Z-axis constitute a right-handed coordinate system. In this specification, the plane parallel to the upper surface or the lower surface of the semiconductor substrate is referred to as the XY plane, and the depth direction of the semiconductor substrate perpendicular to the upper surface or the lower surface of the semiconductor substrate is referred to as the Z axis.

[0073] In this specification, the first conductivity type is P type and the second conductivity type is N type, but the first conductivity type may be N type and the second conductivity type may be P type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment become opposite conductivity types. In addition, in this specification, when it is recorded as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when it is recorded as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type.

[0074] In this specification, doping concentration refers to the concentration of impurities that have been transformed into donors or acceptors. In this specification, the difference between the concentrations of donors and acceptors is sometimes referred to as net doping concentration or simply as doping concentration. In addition, the peak value of the doping concentration distribution is sometimes referred to as doping concentration.

[0075] Figure 11 is a top view of a semiconductor device 100 according to an embodiment of the present invention. Figure 1 This is a diagram obtained by observing the semiconductor device 100 from the upper surface side of the semiconductor substrate 10 in parallel with the Z axis. Figure 1 In order to facilitate understanding of the configuration relationship of each region, components such as the emitter electrode and the passivation film are appropriately omitted.

[0076] The semiconductor device 100 has a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a nitride semiconductor substrate such as gallium nitride (GaN). The semiconductor substrate 10 in the present embodiment is a silicon substrate. When a silicon substrate is used, the N-type dopant may be one or more elements selected from phosphorus (P) and arsenic (As), and the P-type dopant may be one or more elements selected from boron (B) and aluminum (Al).

[0077] The semiconductor device 100 includes an active region 110, an edge termination structure region 90, and a gate flow channel portion 50. The active region 110 may include a transistor region where a main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the transistor provided in the semiconductor device 100 is set to an on state, and a diode region where a main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the transistor is set to an off state. Alternatively, the active region 110 may also be a region where an emitter electrode is provided when viewed from above. The active region 110 of the present embodiment is a region surrounded by the gate flow channel portion 50 when viewed from above, excluding the pad region 112.

[0078] The semiconductor device 100 of the present embodiment has an IGBT region 70 and a FWD (Free Wheeling Diode) region 80 in an active region 110 of a semiconductor substrate 10. That is, the semiconductor device 100 of the present embodiment is an RC-IGBT. The IGBT region 70 is an example of a transistor region, and the FWD region 80 is an example of a diode region. In the present embodiment, the IGBT region 70 and the FWD region 80 are alternately arranged in the X-axis direction. In addition, in the present embodiment, the IGBT region 70 is provided at both ends of the active region 110 in the X-axis direction.

[0079] The IGBT region 70 may have a P+ type collector region in a region connected to the lower surface of the semiconductor substrate 10. The IGBT region 70 of the present embodiment is located in the active region 110 and is provided with a collector region on the lower surface of the semiconductor substrate 10. The IGBT region 70 may be a unit structure including an N+ type emitter region and a P+ type contact region periodically provided on the upper surface of the semiconductor substrate 10.

[0080] The FWD region 80 of the present embodiment is a region located in the active region 110 and having an N+ type cathode region provided in a region in contact with the lower surface of the semiconductor substrate 10. The cathode region may be located near the gate flow channel portion 50 and the pad region 112 and may be retreated to the inner side of the active region 110 in the Y-axis direction. For example, the end of the cathode region in the Y-axis direction is located near the gate flow channel 50 and is located closer to the inner side of the active region 110 than the gate flow channel portion 50. However, even when the end of the cathode region in the Y-axis direction is located inside the active region 110, the region from one end of the gate flow channel portion 50 to the other end opposite to the one end in the Y-axis direction may be regarded as the FWD region 80 because the gate trench portion and the emitter region are not provided.

[0081] In this embodiment, the boundary 72 between the IGBT region 70 and the FWD region 80 in the X-axis direction is the boundary between the cathode region and the collector region. Figure 1 In the figure, for the sake of readability, symbols are only marked on the boundary 72 crossed by AA.

[0082] The edge termination structure region 90 may be disposed between the active region 110 and the outer peripheral end of the semiconductor substrate 10 when viewed from above. The edge termination structure region 90 may be configured on the upper surface of the semiconductor substrate 10 in a manner of surrounding the active region 110. The edge termination structure region 90 of the present embodiment is configured in a rectangular ring shape along the outer peripheral end of the semiconductor substrate 10. The edge termination structure region 90 may have a function of alleviating the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure region 90 may have, for example, any one of a guard ring, a field plate, and a reduced surface electric field (RESURF), or a structure combining two or more of them.

[0083] The gate runner portion 50 of this embodiment is disposed between the active region 110 and the edge termination structure region 90 in a plan view. The gate runner portion 50 can transmit a gate signal provided from the gate pad 114 to the gate trench portion of the IGBT region 70. The gate runner portion 50 can have a stacked structure of a metal layer and a polysilicon layer.

[0084] The metal layer of the gate flow channel portion 50 may be a metal layer formed of aluminum, aluminum-silicon alloy or aluminum-silicon-copper (Cu) alloy. The polysilicon layer of the gate flow channel portion 50 may be a polysilicon layer doped with impurities such as phosphorus.

[0085] An insulating film may be provided between the polysilicon layer of the gate flow channel portion 50 and the upper surface of the semiconductor substrate 10. The gate flow channel portion 50 may be electrically separated from the semiconductor substrate 10 by the insulating film except for the portion connected to the gate trench portion. In addition, a metal layer of the gate flow channel portion 50 may be provided on the polysilicon layer. The metal layer may be connected to the polysilicon layer via a predetermined contact region (e.g., an opening region of the interlayer insulating film).

[0086] The pad region 112 of the present embodiment is a region formed by cutting out a portion of the active region 110. That is, the pad region 112 of the present embodiment is not included in the active region 110. The range of the pad region 112 when viewed from above may be the range of a P+ type well region provided in a region in contact with the upper surface of the semiconductor substrate 10. The gate pad 114 may be provided in a range narrower than the P+ type well region. The gate pad 114 of the present embodiment is electrically connected to the gate flow channel portion 50. A gate signal may be provided to the gate pad 114 from the outside of the semiconductor device 100.

[0087] Figure 2 It is shown Figure 1 FIG. 2 is a diagram of an AA cross section of FIG. The AA cross section is a cross section parallel to the XZ plane and passes through the boundary 72 between the collector region 22 of the IGBT region 70 and the cathode region 82 of the FWD region 80. In the AA cross section, the semiconductor device 100 has the emitter electrode 52, the interlayer insulating film 38, the semiconductor substrate 10, and the collector electrode 24.

[0088] The interlayer insulating film 38 may be formed of one or more materials selected from silicon dioxide (SiO2), BPSG (Boro-Phospho Silicate Glass), PSG (Phosphorus Silicate Glass), and BSG (Borosilicate Glass). The interlayer insulating film 38 of the present embodiment is disposed on the dummy groove portion 30 and the gate groove portion 40. The interlayer insulating film 38 of the present embodiment has a plurality of openings 54. The openings 54 may function as a contact portion for electrically connecting the emitter electrode 52 to the upper surface 62 of the semiconductor substrate 10.

[0089] The emitter electrode 52 and the collector electrode 24 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper (Cu) alloy. The emitter electrode 52 and the collector electrode 24 may have a barrier metal layer formed of titanium (Ti) or a titanium compound, etc., in the lower layer. The upper surface 62 of the semiconductor substrate 10 and the emitter electrode 52 may be directly connected. It should be noted that a plug formed of tungsten (W) or the like may be provided in the opening 54. The upper surface 62 of the semiconductor substrate 10 and the emitter electrode 52 may be electrically connected via the plug.

[0090] The semiconductor substrate 10 of the present embodiment has a plurality of grooves in a region in contact with the upper surface 62. The plurality of grooves include a gate groove 40 and a dummy groove 30. The distance between adjacent grooves in the X-axis direction may be constant.

[0091] A mesa portion 60 is provided between each groove portion. In the present embodiment, the mesa portion 60 is a region extending from the bottom of the groove portion to the upper surface 62, and is a region of the semiconductor substrate 10 sandwiched between two adjacent groove portions in the X-axis direction. The mesa portion 60 may include an N+ type emitter region 12, a P+ type contact region 15, a P- type base region 14, and an N+ type accumulation region 16. It should be noted that the mesa portion 60 includes a mesa portion 60-1 described later and a mesa portion 60-2 described later.

[0092] In this embodiment, the mesa portion 60 of the IGBT region 70 has emitter regions 12 and contact regions 15 alternately arranged in the Y-axis direction and exposed on the upper surface 62. In the AA cross section, the emitter region 12 exists in the mesa portion 60-1 of the IGBT region 70, but the contact region 15 does not exist.

[0093] In the mesa portion 60-1a closest to the boundary 72 of the IGBT region 70, the emitter region 12 may not be provided in order to reduce the current interference between the IGBT region 70 and the FWD region 80. In the mesa portion 60-1a of the IGBT region 70, in the Y-axis direction, the contact region 15 and the P-type base region 14 may be exposed on the upper surface 62, respectively. It should be noted that in the AA cross section, the contact region 15 exists in the mesa portion 60-1a, but the base region 14 does not exist.

[0094] In the mesa portion 60 of the IGBT region 70, the base region 14 is located below the emitter region 12 and the contact region 15 within the range where the emitter region 12 and the contact region 15 exist. The portion of the base region 14 that contacts the gate groove portion 40 can function as a channel formation region. If an on voltage is applied to the gate groove portion 40 as a gate signal, a channel as a charge inversion layer can be formed in the base region 14. By forming a channel in the base region 14, electrons can flow between the emitter region 12 and the drift region 18.

[0095] The accumulation region 16 of the present embodiment is provided in a manner covering the entire lower surface of the base region 14 in each mesa portion 60. The accumulation region 16 may be sandwiched by two groove portions in the X-axis direction. The bottom of the accumulation region 16 may be provided at a position closer to the upper surface 62 than the bottom of each groove portion. That is, the bottom of the accumulation region 16 may be provided at a position shallower than the bottom of each groove portion. By providing the accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect: Injection-Enhancement effect) can be increased, thereby reducing the on-voltage in the IGBT region 70.

[0096] The gate trench portion 40 includes a gate trench 42, a gate insulating film 43, and a gate conductive portion 44. The gate trench 42 can be formed by selectively etching the semiconductor substrate 10 from the upper surface 62 to a predetermined depth. The gate insulating film 43 can be provided in a manner in contact with the inner wall of the gate trench 42. The gate insulating film 43 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench 42. The gate conductive portion 44 is provided at a position closer to the inner side of the gate trench 42 than the gate insulating film 43 in a manner in contact with the gate insulating film 43. The gate insulating film 43 can electrically insulate the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 can be formed of a conductive material such as polysilicon.

[0097] The dummy trench portion 30 includes a dummy trench 32, a dummy trench insulating film 33, and a dummy trench conductive portion 34. The dummy trench insulating film 33 and the dummy trench conductive portion 34 can be formed by the same method as the gate insulating film 43 and the gate conductive portion 44.

[0098] In the present embodiment, the IGBT region 70 has a plurality of gate trench portions 40 and a plurality of dummy trench portions 30. Two dummy trench portions 30 are provided between the dummy trench portion 30-b located above the boundary 72 and the gate trench portion 40 closest to the dummy trench portion 30-b in the X-axis direction. Two dummy trench portions 30 and one gate trench portion 40 form a set and may be repeatedly provided in the X-axis direction.

[0099] A dummy groove portion 30-b may also be provided similarly above the boundary 72 between the IGBT region 70 and the FWD region 80 connected to the IGBT region 70 in the negative direction of the X axis. Two dummy groove portions 30 may also be provided between the dummy groove portion 30-b and the gate groove portion 40 closest to the dummy groove portion 30-b in the X axis direction. In contrast, all the groove portions in the FWD region 80 may be dummy groove portions 30.

[0100] In the present embodiment, the mesa portion 60-2 of the FWD region 80 has a base region 14 and a contact region 15 respectively exposed on the upper surface 62. In addition, in the AA cross section, the base region 14 exists in the mesa portion 60-2.

[0101] In the FWD region 80, the base region 14 may be larger than the contact region 15 in terms of the area exposed on the upper surface 62. The base region 14 in the FWD region 80 may function as an anode region of a diode. The contact region 15 may be provided locally only in a predetermined region near the end in the Y-axis direction (for example, a region near the gate flow channel portion 50). In the mesa portion 60-2 of the present embodiment, the accumulation region 16 is provided so as to cover the entire lower surface of the base region 14.

[0102] In the present embodiment, the structure including the mesa portion 60, the groove portion, the interlayer insulating film 38, and the emitter electrode 52 is referred to as the upper surface structure 116. However, the upper surface structure 116 may include a lifetime control region near the upper surface 62 of the semiconductor substrate 10. The vicinity of the upper surface 62 of the semiconductor substrate 10 may refer to a position above half the thickness of the semiconductor substrate 10 (i.e., the length from the upper surface 62 to the lower surface 64 in the Z-axis direction).

[0103] The lifetime control region refers to a region where a lifetime control body is intentionally formed by injecting impurities into the interior of the semiconductor substrate 10. The lifetime control body may be a recombination center of carriers inside the semiconductor substrate 10. The recombination center of carriers may be: a crystal defect; a vacancy; a divacancy; a composite defect of a crystal defect, a vacancy, a divacancy and an element constituting the semiconductor substrate 10; a dislocation; a rare gas element such as helium and neon or a metal element such as platinum, etc.

[0104] In this embodiment, the structure including the N+ type field stop (FS) region 20, the P type floating region 84, the P+ type collector region 22, and the N+ type cathode region 82 is referred to as the lower surface structure 118. The lower surface structure 118 may include a lifetime control region between a position at half the thickness of the semiconductor substrate 10 and the upper portion of the FS region 20.

[0105] The FS region 20 may have a function of preventing the depletion layer extending from the bottom of the base region 14 to the lower surface 64 from reaching the collector region 22 when the semiconductor device 100 is turned off. The FS region 20 may be an N-type semiconductor region and may have one or more peaks of doping concentration distribution. The multiple peaks of the doping concentration distribution in the FS region 20 may be discretely arranged in the Z-axis direction.

[0106] The floating region 84 is a P-type region in an electrically floating state. The floating region 84 may be provided in the FWD region 80. In the present embodiment, the floating region 84 is provided dispersedly in the entire FWD region 84.

[0107] In principle, being in an electrically floating state refers to a state in which the collector electrode 24 and the emitter electrode 52 are not electrically connected. By providing a floating region 84, the injection of electrons from the cathode region 82 can be suppressed. Thus, even if a lifetime control body is not provided on the lower surface 64 side of the semiconductor substrate 10, the carrier distribution in the depth direction of the semiconductor substrate 10 can be adjusted. Therefore, the cost of providing a lifetime control region can be reduced. In addition, the leakage current caused by the lifetime control region can also be reduced.

[0108] The floating region 84 may be located within the FWD region 80. In the present embodiment, the end 91 of the floating region 84 does not reach the boundary 72 in the X-axis direction. It should be noted that the end 91 of the present embodiment is the end of the floating region 84 closest to the boundary 72. The distance L1 between the boundary 72 and the end 91 may be more than several nm and less than several μm. It should be noted that in the present embodiment, the X-axis direction is a direction parallel to the arrangement direction of the cathode region 82 and the collector region 22 from the cathode region 82 toward the collector region 22.

[0109] The floating region 84 of the present embodiment is located in the FS region 20 in the Z-axis direction. That is, in the present embodiment, the upper end of the floating region 84 is closer to the lower surface 64 than the upper end of the FS region 20. In addition, in the present embodiment, the lower end of the floating region 84 is consistent with the lower end of the FS region 20, but the lower end of the floating region 84 may be closer to the upper surface 62 than the lower end of the FS region 20.

[0110] Figure 3 yes Figure 1 The enlarged view of region B. The lengths of the semiconductor substrate 10 in the X-axis direction and the Y-axis direction can be respectively more than several mm and less than ten mm. The width of the IGBT region 70 in the X-axis direction can be more than one time and less than three times the width of the FWD region 80 in the X-axis direction, or more than two times and less than three times. For example, the width of the IGBT region 70 in the X-axis direction is more than 1000μm and less than 1500μm, and the width of the FWD region 80 in the X-axis direction is more than 400μm and less than 500μm. It should be noted that the width of the IGBT region 70 in the Y-axis direction and the width of the FWD region 80 in the Y-axis direction can be the same.

[0111] In the XY plane, the area of ​​the floating region 84 may be smaller than the area of ​​the FWD region 80. In the XY plane, the floating region 84 may cover a range of more than 90% and less than 100% of the cathode region 82, or may cover a range of more than 90% and less than 95% of the cathode region 82. Each of the floating regions 84 may be an island-shaped region dispersedly arranged in the XY plane. Each floating region 84 may be separated by a predetermined same distance L in the X-axis direction and the Y-axis direction. F .

[0112] Figure 4A1 is a flowchart showing a method for manufacturing the semiconductor device 100 according to the first embodiment. The method for manufacturing the first embodiment comprises: a step of forming the upper surface structure 116 (S10), a step of implanting the collector region 22 (S20), a step of implanting the cathode region 82 (S30), a step of implanting the floating region 84 (S40), a first annealing step (S50), a step of implanting the FS region 20 (S60), a second annealing step (S70), and a step of forming the collector electrode 24 (S80). In the first embodiment, the steps are performed in the order of the number following S from small to large.

[0113] Figure 4B The diagrams show the steps of the method for manufacturing the semiconductor device 100 according to the first embodiment. Figure 4B (a) shows a step (S10) of forming an upper surface structure 116. In step S10, a groove portion can be formed in an N-type semiconductor substrate 10. When forming the dummy groove conductive portion 34 and the gate conductive portion 44, a polysilicon layer of the gate flow channel portion 50 can be formed. After the groove portion is formed, a P-type dopant for the base region 14 is injected into the upper surface 62 of the semiconductor substrate 10. The dopant can be accelerated by an injection device in an ion state and injected into the semiconductor substrate 10. Thereafter, the semiconductor substrate 10 can be annealed at about 1150° C. for three hours.

[0114] In step S10, N-type dopants for the accumulation region 16, N-type dopants for the emitter region 12, and P-type dopants for the contact region 15 may be selectively injected in sequence. However, the injection sequence may be appropriately changed. Thereafter, the semiconductor substrate 10 may be annealed at about 1000° C. for 30 minutes. In step S10, an interlayer insulating film 38 may be formed by CVD thereafter. Thereafter, the interlayer insulating film 38 and the thermal oxide film on the upper surface 62 may be selectively removed by etching to form an opening 54. The thermal oxide film is, for example, an insulating film disposed on the upper surface 62 when the gate insulating film 43 and the dummy trench insulating film 33 are formed.

[0115] In step S10, the emitter electrode 52 may be deposited by sputtering afterwards. When the emitter electrode 52 is deposited by sputtering, the metal layer of the gate runner portion 50 and the gate pad 114 may also be deposited. After deposition, the emitter electrode 52, the metal layer of the gate runner portion 50 and the gate pad 114 may be patterned into a predetermined shape. Step S10 may also include the step of forming a passivation layer including a predetermined opening on the upper portion of the emitter electrode 52 and the like.

[0116] It should be noted that step S10 of the present embodiment includes grinding the surface of the semiconductor substrate 10 on the side opposite to the upper surface 62 in the Z-axis direction after forming the upper surface structure 116. The semiconductor substrate 10 can be thinned to have a thickness corresponding to a predetermined withstand voltage. The lower surface 64 of the present embodiment is the surface of the semiconductor substrate 10 exposed after thinning.

[0117] Figure 4B (b) shows a collector region 22 implantation step (S20). In step S20, a P-type dopant is implanted into the entire lower surface 64 of the semiconductor substrate 10. Step S20 may be a dopant implantation for the purpose of forming the collector region 22 in the IGBT region 70. That is, in step S20, the P-type dopant may be doped at a doping amount corresponding to the doping concentration of the collector region 22 in the semiconductor device 100.

[0118] Figure 4B (c) shows an injection step (S30) for the cathode region 82. In step S30, a mask 68 of a photoresist material or the like is first formed in contact with the entire lower surface 64. Thereafter, in the XY plane, the mask 68-1 is patterned in a range corresponding to the collector region 22. Thereafter, an N-type dopant is injected into the lower surface 64 of the semiconductor substrate 10. Step S30 may be a dopant injection for the purpose of forming the cathode region 82 in the FWD region 80. That is, in step S30, the N-type dopant may be doped with a doping amount corresponding to the doping concentration of the cathode region 82 in the semiconductor device 100.

[0119] Thus, in the range where the mask 68-1 is not provided, the region where the P-type dopant is implanted is counter-doped. It should be noted that the N-type dopant may not be implanted in the range where the mask 68-1 is provided. After doping, the mask 68-1 may be removed.

[0120] Figure 4B (d) shows the implantation step (S40) for the floating region 84. In step S40, a mask 68-2 is set in the XY plane in a range corresponding to the floating region 84. The mask 68-2 of this embodiment is formed in the same way as the mask 68-1, but is set in a range different from that of the mask 68-1 in the XY plane.

[0121] Afterwards, a P-type dopant is injected into the lower surface 64 of the semiconductor substrate 10. Step S40 may be a dopant injection for the purpose of forming a P-type floating region 84. That is, in step S40, the P-type dopant may be doped with a doping amount corresponding to the doping concentration of the floating region 84 in the semiconductor device 100. The implantation depth range of step S40 may be shallower than the implantation depth range of the cathode region 82. After doping, the mask 68-2 may be removed.

[0122] As described above, in steps S30 and S40, a mask process of forming a mask 68, patterning the mask 68, and removing the mask 68 is performed multiple times. Therefore, the possibility of generating and / or attaching particles 86 becomes higher in the later implantation steps among the multiple implantation steps. Therefore, there is a possibility of generating defects 88 or causing damage in the semiconductor substrate 10 due to the particles. Since the defects 88 and / or damage generated in the cathode region 82 directly affect the electrical characteristics of the FWD region 80, the impact on the semiconductor device 100 is relatively large. For example, if the defects 88 and / or damage are generated in the cathode region 82, it will cause junction leakage, poor withstand voltage, and reduced switching characteristics.

[0123] Therefore, in the present embodiment, the step of implanting the floating region 84 (S40) is performed after the step of implanting the cathode region 82 (S30). Thus, compared with the case where the step of implanting the cathode region 82 is performed after the step of implanting the floating region 84, the step of implanting the cathode region 82 can be performed on the lower surface 64 in a cleaner state. Therefore, the risk of generating defects 88 and / or damage in the cathode region 82 in step S30 can be reduced. Therefore, in the semiconductor device 100, current leakage and withstand voltage failure can be reduced. Thus, in the present embodiment, the yield rate of the RC-IGBT can be improved.

[0124] It should be noted that, in the present embodiment, since the collector region 22 is implanted with the lower surface 64 clean, the defects 88 and / or damage in the collector region 22 can also be reduced. As a result, current leakage and poor withstand voltage can also be reduced in the collector region 22. However, in the present embodiment, more defects 88 are introduced into the floating region 84 compared to the case where the cathode region 82 is implanted with the implant step (S30) after the floating region 84 implant step (S40). However, compared to the case where defects 88 and / or damage are introduced into the cathode region 82, the defects 88 introduced into the floating region 84 have less effect on the FWD region 80. Therefore, in the present embodiment, it can be considered that the defects 88 introduced into the floating region 84 are allowable.

[0125] Figure 4B (e) shows a first annealing step (S50). In this embodiment, the semiconductor substrate 10 is annealed at a temperature of 1000° C. by irradiating the lower surface 64 with laser. The laser may have energy higher than the band gap energy of the semiconductor substrate 10. Through step S50, crystal defects generated by dopant ion implantation can be restored and the implanted dopant can be activated.

[0126] Figure 4B(f) shows an implantation step (S60) for the FS region 20. In the present embodiment, hydrogen is implanted from the lower surface 64 to a predetermined depth range for the purpose of forming the FS region 20. It should be noted that hydrogen can be implanted into the semiconductor substrate 10 in the form of hydrogen ions (i.e., protons). The implantation energy can be changed in such a way that a plurality of peaks are provided in the Z-axis direction in the FS region 20, and the hydrogen ions can be implanted into the semiconductor substrate 10 in multiple stages.

[0127] Figure 4B (g) shows a second annealing step (S70). In the present embodiment, the semiconductor substrate 10 is placed in a heat treatment furnace 150 and annealed at a temperature of about 400°C. By performing the annealing of the FS region 20 separately from step S50, the hydrogen in the FS region 20 can be activated at a temperature different from that of the P-type dopant and the N-type dopant injected in steps S20 to S40 and at a temperature that is most suitable for the activation of hydrogen. In addition, by performing the injection step for the FS region 20 after step S50, the accuracy of the dopant injection for the FS region 20 can be improved compared to the case where the injection step for the FS region 20 is performed before step S50.

[0128] Figure 4B (h) shows the collector electrode 24 forming step (S80). In the present embodiment, the collector electrode 24 in contact with the entire lower surface 64 is formed by sputtering. Thus, the semiconductor device 100 is completed. It should be noted that the position of the end 91 may be the position after the collector region 22 injection step, the cathode region 82 injection step, and the floating region 84 injection step. The position of the end 91 in the present embodiment is the position of the end 91 after step S80.

[0129] Figure 5A 1 is a flowchart showing a method for manufacturing a semiconductor device 120 according to a first modification of the first embodiment. It should be noted that the semiconductor device 120 is shown in the following figure. In this embodiment, the collector region 22 injection step (S20) is performed after the cathode region 82 injection step (S12), and the floating region 84 injection step (S40) is performed after the collector region 22 injection step (S20). This is different from the first embodiment. The description of the same steps as the first embodiment is omitted.

[0130] Figure 5B 1 and 2 are diagrams showing the steps of a method for manufacturing the semiconductor device 120 according to the first modification of the first embodiment. Figure 5B Step S12 of (a) and Figure 4B Corresponding to step S30 of (c), Figure 5B Step S20 of (b) and Figure 4B Corresponding to step S20 of (b), Figure 5BStep S40 of (c) and Figure 4B The step S40 of (d) corresponds to, Figure 5B Step S80 of (d) and Figure 4B This corresponds to step S80 of (h). In the first modification, current leakage and withstand voltage failure in the cathode region 82 and the collector region 22 can also be reduced, so the yield of the RC-IGBT can be improved.

[0131] Fig. 6A 1 is a flowchart showing a method for manufacturing a semiconductor device 140 according to a second modification of the first embodiment. It should be noted that the semiconductor device 140 is shown in the following figure. In this embodiment, the implantation step (S40) for the floating region 84 is performed after the implantation step (S30) for the cathode region 82, and the implantation step (S42) for the collector region 22 is performed after the implantation step (S40) for the floating region 84. This is different from the first embodiment. The description of the same steps as the first embodiment is omitted.

[0132] Figure 6B 1 and 2 are diagrams showing the steps of a method for manufacturing a semiconductor device 140 according to a second modification of the first embodiment. Figure 6B Step S30 of (a) and Figure 4B Corresponding to step S30 of (c), Figure 6B Step S40 of (b) and Figure 4B (d) corresponds to step S40, Figure 6B Step S42 of (c) and Figure 4B Corresponding to step S20 of (b), Figure 6B Step S80 of (d) and Figure 4B This corresponds to step S80 of (h). In the second modification, the current leakage and the withstand voltage failure in the cathode region 82 can be reduced, so the yield of the RC-IGBT can be improved.

[0133] Figure 7 7 is a diagram showing the concentration distribution of electrons and holes near the boundary 72 of the first embodiment. Figure 7 The center of FIG. 1 shows a partial enlarged view of the vicinity of the boundary 72 in the semiconductor device 100. Figure 7 The electron-hole concentration distribution in the CC section and the DD section of the partial enlarged view are shown respectively through the partial enlarged view near the boundary 72. In the CC section and the DD section, the horizontal axis is the electron concentration or the hole concentration (cm -3 ), and the vertical axis is the depth position (μm). It should be noted that in this specification, the electron concentration and the hole concentration are effective (ie, net) concentrations. The effective concentration is, for example, the difference between the electron concentration and the hole concentration.

[0134] The CC cross section passes through the drift region 18, the FS region 20 and the collector region 22 in order from near to far from the upper surface 62. Since the drift region 18 and the FS region 20 are N-type regions, they are regions where electrons become the majority carriers. It should be noted that the concentration of the N-type region represents the electron concentration. In contrast, since the collector region 22 is a P-type region, it is a region where holes become the majority carriers. It should be noted that the concentration of the P-type region represents the hole concentration. In the depth direction, the peaks of the ion-implanted P-type and N-type dopant concentration distributions can be consistent with the peak positions of the hole concentration and the electron concentration, respectively. It should be noted that due to annealing after dopant injection, the concentration peak position of the injected dopant may not be completely consistent with the concentration peak position of the electrons or holes. However, it can be regarded as that the relative position relationship of each peak is roughly the same.

[0135] The DD cross section passes through the drift region 18, the FS region 20, the floating region 84, and the cathode region 82 in order from near to far from the upper surface 62. The concentration in the floating region 84 is the hole concentration, and the concentration in the cathode region 82 is the electron concentration.

[0136] Figure 8 1 and 2 are diagrams showing steps of a method for manufacturing a semiconductor device 160 according to a third modification of the first embodiment. Figure 8 Step S140 of (a) and Figure 4B (d) corresponds to step S40, Figure 8 Step S180 of (b) and Figure 4B It corresponds to step S80 of (h). It should be noted that the description of the same steps as those in the first embodiment is omitted. The difference between the third variant and the first embodiment is that the floating region 84 is formed in the cathode region 82. In the third variant, there may be a tail region for forming the P-type dopant concentration distribution of the floating region 84 in the cathode region 82 between the upper end of the floating region 84 and the FS region 20. Similarly, there may also be a tail region for forming the P-type dopant concentration distribution of the floating region 84 in the cathode region 82 between the lower end of the floating region 84 and the lower surface 64.

[0137] In addition, the peak of the P-type dopant concentration distribution of the floating region 84 may exist at a position closer to the FS region 20 than half the depth position of the cathode region 82. In the third modification, the floating region 84 is disposed at a position closer to the FS region 20 than the lower surface 64. Thus, although the floating region 84 is disposed in the cathode region 82, the risk of the floating region 84 being exposed at the lower surface 64 of the semiconductor device 160 can be reduced. Figure 8 The third variant can also be Figure 5A and Figure 5B The first variant example and Fig. 6A and Figure 6B The second variant example is combined.

[0138] Fig. 9 1 and 2 are diagrams showing steps of a method for manufacturing a semiconductor device 180 according to a fourth modification of the first embodiment. Fig. 9 Step S240 of (a) and Figure 4B The step S40 of (d) corresponds to, Fig. 9 Step S280 of (b) and Figure 4B It corresponds to step S80 of (h). It should be noted that the description of the same steps as those of the first embodiment is omitted. The fourth variant is different from the first embodiment in that the lower end of the floating region 84 is formed at a position higher than the cathode region 82. Fig. 9 In (b), the distance between the lower end of the floating region 84 and the upper end of the cathode region 82 is shown as L2. In the fourth modification, a tail region for forming the P-type dopant concentration distribution of the floating region 84 may exist in the FS region 20 between the lower end of the floating region 84 and the upper end of the cathode region 82. In addition, similarly to the third modification of the first embodiment, a tail region for forming the P-type dopant concentration distribution of the floating region 84 may exist between the upper end of the floating region 84 and the upper end of the FS region 20. Fig. 9 The fourth variant can also be Figure 5A and Figure 5B The first variant example and Fig. 6A and Figure 6B The second variant example is combined.

[0139] Fig. 10A 2 is a flowchart showing a method for manufacturing a semiconductor device 200 according to a second embodiment. It should be noted that the semiconductor device 200 is shown in the following figure. The manufacturing method according to the second embodiment comprises: a step of forming an upper surface structure 116 (S410), an implantation step for the collector region 22 (S420), an implantation step for the floating region 84 (S440), an implantation step for the cathode region 82 (S444), a first annealing step (S450), an implantation step for the FS region 20 (S460), a second annealing step (S470), and a collector electrode 24 forming step (S480). In the second embodiment, each step is performed in the order of the number following S from small to large.

[0140] Fig. 10B It is a diagram showing each step of the method for manufacturing the semiconductor device 200 according to the second embodiment. Fig. 10B Step S410 of (a) and Figure 4B This corresponds to step S10 of (a). Fig. 10B Step S420 of (b) and Figure 4B This corresponds to step S20 of (b). Fig. 10B Step S440 of (c) and Figure 4B This corresponds to step S40 of (d). Fig. 10B Step S444 of (d) and Figure 4B This corresponds to step S30 of (c). Fig. 10B Step S450 of (e) and Figure 4B This corresponds to step S50 of (e). Fig. 10B Step S460 of (f) and Figure 4B This corresponds to step S60 of (f). Fig. 10B Step S470 of (g) and Figure 4B This corresponds to step S70 of (g). Fig. 10B Step S480 of (h) and Figure 4B This corresponds to step S80 of (h).

[0141] In the case where the implantation step for the floating region 84 is performed after the implantation step for the collector region 22 and the implantation step for the cathode region 82, in addition to the P-type dopant for the collector region 22, the N-type dopant for the cathode region 82 is also implanted in the cathode region 82. Therefore, the disorder of crystallinity in the cathode region 82 directly below the floating region 84 becomes larger. In the case where the disorder of crystallinity in the cathode region 82 is large, the implantation range of the P-type dopant for the floating region 84 may deviate from the designed range. For example, the P-type dopant may deviate in the XY plane direction in addition to the Z-axis direction.

[0142] In contrast, in the second embodiment, the cathode region 82 implantation step (S444) is performed after the collector region 22 implantation step (S420) and the floating region 84 implantation step (S440). In the second embodiment, the P-type dopant (S440) for the floating region 84 is implanted after the P-type dopant implantation step (S420) for the collector region 22 and before the N-type dopant implantation step (S444) for the cathode region 82, so that the floating region 84 can be set with better controllability. Thus, the implantation range of the P-type dopant for the floating region 84 can be set within the designed range. Therefore, the characteristic deviation among the plurality of semiconductor devices 200 can be reduced.

[0143] Furthermore, in this embodiment, since the collector region 22 implantation step (S420) is performed while the lower surface 64 is clean, defects 88 and / or damage in the collector region 22 can be reduced. Thus, current leakage and withstand voltage failure can be reduced in the semiconductor device 200. Figure 8 As in the semiconductor device 160 of FIG. 1 , the floating region 84 is formed in the cathode region 82. Fig. 9 As in the semiconductor device 180 , the lower end of the floating region 84 is formed at a position higher than the cathode region 82 .

[0144] Fig.11A 1 is a flowchart showing a method for manufacturing a semiconductor device 220 according to a first modification of the second embodiment. It should be noted that the semiconductor device 220 is shown in the following figure. In the first modification, the collector region 22 implantation step (S442) is performed after the floating region 84 implantation step (S440), and the cathode region 82 implantation step (S444) is performed after the collector region 22 implantation step (S442). This is different from the second embodiment.

[0145] Fig. 11B It is a diagram showing each step of a method for manufacturing a semiconductor device 220 according to a first modification of the second embodiment. Fig. 11B Step S440 of (a) and Fig. 10B Corresponding to step S440 of (c). Fig. 11B Step S442 of (b) and Fig. 10B Corresponding to step S420 of (b). Fig. 11B Step S444 of (c) and Fig. 10B Corresponding to step S444 of (d). Fig. 11B Step S480 of (d) and Fig. 10B In the first modification, since the floating region 84 is initially formed during the formation of the lower surface structure 118, the controllability of the floating region 84 can be further improved than in the second embodiment.

[0146] Fig. 12A 1 is a flowchart showing a method for manufacturing a semiconductor device 240 according to a second modification of the second embodiment. It should be noted that the semiconductor device 240 is shown in the following figure. In the second modification, the cathode region 82 implantation step (S444) is performed after the floating region 84 implantation step (S440), and the collector region 22 implantation step (S448) is performed after the cathode region 82 implantation step (S444). This is different from the second embodiment.

[0147] Fig. 12B It is a diagram showing each step of a method for manufacturing a semiconductor device 240 according to a second modification of the second embodiment. Fig. 12B Step S440 of (a) and Fig. 10B Corresponding to step S440 of (c). Fig. 12B Step S444 of (b) and Fig. 10B Corresponding to step S444 of (d). Fig. 12B Step S448 of (c) and Fig. 10B Corresponding to step S420 of (b). Fig. 12B Step S480 of (d) and Fig. 10BIn the second modification, since the floating region 84 is initially formed during the formation of the lower surface structure 118, the controllability of the floating region 84 can be further improved than in the second embodiment.

[0148] It should be noted that in the second embodiment, the first variation of the second embodiment, and the second variation of the second embodiment, Figure 8 As in the semiconductor device 160 of FIG. 1 , the floating region 84 is formed in the cathode region 82. Fig. 9 As in the semiconductor device 180 , the lower end of the floating region 84 is formed at a position higher than the cathode region 82 .

[0149] Fig.13A 1 is a flowchart showing a method for manufacturing a semiconductor device 300 according to a third embodiment. The semiconductor device 300 is shown in the following figure. The third embodiment differs from the above-mentioned embodiments in that the position of the boundary 72 coincides with the end 91 of the floating region 84 . Fig.13A The order of the steps shown is similar to Figure 4A Same, but can also be Figure 5A , Fig. 6A , Fig. 10A , Fig.11A and Fig. 12A Steps S520, S530 and S540 may be appropriately replaced as in the various embodiments.

[0150] Fig. 13B (a) and (b) are diagrams showing steps of a method for manufacturing a semiconductor device 300 according to the third embodiment. Fig. 13B (a) is a floating region 84 injection step (S540), Fig. 13B (b) is a collector electrode 24 forming step (S580). In step S540, the end 69 in the X-axis direction of the mask 68-2 corresponding to the floating region 84 is aligned with the boundary 72. As a result, as shown in step S580, the end 91 of the floating region 84 in the semiconductor device 300 is located at the boundary 72 in the X-axis direction. It should be noted that in this embodiment, the position of the end 91 is also the position in step S580 after the collector region 22 implantation step (S520), the cathode region 82 implantation step (S530), and the floating region 84 implantation step (S540).

[0151] In step S540 , a P-type dopant may be implanted in a region closer to the upper surface 62 than the cathode region 82 . As a result, in the semiconductor device 300 , the lower end 94 of the floating region 84 may be separated from the upper end 83 of the cathode region 82 .

[0152] In the present embodiment, although the floating region 84 is placed as close as possible to the IGBT region 70 in the XY plane direction, the floating region 84 can be reliably separated from the collector region 22 in the Z axis direction. Therefore, compared with the case where the floating region 84 is provided in the IGBT region 70, it is possible to more reliably prevent the floating region 84 from being short-circuited with the collector region 22. It should be noted that in the semiconductor device 300, the upper end 93 of the floating region 84 may be closer to the lower surface 64 than the upper end of the FS region 20. That is, the FS region 20 may be present above the upper end 93 of the floating region 84.

[0153] Fig. 13C is a diagram showing the concentration distribution of electrons and holes near the boundary 72 of the third embodiment. Fig. 13C The center of FIG. 1 shows a partial enlarged view of the vicinity of the boundary 72 in the semiconductor device 300. Fig. 13C The electron-hole concentration distributions of the EE section and the FF section of the partial enlarged view are shown respectively through the partial enlarged view near the boundary 72. In the EE section and the FF section, the horizontal axis is the electron concentration or the hole concentration (cm -3 ), the vertical axis is the depth position (μm).

[0154] Since the EE cross section Figure 7 The CC section is the same as that of the Figure 7 However, in the FF cross section, the FS region 20 is provided between the upper end 83 of the cathode region 82 and the lower end 94 of the floating region 84. The FF cross section may be similar to the DD cross section of FIG. 1 except for the position of the end 91 of the floating region 84. Fig. 9 The same as (b).

[0155] like Fig. 13C As shown, the floating region 84 may be separated from the upper end 83 of the cathode region 82. In the present embodiment, in which the upper end positions of the cathode region 82 and the collector region 22 are the same in the Z-axis direction, the lower end 94 of the floating region 84 is closer to the upper surface 62 than the upper end 23 of the collector region 22. In addition, the upper end 93 of the floating region 84 is located at a position lower than the upper end of the FS region 20. It should be noted that in the present embodiment, in the Z-axis direction, the upper end 83 of the cathode region 82 may be closer to the upper surface 62 than the upper end 23 of the collector region 22, and the floating region 84 is separated from the upper end 83 of the cathode region 82.

[0156] Fig.13D : is a diagram showing the concentration distribution of electrons and holes near the boundary 72 of the first modified example of the third embodiment. Fig.13D The center of the figure shows a partial enlarged view near the boundary 72. Fig.13DThe left and right sides of the diagram respectively show the dopant concentration distribution of the GG cross section and the HH cross section of the local enlarged view. The horizontal axis and the vertical axis of the GG cross section and the HH cross section are Fig. 13C same.

[0157] In this first variant, the thickness of the cathode region 82 in the Z-axis direction is set to be thicker than the thickness of the collector region 22 in the Z-axis direction. The upper end 83 of the cathode region 82 and the lower end 94 of the floating region 84 are set to be positions where the electron concentration and the hole concentration form a valley. For example, after the collector region 22 injection step S520 of injecting a P-type dopant into the lower surface 64, the cathode region 82 injection step S530 of injecting an N-type dopant is performed, thereby forming a cathode region 82 thicker than the collector region 22. It should be noted that the cathode region 82 injection step S530 of injecting an N-type dopant may be performed first, and then the collector region 22 injection step S520 is performed.

[0158] In the first modified example, since the cathode region 82 is thicker than the collector region 22, the upper end 83 of the cathode region 82 is located closer to the upper surface 62 than the upper end 23 of the collector region 22. In addition, the lower end 94 of the floating region 84 is closer to the upper surface 62 than the upper end 23 of the collector region 22. As a result, it is possible to reliably prevent the floating region 84 from short-circuiting with the collector region 22. Therefore, the characteristics of the semiconductor device 300 can be made close to the designed characteristics. In addition, not limited to the third embodiment in which the position of the boundary 72 is made consistent with the end 91 of the floating region 84, in the first embodiment and the second embodiment, it is also possible to make the cathode region 82 thicker than the collector region 22 to facilitate the manufacture of the desired structure and further improve the reliability. It should be noted that the cathode region 82 being thicker than the collector region 22 is not limited to the case where the cathode region 82 is slightly thicker than the collector region 22, but may also refer to the case where the cathode region 82 is significantly thicker than the collector region 22. Specifically, the thickness of the cathode region 82 may be about 1.2 times the thickness of the collector region 22 , preferably, the thickness of the cathode region 82 may be about 1.4 times the thickness of the collector region 22 , and more preferably, the thickness of the cathode region 82 may be about 1.6 times the thickness of the collector region 22 .

[0159] It should be noted that the implantation step S540 for the floating region 84 may be performed before the implantation step S520 for the collector region 22 and the implantation step S530 for the cathode region 82. In addition, the implantation step S540 for the floating region 84 may be performed between the implantation step S520 for the collector region 22 and the implantation step S530 for the cathode region 82 or after the implantation step S520 for the collector region 22 and the implantation step S530 for the cathode region 82. It should be noted that in this first modification, the end 91 of the floating region 84 is also located at the boundary 72.

[0160] Fig.13E: is a diagram showing the concentration distribution of electrons and holes near the boundary 72 of the second modification example of the third embodiment. Fig.13E The center of the figure shows a partial enlarged view near the boundary 72. Fig.13E The dopant concentration distribution of the II section and the JJ section of the partial enlarged view are shown respectively through the partial enlarged view near the boundary 72. The horizontal axis and the vertical axis of the II section and the JJ section are Fig. 13C same.

[0161] In this second modified example, the thickness of the cathode region 82 in the depth direction is also set to be thicker than the thickness of the collector region 22 in the Z-axis direction. It should be noted that the depth direction may be parallel to the direction from the lower surface 64 toward the upper surface 62. In the cathode region 82 implantation step, N-type ions may also be implanted with different acceleration energies. That is, in the cathode region 82 implantation step, ion implantation may be performed in a manner that the concentration distribution of the N-type ions has a peak at one position in the depth direction, or in a manner that the concentration distribution of the N-type ions has peaks at multiple different positions in the depth direction.

[0162] In the case where the cathode region 82 has peaks at different multiple positions in the depth direction, the peak position of the P-type dopant concentration distribution of the floating region 84 may be set between the multiple peaks of the N-type dopant concentration distribution of the cathode region 82. Each of the multiple peak concentrations in the N-type dopant concentration distribution of the cathode region 82 may be the same, may decrease toward the upper surface 62, or may increase toward the upper surface 62. In addition, the P-type dopant concentration injected in the floating region 84 injection step S540 may be higher than the N-type dopant concentration injected into the region of the floating region 84 in the cathode region 82 injection step S530.

[0163] In the second variant, N-type dopants are injected in step S530 in such a manner that the cathode region 82 has two N-type dopant concentration peaks at different positions in the depth direction. Thus, the cathode region 82 has two electron concentration peaks at different positions in the depth direction. Further, in the second variant, P-type dopants are injected in step S540 in such a manner that the peak of the P-type dopant concentration of the floating region 84 is located between the two peaks of the N-type dopant concentration. Thus, the peak position of the hole concentration in the floating region 84 is located between the two electron concentration peaks in the cathode region 82 in the depth direction. In the second variant, compared with the case where the peak position of the cathode region 82 and the peak position of the floating region 84 overlap in the depth direction, even if the P-type dopant concentration is reduced in the step of injecting the floating region 84, a floating region 84 having sufficient P-type characteristics can be obtained.

[0164] In addition, in another embodiment, the cathode region 82 may have three or more peaks of N-type dopant concentration at different positions in the depth direction. In this case, the peak position of the floating region 84 may be set between any two peak positions of the cathode region 82 .

[0165] In the second modified example, the entire range of the floating region 84 in the Z-axis direction is located in the cathode region 82. In addition, the lower end 94 of the floating region 84 is closer to the upper surface 62 than the upper end 23 of the collector region 22. Therefore, although the floating region 84 is as close to the IGBT region 70 as possible in the XY plane direction, the floating region 84 can be reliably separated from the collector region 22 in the Z-axis direction. It should be noted that in another embodiment, at least a portion of the floating region 84 may be located in the cathode region 82. That is, the lower portion of the floating region 84 may overlap with the upper portion of the cathode region 82, and the upper end 93 of the floating region 84 may be located above the upper end 83 of the cathode region 82. When the peak concentration of the floating region 84 is higher than the peak concentration of the cathode region 82, such a shape is easily formed.

[0166] It should be explained that Figure 13B to Figure 13E The description of the collector region 22 , the cathode region 82 , and the floating region 84 can also be applied to the first embodiment and the second embodiment in which the end 91 of the floating region 84 does not reach the boundary 72 in the X-axis direction.

[0167] Fig.14 1 is a top view of the FWD region 80 of the fourth embodiment. The semiconductor device of the fourth embodiment may include both the FWD region 80 and the IGBT region 70 on one semiconductor substrate 10, or may include only the FWD region 80. The IGBT region 70 is the same as the IGBT region 70 of any one of the first to third embodiments. The IGBT region 70 and the FWD region 80 are arranged side by side when viewed from above.

[0168] In this example, a region where a gate structure including a gate trench portion 40 and an emitter region 12 is periodically arranged is set as an IGBT region 70. In addition, a region where the gate structure is not provided and cathode regions 82 are periodically arranged on the lower surface 64 of the semiconductor substrate 10 is set as an FWD region 80. On the upper surface of each mesa portion 60 of the FWD region 80, more than 80% of the area can be a P-type region such as the base region 14.

[0169] The FWD region 80 of this example is different from the FWD region 80 in the first to third embodiments in that it includes an inter-cathode region 81 of the first conductivity type (in this example, P+ type) exposed on the lower surface 64 of the semiconductor substrate 10. The structure other than the inter-cathode region 81 is the same as any one of the first to third embodiments. The doping concentration and the thickness in the Z-axis direction of the inter-cathode region 81 can be the same as those of the collector region 22 of the IGBT region 70.

[0170] The cathode inter-regions 81 are arranged alternately with the cathode regions 82 in a predetermined direction in a plane parallel to the lower surface 64. Fig.14 In the example, the cathode inter-regions 81 and the cathode regions 82 are alternately arranged along the Y-axis direction. The cathode inter-regions 81 and the cathode regions 82 may have a strip shape extending along the X-axis direction from one end to the other end of the FWD region 80 in the X-axis direction.

[0171] In another example, the cathode inter-region 81 and the cathode region 82 may be alternately arranged along a direction different from the Y-axis direction. In addition, the cathode inter-region 81 and the cathode region 82 may be alternately arranged in two directions. The cathode inter-region 81 and the cathode region 82 may also be alternately arranged in two directions, the X-axis direction and the Y-axis direction.

[0172] The floating region 84 is provided above the cathode region 82 and above the inter-cathode region 81. However, the floating region 84 is not provided above a partial region of the cathode region 82. Furthermore, the floating region 84 is not provided above a partial region of the inter-cathode region 81.

[0173] By providing the inter-cathode region 81 and the floating region 84 in the FWD region 80, the amount of carriers injected from the cathode region 82 can be adjusted more accurately. Therefore, the characteristics of the semiconductor device can be adjusted more accurately.

[0174] Fig.15 Yes Fig.14 The three-dimensional cross-sectional view of the KK section and the LL section in the figure. The KK section is the XZ plane, and the LL section is the YZ plane. Fig.15 , a cross section of the semiconductor substrate 10 is shown, and the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 are omitted.

[0175] like Fig.14 and Fig.15As shown, the floating region 84 of this example is arranged to overlap with a portion of each cathode region 82 in the X-axis direction. That is, a portion of the cathode region 82 in the X-axis direction does not overlap with the floating region 84. The floating region 84 may be arranged to overlap with a portion of each cathode inter-region 81 in the X-axis direction. A portion of the cathode inter-region 81 in the X-axis direction may not overlap with the floating region 84. It should be noted that overlapping refers to relative positions arranged in the Z-axis direction. Fig.14 As shown, the floating regions 84 may be discretely arranged in the X-axis direction. A drift region 18 or a FS region 20 may be disposed between two floating regions 84 .

[0176] like Fig.14 and Fig.15 As shown, the floating region 84 of this example is arranged to overlap with the entire cathode region 82 in the Y-axis direction. The floating region 84 of this example extends to a position overlapping with a portion of the cathode inter-region 81 in the Y-axis direction. Fig.14 As shown, the floating region 84 can be discretely arranged in the Y-axis direction. Both ends of each cathode region 82 in the Y-axis direction can overlap with the floating region 84. In another example, the floating region 84 can also be arranged to overlap with the entirety of each inter-cathode region 81 in the Y-axis direction. In this case, the floating region 84 can extend in the Y-axis direction to a position overlapping with a portion of the cathode region 82.

[0177] like Fig.15 As shown, the dummy groove portion 30 is extended along a predetermined extension direction (in this example, the Y-axis direction). The extension direction of the dummy groove portion 30 is the long side direction of the dummy groove portion 30 in the top view. The cathode inter-region 81 and the cathode region 82 are alternately arranged along the extension direction (Y-axis direction) of the dummy groove portion 30. Therefore, both the cathode inter-region 81 and the cathode region 82 are arranged below each mesa portion 60-2. Therefore, in each mesa portion 60-2, the carrier injection amount from the cathode region 82 can be made uniform.

[0178] Furthermore, the floating region 84 is arranged apart from the inter-cathode region 81 in the depth direction of the semiconductor substrate 10. Thus, the floating region 84 is prevented from being connected to the collector electrode 24 via the inter-cathode region 81. Between the inter-cathode region 81 and the floating region 84, the FS region 20 or the drift region 18 may be provided.

[0179] Fig.161 is an enlarged top view illustrating an example of the configuration of the floating region 84, the cathode region 82, and the inter-cathode region 81. In this example, the region where the floating region 84 overlaps with the inter-cathode region 81 is set as the first region 101, the region where the inter-cathode region 81 is set and the floating region 84 is not set is set as the second region 102, the region where the cathode region 82 overlaps with the floating region 84 is set as the third region 103, and the region where the cathode region 82 is set and the floating region 84 is not set is set as the fourth region 104. The first region 101 is a region where the injection amount of electrons from the lower surface 64 side is the least, that is, a region where there is substantially no injection amount of electrons, and the fourth region 104 is a region where the injection amount of electrons from the lower surface 64 side is the largest. The second region 102 is also a region where there is substantially no injection amount of electrons, similarly to the first region 101. On the other hand, the first region 101 and the second region 102 have the effect of injecting holes during reverse recovery, and the injection amount of holes can also be adjusted by the floating region 84. The third region 103 is a region where the amount of electrons injected from the lower surface 64 side is larger than that of the first region 101 and the second region 102, and smaller than that of the fourth region 104. The amount of electrons injected is an amount per unit area.

[0180] In this way, by arranging the floating region 84 to overlap with the cathode region 82 and the inter-cathode region 81, the first region 101, the second region 102, the third region 103, and the fourth region 104 for adjusting the injection of carriers (electrons / holes) can be provided. By adjusting the area ratio of these regions, the total injection amount of carriers (electrons / holes) in the FWD region 80 can be adjusted with good precision. In addition, by arranging the floating region 84 for each cathode region 82 in the Y-axis direction and setting the width of the floating region 84 to be larger than the width of the cathode region 82, the first region 101 can be arranged at each boundary between the cathode region 82 and the inter-cathode region 81.

[0181] As an example, the area of ​​the floating region 84 when viewed from above may be larger than the area of ​​the cathode region 82. The area of ​​the floating region 84 is larger than the area of ​​the first region 101. In addition, the area of ​​the floating region 84 is larger than the area of ​​the third region 103. The area of ​​the floating region 84 may be less than 90% of the sum of the areas of the cathode region 82 and the inter-cathode region 81. In addition, the area of ​​the inter-cathode region 81 when viewed from above may be larger than the area of ​​the cathode region 82. It should be noted that the area of ​​each region refers to the total area of ​​each region in the FWD region 80.

[0182] Fig.17 : is a diagram showing the cathode region 82 and the inter-cathode region 81 in the YZ plane. With the lower surface 64 of the semiconductor substrate 10 as a reference, the cathode region 82 is set to reach a position deeper than the inter-cathode region 81. The thickness of the cathode region 82 in the depth direction (Z-axis direction) is set to Z2, and the thickness of the inter-cathode region 81 is set to Z1. The thickness Z2 is greater than the thickness Z1.

[0183] The floating region 84 is arranged above the upper end of the cathode region 82. By increasing the thickness Z2 of the cathode region 82, it is possible to suppress the floating region 84 from contacting the inter-cathode region 81. The floating region 84 and the cathode region 82 may be in contact or separated.

[0184] Fig.18 FIG. 8 is a top view of the FWD region 80 of the first modified example of the fourth embodiment. Figure 14 to Figure 16 The difference between the example described in the embodiment is the configuration of the floating region 84 in the Y-axis direction. Figure 14 to Figure 16 The example described in is the same.

[0185] The floating region 84 of this example is arranged so as to overlap the entire inter-cathode region 81 in the Y-axis direction and overlap a partial region of the cathode region 82 in the Y-axis direction. Fig.14 In the example shown, it is possible to reduce Fig.16 The area of ​​the fourth region 104 shown in the figure can reduce the amount of electrons injected from the cathode region 82. In this example, since the area of ​​the fourth region 104 is increased, the amount of electrons injected from the cathode region 82 is increased. In this way, by providing the floating region 84 and the inter-cathode region 81, the amount of electrons injected from the cathode region 82 can be easily adjusted.

[0186] Fig.19 FIG. 8 is a top view of the FWD region 80 of the second modified example of the fourth embodiment. Figure 14 to Figure 18 The difference between the example described in the embodiment is that the cathode regions 82 and the inter-cathode regions 81 are arranged alternately along the X-axis direction. Figure 14 to Figure 18 The example described in is the same.

[0187] exist Fig.19 In the embodiment, the floating region 84 is configured to overlap with the entire cathode region 82 in the X-axis direction and to overlap with a partial region in the X-axis direction of the cathode inter-region 81. In another example, the floating region 84 may also be configured to overlap with the entire cathode inter-region 81 in the X-axis direction and to overlap with a partial region in the X-axis direction of the cathode region 82. According to this example, the amount of electrons injected from the cathode region 82 of the FWD region 80 can also be controlled with good accuracy.

[0188] Fig. 20 FIG. 8 is a top view of the FWD region 80 of the third modified example of the fourth embodiment. Figures 14 to 19 The difference between the example described in FIG. 1 and FIG. 2 is the configuration of the floating region 84. The other structures are the same as those in FIG. Figures 14 to 19 The example described in is the same.

[0189] In this example, the width in the X-axis direction of the floating region 84 that is configured closest to the boundary 72 with the IGBT region 70 is set to X1. In addition, the width in the X-axis direction of the floating region 84 that is configured in the center of the FWD region 80 in the X-axis direction is set to X2. The width X1 in this example is larger than the width X2. The width X1 can be more than 1.5 times the width X2, or more than 2 times the width X2. As a result, the injection of electrons from the cathode region 82 can be suppressed near the boundary 72 with the IGBT region 70. Therefore, the carriers flowing from the FWD region 80 to the IGBT region 70 can be reduced. The width in the X-axis direction of the floating region 84 that is configured closest to the boundary 72 with the IGBT region 70 can be the largest among the multiple floating regions 84.

[0190] In another example, the width X1 may be smaller than the width X2. The width X2 may be 1.5 times or more of the width X1, or may be 2 times or more of the width X1. The width of the floating region 84 closest to the boundary 72 with the IGBT region 70 in the X-axis direction may be the smallest among the plurality of floating regions 84.

[0191] Fig.21 FIG. 8 is a top view of the FWD region 80 of the third modified example of the fourth embodiment. Figures 14 to 20 The difference between the example described in FIG. 1 and FIG. 2 is the configuration of the floating region 84. The other structures are the same as those in FIG. Figures 14 to 20 The example described in is the same.

[0192] The floating region 84 of this example is continuously provided across the entirety of one or more cathode regions 82 and the entirety of one or more inter-cathode regions 81 in the Y-axis direction. The floating region 84 may also be continuously provided across a plurality of cathode regions 82 and a plurality of inter-cathode regions 81.

[0193] Fig. 22 It is shown Fig.21 An example of a MM cross section in FIG. Fig. 22 , a cross section near the lower surface 64 of the semiconductor substrate 10 is shown. In this example, the distance in the depth direction (Z-axis direction) between the upper end of the cathode region 82 and the lower end of the floating region 84 is set to Z5. In addition, the distance in the depth direction (Z-axis direction) between the upper end of the cathode inter-region 81 and the lower end of the floating region 84 is set to Z3.

[0194] Each distance in the depth direction can be measured at the center of the cathode region 82 in the Y-axis direction and the center of the inter-cathode region 81 in the Y-axis direction. In addition, the average value of the distance between the cathode region 82 and the floating region 84 can be set as the distance Z5. In addition, the average value of the distance between the inter-cathode region 81 and the floating region 84 can be set as the distance Z3.

[0195] The distance Z5 may be smaller than the distance Z3. Thus, the distance between the cathode region 82 into which electrons are injected and the floating region 84 is reduced, and the injection of electrons is easily suppressed. In addition, by setting the distance Z3 to be larger than the distance Z5, the contact between the floating region 84 and the cathode inter-region 81 can be suppressed. The distance Z3 may be more than 1.1 times the distance Z5, more than 1.2 times the distance Z5, or more than 1.5 times the distance Z5. In addition, the distance Z5 may be zero, and the distance Z3 may be larger than zero.

[0196] In this example, use Fig.21 The example shown illustrates the shape of the floating region 84, but in Figures 14 to 20 In the example shown, the floating region 84 may also have the same shape. In the case where the floating region 84 is formed by injecting a P-type dopant from the lower surface 64 side after forming both the cathode region 82 and the inter-cathode region 81, Figures 14 to 20 In the example shown, the distance Z5 is also smaller than the distance Z3. The shape of the floating region 84 is not limited to the shape of Fig.21 and Fig. 22 The floating region 84 shown in the figure is formed over a plurality of cathode regions 82 and a plurality of inter-cathode regions 81. In addition, in this cross section, the shape of the floating region 84 is stepped near the boundary 72, but in another example, the shape of the floating region 84 may be curved near the boundary 72.

[0197] Fig.23 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the fourth embodiment. Fig. 22 The method for manufacturing a semiconductor device having a FWD region 80 shown in FIG. Fig.13A Steps S510 and S550 to S580 are the same.

[0198] Fig.24 Yes Description Fig.23 FIG. 6 is a diagram of a P-type dopant implantation step S620, a cathode region implantation step S632, and a floating region implantation step S640. Fig.24 Although only the FWD region 80 is shown in the figure, the semiconductor device may include the IGBT region 70 similar to that of the first to third embodiments.

[0199] In step S620, a P+ type collector region 22 and a P+ type cathode inter-region 81 are formed. The collector region 22 can be formed on the entire lower surface of the IGBT region 70. The cathode inter-region 81 can be formed on the entire lower surface of the FWD region 80. The collector region 22 and the cathode inter-region 81 can be formed in the same process. Next, in step S632, N-type dopants are selectively counter-doped into the cathode inter-region 81 of the FWD region 80 from the lower surface 64 of the semiconductor substrate 10. As a result, a local area of ​​the cathode inter-region 81 of the FWD region 80 is inverted to N+ type. Among the cathode inter-region 81 of the FWD region 80, the area inverted to N+ type becomes the cathode region 82, and the area where the P+ type state remains remains as the cathode inter-region 81. In step S632, N-type dopants are selectively implanted in a manner that the cathode regions 82 and the cathode inter-region 81 are alternately arranged in a predetermined direction. In step S632 , the mask 68 - 1 may be used to select a region where an N-type dopant is implanted.

[0200] Next, in step S640, a P-type dopant for forming the floating region 84 is injected from the lower surface 64 of the semiconductor substrate 10. Before the P-type dopant is injected, the mask 68-1 may be removed and a new mask 68-2 may be provided on the lower surface 64 of the semiconductor substrate 10. The cathode region 82 contains both the P-type dopant for forming the cathode inter-region 81 and the N-type dopant for forming the cathode region 82. Therefore, in step S640, the P-type dopant passing through the cathode region 82 is more likely to be injected into a position with a shorter distance from the lower surface 64 than the P-type dopant passing through the cathode inter-region 81.

[0201] Therefore, by injecting P-type dopants into the cathode region 82 and the inter-cathode region 81 under the same conditions, it is possible to form Fig. 22 In another example, a mask or the like for shortening the range of the P-type dopant may be selectively provided on the lower surface of the cathode region 82, and then the P-type dopant may be implanted.

[0202] In addition, since the cathode region 82 is formed before the floating region 84 is formed, the Figure 4B The possibility of generation and / or attachment of particles 86 described in the above is reduced. Therefore, the influence of junction leakage, withstand voltage failure, switching characteristics, etc. can be suppressed.

[0203] Fig.25 is a flowchart showing another example of the method for manufacturing a semiconductor device according to the fourth embodiment. Steps S610 and S650 to S680 of this example are the same as Fig.13A The steps S510 and S550 to S580 in the embodiment are the same. Fig.23 and Fig.24In the manufacturing method shown, the order of the floating region implantation step and the cathode region implantation step is reversed.

[0204] Fig.26 Yes Description Fig.25 FIG. 6 is a diagram of the P-type dopant implantation step S620, the floating region implantation step S642, and the cathode region implantation step S634. Fig.26 Although only the FWD region 80 is shown in the figure, the semiconductor device may include the IGBT region 70 similar to that of the first to third embodiments.

[0205] In step S620, a P+ type cathode inter-region 81 is formed. Fig.23 and Fig.24 Next, in step S642, a P-type dopant for forming the floating region 84 is implanted from the lower surface 64 of the semiconductor substrate 10. Before implanting the P-type dopant, a mask 68-2 may be provided on the lower surface 64 of the semiconductor substrate 10.

[0206] Next, in step S634, N-type dopants are selectively counter-doped into the cathode inter-region 81 of the FWD region 80 from the lower surface 64 of the semiconductor substrate 10. As a result, a local area of ​​the cathode inter-region 81 is inverted to N+ type. Among the cathode inter-region 81 of the FWD region 80, the area inverted to N+ type becomes the cathode region 82, and the area with P+ type remaining is retained as the cathode inter-region 81. Step S634 and Fig.23 and Fig.24 The same as step S632 in.

[0207] In this example, a P-type dopant for forming the floating region 84 is injected before the cathode region 82 is formed. Therefore, the floating region 84 is formed at a fixed depth position. That is, the floating region 84 can be easily formed at a predetermined depth position. For example, if the floating region 84 is formed in a manner to reach the drift region 18 with a lower doping concentration, the region inverted to the P-type is likely to expand, and there is a situation where it is difficult to control the depth position of the floating region 84. According to this example, since the entire floating region 84 can be easily formed in the FS region 20 with a higher doping concentration, the position of the floating region 84 can be easily controlled.

[0208] Fig.27A is a flowchart showing another example of the method for manufacturing a semiconductor device according to the fourth embodiment. Steps S610 and S620 to S680 of this example are similar to Fig.23 The steps S610 and S620 to S680 in FIG. 1 are the same. In addition, the manufacturing method of this example is relative to Fig.23 and Fig.24 In the manufacturing method shown, the order of the implantation step for the cathode region and the implantation step for the collector region and the cathode inter-region is reversed.

[0209] In this example, after step S610, a cathode region injection step S636 is performed. In step S636, the cathode region is injected using Fig.24 The N-type dopant is selectively implanted in the region where the cathode region 82 is to be formed using the mask 68-1 shown in step S632. The mask 68-1 is provided to cover the entire lower surface of the IGBT region 70 and the region of the FWD region 80 where the cathode inter-region 81 is to be formed.

[0210] Next, in step S620, a P-type dopant is injected from the lower surface 64 of the semiconductor substrate 10 to form the collector region 22 and the cathode inter-region 81. In step S620, the P-type dopant can be injected into the entire lower surface 64 of the semiconductor substrate 10. That is, the cathode region 82 into which the N-type dopant is injected in step S636 can also be injected with the P-type dopant. In this case, in step S636, the N-type dopant is injected at a concentration such that the cathode region 82 can maintain the N+ type even if the P-type dopant is injected in step S620.

[0211] After step S620, a floating region 84 is formed. Fig.23 and Fig.24 Similarly, the example can be formed in Fig. 22 Furthermore, since the cathode region 82 is formed before the floating region 84 is formed, the cathode region 82 can be reduced. Figure 4B The possibility of generation and / or attachment of particles 86 described in the above is reduced. Therefore, the influence of junction leakage, withstand voltage failure, switching characteristics, etc. can be suppressed.

[0212] Fig.27B is a flowchart showing another example of the method for manufacturing a semiconductor device according to the fourth embodiment. Fig.27A The difference between the manufacturing method described in the embodiment is that the order of step S620 and step S640 is reversed. Fig.27A Same as the example.

[0213] In this example, after step S636, a floating region injection step S640 is performed. In step S640, the floating region may be implanted as follows: Fig.24 After step S640, in step S620, P-type dopants are implanted from the lower surface 64 of the semiconductor substrate 10 to form the collector region 22 and the cathode inter-region 81. Step S620 and Fig.27A In this example, since the floating region 84 is formed after the cathode region 82 is selectively formed, the floating region 84 can be formed. Fig. 22 A floating region 84 of the shape illustrated in FIG.

[0214] Fig.28A is a flowchart showing another example of the method for manufacturing a semiconductor device according to the fourth embodiment. Steps S610 and S620 to S680 of this example are similar to Fig.23 The steps S610 and S620 to S680 in FIG. 1 are the same. In addition, the manufacturing method of this example is relative to Fig.23 and Fig.24 In the manufacturing method shown, the order of the implantation step for the floating region, the implantation step for the cathode region, and the implantation step for the collector region and the inter-cathode region is reversed.

[0215] In this example, after step S610, a floating area injection step S644 is performed. In step S644, the floating area is injected using Fig.26 The P-type dopant is selectively implanted into the region where the floating region 84 is to be formed through the mask 68 - 2 shown in step S642 .

[0216] Next, in step S620, P-type dopants are implanted from the lower surface 64 of the semiconductor substrate 10 to form the collector region 22 and the inter-cathode region 81. In step S620, the P-type dopants may be implanted into the entire lower surface 64 of the semiconductor substrate 10.

[0217] Next, in step S632, N-type dopants are selectively counterdoped into the cathode inter-region 81 of the FWD region 80 from the lower surface 64 of the semiconductor substrate 10. Thus, a portion of the cathode inter-region 81 is inverted into an N+ type region, forming a cathode region 82.

[0218] In this case, also with Fig.25 and Fig.26 Similarly to the example of FIG. 8 , the floating region 84 is formed at a fixed depth position. That is, the floating region 84 can be easily formed at a predetermined depth position.

[0219] Fig.28B is a flowchart showing another example of the method for manufacturing a semiconductor device according to the fourth embodiment. Fig.28A The difference between the manufacturing method described in the embodiment is that the order of step S620 and step S632 is reversed. Fig.28A Same as the example.

[0220] In this example, step S620 and step S632 are performed after step S644. Step S620 and step S632 are Fig.27A Step S620 is the same as step S636.

[0221] In this case, also with Fig.25 and Fig.26Similarly to the example of FIG. 8 , the floating region 84 is formed at a fixed depth position. That is, the floating region 84 can be easily formed at a predetermined depth position.

[0222] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the manner in which such changes or improvements are made can obviously also be included in the technical scope of the present invention.

[0223] It should be noted that the execution order of each process such as actions, processes, steps and stages in the device, system, program and method shown in the claims, specifications and drawings can be implemented in any order as long as "earlier than" or "in advance" is not specifically stated, and the previous processing results are not used in the subsequent processing. Even if the action flow in the claims, specifications and drawings is explained using "first" or "next" for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: The semiconductor device has a diode region disposed on a semiconductor substrate. The diode region comprises: A base region of a first conductivity type is provided in a manner of being exposed on the upper surface of the semiconductor substrate; A cathode region of the second conductivity type is disposed in a manner of being exposed on the lower surface of the semiconductor substrate; a first conductivity type inter-cathode region, which is provided in a manner of being exposed on the lower surface of the semiconductor substrate and is arranged alternately with the cathode region in a predetermined direction; and A floating region of the first conductivity type is arranged above the cathode region and above the inter-cathode region, The diode region further includes a dummy groove portion, wherein the dummy groove portion is extended along an extension direction on the upper surface of the semiconductor substrate. The cathode regions and the inter-cathode regions are alternately arranged in the extending direction, In the extending direction in a plan view, the floating region overlaps with the entirety of one or more inter-cathode regions and does not overlap with a portion of the cathode region.

2. The semiconductor device according to claim 1, wherein: The inter-cathode region and the cathode region have a strip shape extending from one end of the diode region in a direction perpendicular to the extending direction to the other end in the perpendicular direction.

3. A semiconductor device, characterized in that: The semiconductor device has a diode region disposed on a semiconductor substrate. The diode region comprises: A base region of a first conductivity type is provided in a manner of being exposed on the upper surface of the semiconductor substrate; A cathode region of the second conductivity type is disposed in a manner of being exposed on the lower surface of the semiconductor substrate; a first conductivity type inter-cathode region, which is provided in a manner of being exposed on the lower surface of the semiconductor substrate and is arranged alternately with the cathode region in a predetermined direction; and A floating region of the first conductivity type is arranged above the cathode region and above the inter-cathode region, The diode region further includes a dummy groove portion, wherein the dummy groove portion is extended along an extension direction on the upper surface of the semiconductor substrate. The cathode regions and the inter-cathode regions are alternately arranged in the extending direction, In the extending direction in a plan view, the floating region overlaps with the entirety of one or more inter-cathode regions and does not overlap with a portion of the inter-cathode regions.

4. The semiconductor device according to claim 3, wherein: The inter-cathode region and the cathode region have a strip shape extending from one end of the diode region in a direction perpendicular to the extending direction to the other end in the perpendicular direction.

5. A semiconductor device, characterized in that: The semiconductor device has a diode region disposed on a semiconductor substrate. The diode region comprises: A base region of a first conductivity type is provided in a manner of being exposed on the upper surface of the semiconductor substrate; A cathode region of the second conductivity type is disposed in a manner of being exposed on the lower surface of the semiconductor substrate; a first conductivity type inter-cathode region, which is provided in a manner of being exposed on the lower surface of the semiconductor substrate and is arranged alternately with the cathode region in a predetermined direction; and A floating region of the first conductivity type is arranged above the cathode region and above the inter-cathode region, The diode region further includes a dummy groove portion, wherein the dummy groove portion is extended along an extension direction on the upper surface of the semiconductor substrate. The cathode regions and the inter-cathode regions are alternately arranged in the extending direction, The widths of the cathode region and the inter-cathode region in the extending direction are greater than the width of the dummy trench portion in a direction perpendicular to the extending direction.

6. A semiconductor device, characterized in that: The semiconductor device has a diode region disposed on a semiconductor substrate. The diode region comprises: A base region of a first conductivity type is provided in a manner of being exposed on the upper surface of the semiconductor substrate; A cathode region of the second conductivity type is disposed in a manner of being exposed on the lower surface of the semiconductor substrate; The first conductive type inter-cathode region is provided in a manner of being exposed on the lower surface of the semiconductor substrate and is arranged alternately with the cathode region in a predetermined direction; A floating region of the first conductivity type, arranged above the cathode region and above the inter-cathode region; A drift region of a second conductivity type; and A buffer zone of the second conductivity type is disposed between the drift region and the lower surface of the semiconductor substrate, and has a concentration higher than that of the drift region. The doping concentration of the cathode region is higher than the doping concentration of the buffer region, In the diode region, the cathode region is provided deeper than the inter-cathode region with respect to the lower surface of the semiconductor substrate.

7. A semiconductor device, characterized in that: The semiconductor device has a diode region disposed on a semiconductor substrate. The diode region comprises: A base region of a first conductivity type is provided in a manner of being exposed on the upper surface of the semiconductor substrate; A cathode region of the second conductivity type is disposed in a manner of being exposed on the lower surface of the semiconductor substrate; The first conductive type inter-cathode region is provided in a manner of being exposed on the lower surface of the semiconductor substrate and is arranged alternately with the cathode region in a predetermined direction; A floating region of the first conductivity type, arranged above the cathode region and above the inter-cathode region; A drift region of a second conductivity type; and A buffer zone of the second conductivity type is disposed between the drift region and the lower surface of the semiconductor substrate, and has a concentration higher than that of the drift region. The doping concentration of the cathode region is higher than the doping concentration of the buffer region, In a depth direction of the semiconductor substrate, a distance between an upper end of the cathode region and a lower end of the floating region is smaller than a distance between an upper end of the inter-cathode region and a lower end of the floating region.

8. A semiconductor device, characterized in that: The semiconductor device includes a transistor region and a diode region on a semiconductor substrate. The diode region comprises: A base region of a first conductivity type is provided in a manner of being exposed on the upper surface of the semiconductor substrate; A cathode region of the second conductivity type is disposed in a manner of being exposed on the lower surface of the semiconductor substrate; The first conductive type inter-cathode region is provided in a manner of being exposed on the lower surface of the semiconductor substrate and is arranged alternately with the cathode region in a predetermined direction; A floating region of the first conductivity type, arranged above the cathode region and above the inter-cathode region; A drift region of a second conductivity type; and A buffer zone of the second conductivity type is disposed between the drift region and the lower surface of the semiconductor substrate, and has a concentration higher than that of the drift region. The transistor region includes a collector region of a first conductivity type exposed on the lower surface of the semiconductor substrate. The doping concentration of the cathode region is higher than the doping concentration of the buffer region, An upper end of the cathode region is closer to an upper surface of the semiconductor substrate than an upper end of the collector region.

9. A semiconductor device, characterized in that: The semiconductor device includes a transistor region and a diode region on a semiconductor substrate. The diode region comprises: A base region of a first conductivity type is provided in a manner of being exposed on the upper surface of the semiconductor substrate; A cathode region of the second conductivity type is disposed in a manner of being exposed on the lower surface of the semiconductor substrate; a first conductivity type inter-cathode region, which is provided in a manner of being exposed on the lower surface of the semiconductor substrate and is arranged alternately with the cathode region in a predetermined direction; and A floating region of the first conductivity type is arranged above the cathode region and above the inter-cathode region, The transistor region includes a collector region of a first conductivity type exposed on the lower surface of the semiconductor substrate. The lower end of the floating region is closer to the upper surface of the semiconductor substrate than the upper end of the collector region. At least a portion of the floating region is located in the cathode region, The cathode region has at least two electron concentration peaks at different positions in the depth direction from the lower surface toward the upper surface, The peak position of the hole concentration in the floating region is located between two peaks of at least two electron concentration peaks in the cathode region in the depth direction.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The semiconductor device further includes a transistor region provided on the semiconductor substrate and arranged to be aligned with the diode region when the semiconductor substrate is viewed from above.

11. The semiconductor device according to any one of claims 1 to 9, wherein: The inter-cathode region is arranged to be separated from the floating region in a depth direction of the semiconductor substrate.

12. The semiconductor device according to any one of claims 1 to 9, wherein: When the semiconductor substrate is viewed from above, an area of ​​the floating region provided in the diode region is larger than an area of ​​the cathode region provided in the diode region.

13. The semiconductor device according to any one of claims 1 to 9, characterized in that When the semiconductor substrate is viewed in plan, an area of ​​the inter-cathode region provided in the diode region is larger than an area of ​​the cathode region provided in the diode region.

14. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device has a transistor region and a diode region on a semiconductor substrate. The method for manufacturing a semiconductor device comprises: A collector region implantation step of implanting a first conductive type dopant into the lower surface of the semiconductor substrate to form a collector region in the transistor region; a cathode region implantation step of implanting a second conductive type dopant into the lower surface of the semiconductor substrate to form a cathode region in the diode region; and a floating region implantation step, after the cathode region implantation step, implanting a first conductivity type dopant into the lower surface of the semiconductor substrate to form a first conductivity type floating region disposed in the diode region, A lower end of the floating region is closer to an upper surface of the semiconductor substrate than an upper end of the collector region.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The cathode region implantation step is performed after the collector region implantation step.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: The collector region implantation step is performed after the cathode region implantation step, and the floating region implantation step is performed after the collector region implantation step.

17. The method for manufacturing a semiconductor device according to claim 14, wherein: The collector region implantation step is performed after the floating region implantation step.

18. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device has a transistor region and a diode region on a semiconductor substrate. The method for manufacturing a semiconductor device comprises: A collector region implantation step of implanting a first conductive type dopant into the lower surface of the semiconductor substrate to form a collector region in the transistor region; A floating region implantation step of implanting a first conductivity type dopant into the lower surface of the semiconductor substrate to form a first conductivity type floating region disposed in the diode region; and a cathode region implantation step, after the floating region implantation step, implanting a second conductive type dopant into the lower surface of the semiconductor substrate to form a cathode region in the diode region, A lower end of the floating region is closer to an upper surface of the semiconductor substrate than an upper end of the collector region.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The floating region implantation step is performed after the collector region implantation step.

20. The method for manufacturing a semiconductor device according to claim 18, wherein: The collector region implantation step is performed after the floating region implantation step, and the cathode region implantation step is performed after the collector region implantation step.

21. The method for manufacturing a semiconductor device according to claim 18, wherein: The collector region implantation step is performed after the cathode region implantation step.

22. The method for manufacturing a semiconductor device according to any one of claims 14 to 21, characterized in that: After the collector region implantation step, the cathode region implantation step and the floating region implantation step, An end of the floating region closest to the boundary between the collector region and the cathode region does not reach the boundary in a direction parallel to an arrangement direction of the cathode region and the collector region from the cathode region toward the collector region. The floating region is located within the diode region.

23. The method for manufacturing a semiconductor device according to any one of claims 14 to 21, characterized in that: After the collector region implantation step, the cathode region implantation step and the floating region implantation step, An end portion of the floating region closest to a boundary between the collector region and the cathode region is located at the boundary in a direction parallel to an arrangement direction of the cathode region and the collector region from the cathode region toward the collector region.

24. The method for manufacturing a semiconductor device according to any one of claims 14 to 21, wherein: After the collector region implantation step, the cathode region implantation step and the floating region implantation step, At least a portion of the floating region is located in the cathode region.

25. The method for manufacturing a semiconductor device according to claim 24, wherein: The cathode region has at least two electron concentration peaks at different positions in a depth direction from the lower surface toward the upper surface, The peak position of the hole concentration in the floating region is located between two peaks of at least two electron concentration peaks in the cathode region in the depth direction.

26. The method for manufacturing a semiconductor device according to any one of claims 14 to 21, wherein: A lower end of the floating region is separated from an upper end of the cathode region.

27. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device has a transistor region and a diode region on a semiconductor substrate. The method for manufacturing a semiconductor device comprises: A collector region implantation step of implanting a first conductive type dopant into the lower surface of the semiconductor substrate to form a collector region in the transistor region; a cathode region implantation step of implanting a second conductive type dopant into the lower surface of the semiconductor substrate to form a cathode region in the diode region; and a floating region implantation step, after the cathode region implantation step, implanting a first conductivity type dopant into the lower surface of the semiconductor substrate to form a first conductivity type floating region disposed in the diode region, After the collector region implantation step, the cathode region implantation step and the floating region implantation step, An upper end of the cathode region is closer to an upper surface of the semiconductor substrate than an upper end of the collector region.

28. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device has a transistor region and a diode region on a semiconductor substrate. The method for manufacturing a semiconductor device comprises: A collector region implantation step of implanting a first conductive type dopant into the lower surface of the semiconductor substrate to form a collector region in the transistor region; A floating region implantation step of implanting a first conductivity type dopant into the lower surface of the semiconductor substrate to form a first conductivity type floating region disposed in the diode region; and a cathode region implantation step, after the floating region implantation step, implanting a second conductive type dopant into the lower surface of the semiconductor substrate to form a cathode region in the diode region, After the collector region implantation step, the cathode region implantation step and the floating region implantation step, An upper end of the cathode region is closer to an upper surface of the semiconductor substrate than an upper end of the collector region.

29. The method for manufacturing a semiconductor device according to any one of claims 14 to 21, wherein: In the cathode region implantation step, a second conductivity type dopant is implanted into a local region of the lower surface of the semiconductor substrate in the diode region to form the cathode region and a first conductivity type inter-cathode region alternately arranged with the cathode region in a predetermined direction.

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