semiconductor devices

Abstract

A semiconductor device includes: a substrate; a gate electrode on the substrate; a gate spacer on a sidewall of the gate electrode; an active pattern penetrating the gate electrode and the gate spacer; and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction intersecting the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2017-0180511 filed on December 27, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a gate all-around structure and a method for manufacturing the same. Background Art

[0004] In order to increase the integration density of integrated circuit devices, a multi-gate transistor has been proposed, which includes a fin-shaped or nanowire-shaped silicon body on a substrate and a gate on the silicon body.

[0005] Because multi-gate transistors can utilize a three-dimensional channel, they can be scaled down. Furthermore, the current control capability of a multi-gate transistor can be improved without increasing the gate length of the multi-gate transistor. Short channel effects (SCEs), in which the potential of the channel region is affected by the drain voltage, can be effectively reduced and / or suppressed in multi-gate transistors. Summary of the Invention

[0006] According to an example embodiment of the present inventive concept, a semiconductor device may include: a substrate; a gate electrode on the substrate; a gate spacer on a sidewall of the gate electrode; an active pattern penetrating the gate electrode and the gate spacer; and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode may extend in a first direction. The gate spacer may include a semiconductor material layer. The active pattern may extend in a second direction intersecting the first direction.

[0007] According to example embodiments of the present inventive concepts, a semiconductor device may include: a substrate; a first active pattern on the substrate; a gate electrode surrounding the first active pattern; an inner spacer on a sidewall of the gate electrode; and an epitaxial pattern in contact with the first active pattern and the inner spacer. The inner spacer may be between the first active pattern and the substrate and include a semiconductor material.

[0008] According to an example embodiment of the present inventive concept, a semiconductor device may include: a substrate including a first region and a second region; a first gate electrode on the first region; a first gate spacer on a sidewall of the first gate electrode; a first active pattern penetrating the first gate electrode and the first gate spacer; a first epitaxial pattern on the sidewall of the first gate spacer; a second gate electrode on the second region; and a second epitaxial pattern on the sidewall of the second gate electrode. The first gate electrode may extend in a first direction. The first gate spacer may include a first semiconductor material. The first active pattern may extend in a second direction intersecting the first direction. The second gate electrode extends in a third direction. The second active pattern may extend in a fourth direction intersecting the third direction.

[0009] According to an example embodiment of the present invention, a method for manufacturing a semiconductor device may include: forming a fin structure including at least one sacrificial pattern and at least one active pattern alternately stacked on a substrate; selectively recessing a sidewall of at least one sacrificial pattern; forming an inner spacer along the sidewall of at least one active pattern and the recessed sidewall of at least one sacrificial pattern; forming an inner spacer on the recessed sidewall of at least one sacrificial pattern by removing a portion of the inner spacer on the sidewall of at least one active pattern; and forming an epitaxial pattern in contact with the inner spacer and the at least one active pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a perspective view of a semiconductor device according to example embodiments.

[0011] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'.

[0012] Figure 3a and Figure 3b yes Figure 2 An enlarged view of portion R1.

[0013] Figure 4 It is along Figure 1 A cross-sectional view taken along line BB'.

[0014] Figure 5 is a cross-sectional view of a semiconductor device according to example embodiments.

[0015] Figure 6 is a cross-sectional view of a semiconductor device according to example embodiments.

[0016] Figure 7 yes Figure 6 An enlarged view of portion R2.

[0017] Figure 8 is a cross-sectional view of a semiconductor device according to example embodiments.

[0018] Figure 9 is a perspective view of a semiconductor device according to example embodiments.

[0019] Figure 10 It is along Figure 9 A cross-sectional view taken along line CC' and line DD'.

[0020] Figure 11 is a perspective view of a semiconductor device according to example embodiments.

[0021] Figure 12 It is along Figure 11 A cross-sectional view taken along line EE' and line FF'.

[0022] Figure 13 is a perspective view of a semiconductor device according to example embodiments.

[0023] Figure 14 and Figure 15 It is along Figure 13 A cross-sectional view taken along line GG' and line HH'.

[0024] Figures 16 to 29 are views illustrating stages in a method of manufacturing an image sensor according to example embodiments. DETAILED DESCRIPTION

[0025] Various example embodiments will now be described more fully hereinafter with reference to the accompanying drawings.Throughout this application, like reference numerals may refer to like elements.

[0026] In the following, reference will be made to Figures 1 to 15 A semiconductor device according to example embodiments is described. For ease of illustration, device isolation layers such as shallow trench isolation (STI) are omitted in the drawings.

[0027] Figure 1 is a perspective view of a semiconductor device according to example embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'. Figure 3a and Figure 3b yes Figure 2 An enlarged view of portion R1. Figure 4 It is along Figure 1 For simplicity, Figure 1 The interlayer insulating layer 160 is not shown.

[0028] Reference Figures 1 to 4The semiconductor device includes a substrate 100, a field insulation layer 105, a first active pattern 110, a second active pattern 120, a first gate structure 150, a first gate spacer 130, a first epitaxial pattern 140, and an interlayer insulation layer 160. The terms "first," "second," "third," etc., used herein are merely used to distinguish directions, regions, parts, or elements from one another.

[0029] Substrate 100 may include a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In some embodiments, substrate 100 may include, for example, at least one of silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Substrate 100 may include an epitaxial layer formed on a base substrate. Hereinafter, for ease of description, substrate 100 will be described as including silicon.

[0030] The substrate 100 includes a first fin protrusion 100P. The first fin protrusion 100P may protrude from the upper surface of the substrate 100 and extend longitudinally in a first direction X1. Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and "higher" are intended to encompass different orientations of the device during use or operation other than the orientation depicted in the accompanying drawings. The first fin protrusion 100P may be formed by etching a portion of the substrate 100 or may be an epitaxial layer grown from the substrate 100.

[0031] The first fin protrusion 100P may include silicon or germanium. In addition, the first fin protrusion 100P may include a compound semiconductor, such as a Group IV-IV compound semiconductor or a Group III-V compound semiconductor.

[0032] Group IV-IV compound semiconductors may include binary or ternary compounds (each compound including at least two of carbon (C), silicon (Si), germanium (Ge), or tin (Sn)) or compounds doped with Group IV elements.

[0033] Group III-V compound semiconductors may include binary compounds, ternary compounds, or quaternary compounds, each of which is formed by combining a Group III element (e.g., at least one of aluminum (Al), gallium (Ga), or indium (In)) and a Group V element (e.g., at least one of phosphorus (P), arsenic (As), or antimony (Sb)).

[0034] A field insulating layer 105 may be formed on the substrate 100 . The field insulating layer 105 may surround at least a portion of a sidewall of the first fin protrusion 100P. The term “surrounding” as used herein does not necessarily mean completely or totally surrounding. The first fin protrusion 100P may be defined by the field insulating layer 105 .

[0035] Reference Figure 4, a sidewall of the first fin protrusion 100P may be partially or completely surrounded by the field insulation layer 105. However, the inventive concept is not limited thereto.

[0036] The field insulating layer 105 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

[0037] The first active pattern 110 may be formed on the substrate 100. The first active pattern 110 may be spaced apart from the substrate 100. The first active pattern 110 may extend in a first direction X1.

[0038] The first active pattern 110 may be formed on the first fin protrusion 100P and spaced apart from the first fin protrusion 100P. The first active pattern 110 may vertically overlap the first fin protrusion 100P. For example, the first active pattern 110 may overlap the first fin protrusion 100P in the third direction Z1. Therefore, the first active pattern 110 may not be formed on the field insulating layer 105, but may be formed on the first fin protrusion 100P.

[0039] The second active pattern 120 may be formed on the first active pattern 110. The second active pattern 120 may be spaced apart from the first active pattern 110. The second active pattern 120 may extend in the first direction X1. The second active pattern 120 may vertically overlap with the first active pattern 110. For example, the second active pattern 120 may overlap with the first active pattern 110 in the third direction Z1.

[0040] The first active pattern 110 and the second active pattern 120 may include silicon or germanium. In some embodiments, the first active pattern 110 and the second active pattern 120 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0041] The first active pattern 110 and the second active pattern 120 may include the same material as the first fin protrusion 100P or a different material.

[0042] Each of the first active pattern 110 and the second active pattern 120 may function as a channel region of a transistor.

[0043] Although the semiconductor device including two active patterns is shown in the drawings, the inventive concept is not limited thereto. For example, the semiconductor device may include one or three or more active patterns.

[0044] The first gate structure 150 includes a first gate insulating film 152 and a first gate electrode 154 .

[0045] The first gate electrode 154 may be formed on the substrate 100. The first gate electrode 154 may cross the first active pattern 110 and the second active pattern 120. For example, the first gate electrode 154 may lengthwise extend in the second direction Y1.

[0046] The first gate electrode 154 may surround the first active pattern 110 and the second active pattern 120. For example, the first active pattern 110 and the second active pattern 120 may penetrate or extend through the first gate electrode 154 in the first direction X1. The first gate electrode 154 may completely surround the perimeter of the first active pattern 110 and the perimeter of the second active pattern 120, or otherwise extend along the perimeter of the first active pattern 110 and the perimeter of the second active pattern 120. The first gate electrode 154 may be disposed between the first active pattern 110 and the substrate 100.

[0047] The first gate electrode 154 may include a conductive material. The first gate electrode 154 may be formed of a single layer or multiple layers. For example, the first gate electrode 154 may include a work function control conductive layer and a filling conductive layer filling a space formed by the work function control conductive layer.

[0048] The first gate electrode 154 may include, for example, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, or a combination thereof. In some embodiments, the first gate electrode 154 may include silicon or silicon germanium. The first gate electrode 154 may be formed by a gate replacement process, but the present invention is not limited thereto.

[0049] The first gate spacer 130 may be formed on opposite sidewalls of the first gate electrode 154 and extend in the second direction Y1. The first gate spacer 130 may define a first trench TR1 crossing the first active pattern 110 and the second active pattern 120.

[0050] The first gate spacer 130 may be formed on opposite ends of the first active pattern 110 and the second active pattern 120. For example, the first gate spacer 130 may contact opposite ends of the first active pattern 110 and the second active pattern 120. The term "contact" may indicate that there is no intermediate element (e.g., a layer or substrate) between the elements in contact. Conversely, when an element is referred to as being "on" or "adjacent" another element, the element may be in contact with the other element, or an intermediate element may be present. In some embodiments, the first active pattern 110 and / or the second active pattern 120 may penetrate or extend through the first gate spacer 130.

[0051] Each of the first gate spacers 130 includes a first outer spacer 132 and a first inner spacer 134 .

[0052] The first inner spacer 134 may be formed on the sidewall of the portion of the first gate electrode 154 surrounding the first active pattern 110 and the second active pattern 120. The first outer spacer 132 may be formed on the first inner spacer 134. The first outer spacer 132 may be disposed on the second active pattern 120. For example, referring to Figure 2 、 Figure 3a and Figure 3b , the first inner spacer 134 may be disposed between the first fin protrusion 100P and the first active pattern 110 . The first inner spacer 134 may also be disposed between the first active pattern 110 and the second active pattern 120 .

[0053] In some embodiments, according to a multi-layer stack structure for forming the first active pattern 110 and the second active pattern 120 , the first inner spacer 134 and the first outer spacer 132 may be disposed on the second active pattern 120 .

[0054] Reference Figure 2 , the width of the first outer spacer 132 may be equal to the width of the first inner spacer 134. Here, the width of the first outer spacer 132 and the width of the first inner spacer 134 refer to a first width W11 of the first outer spacer 132 and a second width W12 of the first inner spacer 134 in the first direction X1, respectively. In some embodiments, the first width W11 of the first outer spacer 132 may be smaller than or larger than the second width W12 of the first inner spacer 134.

[0055] The first gate spacer 130 may include a material similar to that of the first active pattern 110 and the second active pattern 120. For example, the first gate spacer 130 may include a semiconductor material layer. The semiconductor material layer may include a semiconductor material. The semiconductor material may not include an insulating material, such as an oxide or nitride. In other words, the first gate spacer 130 may not include oxides, nitrides, and / or other insulating materials.

[0056] In some embodiments, the first inner spacer 134 of each first gate spacer 130 may include a semiconductor material layer.

[0057] For example, when the first active pattern 110 and the second active pattern 120 include silicon, the first inner spacer 134 may include silicon (Si) or silicon germanium (SiGe). In this case, for example, the silicon concentration in the first inner spacer 134 may be greater than the silicon concentration in each of the first active pattern 110 and the second active pattern 120. In some embodiments, when the first active pattern 110 and the second active pattern 120 include germanium (Ge) or silicon germanium (SiGe), the first inner spacer 134 may include germanium (Ge) or silicon germanium (SiGe). In this case, for example, the germanium concentration in the first inner spacer 134 may be greater than the germanium concentration in each of the first active pattern 110 and the second active pattern 120.

[0058] The first outer spacer 132 may be the same material as or a different material from the first inner spacer 134 .

[0059] In some embodiments, the first outer spacer 132 may include an insulating material layer. For example, the first outer spacer 132 may include silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, or a combination thereof.

[0060] The first gate insulating layer 152 may be disposed between the first active pattern 110 and the first gate electrode 154 and between the second active pattern 120 and the first gate electrode 154. Thus, the first gate insulating layer 152 may be formed along surfaces of the first active pattern 110 and the second active pattern 120. The first gate insulating layer 152 may surround the first active pattern 110 and the second active pattern 120. In addition, the first gate insulating layer 152 may be formed on an upper surface of the field insulating layer 105 and on an upper surface of the first fin protrusion 100P.

[0061] The first gate insulating layer 152 may extend along inner sidewalls of the first gate spacer 130. For example, the first gate insulating layer 152 may extend along sidewalls and a lower surface of the first trench TR1.

[0062] The first gate insulating layer 152 may include a high-k dielectric material having a dielectric constant greater than that of silicon oxide, silicon nitride, or silicon oxynitride. For example, the first gate insulating layer 152 may include, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium zirconium oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate, or a combination thereof, but is not limited thereto.

[0063] Although not shown in the drawings, an interfacial layer may be formed between the first gate insulating layer 152 and the first active pattern 110, between the first gate insulating layer 152 and the second active pattern 120, and between the first gate insulating layer 152 and the first fin protrusion 100P. Depending on the method of forming the interfacial layer, the interfacial layer may be formed along the contour or periphery of the first gate insulating layer 152. However, the present invention is not limited thereto.

[0064] The first epitaxial pattern 140 may be formed on opposite sides of the first gate electrode 154. The first epitaxial pattern 140 may contact the first active pattern 110, the second active pattern 120, and the first gate spacer 130. For example, the first epitaxial pattern 140 may be formed on sidewalls of the first active pattern 110, sidewalls of the second active pattern 120, and outer sidewalls of the corresponding first gate spacer 130.

[0065] Each first epitaxial pattern 140 may include an epitaxial layer formed on the first fin protrusion 100P. The first epitaxial pattern 140 may be an elevated source / drain region whose upper surface protrudes above the upper surface of the substrate 100. However, the present invention is not limited thereto. For example, the source / drain region may be an impurity region formed in the substrate 100.

[0066] In some embodiments, each first epitaxial pattern 140 may include multiple layers. For example, each first epitaxial pattern 140 may include a first epitaxial layer 142 and a second epitaxial layer 144 sequentially formed on the substrate 100 .

[0067] The first epitaxial layer 142 may be formed on the first fin protrusion 100P, the first active pattern 110, the second active pattern 120, and the first inner spacer 134. The first epitaxial layer 142 may be formed by an epitaxial growth process from the first fin protrusion 100P, the first active pattern 110, the second active pattern 120, and the first inner spacer 134. The first epitaxial layer 142 may extend along the upper surface of the first fin protrusion 100P, the sidewalls of the first active pattern 110, the sidewalls of the second active pattern 120, and the outer sidewalls of the first inner spacer 134.

[0068] The first epitaxial layer 142 may serve as a seed for growing each of the first epitaxial patterns 140. However, in some embodiments, the first epitaxial layer 142 may be omitted.

[0069] The second epitaxial layer 144 may be formed on the first epitaxial layer 142. The second epitaxial layer 144 may be formed to fill the trench formed on the substrate 100.

[0070] The second epitaxial layer 144 may have a rhombus, pentagonal, or hexagonal cross section. However, the present inventive concept is not limited thereto. The second epitaxial layer 144 may have a cross section of various shapes.

[0071] In some embodiments, when the semiconductor device is a PMOS transistor, the first epitaxial pattern 140 may include p-type impurities or impurities for preventing the diffusion of p-type impurities. For example, the first epitaxial pattern 140 may include B, C, In, Ga, Al, or a combination thereof.

[0072] In some embodiments, when the semiconductor device is a PMOS transistor, the first epitaxial pattern 140 may include a compressive stress material, i.e., a material configured to induce compressive stress or strain. For example, when each of the first active pattern 110 and the second active pattern 120 is a silicon pattern, the first epitaxial pattern 140 may include a material having a lattice constant greater than that of silicon. For example, the first epitaxial pattern 140 may include silicon germanium (SiGe). The compressive stress material may apply compressive stress to the first active pattern 110 and the second active pattern 120, thereby increasing carrier mobility in the channel region of the transistor (e.g., the first active pattern 110 and the second active pattern 120).

[0073] In some embodiments, when the semiconductor device is an NMOS transistor, the first epitaxial pattern 140 may include n-type impurities or impurities for preventing diffusion of n-type impurities. For example, the first epitaxial pattern 140 may include P, Sb, As, or a combination thereof.

[0074] In some embodiments, when the semiconductor device is an NMOS transistor, the first epitaxial pattern 140 may include a tensile stress material, that is, a material configured to induce tensile stress or strain. For example, when each of the first active pattern 110 and the second active pattern 120 is a silicon pattern, the first epitaxial pattern 140 may include a material having a lattice constant less than that of silicon. For example, the first epitaxial pattern 140 may include silicon carbide (SiC). The tensile stress material may apply tensile stress to the first active pattern 110 and the second active pattern 120, so that the carrier mobility in the channel region of the transistor (e.g., the first active pattern 110 and the second active pattern 120) may be increased. In some embodiments, the first epitaxial pattern 140 may not include a tensile stress material.

[0075] In some embodiments, the first epitaxial layer 142 and the second epitaxial layer 144 may include different concentrations of the first semiconductor material. For example, when the semiconductor device is a PMOS transistor, the first epitaxial layer 142 may include the first semiconductor material at a first concentration that is a compressive stress material. When the first active pattern 110 and the second active pattern 120 include silicon (Si), the first semiconductor material may be, for example, germanium (Ge).

[0076] At this time, the second epitaxial layer 144 may include a second concentration of the first semiconductor material that is different from the first concentration. For example, the germanium concentration in the second epitaxial layer 144 may be greater than the germanium concentration in the first epitaxial layer 142. The first concentration may be 10% to 30%, and the second concentration may be 40% to 65%. As the concentration of the first semiconductor material increases, the compressive stress applied to the channel region of the transistor (e.g., the first active pattern 110 and the second active pattern 120) may increase. Therefore, the second epitaxial layer 144 including the first semiconductor material having a second concentration greater than the first concentration can be used to increase carrier mobility.

[0077] In some embodiments, the first concentration can be equal to the second concentration.

[0078] In some embodiments, a portion of each first epitaxial pattern 140 adjacent to the first active pattern 110, the second active pattern 120, and the first gate spacer 130 may include a high concentration of the first semiconductor material. For example, the germanium concentration of the first epitaxial layer 142 may be greater than 30%.

[0079] An interlayer insulating layer 160 may be formed on the substrate 100. The interlayer insulating layer 160 may surround outer sidewalls of the first gate spacer 130 defining the first trench TR1.

[0080] The interlayer insulating layer 160 may include, for example, silicon oxide, silicon nitride, silicon oxynitride and / or a low-k dielectric material. The term "and / or" includes any and all combinations of one or more items listed in association. For example, the low-k dielectric material may include, but is not limited to, flowable oxide (FOX), doline silazane (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorinated silicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), parylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer materials, or combinations thereof.

[0081] In some embodiments, the first gate spacers 130 may include impurities. For example, the first inner spacers 134 of each first gate spacer 130 may include p-type impurities or n-type impurities. That is, the first inner spacers 134 may be p-type or n-type.

[0082] The first gate spacer 130 may include the same type of impurities as or a different type of impurities as the first epitaxial pattern 140 (eg, the same conductivity type as or a different conductivity type as the first epitaxial pattern 140 ).

[0083] For example, the first epitaxial pattern 140 may include a first impurity, and the first gate spacer 130 may include a second impurity of the same conductivity type as the first impurity. Figure 3a As shown, each of the first epitaxial pattern 140 and the first inner spacer 134 may include p-type impurities.

[0084] In this case, the first inner spacer 134 can improve the performance of the semiconductor device. For example, when the first epitaxial pattern 140 includes a low concentration of the first impurity, the first inner spacer 134 can include a second impurity having a higher concentration than the first impurity, thereby improving the performance of the semiconductor device. In some embodiments, the concentration of the second impurity can be substantially equal to or lower than the concentration of the first impurity.

[0085] In some embodiments, the first epitaxial pattern 140 may include a first impurity, and the first gate spacer 130 may include a second impurity of a different type than the first impurity. Figure 3b As shown, the first epitaxial pattern 140 may include p-type impurities, and the first inner spacer 134 may include n-type impurities.

[0086] In this case, the first inner spacer 134 can effectively suppress the short channel effect (SCE). For example, when the first epitaxial pattern 140 includes a high concentration of the first impurity, the first impurity may diffuse into the channel region (e.g., the first active pattern 110 and the second active pattern 120), so that the SCE may be enhanced. However, the second impurity of a different conductivity type from the first impurity can diffuse into the first active pattern 110 and the second active pattern 120 adjacent thereto, thereby effectively suppressing the SCE.

[0087] In the semiconductor device according to example embodiments, defects in the source / drain region may be reduced or prevented. For example, stacking faults in the source / drain region may be reduced or prevented.

[0088] Source / drain regions can be formed from an active pattern and gate spacers through an epitaxial growth process. However, due to the difference in lattice constants between the active pattern and the gate spacer, stacking faults may be included in the source / drain regions. This can make it difficult to improve the performance of the semiconductor device. Consequently, the performance of the semiconductor device may be reduced or degraded.

[0089] However, in the semiconductor device according to example embodiments, the first gate spacer 130 including a semiconductor material layer similar to the first active pattern 110 and the second active pattern 120 may be used, so that stacking faults may be reduced or prevented from forming in the source / drain region (e.g., the first epitaxial pattern 140). In addition, the source / drain region (e.g., the first epitaxial pattern 140) may be prevented from being damaged or the possibility of damage may be reduced.

[0090] To manufacture a semiconductor device having a gate all around (GAA) structure, active layers having etching selectivities relative to each other may be used (see, for example, Figure 16 2002) and sacrificial layers (see e.g. Figure 16 2001). For example, a sacrificial layer comprising germanium (Ge) (see e.g. Figure 16 2001) with respect to an active layer comprising silicon (Si) (see e.g. Figure 16 2002) can have etching selectivity. When the semiconductor device is a PMOS transistor, the first epitaxial pattern 140 can also include germanium (Ge). Therefore, due to the presence of the sacrificial layer (see, for example, Figure 16 Due to the low etching selectivity during the removal process of the first epitaxial pattern 140 (2001), the first epitaxial pattern 140 may be damaged. Therefore, the performance and reliability of the semiconductor device may be reduced or degraded.

[0091] However, in the semiconductor device according to example embodiments, the first gate spacer 130 including a semiconductor material layer similar to the first active pattern 110 and the second active pattern 120 (the first active pattern 110 and the second active pattern 120 are channel regions) can be used to reduce or prevent damage to the source / drain region (e.g., the first epitaxial pattern 140). For example, the first gate spacer 130 can include a semiconductor material layer similar to the first active pattern 110 and the second active pattern 120, thereby protecting the first epitaxial pattern 140 from damage on the sacrificial layer (see, e.g., FIG. Figure 16 2001) is damaged during the removal process due to the etching selectivity of the first gate spacer 130.

[0092] Figure 5 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 5 In the Figures 1 to 4 The same components as shown in .

[0093] Reference Figure 5 In the semiconductor device according to example embodiments, the first inner spacer 134 may be formed of a plurality of parts. For example, the first inner spacer 134 includes a first sub-spacer 134 a and a second sub-spacer 134 b.

[0094] The first subspacer 134a may be formed along an outline of a surface of the first gate insulating layer 152. The second subspacer 134b may be formed on a sidewall of the first subspacer 134a.

[0095] In some embodiments, the first subspacer 134 a and the second subspacer 134 b may include different concentrations of semiconductor materials.

[0096] For example, when the first active pattern 110 and the second active pattern 120 include silicon (Si), the first subspacer 134a and the second subspacer 134b may include silicon (Si) or silicon germanium (SiGe). In this case, the silicon concentration in the first subspacer 134a may be higher than the silicon concentration in the second subspacer 134b. Therefore, in the sacrificial layer including germanium (Ge) (see, for example, Figure 16 During the removal process of 2001), the first epitaxial pattern 140 can be protected from damage due to the etching selectivity of the first sub-spacer 134a.

[0097] In some embodiments, when the first active pattern 110 and the second active pattern 120 include silicon germanium (SiGe) or germanium (Ge), the first subspacer 134a and the second subspacer 134b may include silicon germanium (SiGe) or germanium (Ge). In this case, the germanium concentration in the first subspacer 134a may be higher than the germanium concentration in the second subspacer 134b. Therefore, in the sacrificial layer including silicon (Si) (see, for example, Figure 16 During the removal process of 2001), the first epitaxial pattern 140 can be protected from damage due to the etching selectivity of the first sub-spacer 134a.

[0098] In some embodiments, the first subspacer 134 a may include an insulating material, and the second subspacer 134 b may include a semiconductor material layer similar to the first and second active patterns 110 and 120 .

[0099] For example, the first subspacer 134a may include a low-k dielectric material, silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, or a combination thereof. The low-k dielectric material of the first subspacer 134a may be a material having a dielectric constant less than that of silicon oxide. The first subspacer 134a may be used to reduce parasitic capacitance between the first gate electrode 154 and the first epitaxial pattern 140.

[0100] For example, when the first active pattern 110 and the second active pattern 120 include silicon (Si), the second subspacer 134b may include silicon (Si) or silicon germanium (SiGe). For example, when the first active pattern 110 and the second active pattern 120 include silicon germanium (SiGe) or germanium (Ge), the second subspacer 134b may include silicon germanium (SiGe) or germanium (Ge). The second subspacer 134b may be used to reduce or prevent the formation of stacking faults in the first epitaxial pattern 140.

[0101] Figure 6 is a cross-sectional view of a semiconductor device according to example embodiments. Figure 7 yes Figure 6 An enlarged view of part R2. Figure 6 and Figure 7 In the Figures 1 to 4 The same components as shown in .

[0102] Reference Figure 6 and Figure 7 In the semiconductor device according to example embodiments, at least one sidewall of the first inner spacer 134 may have a curved surface. For example, a first sidewall 134S1 of the first inner spacer 134 adjacent to the first gate electrode 154 may have a convex curved shape toward the first gate electrode 154 .

[0103] The first gate insulating layer 152 may extend along the contour of the first sidewall 134S1 of the first inner spacer 134. Therefore, the surface of the portion of the first gate insulating layer 152 adjacent to the first inner spacer 134 may be concavely curved toward the first inner spacer 134. Similarly, the sidewall of the first gate electrode 154 adjacent to the first inner spacer 134 may be concavely curved. In other words, the first sidewall 134S1 of the first inner spacer 134 may conformally extend along the sidewalls of the gate electrode structures 152 and 154.

[0104] The second sidewall 134S2 of the first inner spacer 134 adjacent to each first epitaxial pattern 140 may be flat or planar, but is not limited thereto. In some embodiments, the second sidewall 134S2 of the first inner spacer 134 may have a similar profile to the first sidewall 134S1. For example, the second sidewall 134S2 of the first inner spacer 134 may have a concave curved shape.

[0105] In some embodiments, the width of the first inner spacer 134 in the first direction X1 may vary. For example, the third width W21 of the portion of the first inner spacer 134 adjacent to the first active pattern 110 or the second active pattern 120 may be smaller than the fourth width W22 of the middle portion of the first inner spacer 134.

[0106] In some embodiments, a sidewall of the first inner spacer 134 adjacent to the first active pattern 110 or the second active pattern 120 may form an obtuse angle relative to the first active pattern 110 or the second active pattern 120. For example, a first sidewall 134S1 of the first inner spacer 134 may form an obtuse angle relative to a lower surface of the second active pattern 120.

[0107] The shape of the first inner spacer 134 can be determined by referring to Figures 24 to 26 A process for fabricating a semiconductor device is described.

[0108] Figure 8 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 8 In the Figures 1 to 4 、 Figure 6 and Figure 7 The same components as shown in .

[0109] Reference Figure 8 In the semiconductor device, the first inner spacer 134 may extend (eg, continuously) along the upper surface of the first fin protrusion 100P, the sidewall of the first active pattern 110 , and the sidewall of the second active pattern 120 .

[0110] For example, the first inner spacer 134 may extend along the outline of the first fin protrusion 100P, the outline of the first gate insulating layer 152, the outline of the first active pattern 110, and the outline of the second active pattern 120. Therefore, the first inner spacer 134 may be interposed between the first active pattern 110 and each of the first epitaxial patterns 140 and between the second active pattern 120 and each of the first epitaxial patterns 140.

[0111] In some embodiments, the first epitaxial layer 142 of each first epitaxial pattern 140 may extend along an outline of the first inner spacer 134. In other embodiments, the first epitaxial layer 142 may be omitted.

[0112] In some embodiments, the first inner spacer 134 may include impurities. For example, when the semiconductor device is a PMOS transistor, the first inner spacer 134 may include p-type impurities. In this case, the junction region of the PMOS transistor can be adjusted according to the concentration of the p-type impurities in the first inner spacer 134.

[0113] Figure 9 is a perspective view of a semiconductor device according to example embodiments. Figure 10 It is along Figure 9 The cross-sectional view taken along the lines CC' and D-D'. Figure 9 and Figure 10 In the Figures 1 to 4 The same components as shown in .

[0114] Reference Figure 9 and Figure 10 In a semiconductor device according to an example embodiment, a substrate 100 includes a first region I and a second region II. The first region I and the second region II may be separated from each other or may be connected to each other. Transistors of the same conductivity type or transistors of different conductivity types may be formed on the first region I and the second region II.

[0115] The first region I and the second region II may each be, for example, a logic region, a static random access memory (SRAM) region, or an input / output (IO) region. For example, the first region I and the second region II may be regions where semiconductor devices for performing the same function or different functions are provided.

[0116] In some embodiments, the semiconductor device on the first region I is Figures 1 to 4 The semiconductor devices described are the same, so detailed descriptions thereof are omitted.

[0117] The semiconductor device on the second region II includes a second fin protrusion 200P, a third active pattern 210 , a fourth active pattern 220 , a second gate structure 250 , a second gate spacer 230 , and a second epitaxial pattern 240 .

[0118] The second fin protrusion 200P may protrude from the upper surface of the substrate 100 and extend lengthwise in the fourth direction X2. The second fin protrusion 200P may be formed by etching a portion of the substrate 100 or may include an epitaxial layer grown from the substrate 100.

[0119] The third active pattern 210 may be formed on the substrate 100. The third active pattern 210 may be spaced apart from the substrate 100. The third active pattern 210 may extend in a fourth direction X2.

[0120] The fourth active pattern 220 may be formed on the third active pattern 210 and spaced apart from the third active pattern 210. The fourth active pattern 220 may extend in the fourth direction Y2.

[0121] The third active pattern 210 and the fourth active pattern 220 may include the same material as the first active pattern 110 and the second active pattern 120 or a different material.

[0122] The second gate structure 250 includes a second gate insulating layer 252 and a second gate electrode 254 .

[0123] The second gate electrode 254 may be formed on the substrate 100. The second gate electrode 254 may cross the third active pattern 210 and the fourth active pattern 220. The second gate electrode 254 may lengthwise extend in the fifth direction Y2.

[0124] The second gate electrode 254 may surround the third active pattern 210 and the fourth active pattern 220. The third active pattern 210 and the fourth active pattern 220 may penetrate or extend through the second gate electrode 254.

[0125] The second gate spacer 230 may be formed on the sidewall of the second gate electrode 254. The second gate spacer 230 may define a second trench TR2 crossing the third active pattern 210 and the fourth active pattern 220.

[0126] The second gate spacer 230 may be disposed on opposite ends of the third active pattern 210 and / or the fourth active pattern 220. In some embodiments, the third active pattern 210 and the fourth active pattern 220 may penetrate or extend through the second gate spacer 230. In some embodiments, the second gate spacer 230 may not include an inner spacer.

[0127] The second gate insulating layer 252 may be interposed between the third active pattern 210 and the second gate electrode 254 and between the fourth active pattern 220 and the second gate electrode 254. The second gate insulating layer 252 may surround the third active pattern 210 and the fourth active pattern 220. The second gate insulating layer 252 may be formed on an upper surface of the field insulating layer 105 and an upper surface of the second fin protrusion 200P.

[0128] The second gate insulating layer 252 may extend along inner sidewalls of the second gate spacer 230. For example, the second gate insulating layer 252 may extend along sidewalls and a lower surface of the second trench TR2.

[0129] The second epitaxial pattern 240 may be formed on opposite sides of the second gate electrode 254. The second epitaxial pattern 240 may contact the third active pattern 210, the fourth active pattern 220, and the second gate insulating layer 252. For example, the second epitaxial pattern 240 may be formed on sidewalls of the third active pattern 210, sidewalls of the fourth active pattern 220, and an outer surface of the second gate insulating layer 252.

[0130] In some embodiments, each second epitaxial pattern 240 may include multiple layers. For example, each second epitaxial pattern 240 may include a third epitaxial layer 242 and a fourth epitaxial layer 244 sequentially formed on the substrate 100 .

[0131] In some embodiments, the transistors on the first region I and the second region II may be PMOS transistors.For example, each of the first epitaxial pattern 140 and the second epitaxial pattern 240 may include p-type impurities.

[0132] In some embodiments, the first epitaxial pattern 140 and the second epitaxial pattern 240 may include semiconductor materials having different concentrations. For example, the first epitaxial pattern 140 and the second epitaxial pattern 240 may include silicon germanium (SiGe). In some embodiments, the germanium concentration in each first epitaxial pattern 140 may be higher than the germanium concentration in each second epitaxial pattern 240. In some embodiments, the germanium concentration in the first epitaxial layer 142 may be higher than the germanium concentration in the third epitaxial layer 242.

[0133] When the semiconductor device is a PMOS transistor, the sacrificial layer (see, for example, Figure 16The source / drain regions including high-concentration germanium may be damaged during the removal process of the first active pattern 110 (2001). In the semiconductor device according to example embodiments, the first epitaxial pattern 140 may be prevented from being damaged by using the first gate spacer 130 including a semiconductor material layer similar to the channel region (e.g., the first active pattern 110 and the second active pattern 120).

[0134] Figure 11 is a perspective view of a semiconductor device according to example embodiments. Figure 12 It is along Figure 11 The cross-sectional view taken along line EE' and line FF'. Figure 11 and Figure 12 In the Figures 1 to 4 、 Figure 9 and Figure 10 The same components as shown in .

[0135] Reference Figure 11 and Figure 12 In the semiconductor device according to example embodiments, each of the second gate spacers 230 may include a second outer spacer 232 and a second inner spacer 234 .

[0136] The second inner spacer 234 may be formed on sidewalls of the second gate electrode 254 surrounding the third active pattern 210 and the fourth active pattern 220. The second outer spacer 232 may be formed on the second inner spacer 234. The second outer spacer 232 may be formed on the fourth active pattern 220.

[0137] The second inner spacer 234 may be formed between the second fin protrusion 200P and the third active pattern 210 and between the third active pattern 210 and the fourth active pattern 220 .

[0138] In some embodiments, the transistors on the first region I and the second region II may be NMOS transistors.For example, each of the first epitaxial pattern 140 and the second epitaxial pattern 240 may include n-type impurities.

[0139] In some embodiments, the first inner spacer 134 may include a semiconductor material layer similar to the first active pattern 110 and the second active pattern 120. The second inner spacer 234 may include an insulating material layer.

[0140] For example, when the first active pattern 110 and the second active pattern 120 include silicon (Si), the first inner spacer 134 may include silicon (Si) or silicon germanium (SiGe). For example, when the first active pattern 110 and the second active pattern 120 include silicon germanium (SiGe) or germanium (Ge), the first inner spacer 134 may include silicon germanium (SiGe) or germanium (Ge).

[0141] The second inner spacer 234 may include, for example, a low-k dielectric material, silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, or a combination thereof. The low-k dielectric material may have a lower dielectric constant than that of silicon oxide.

[0142] In a semiconductor device according to example embodiments, for example, stacking faults in source / drain regions of a transistor, for example, on a first region I, can be reduced or prevented, and parasitic capacitance between a gate electrode and source / drain regions of a transistor, for example, on a second region II, can be reduced or prevented.

[0143] Figure 13 is a perspective view of a semiconductor device according to example embodiments. Figure 14 and Figure 15 It is along Figure 13 The cross-sectional view taken along the line G-G' and the line H-H'. Figures 13 to 15 In the Figures 1 to 4 and Figures 9 to 12 The same components as shown in .

[0144] Reference Figure 13 and Figure 14 In the semiconductor device according to example embodiments, the transistors on the first region I are PMOS transistors, and the transistors on the second region II are NMOS transistors. For example, the first epitaxial pattern 140 may include p-type impurities. The second epitaxial pattern 240 may include n-type impurities.

[0145] In some embodiments, the first inner spacer 134 may include a first semiconductor material layer similar to the first and second active patterns 110 and 120 , and the second inner spacer 234 may include a second semiconductor material layer similar to the third and fourth active patterns 210 and 220 .

[0146] For example, when the first active pattern 110 and the second active pattern 120 include silicon (Si), the first inner spacer 134 may include silicon (Si) or silicon germanium (SiGe). For example, when the first active pattern 110 and the second active pattern 120 include silicon germanium (SiGe) or germanium (Ge), the first inner spacer 134 may include silicon germanium (SiGe) or germanium (Ge).

[0147] For example, when the third active pattern 210 and the fourth active pattern 220 include silicon (Si), the second inner spacer 234 may include silicon (Si) or silicon germanium (SiGe). For example, when the third active pattern 210 and the fourth active pattern 220 include silicon germanium (SiGe) or germanium (Ge), the second inner spacer 234 may include silicon germanium (SiGe) or germanium (Ge).

[0148] Reference Figure 13 and Figure 15 In the semiconductor device according to example embodiments, the transistors on the first region I are PMOS transistors, and the transistors on the second region II are NMOS transistors. For example, the first epitaxial pattern 140 may include p-type impurities. The second epitaxial pattern 240 may include n-type impurities.

[0149] In some embodiments, the first inner spacer 134 may include a first semiconductor material layer similar to the first active pattern 110 and the second active pattern 120 , and the second inner spacer 234 may include an insulating material layer.

[0150] For example, when the first active pattern 110 and the second active pattern 120 include silicon (Si), the first inner spacer 134 may include silicon (Si) or silicon germanium (SiGe). For example, when the first active pattern 110 and the second active pattern 120 include silicon germanium (SiGe) or germanium (Ge), the first inner spacer 134 may include silicon germanium (SiGe) or germanium (Ge).

[0151] For example, the second inner spacer 234 may include a low-k dielectric material, silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, or a combination thereof. The low-k dielectric material may have a lower dielectric constant than that of silicon oxide.

[0152] Figures 16 to 29 are diagrams illustrating example stages or operations in a method of fabricating a semiconductor device according to example embodiments. Figure 17 、 Figure 19 、 Figure 21 and Figures 23 to 28 It is along Figure 16 A cross-sectional view taken along line AA'. Figure 18 、 Figure 20 、 Figure 22 and Figure 29 It is along Figure 16 A cross-sectional view taken along line BB'. Figures 16 to 29 In the Figures 1 to 15 The same components as shown in .

[0153] Reference Figures 16 to 18 A semiconductor stack 2000 including alternately stacked sacrificial layers 2001 and active layers 2002 is formed on a substrate 100. The active layers 2002 may include a material having an etching selectivity relative to the sacrificial layers 2001. The sacrificial layers 2001 and the active layers 2002 may be formed by an epitaxial growth process.

[0154] refer to Figure 16 and Figure 18, two sacrificial layers 2001 and two active layers 2002 are formed on the substrate 100. However, the number of sacrificial layers 2001 and the number of active layers 2002 are not limited thereto. In addition, the stacking order of the sacrificial layers 2001 and the active layers 2002 can be changed. For example, in the semiconductor stack 2000, one of the active layers 2002 can be arranged at the uppermost layer, as shown in the figure. In some embodiments, one of the sacrificial layers 2001 can be arranged at the uppermost layer in the semiconductor stack 2000.

[0155] A first mask pattern 2101 may be formed on the semiconductor stack 2000. The first mask pattern 2101 may lengthwise extend in a first direction X1.

[0156] refer to Figure 19 and Figure 20 The semiconductor stack 2000 and the substrate 100 are etched using the first mask pattern 2101 as an etching mask. Thus, a fin structure F1 may be formed on the substrate 100.

[0157] The sacrificial layer 2001 may be etched to form first and second sacrificial patterns 112 and 122 extending lengthwise in the first direction X1. The active layer 2002 may be etched to form first and second active patterns 110 and 120 extending lengthwise in the first direction X1.

[0158] The fin structure F1 includes a first fin protrusion 100P, a first sacrificial pattern 112 , a first active pattern 110 , a second sacrificial pattern 122 , and a second active pattern 120 , which are sequentially stacked.

[0159] Reference Figure 21 and Figure 22 The field insulating layer 105 is formed on the substrate 100 and covers at least a portion of the sidewall of the fin structure F1. During the formation of the field insulating layer 105, the first mask pattern 2101 may be removed.

[0160] A dummy gate electrode 150D is formed on the fin structure F1. The dummy gate electrode 150D may intersect the fin structure F1 and extend longitudinally in the second direction Y1. The second mask pattern 2102 may be used as an etching mask to form the dummy gate electrode 150D. Although not shown in the figure, a dummy gate insulating layer or a fin structure protection layer may be further formed between the dummy gate electrode 150D and the fin structure F1.

[0161] A preliminary gate spacer 130P is formed on the sidewall of the dummy gate electrode 150D.

[0162] refer to Figure 23 The fin structure F1 is etched using the dummy gate electrode 150D and the preliminary gate spacer 130P as an etching mask.

[0163] Thus, a portion of the first sacrificial pattern 112, a portion of the first active pattern 110, a portion of the second sacrificial pattern 122, and a portion of the second active pattern 120 may be removed. In some embodiments, an undercut region may be formed in the fin structure F1. For example, the undercut region may be formed under the dummy gate electrode 150D and the preliminary gate spacer 130P.

[0164] In some embodiments, when the fin structure F1 is etched, an upper surface of the first fin protrusion 100P may be exposed. In some embodiments, when the fin structure F1 is etched, a portion of the first fin protrusion 100P may be etched.

[0165] Reference Figure 24 , the sidewalls of the first sacrificial pattern 112 and the sidewalls of the second sacrificial pattern 122 are selectively recessed.

[0166] For example, when etching the fin structure F1, sidewalls of the first sacrificial pattern 112, the first active pattern 110, the second sacrificial pattern 122, and the second active pattern 120 may be exposed. At this time, the exposed sidewalls of the first sacrificial pattern 112 and the exposed sidewalls of the second sacrificial pattern 122 are selectively recessed.

[0167] Since the first and second active patterns 110 and 120 include a material having an etching selectivity with respect to the first and second sacrificial patterns 112 and 122 , the first and second sacrificial patterns 112 and 122 may be selectively etched.

[0168] Thus, a first groove RC1 is formed on the sidewalls of the first sacrificial pattern 112 between the first fin protrusion 100P and the first active pattern 110. Furthermore, a second groove RC2 is formed on the sidewalls of the second sacrificial pattern 122 between the first active pattern 110 and the second active pattern 120. As shown in the figure, the sidewalls of the first sacrificial pattern 112 and the sidewalls of the second sacrificial pattern 122 (on which the first groove RC1 and the second groove RC2 are formed) can be flat or planar, but are not limited thereto. For example, depending on the recessing process, the sidewalls of the first sacrificial pattern 112 and the sidewalls of the second sacrificial pattern 122 can have a concave or other curved shape.

[0169] Reference Figure 25 , an inner spacer layer 134L including a material similar to the first active pattern 110 and the second active pattern 120 is formed on the substrate 100. For example, the inner spacer layer 134L including a semiconductor material may be formed on the substrate 100.

[0170] For example, when the first active pattern 110 and the second active pattern 120 include silicon (Si), the inner spacer layer 134L may include silicon (Si) or silicon germanium (SiGe). In this case, the silicon concentration in the inner spacer layer 134L may be higher than the silicon concentration in each of the first active pattern 110 and the second active pattern 120. In some embodiments, the silicon concentration in the inner spacer layer 134L may be higher than the silicon concentration in each of the first sacrificial pattern 112 and the second sacrificial pattern 122.

[0171] For example, when the first active pattern 110 and the second active pattern 120 are silicon germanium (SiGe) or germanium (Ge), the inner spacer layer 134L may include silicon germanium (SiGe) or germanium (Ge). In this case, the germanium concentration in the inner spacer layer 134L may be higher than the germanium concentration in each of the first active pattern 110 and the second active pattern 120. In some embodiments, the germanium concentration in the inner spacer layer 134L may be higher than the germanium concentration in each of the first sacrificial pattern 112 and the second sacrificial pattern 122.

[0172] The inner spacer layer 134L may extend along the upper surface of the first fin protrusion 100P, the sidewalls of the first sacrificial pattern 112, the sidewalls of the first active pattern 110, the sidewalls of the second sacrificial pattern 122, and the sidewalls of the second active pattern 120. For example, the inner spacer layer 134L may extend along the contours of the first fin protrusion 100P, the first sacrificial pattern 112, the first active pattern 110, the second sacrificial pattern 122, and the second active pattern 120.

[0173] The inner spacer layer 134L can be formed, for example, by an epitaxial growth process, but is not limited thereto. For example, the inner spacer layer 134L can be formed by a deposition process. The inner spacer layer 134L can be formed from a single layer, but is not limited thereto. In some embodiments, the inner spacer layer 134L can be formed from multiple layers including semiconductor materials of varying concentrations. In some embodiments, the inner spacer layer 134L can include a multilayer structure in which at least one insulating material layer and at least one semiconductor material layer are sequentially stacked.

[0174] Reference Figure 26 Portions of the inner spacer layer 134L on the sidewalls of the first active pattern 110 and the second active pattern 120 are removed. Thus, first gate spacers 130 are formed, each of which includes a first outer spacer 132 and a first inner spacer 134.

[0175] The portion of the inner spacer layer 134L on the sidewalls of the first active pattern 110 and the second active pattern 120 can be removed by an etching process using the dummy gate electrode 150D and the preliminary gate spacer 130P as an etching mask. The etching process may include, for example, a gas phase reaction etching process, a plasma etching process, and / or a wet etching process. In addition, the portion of the inner spacer layer 134L on the upper surface of the first fin protrusion 100P can be removed by the etching process.

[0176] The opposing sidewalls of the first inner spacer 134 may be flat or planar, but are not limited thereto. For example, when the sidewalls of the first sacrificial pattern 112 including the first groove RC1 have a concave curved shape, the sidewalls of the first inner spacer 134 adjacent to the first sacrificial pattern 112 may have a convex curved shape. Additionally, when the sidewalls of the second sacrificial pattern 122 including the second groove RC2 have a concave curved shape, the sidewalls of the first inner spacer 134 adjacent to the second sacrificial pattern 122 may have a convex curved shape.

[0177] Reference Figure 27 , a first epitaxial pattern 140 is formed on opposite sides of the dummy gate electrode 150D.

[0178] For example, each first epitaxial pattern 140 may be formed by growing from the first fin protrusion 100P, the first active pattern 110, the second active pattern 120, and the first inner spacer 134 using an epitaxial growth process.

[0179] In some embodiments, each first epitaxial pattern 140 may include multiple layers. For example, each first epitaxial pattern 140 may include a first epitaxial layer 142 and a second epitaxial layer 144 .

[0180] An interlayer insulating layer 160 is formed on the substrate 100 to cover the first epitaxial pattern 140. The dummy gate electrode 150D may be exposed through the interlayer insulating layer 160.

[0181] For example, the interlayer insulating layer 160 may be formed to cover the first epitaxial pattern 140 and then may be planarized until the upper surface of the dummy gate electrode 150D is exposed.

[0182] The second mask pattern 2102 may be removed during the formation of the interlayer insulating layer 160 .

[0183] refer to Figure 28 and Figure 29The dummy gate electrode 150D, the first sacrificial pattern 112, and the second sacrificial pattern 122 are removed. Thus, a first trench TR1 extending longitudinally in the second direction Y1 may be formed. The first active pattern 110 and the second active pattern 120 may also be exposed.

[0184] The first active pattern 110 may be spaced apart from the first fin protrusion 100P. The second active pattern 120 may be spaced apart from the first active pattern 110 .

[0185] Refer again Figures 1 to 4 , a first gate insulating layer 152 and a first gate electrode 154 are formed in the first trench TR1.

[0186] The first gate electrode 154 may be formed of a single layer, but is not limited thereto. In some embodiments, the first gate electrode 154 may be formed of multiple layers. For example, the first gate electrode 154 may include a work function control conductive layer and a filling conductive layer located in a space formed by the work function control conductive layer.

[0187] While the inventive concept has been shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A semiconductor device comprising: substrate; a gate electrode on the substrate, the gate electrode extending in a first direction; a gate spacer on a sidewall of the gate electrode, the gate spacer comprising a semiconductor material layer; an active pattern penetrating the gate electrode and the gate spacer, the active pattern extending in a second direction intersecting the first direction; as well as an epitaxial pattern contacting the active pattern and the gate spacer, wherein the sidewall of the gate spacer adjacent to the gate electrode has a convex curved shape, wherein the epitaxial pattern includes a first impurity, and The semiconductor material layer of the gate spacer includes a second impurity of a different conductivity type from the first impurity.

2. The semiconductor device according to claim 1, wherein The semiconductor material layer of the gate spacer includes silicon.

3. The semiconductor device according to claim 1, wherein The epitaxial pattern contacts the active pattern at a sidewall of the active pattern, wherein the sidewall of the active pattern is free of the gate spacer.

4. The semiconductor device according to claim 1, wherein The semiconductor material layer of the gate spacer includes germanium. The semiconductor device according to claim 1 , wherein The epitaxial pattern contacts the semiconductor material layer of the gate spacer, and the semiconductor material layer of the gate spacer does not contain oxide or nitride. The semiconductor device according to claim 1 , wherein: The epitaxial pattern includes p-type impurities and silicon germanium.

7. The semiconductor device according to claim 6, wherein The epitaxial pattern includes a first epitaxial pattern and a second epitaxial pattern on the first epitaxial pattern, the first epitaxial pattern contacts the active pattern and the gate spacer, and a germanium concentration in the second epitaxial pattern is higher than a germanium concentration in the first epitaxial pattern.

8. A semiconductor device comprising: substrate; a first active pattern on the substrate; a gate electrode surrounding the first active pattern; an inner spacer on a sidewall of the gate electrode, wherein the inner spacer is located between the first active pattern and the substrate; and an epitaxial pattern contacting the first active pattern and the inner spacer, Wherein, the inner spacer comprises a semiconductor material layer, wherein the sidewall of the inner spacer adjacent to the gate electrode has a convex curved shape, wherein the epitaxial pattern includes a first impurity, and The semiconductor material layer of the inner spacer includes a second impurity of a different conductivity type from the first impurity.

9. The semiconductor device according to claim 8, further comprising: outer spacers on the sidewalls of the gate electrode, Wherein, the outer spacer is disposed on the first active pattern and the inner spacer.

10. The semiconductor device according to claim 9, wherein The outer spacer includes an insulating material, and the inner spacer does not contain oxide or nitride.

11. The semiconductor device according to claim 8, further comprising: a second active pattern on the first active pattern, The gate electrode further surrounds the second active pattern, the inner spacer is further disposed between the first active pattern and the second active pattern, and the first active pattern and the second active pattern extend through the inner spacer to contact the epitaxial pattern.

12. A semiconductor device comprising: a substrate comprising a first region and a second region; a first gate electrode on the first region, the first gate electrode extending in a first direction; a first gate spacer on a sidewall of the first gate electrode, the first gate spacer comprising a first semiconductor material layer; a first active pattern penetrating the first gate electrode and the first gate spacer, the first active pattern extending in a second direction crossing the first direction; a first epitaxial pattern on a sidewall of the first gate spacer; a second gate electrode on the second region, the second gate electrode extending in a third direction; a second active pattern penetrating the second gate electrode, the second active pattern extending in a fourth direction crossing the third direction; and a second epitaxial pattern on a sidewall of the second gate electrode, wherein the sidewall of the first gate spacer adjacent to the first gate electrode has a convex curved shape, wherein the first epitaxial pattern includes a first impurity, and The first semiconductor material layer of the first gate spacer includes a second impurity of a different conductivity type from the first impurity.

13. The semiconductor device according to claim 12, further comprising: a gate insulating layer between the second gate electrode and the second epitaxial pattern, the gate insulating layer being in contact with the second epitaxial pattern, The first epitaxial pattern and the second epitaxial pattern include p-type impurities.

14. The semiconductor device according to claim 12, further comprising: a second gate spacer between the second epitaxial pattern and the second gate electrode, the second gate spacer being in contact with the second epitaxial pattern, wherein the first epitaxial pattern and the second epitaxial pattern include n-type impurities, and The second gate spacer includes an insulating material.

15. The semiconductor device according to claim 12, further comprising: a second gate spacer between the second epitaxial pattern and the second gate electrode, the second gate spacer being in contact with the second epitaxial pattern, wherein the first epitaxial pattern includes p-type impurities, The second epitaxial pattern includes n-type impurities, and The second gate spacer includes an insulating material.

16. The semiconductor device according to claim 12, further comprising: a second gate spacer between the second epitaxial pattern and the second gate electrode, the second gate spacer being in contact with the second epitaxial pattern, wherein the first epitaxial pattern includes p-type impurities, The second epitaxial pattern includes n-type impurities, and The second gate spacer includes a second semiconductor material layer.

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