Method for growing low-surface-defect epitaxial wafer on heavily-doped silicon substrate and epitaxial wafer

Abstract

The invention discloses a method for growing a low-surface-defect epitaxial wafer on a heavily-doped silicon substrate and the epitaxial wafer, and belongs to the field of semiconductor material preparation. The method comprises the following steps: carrying out rapid heat treatment on a heavily doped silicon substrate of which the resistivity is not greater than 1.15 m omega.cm in an inert atmosphere at the treatment temperature of 1000-1500 DEG C and the heating / cooling rate of 10-120 DEG C / s, and keeping the high temperature for 30-120 seconds; then HCl gas phase polishing is carried out at the temperature of 650-1250 DEG C, and mixed gas of HCl and hydrogen is introduced to remove a surface silicon layer by 50-150 nm; and finally growing an epitaxial layer. And the substrate can be subjected to particle detection and screening, and only the substrate with the specific pattern defect is subjected to the treatment. According to the method, through the synergistic effect of RTP and HCl polishing, in-vivo defect repairing and surface finishing are achieved, the number of LPDs, larger than or equal to 55 nm, on the surface of the epitaxial wafer is stably reduced to 10 or below, and the quality of the epitaxial wafer is remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor material preparation, specifically to a method for growing low-surface-defect epitaxial wafers on heavily doped silicon substrates and the epitaxial wafers themselves. Background Technology

[0002] Power devices require epitaxial wafers with extremely low resistivity, and the demand for heavily doped wafers with resistivity of 1 mΩ·cm and below has been increasing in recent years. Heavily doped phosphorus silicon single crystals (resistivity < 1 mΩ·cm, carrier concentration ≥ 10⁻⁶) are a prime example. 20 cm -3 It is a key material for realizing low on-resistance, wide-band infrared plasmon resonance and high-power N-type substrate.

[0003] However, during the cooling process of heavily phosphorus-doped single crystals, due to the extremely high phosphorus doping concentration, supersaturated interstitial silicon atoms are released and aggregate, especially when the residence time is too long in a specific cooling temperature range (such as 570±70℃), which easily forms defect clusters. In subsequent high-temperature epitaxial growth, these defects induce a large number of stacking faults (SF) in the epitaxial layer. These epitaxial layer defects manifest as surface spot defects (LPD) in subsequent detection. These LPDs seriously affect the quality of the epitaxial wafer, ultimately leading to a significant decrease in device performance and yield.

[0004] To address this issue, existing technologies have proposed various solutions, such as controlling the thermal history of single crystal growth (e.g., WO2014175120) or performing argon annealing under specific conditions after forming an oxide film on the back side of the substrate (e.g., US9755022B2), to eliminate or reduce bulk defects caused by oxygen and dopant clusters (phosphorus oxygen clusters: PO clusters), thereby indirectly suppressing SF in the epitaxial layer. For example, US20230055929 A1 optimized single crystal growth parameters (pulling speed 0.5-1.0 mm / min, magnetic field 2000-4000 G, and forced cooling to shorten the dwell time in the 600-700℃ temperature range) and stepped heat treatment process (first stage: 700-850℃, 30-120 minutes, hydrogen partial pressure 50%-80%; second stage: 1100-1250℃, 30-120 minutes, hydrogen partial pressure 0.01%-20%; cooling stage: 700-450℃, time <10 minutes) to suppress the formation and growth of Si-P defects.

[0005] However, these methods all have limitations such as a narrow process window and strong dependence on the thermal history of the original single crystal ingot (e.g., residence time within a specific solidification rate range). In particular, when the single crystal ingot is held for too long in the SF nucleation temperature range of approximately 570±70℃, the suppression effect of the above methods will decrease sharply.

[0006] Therefore, there is an urgent need for a simple and effective method for treating heavily phosphorus-doped substrates to reduce substrate-induced stacking fault defects in the epitaxial layer and to prepare epitaxial wafers with low surface defect (LPD) density. Summary of the Invention

[0007] This invention aims to solve the technical challenges of stacking faults, defect aggregation, and resource waste during epitaxial growth on heavily phosphorus-doped silicon substrates. It provides a method for growing low-surface-defect epitaxial wafers on heavily phosphorus-doped silicon substrates. This method overcomes the problem of strong dependence on the thermal history of the substrate in existing processes, achieves synergistic control of substrate bulk defects (such as interstitial atomic clusters) and near-surface lattice defects, thereby reducing substrate-induced stacking fault defects in the epitaxial layer and obtaining epitaxial wafers with low surface defects (LPD).

[0008] To achieve the above-mentioned objectives, the present invention adopts the following technical solution. This invention provides a method for growing low-surface-defect epitaxial wafers on heavily doped silicon substrates, the method comprising the following steps: Step 1: The heavily doped silicon substrate is placed in an inert gas atmosphere for high-temperature rapid thermal annealing (RTP). The process parameters of the high-temperature rapid thermal annealing are controlled as follows: heat treatment temperature 1000-1500°C, heating rate 25-150°C / s, high-temperature dwell time 30-120 seconds, and cooling rate 10-120°C / s.

[0009] The heavily doped silicon substrate refers to a single-crystal silicon wafer with a mirror-like surface obtained from a Czochralski-grown heavily phosphorus-doped silicon single-crystal ingot through slicing, grinding, chemical etching, polishing, and cleaning. Further, the resistivity of the heavily doped silicon substrate is ≤1.15 mΩ·cm, and more preferably, it is 0.6 mΩ·cm to 0.9 mΩ·cm. Typically, when the resistivity of the silicon substrate is reduced to below 1.15 mΩ·cm through heavy phosphorus doping, the introduction of interstitial atoms leads to the formation of batch defects on the epitaxial surface, manifesting as photoluminescent defects (LPDs), which severely affect wafer quality. Especially when the resistivity is reduced to below 0.9 mΩ·cm due to phosphorus doping, a large number of stacking faults are generated during subsequent epitaxial growth, resulting in a rapid increase in LPDs and a severe decline in device quality. The solution provided by this invention effectively addresses the problem of a large number of LPDs forming on the epitaxial surface due to the introduction of interstitial atoms in heavily doped phosphorus-silicon substrates, for the specific reasons described below.

[0010] The first step of this invention achieves bulk vacancy control and bulk repair through high-temperature rapid thermal treatment. This is mainly reflected in: 1) Suppressing defect nucleation and aggregation: The extremely short heating and high-temperature dwell time prevents supersaturated interstitial atoms (such as silicon self-interstitial atoms and interstitial phosphorus atoms) in the substrate from aggregating to form stable defect nuclei, thereby suppressing the nucleation and growth of bulk defects such as dislocations, inhibiting bulk defects such as dislocations in the substrate from the source. 2) Promoting rapid annihilation of interstitial atoms: At high temperatures, the diffusion of interstitial atoms accelerates. The short-term high-temperature conditions of RTP cause interstitial atoms to rapidly diffuse and recombine to annihilation points such as the substrate surface and grain boundaries, rapidly reducing supersaturation and achieving the repair of bulk defects in the substrate. 3) Introducing supersaturated vacancies: During rapid cooling, vacancies are difficult to recombine with self-interstitial atoms, resulting in a large number of vacancies generated by high-temperature Frankel pairs (VI pairs) being retained, thus forming a vacancy supersaturation distribution within the substrate silicon wafer. These vacancies provide conditions for subsequent neutralization of residual interstitial atoms and defect repair. 4) Formation of a deep vacancy concentration gradient: After RTP treatment, the vacancy concentration shows a distribution that gradually increases from the surface to the bulk, with the vacancy concentration in the near-surface region being relatively low, and some interstitial atoms may still not be completely recombinated.

[0011] Step two involves performing HCl vapor phase polishing on the heavily doped silicon substrate after high-temperature rapid thermal annealing to remove interstitial atoms from the surface that have not been fully recombinated. Specifically, in an epitaxial furnace, a mixture of HCl and hydrogen is introduced, and the heavily doped silicon substrate after high-temperature rapid thermal annealing is polished with HCl at 650-1250℃. The HCl flow rate is 1-2 L / min, the vapor phase polishing time is 20-200 seconds, and 5nm-150nm of surface silicon layer is removed.

[0012] After HCl vapor-phase polishing, near-surface defects in the substrate are first removed. The vacancy concentration in the heavily doped silicon substrate, after rapid high-temperature thermal treatment, gradually increases from the surface to the bulk, with a relatively low vacancy concentration in the near-surface region, where some interstitial atoms may still be incompletely recombine. This step involves direct surface etching with vapor-phase HCl to remove any remaining interstitial atom-rich layers, micro-defects, dopant clusters, or lattice damage layers. Secondly, the HCl vapor-phase polishing and etching process exposes an atomically clean surface of the silicon substrate and a complete silicon lattice, providing an ideal interface for epitaxial growth.

[0013] Furthermore, the HCl vapor phase polishing in this step works synergistically with the preceding high-temperature rapid thermal treatment step: First, during HCl vapor phase polishing, surface silicon atoms are removed. To maintain equilibrium, this promotes the diffusion and consumption of internal interstitial atoms to the surface, while vacancies in the bulk cannot migrate outward due to the short processing time, further optimizing the defect distribution. Second, the sequential synergy between RTP and HCl polishing forms a hierarchical removal process of "bulk repair + surface refinement": RTP eliminates oversaturated interstitial atoms in the bulk and introduces beneficial vacancy oversaturation, repairing bulk defects; subsequent HCl polishing removes near-surface residual defects, preparing an ideal surface. The combination of these two processes fundamentally and significantly reduces the nucleation sources of epitaxial stacking faults. As a result, the solution of this invention, through the synergy of the two processes, can stably reduce the number of stacking faults (LPD) in large-size epitaxial wafers (≥55 nm) formed on heavily phosphorus-doped silicon substrates to below 10.

[0014] Step 3, Epitaxial Growth: Adjust the temperature inside the epitaxial furnace to the epitaxial growth process temperature, introduce the epitaxial growth gas source and doping source, grow the epitaxial layer, and obtain an epitaxial wafer with low defect density.

[0015] Furthermore, prior to HCl vapor phase polishing, the epitaxial furnace underwent epitaxial substrate treatment: HCl gas was used to etch the epitaxial furnace substrate at high temperature to remove residual deposits, and then a layer of undoped polycrystalline silicon was re-coated onto the substrate. The specific steps were as follows: HCl gas with a purity ≥99.99% was introduced at a flow rate of 1~2 L / min, the substrate temperature was set to 1150℃, and the HCl etching time was 5 min; immediately after the substrate etching was completed, a layer of undoped polycrystalline silicon was re-coated onto the substrate: the growth material was SiHCl3, the flow rate was set to 16 g / min, and the growth time was 10 min.

[0016] Furthermore, as a resource optimization method, in order to achieve accurate identification of substrate defects, the above scheme is only applied to substrates with a high probability of epitaxial stacking fault density, avoiding over-processing. This invention screens the heavily doped silicon substrates: by identifying substrates with fixed-position or special pattern defects through high-resolution detection, the above-mentioned synergistic process of RTP and HCl vapor phase polishing is only applied to high-risk heavily doped silicon substrates, avoiding over-processing of good products and improving process economy.

[0017] Specifically, the process involves using high-resolution particle detection technology (such as KLA-Tencor SP7) to scan heavily doped silicon substrates, with a sensitivity threshold set to detect particles or defects ≥15nm in size. The particle map (MAP) of the silicon wafers from the entire ingot from which the heavily doped silicon substrate originates is analyzed to identify defects with "fixed positions or special patterns." Identifying defects with fixed positions refers to the presence of particle defects with the same regular distribution at the same location on 10 or more consecutive adjacent silicon wafers of the ingot. Identifying defects with special patterns refers to defect distributions that differ from the dispersion characteristics of conventional surface particles, exhibiting linear or clustered distributions. This screening step, based on the spatial distribution characteristics of defects, targets and locks high-risk areas, providing personalized input for subsequent RTP and HCl polishing, overcoming the limitations of the "one-size-fits-all" approach of existing technologies and saving resources.

[0018] The present invention also provides an ultra-low resistivity silicon epitaxial wafer prepared by the above method, the epitaxial wafer comprising: a heavily phosphorus-doped silicon substrate with resistivity ≤1.15 mΩ·cm; and a silicon epitaxial layer formed on the silicon substrate; wherein the silicon epitaxial layer has fewer than 10 light scattering defects (LPDs) of size ≥55nm within a 12-inch (300mm diameter) wafer range, preferably fewer than 5.

[0019] Furthermore, the number of LPDs with a silicon epitaxial layer size ≥ 55nm is no more than 3.

[0020] Furthermore, the heavily doped silicon substrate is a heavily phosphorus-doped silicon substrate with a resistivity of 0.6~0.9 mΩ·cm.

[0021] The beneficial technical effects of the present invention are as follows: This invention achieves control of stacking faults after epitaxy of heavily doped silicon substrates by using RTP and HCl vapor phase polishing before epitaxy, and solves the problem of synergistic control of bulk defects and near-surface defects in heavily phosphorus-doped silicon substrates.

[0022] This invention enhances the versatility of the method, making it applicable to substrates with varying thermal histories. It is particularly suitable for 300mm thick heavily phosphorus-doped substrates with extremely low resistivity (≤0.9 mΩ·cm) cut from ingot regions with unfavorable thermal histories (long dwell time in the SF nucleation temperature region). It can stably control the number of surface defects (LPD) with a post-epitaxy size ≥55nm to an extremely low level (<10 defects / wafer), significantly outperforming existing technologies and providing high-quality materials for high-performance power devices.

[0023] Furthermore, this invention links pre-epitaxy treatment with the defect characteristics of the original crystal. By screening in advance and analyzing the defect distribution characteristics of the silicon wafer, the invention achieves precise targeted application of the process, avoiding over-processing of good products and under-processing of risky products, thus improving process efficiency and versatility. Attached Figure Description

[0024] Figure 1 This is a graph showing the particle detection results of the heavily phosphorus-doped silicon substrate in Example 1 before high-temperature rapid heat treatment.

[0025] Figure 2 This is a magnified view of the central region of the particle detection image of the heavily phosphorus-doped silicon substrate in Example 1 before high-temperature rapid heat treatment.

[0026] Figure 3 This is an LPD particle distribution diagram of the epitaxial wafer with a size ≥55nm obtained from the substrate pretreated by RTP and HCl vapor phase polishing in Example 1.

[0027] Figure 4 The LPD particle distribution diagram for the epitaxial wafer with a size ≥ 55 nm prepared on the heavily phosphorus-doped silicon substrate in Comparative Example 1 is shown.

[0028] Figure 5 The image shows a typical stacking fault defect under an optical microscope on an epitaxial wafer fabricated on a heavily phosphorus-doped silicon substrate in Comparative Example 1.

[0029] Figure 6 The image shows the LPD particle distribution of the epitaxial wafer with a size ≥ 55 nm obtained from the substrate that only underwent RTP pretreatment in Comparative Example 2.

[0030] Figure 7 The image shows the LPD particle distribution of the epitaxial wafer with a size ≥ 55 nm obtained from the substrate that underwent only HCl vapor phase polishing pretreatment in Comparative Example 3. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to the embodiments, but the scope of protection of the present invention is not limited thereto.

[0032] Example 1

[0033] Substrate Inspection: A 12-inch heavily phosphorus-doped silicon substrate with a resistivity of approximately 0.9 mΩ·cm was used. This substrate was obtained from a Czochralski-grown heavily phosphorus-doped silicon single crystal ingot, and was a single crystal silicon wafer with a mirror-like surface obtained through slicing, grinding, chemical etching, polishing, and cleaning. A KLA-Tencor SP7 inspection system was used to scan and record the distribution of particles ≥15nm in the substrate. Simultaneously, particle scanning was performed on other adjacent silicon wafers in the same ingot. Analysis showed that the silicon wafers in this ingot exhibited characteristic distribution defects: particle aggregation at fixed locations in the central region, while particles in other regions were scattered without fixed positions or special pattern characteristics, such as... Figure 1 The substrate shown is the one used in this embodiment. Figure 1 (Left image) and its adjacent silicon wafer ( Figure 1 The right image shows the particle distribution. In both images, particles ≥19nm aggregate at the same location in the central region, forming a characteristic pattern, such as... Figure 2 The image shows a magnified particle distribution map of the center of the substrate, revealing a linear pattern of ≥19nm particle defects clustered in the central region. This linear pattern of particle clustering defects is also present in the same location on other silicon wafers of the same ingot, necessitating further processing.

[0034] RTP treatment: The substrate undergoes rapid high-temperature heat treatment (RTP) in an argon atmosphere. It is introduced into the furnace at 400°C, heated to 1250°C at a rate of 25-50°C / s, held at this temperature for 60 seconds, and then cooled to 500°C at a rate of 50-80°C / s, followed by natural cooling. During RTP, vacancy supersaturation is introduced into the substrate, repairing defects, and the vacancies form a gradient distribution along the substrate thickness direction, resulting in insufficient vacancies on the substrate surface.

[0035] HCl vapor phase polishing and epitaxial growth: 1) Substrate Protection Treatment: HCl vapor phase polishing is performed in the epitaxial furnace. Before the substrate undergoes HCl vapor phase polishing, the substrate of the epitaxial furnace is treated to prepare the furnace for subsequent processes. The substrate treatment process is as follows: HCl gas is introduced at 1130℃ at a flow rate of 1.5 L / min to etch the substrate with HCl for 5 minutes. Subsequently, SiHCl3 is introduced at 1150℃ at a flow rate of 15 g / min for approximately 10 minutes to deposit an intrinsic polycrystalline silicon layer with a thickness of approximately 1.2 μm on the substrate.

[0036] 2) HCl vapor phase polishing: The substrate that has undergone rapid high-temperature heat treatment is placed on the epitaxial furnace base. At a temperature of 1150℃, H2 is used as a carrier, and HCl gas is simultaneously introduced into H2 at a flow rate of 1L / min for 60 seconds to remove about 100 nm of silicon layer on the substrate surface, thereby achieving fine finishing of the substrate surface.

[0037] 3) Epitaxial growth: Adjust the epitaxial growth temperature to 1135℃, introduce SiHCl3 and PH3, grow the epitaxial layer to the target thickness, and after the growth is completed, cool down to below 600℃ and take out the wafer to obtain the low-defect epitaxial wafer on the heavily phosphorus-doped silicon substrate of the present invention.

[0038] Example 2

[0039] This embodiment uses a 12-inch heavily phosphorus-doped silicon substrate with a resistivity of approximately 0.6 mΩ·cm, obtained from a Czochralski-grown heavily phosphorus-doped silicon single crystal ingot. The wafers were obtained by slicing, grinding, chemical etching, polishing, and cleaning to achieve a mirror-like surface. The silicon wafers from the source ingot were scanned and analyzed using a KLA-Tencor SP7 inspection system, revealing the presence of clustered, granular defects in a fixed location within the same region. Therefore, prior to epitaxial growth, the substrate underwent RTP treatment and HCl vapor phase polishing. The specific steps are as follows.

[0040] RTP treatment: The substrate is subjected to rapid high-temperature heat treatment (RTP) in an argon atmosphere. It is placed in the furnace at 400°C, heated to 1000°C at a rate of 50~80°C / s, held at that temperature for 120 seconds, and then cooled to 500°C at a rate of 50-80°C / s, followed by natural cooling.

[0041] HCl vapor phase polishing and epitaxial growth: 1) Substrate Protection Treatment: HCl vapor phase polishing is performed in the epitaxial furnace. Before the substrate undergoes HCl vapor phase polishing, the substrate of the epitaxial furnace is treated to prepare the furnace for subsequent processes. The substrate treatment process is as follows: HCl gas is introduced at 1130℃ at a flow rate of 1.5 L / min to etch the substrate with HCl for 5 minutes. Subsequently, SiHCl3 is introduced at 1150℃ at a flow rate of 15 g / min for approximately 10 minutes to deposit an intrinsic polycrystalline silicon layer with a thickness of approximately 1.2 μm on the substrate.

[0042] 2) HCl vapor phase polishing: The substrate that has undergone rapid high-temperature heat treatment is placed on the epitaxial furnace base. At a temperature of 1250°C, H2 is used as a carrier, and HCl gas is simultaneously introduced into H2 at a flow rate of 2L / min for 200 seconds to remove about 150 nm of silicon layer on the substrate surface, thereby achieving fine finishing of the substrate surface.

[0043] 3) Epitaxial growth: Adjust the epitaxial growth temperature to 1135℃, introduce SiHCl3 and PH3, grow the epitaxial layer to the target thickness, and after the growth is completed, cool down to below 600℃ and take out the wafer to obtain the low-defect epitaxial wafer on the heavily phosphorus-doped silicon substrate of the present invention.

[0044] Example 3

[0045] This embodiment uses a 12-inch heavily phosphorus-doped silicon substrate with a resistivity of approximately 1.15 mΩ·cm, obtained from a Czochralski-grown heavily phosphorus-doped silicon single crystal ingot. The wafer, with a mirror-like surface, was obtained through slicing, grinding, chemical etching, polishing, and cleaning. The silicon wafer from the source ingot exhibits particle aggregation defects in fixed locations within the same region; therefore, RTP treatment and HCl vapor phase polishing were performed before epitaxial growth on this substrate. The specific steps are as follows.

[0046] RTP treatment: The substrate is subjected to rapid high-temperature heat treatment (RTP) in an argon atmosphere. It is placed in the furnace at 400°C, heated to 1500°C at a rate of 100~150°C / s, held at this temperature for 30 seconds, and then cooled to 500°C at a rate of 10~40°C / s, followed by natural cooling.

[0047] HCl vapor phase polishing and epitaxial growth: 1) Substrate Protection Treatment: HCl vapor phase polishing is performed in the epitaxial furnace. Before the substrate undergoes HCl vapor phase polishing, the substrate of the epitaxial furnace is treated to prepare the furnace for subsequent processes. The substrate treatment process is as follows: HCl gas is introduced at 1130℃ at a flow rate of 1.5 L / min to etch the substrate with HCl for 5 minutes. Subsequently, SiHCl3 is introduced at 1150℃ at a flow rate of 15 g / min for approximately 10 minutes to deposit an intrinsic polycrystalline silicon layer with a thickness of approximately 1.2 μm on the substrate.

[0048] 2) HCl vapor phase polishing: The substrate that has undergone rapid high-temperature heat treatment is placed on the epitaxial furnace base. At a temperature of 650°C, H2 is used as a carrier, and HCl gas is simultaneously introduced into H2 at a flow rate of 1L / min for 20 seconds to remove about 5nm of silicon layer on the substrate surface, thereby achieving fine finishing of the substrate surface.

[0049] 3) Epitaxial growth: Adjust the epitaxial growth temperature to 1135℃, introduce SiHCl3 and PH3, grow the epitaxial layer to the target thickness, and after the growth is completed, cool down to below 600℃ and take out the wafer to obtain the low-defect epitaxial wafer on the heavily phosphorus-doped silicon substrate of the present invention.

[0050] Comparative Example 1 A silicon wafer with similar defect characteristics, cut from the same ingot source as in Example 1 and located adjacent to the substrate of Example 1, was used as the substrate. The RTP step and HCl vapor phase polishing step in Example 1 were omitted. The substrate was directly fed into the epitaxial furnace cavity, and epitaxial growth was performed directly after substrate treatment. The epitaxial growth conditions were the same as in Example 1.

[0051] Comparative Example 2 A silicon wafer with similar defect characteristics, cut from the same ingot source as in Example 1 and located adjacent to the substrate of Example 1, was used as the substrate. After RTP treatment only, the wafer was placed in the epitaxial furnace cavity. No HCl vapor phase polishing was performed after substrate treatment, and epitaxial layer growth was carried out directly. The RTP treatment and epitaxial growth conditions were the same as in Example 1.

[0052] Comparative Example 3 A silicon wafer with similar defect characteristics, cut from the same ingot source as in Example 1 and located adjacent to the substrate of Example 1, was used as the substrate. The substrate was not subjected to RTP treatment and was directly fed into the epitaxial furnace. After substrate treatment, HCl vapor phase polishing was performed, followed by epitaxial layer growth. The HCl vapor phase polishing and epitaxial growth conditions were the same as in Example 1.

[0053] Defect detection was performed on the epitaxial wafers prepared in each embodiment and comparative example using the KLA-Tencor SP7 inspection system. The results showed that the number of defects in the critical dimension (≥55nm) of the 300mm epitaxial wafers in each embodiment was controlled at an extremely low level (<10 defects / wafer). Figure 3 The image shown is a defect detection result diagram of the epitaxial wafer prepared in Example 1. It shows that the number of LPDs with a size ≥ 55nm is 3 per wafer, and the high-density defect region (central region of the substrate) in the original substrate defect pattern did not show corresponding defect clusters after epitaxy; and from Figure 3 The MAP (Magnetic Mapping) data shows sparse defects, proving that the heavily phosphorus-doped silicon substrate, after rapid RTP thermal annealing and HCl vapor-phase polishing, indeed achieved atomic-level surface cleanliness, providing an ideal growth interface for epitaxy. Different comparative examples show different results, such as... Figure 4 The image shows the defect detection results of the epitaxial wafer prepared in Comparative Example 1. There are 74 LPDs (Laser Defects) ≥55nm, and the defect distribution exhibits a certain degree of clustering, such as... Figure 5 This is a typical stacking fault defect image obtained from the epitaxial wafer defect detection in Comparative Example 1. For example... Figure 6 and Figure 7 The images show the LPD particle distribution diagrams of epitaxial wafers with a particle size of ≥55nm prepared in Comparative Examples 2 and 3, respectively. Figure 6 As can be seen in Comparative Example 2, the epitaxial wafer prepared from a substrate that has only undergone RTP pretreatment has 26 LPD particles with a size ≥ 55 nm. Figure 7 As can be seen in the diagram, the epitaxial wafer prepared from the substrate that underwent only HCl vapor phase polishing pretreatment in Comparative Example 3 has an LPD particle distribution diagram with a size ≥55nm, and the number of LPD particles with a size ≥55nm is 40. Clearly, the rapid thermal processing using RTP in this invention suppresses the nucleation of substrate bulk defects, while HCl vapor phase polishing removes defects such as insufficient near-surface vacancies and a small number of interstitial atom residues. The synergistic effect of both significantly reduces the nucleation sources of epitaxial layer faults.

[0054] The above embodiments are intended to illustrate the essential content of the present invention, but are not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of protection of the present invention.

Claims

1. A method for growing low-surface-defect epitaxial wafers on heavily doped silicon substrates, characterized in that, Includes the following steps: Step 1: The heavily doped silicon substrate is subjected to rapid thermal treatment in an inert atmosphere. The process parameters of the rapid thermal treatment are: thermal treatment temperature 1000-1500℃, heating rate 25-150℃ / s, high temperature holding time 30-120 seconds, and cooling rate 10-120℃ / s. Step 2: Perform HCl vapor phase polishing on the heavily doped silicon substrate that has undergone rapid thermal treatment. In the epitaxial furnace, a mixed gas of HCl and hydrogen is introduced at 650-1250℃, where the HCl flow rate is 1-2 L / min, the vapor phase polishing time is 20-200 seconds, and 5-150 nm of surface silicon layer is removed. Step 3: An epitaxial layer is grown on the substrate after HCl vapor phase polishing to obtain the low surface defect epitaxial wafer; The heavily doped silicon substrate is a single crystal silicon wafer with a mirror surface obtained by slicing, grinding, chemical etching, polishing and cleaning a Czochralski-grown heavily phosphorus-doped silicon single crystal ingot, and its resistivity is not greater than 1.15 mΩ·cm.

2. The method for growing a low-surface-defect epitaxial wafer on a heavily doped silicon substrate according to claim 1, characterized in that: The resistivity of the heavily doped silicon substrate is 0.6-0.9 mΩ·cm.

3. The method for growing a low-surface-defect epitaxial wafer on a heavily doped silicon substrate according to claim 1, characterized in that: The process parameters for HCl vapor phase polishing in step two are: temperature 1150-1250℃, HCl flow rate 1-2 L / min, time 60-200 seconds, and removal of 100-150 nm of surface silicon layer.

4. The method for growing a low-surface-defect epitaxial wafer on a heavily doped silicon substrate according to claim 1, characterized in that: Before step one, there is also a step of particle detection screening of the heavily doped silicon substrate, and steps one and two are only performed on the heavily doped silicon substrate with specific pattern defects; The particle detection screening employs high-resolution particle detection technology, with a sensitivity threshold set to detect particles or defects with a size ≥15 nm. It also identifies defects with fixed positions or special patterns in other silicon wafers from the source ingot of the heavily doped silicon substrate. Fixed position defects refer to particle defects with the same regular distribution in the same position on 10 or more consecutive adjacent silicon wafers. Special pattern defects refer to defects with linear or clustered distribution characteristics.

5. The method for growing a low-surface-defect epitaxial wafer on a heavily doped silicon substrate according to claim 1, characterized in that: The epitaxial layer growth described in step three is carried out at 1135°C, with SiHCl3 and PH3 introduced as growth gas source and doping source.

6. The method for growing a low-surface-defect epitaxial wafer on a heavily doped silicon substrate according to claim 1, characterized in that, Before step two, the process also includes treating the epitaxial furnace base: HCl gas is introduced at 1130-1150℃ at a flow rate of 1-2 L / min for 5 minutes, followed by SiHCl3 at 1150℃ at a flow rate of 15-16 g / min for 10 minutes to deposit an undoped polycrystalline silicon layer on the base.

7. A low-surface-defect epitaxial wafer, characterized in that: The epitaxial wafer is prepared by the method according to any one of claims 1-6, and the epitaxial wafer comprises: Heavy phosphorus-doped silicon substrate with resistivity ≤1.15 mΩ·cm; A silicon epitaxial layer formed on the substrate; The silicon epitaxial layer comprises fewer than 10 LPDs with a size ≥ 55 nm within a wafer diameter of 300 mm.

8. The low surface defect epitaxial wafer according to claim 7, characterized in that: The number of LPDs with a silicon epitaxial layer size ≥ 55nm is ≤ 3.

9. A low-surface-defect epitaxial wafer according to claim 8, characterized in that, The resistivity of the heavily phosphorus-doped silicon substrate is 0.6-0.9 mΩ·cm.

10. A semiconductor power device, characterized in that: The semiconductor power device comprises a low-surface-defect epitaxial wafer as described in any one of claims 7-9.

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