Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are disclosed. A support layer and a mold layer are partially etched from a substrate to form a mold pattern and a support pattern on the substrate, so that a contact hole is formed through the support pattern and the mold pattern, and an interconnection is exposed through the contact hole. A lower electrode layer is formed on a mask pattern to fill the contact hole, and a lower electrode in the contact hole is formed by partially removing the lower electrode layer and the mask pattern. The lower electrode contacts the interconnection and is supported by a support pattern having the same thickness as the support layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2017-0177712 filed on December 22, 2017, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2018-0073791 filed on June 27, 2018, entitled “Semiconductor device and method for manufacturing the same,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments relate to semiconductor devices and methods of manufacturing the same, and more particularly, to dynamic random access memory (DRAM) devices having capacitors and methods of manufacturing the same. Background Art

[0004] Recent DRAM devices tend to require high performance and operating speed as well as small size. Therefore, the lower electrode of the capacitor of the DRAM device can be formed as high as possible in order to increase the capacitance of the capacitor on a silicon substrate of limited size. Summary of the invention

[0005] According to an exemplary embodiment, a method for manufacturing a semiconductor device is provided, comprising: sequentially forming a mold layer, a support layer, and a mask pattern on an entire surface of a substrate, the substrate having a cell region defined by a core region, a lower conductive structure and at least one interconnection contacting the lower conductive structure being located on the cell region of the substrate below the mold layer; partially removing the support layer and the mold layer by an etching process using a mask pattern as an etching mask to form a mold pattern and a support pattern on the mold pattern, so that a contact hole is formed through the support pattern and the mold pattern, thereby exposing the at least one interconnection in the cell region; forming a lower electrode layer on the mask pattern to fill the contact hole, so that the lower electrode layer contacts the interconnection in the contact hole; forming a lower electrode of a capacitor in the contact hole by partially removing the lower electrode layer and removing the mask pattern, so that the lower electrode is supported by the support pattern, and the support pattern has substantially the same thickness as the support layer.

[0006] According to an exemplary embodiment, a method for manufacturing a semiconductor device is provided. A mold layer, a support layer, and a mask pattern that do not contain boron may be sequentially formed on the entire surface of a substrate, the substrate having a cell region defined by a core region, and at least one lower conductive structure and at least one interconnection in contact with the at least one lower conductive structure may be located on the cell region. The support layer and the mold layer may be partially removed from the substrate by an etching process using a mask pattern as an etching mask, thereby forming a mold pattern and a support pattern on the mold pattern, so that a contact hole may be formed through the support pattern and the mold pattern, and the interconnection may be exposed through the contact hole in the cell region. Then, the mask pattern may be removed from the support pattern by a free radical dry cleaning process without causing any substantial damage to the support pattern, and a lower electrode layer may be formed on the support pattern to a thickness that fills the contact hole. Without causing any substantial damage to the support pattern, a lower electrode of a capacitor in contact with the interconnection in the contact hole is formed by partially removing the lower electrode layer.

[0007] According to an exemplary embodiment, a semiconductor device is provided, including: a substrate, a memory cell structure located on the substrate, an interconnection connected to the memory cell structure, and a charge storage structure connected to the interconnection and selectively storing charges. In this case, the charge storage structure may include: a lower electrode connected to the interconnection and supported by at least one support, the lower electrode protruding from the support; a dielectric layer located on the upper surface and side surfaces of the lower electrode and the upper surface of the support; and an upper electrode located on the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figures 1A to 1J A cross-sectional view showing various stages in a method of forming a capacitor for a semiconductor device according to an embodiment;

[0010] FIG. 2A to FIG. 2C shows cross-sectional views of various stages in an improved method of forming a capacitor according to an embodiment;

[0011] FIG. 3A to FIG. 3D shows a cross-sectional view of various stages in another improved method of forming a capacitor according to an embodiment;

[0012] 4A to 4F shows a cross-sectional view of various stages in yet another improved method of forming a capacitor according to an embodiment;

[0013] FIG. 5A to FIG. 5CA cross-sectional view showing various stages in a method of forming a capacitor for a semiconductor device according to an embodiment;

[0014] FIG. 6A to FIG. 6D A cross-sectional view showing various stages in a method of forming a capacitor for a semiconductor device according to an embodiment;

[0015] 7A to 7C shows cross-sectional views of various stages in an improved method of forming a capacitor according to an embodiment;

[0016] FIG. 8A to FIG. 8B shows cross-sectional views of various stages in an improved method of forming a capacitor according to an embodiment;

[0017] 9A to 9D A cross-sectional view showing various stages in a method of forming a capacitor for a semiconductor device according to an embodiment;

[0018] Fig.10 Shows that there is FIG. 2A to FIG. 2C A plan view of a semiconductor device of the capacitor shown; and

[0019] Fig.11 Shown along Fig.10 Cross-sectional view along line AA. DETAILED DESCRIPTION

[0020] Reference will now be made to example embodiments illustrated in the drawings, wherein like reference numerals refer to like components throughout.

[0021] Figures 1A to 1J are cross-sectional views showing stages in a method of forming a capacitor for a semiconductor device according to a first example embodiment.

[0022] Reference Figure 1A , a substrate 10, such as a silicon wafer, may be provided in such a configuration, the substrate 10 may include a cell region C1 and a core region C2, and at least one lower conductive structure 11 and at least one interconnection 16 may be arranged on the cell region C1. A plurality of mold layers 22a and 26a and a plurality of support layers 24a and 28a may be alternately formed on the entire surface of the substrate 10. Therefore, a stacked insulating layer 20 may be formed on the substrate 10, that is, the stacked insulating layer 20 may include alternating mold layers and support layers.

[0023] For example, the substrate 10 may include a substrate body 12, on which a plurality of lower conductive structures 11 may be placed, for example, adjacent to each other in a horizontal direction, and a lower insulating layer 14, which covers the lower conductive structures 11 and the substrate body 12. The lower conductive structures 11 may be insulated from each other by the lower insulating layer 14. A plurality of interconnects 16 (e.g., a plurality of contact pads) may be arranged on the lower insulating layer 14 (e.g., passing through the lower insulating layer 14), and may respectively contact the lower conductive structures 11 through the lower insulating layer 14.

[0024] The substrate body 12 may include a bulk substrate, such as a silicon substrate, a gallium arsenic (Ga-As) substrate, a silicon germanium (Si-Ge) substrate, a ceramic substrate, a quartz substrate, and a glass substrate for a flat panel display device, and / or a multilayer substrate (e.g., a semiconductor on insulator (SOI) substrate). In the present example embodiment, the substrate body 12 may include a silicon wafer.

[0025] A series of semiconductor manufacturing processes may be performed on the substrate body 12 and the lower conductive structure 11. For example, a transistor may be formed on the substrate body 12. Then, a lower insulating layer 14 may be formed on the lower conductive structure 11, and an interconnection 16 may be connected to each lower conductive structure 11 through the lower insulating layer 14. Therefore, the lower conductive structure 11 may be connected to the upper conductive structure through the interconnection 16. For example, in the present exemplary embodiment, the lower conductive structure 11 may include a source and a drain of a transistor, and the interconnection 16 may include a source and a drain that may be connected to the upper conductive structure 11. Figure 1J The buried contacts of the capacitor 90 in FIG.

[0026] A plurality of unit memory structures may be arranged on the cell region C1 of the substrate 10, and a plurality of auxiliary structures (e.g., a driving circuit for driving the unit memory structure and a logic circuit for controlling the unit memory structure) may be arranged on the core region C2 of the substrate 10. A plurality of unit transistors may be arranged in a matrix shape on the cell region C1, and at least one core transistor for a driving circuit or a logic circuit may be arranged on the core region C2.

[0027] The insulating layer 20 may be formed on the entire surface of the substrate 10 having the cell region C1 and the core region C2. For example, a first mold layer 22a, a first support layer 24a, a second mold layer 26a, and a second support layer 28a may be sequentially formed on the substrate 10.

[0028] For example, the etch stopper 18 may be continuously formed, for example, on the lower insulating layer 14 and on the interconnection 16, and the first mold layer 22a, the first supporting layer 24a, the second mold layer 26a, and the second supporting layer 28a may be sequentially formed on the etch stopper 18 by a deposition process. The etch stopper 18 may have an etching selectivity relative to the first mold layer 22a and the second mold layer 26a. In the present example embodiment, the etch stopper 18 may include, for example, a silicon nitride layer, which may be formed by a chemical vapor deposition (CVD) process.

[0029] The first mold layer 22a may be formed, for example, directly on the etch stopper 18, and may include, for example, silicon oxide. Examples of silicon oxide used for the first mold layer 22a may include flowable oxide (FOX), tonn silazen (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), fluorinated silicate glass (FSG), plasma-enhanced oxide (PEOX), high-density plasma CVD (HDP-CVD) oxide, etc. These may be used alone or in combination.

[0030] Taking into account Figure 1B The height of the contact hole H to be formed in the subsequent process described in the above description may be such that the first supporting layer 24a may be formed on the first mold layer 22a to a suitable thickness, as may the etching process time of the contact hole H. For example, the first supporting layer 24a may be formed such that the thickness of the first supporting layer 24a has a predetermined ratio with respect to the thickness of the first mold layer 22a and the thickness of the second mold layer 26a.

[0031] The first supporting layer 24a may have an etch selectivity with respect to the first and second mold layers 22a and 26a. For example, when the first and second mold layers 22a and 26a include oxides, the first supporting layer 24a may include at least one of silicon oxynitride, silicon nitride, and silicon carbonitride.

[0032] The second mold layer 26a may be formed on the first support layer 24a and may include the same material as the first mold layer 22a. For example, the second mold layer 26a may include PE-TEOS or HDP-CVD oxide. In addition, some dopants may be doped into the second mold layer 26a, and the second mold layer 26a may have a different doping concentration than the first mold layer 22a. In this case, the second mold layer 26a may have a different etching rate from the first mold layer 22a.

[0033] The second supporting layer 28a may be formed on the second mold layer 26a, and may have a single-layer structure or a multi-layer structure. Specifically, when the second supporting layer 28a is formed as a multi-layer structure, the shape of the contact hole H may be changed according to the thickness combination of each component layer of the second supporting layer 28a, so that the thickness of each of the component layers of the second supporting layer 28a may be determined in consideration of the configuration of the contact hole H. In the present example embodiment, the second supporting layer 28a may include, for example, silicon nitride or silicon oxynitride.

[0034] In the present exemplary embodiment, the insulating layer 20 may be formed into a multilayer structure in which the first mold layer 22a and the second mold layer 26a may be alternately stacked with the first support layer 24a and the second support layer 28a. However, the insulating layer 20 may also include a single mold layer and a single support layer according to the characteristics and configuration of the capacitor 90. Specifically, when two or more support layers are provided with a capacitor of a semiconductor device, the exemplary embodiment may be mainly applicable to the uppermost support layer, which may be exposed in a subsequent process for forming a lower electrode.

[0035] Thereafter, a mask pattern M may be formed on the insulating layer 20. The mask pattern M may have an etching selectivity with respect to the first and second mold layers 22 and 26a and the first and second supporting layers 24a and 28a. Therefore, the mask pattern M may be used as an etching mask for a subsequent etching process for forming the contact hole H. Therefore, the mask pattern M may be patterned in such a manner that a portion of the second supporting layer 28a above the interconnection 16 may be exposed.

[0036] For example, the mask pattern M may include a photoresist pattern including a photoresist material or a hard mask pattern including polysilicon. In the present example embodiment, the mask pattern M may include polysilicon.

[0037] Reference Figure 1B , by using the mask pattern M as an etching mask, the first and second mold layers 22a and 26a and the first and second supporting layers 24a and 28a may be partially removed from the substrate 10 to form a contact hole H, and the interconnection 16 in the cell region C1 may be exposed by the contact hole H. Therefore, the first and second mold layers 22a and 26a may be formed into the first and second mold patterns 22 and 26, respectively, and the first and second supporting layers 24a and 28a may be formed into the first and second supporting patterns 24b and 28b, respectively.

[0038] For example, a dry etching process may be performed on the insulating layer 20 using the mask pattern M as an etching mask. The etching gas used for the dry etching process may be changed in consideration of the composition of the insulating layer 20. For example, when removing the first support layer 24a and the second support layer 28a from the substrate 10, a nitrogen removal gas may be selected as an etching gas to perform the dry etching process. Conversely, when removing the first mold layer 22a and the second mold layer 26a from the substrate 10, an oxygen removal gas may be selected as an etching gas to perform the dry etching process. Similar to the etching process for the first support layer 24a and the second support layer 28a, the etch stopper 18 may also be removed from the substrate 10 by a dry etching process using a nitrogen removal gas as an etching gas. For example, the second support layer 28a, the second mold layer 26a, the first support layer 24a, the first mold layer 22a, and the etch stopper 18 may be sequentially dry-etched in the order described by alternately using the etching gas using the mask pattern M until the interconnect 16 is exposed by the resulting hole H.

[0039] Thus, a contact hole H may be formed in the insulating layer 20, and the interconnection 16 may be exposed through the contact hole H. During the dry etching process, the mask pattern M may also be slightly removed from the substrate 10, and the mask pattern M may be formed into a first mask pattern M1 and a second mask pattern M2, the first mask pattern M1 may be formed on the second support pattern 28b in the cell region C1, and the second mask pattern M2 may be formed on the second support pattern 28b in the core region C2. Each of the first mask pattern M1 and the second mask pattern M2 may have a thickness slightly smaller than that of the mask pattern M.

[0040] In detail, the plurality of interconnects 16 in the cell region C1 may be densely arranged in a matrix shape at a relatively high density, and the plurality of interconnects 16 may be individually connected to the plurality of transistors. In contrast, at least one core interconnect in the core region C2 may be sparsely arranged at a relatively low density, and the at least one core interconnect may be connected to the core transistor. Therefore, for example, since the number of interconnects in the cell region C1 is very large, the mask pattern M may be more strongly etched away in the cell region C1 compared to the core region C2, so that the first mask pattern M1 may be formed to a relatively small thickness, and the second mask pattern M2 may be formed to a relatively large thickness, that is, the first mask pattern M1 may have a smaller thickness in the vertical direction than the second mask pattern M2.

[0041] Reference Figure 1C , a lower electrode layer 30a filling the contact hole H may be formed on the substrate 10. That is, the lower electrode layer 30a may be formed to a sufficient thickness so that the contact hole H may be sufficiently filled with the lower electrode layer 30a. The first mask pattern M1 and the second mask pattern M2 (eg, upper surfaces thereof) may be covered by the lower electrode layer 30a.

[0042] For example, a conductive material may be deposited on the substrate 10 by a chemical vapor deposition (CVD) process to a sufficient thickness to fill the contact hole H, thereby forming the lower electrode layer 30 a in contact with the interconnection 16 in the contact hole H. Examples of the conductive material for the lower electrode layer 30 a may include conductive metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN)), metals (e.g., ruthenium (Ru), iridium (Ir), titanium (Ti), and tantalum (Ta)), conductive metal oxides (e.g., iridium oxide), etc. These may be used alone or in combination.

[0043] Due to the downsizing trend and the smaller gap distance between adjacent interconnects 16, the aspect ratio of the contact hole H may become larger. Therefore, during deposition 30a, various deposition defects such as voids and seam defects may occur in the lower electrode layer 30a. In this case, the lower electrode layer 30a may be partially removed from the substrate 10 until the voids and seam defects are exposed, and then a conductive material may be deposited again to fill the voids and seam defects in the contact hole H, which will be described in detail below.

[0044] Reference Figure 1D , the lower electrode layer 30a may be partially removed from the substrate 10 by a node-separation etching process using the first mask pattern M1 and the second mask pattern M2 as etching masks, thereby forming the electrode pattern 30b in the contact hole H and the residual mask RM on the second support pattern 28b in the cell region C1 and the core region C2. For example, the lower electrode layer 30a and the first mask pattern M1 and the second mask pattern M2 may be simultaneously removed from the substrate 10 by a dry etch-back process. That is, the dry etch-back process may be used as a node separation process for separating the lower electrode layer 30a through the contact hole H.

[0045] Therefore, the upper portion of the lower electrode layer 30a can be removed from the substrate 10, and the lower electrode layer 30a can be separated through the contact hole H, so that the lower electrode layer 30a can be formed as an electrode pattern 30b filling the contact hole H. In other words, a portion of the lower electrode layer 30a on the upper surface of the first mask pattern M1 and the upper surface of the second mask pattern M2 can be removed by a dry etch-back process, so that only the remaining portion of the electrode layer 30a remains in the contact hole H, for example, so that the resulting electrode patterns 30b in the corresponding contact holes H can be separated from each other via the contact hole H. In addition, the first mask pattern M1 and the second mask pattern M2 can be formed as a residual mask RM on the second support pattern 28b. Specifically, the first mask pattern M1 in the cell region C1 can be formed as a first residual mask M3, and the second mask pattern M2 in the core region C2 can be formed as a second residual mask M4.

[0046] In the dry etch-back process, the lower electrode layer 30a may have an etch rate greater than that of the first and second mask patterns M1 and M2. Therefore, the upper surface of the electrode pattern 30b may be etched lower than the upper surface of the first residual mask M3 in the cell region C1.

[0047] Therefore, the second support pattern 28b can be protected from the dry etch-back process by the residual mask RM, and no substantial damage may be caused to the second support pattern 28b during the dry etch-back process. Therefore, the second support pattern 28b may not be reduced during the dry etch-back process, and the thickness of the second support pattern 28b may remain substantially unchanged during the dry etch-back process.

[0048] Specifically, since the second residual mask M4 is formed to be thicker than the first residual mask M3, some of the lower electrode layer 30a may remain on the sidewall of the second residual mask M4 at the boundary region between the cell region C1 and the core region C2 during the dry etch-back process, thereby forming a residual electrode layer 32 on the sidewall of the second residual mask M4. The residual electrode layer 32 may extend from the outermost electrode pattern 30b at the boundary region.

[0049] If the residual mask RM is removed from the substrate 10 without removing the residual electrode layer 32, the residual electrode layer 32 will protrude upward from the electrode pattern 30b, and in a subsequent photolithography process for forming a dielectric layer on the electrode pattern 30b, a focus error may be generated due to the protruding residual electrode layer 32. Therefore, an additional etching process may be required to remove the residual electrode layer 32. That is, in the additional etching process for removing the residual electrode layer 32, the electrode pattern 30b may be further etched.

[0050] The dry etch-back process may be controlled in such a way that the upper surface of the electrode pattern 30b may be higher than the upper surface of the second support pattern 28b, for example, so that after the dry etch-back process is completed, the electrode pattern 30b may extend to cover the entire sidewall of the second support pattern 28b and the lower portion of the residual mask RM. That is, the surface level of the electrode pattern 30b may be higher than the surface level of the lower electrode 30, and the lower electrode 30 may be formed by the electrode pattern 30b in a subsequent process because the electrode pattern 30b may be etched away in an additional etching process for removing the residual electrode layer 32.

[0051] Reference Figure 1E , before removing the residual mask RM, the residual electrode layer 32 may be removed from the second residual mask M4.

[0052] For example, a wet etching process may be performed on the electrode pattern 30b and the residual electrode layer 32 so that the residual electrode layer 32 may be removed from the second residual mask M4. Specifically, since the residual mask RM may include polysilicon, a low peroxide sulfuric acid-hydrogen peroxide mixture (LPSPM) may be used as an etchant for the wet etching process.

[0053] In the wet etching using LPSPM as an etchant, the conductive material of the residual electrode layer 32 and the electrode pattern 30b can be removed more than the polysilicon of the residual mask RM. Therefore, in the wet etching process, the residual electrode layer 32 can be sufficiently removed from the sidewall of the second residual mask M4, and the thickness or height of the electrode pattern 30b can be reduced.

[0054] Specifically, the wet etching process may be controlled in such a manner that the upper surface of the electrode pattern 30b may be equal to or higher than the upper surface of the second support pattern 28b, for example, the second support pattern 28b may not be exposed to the etchant during the wet etching. When the upper surface of the electrode pattern 30b has the same level as the upper surface of the second support pattern 28b, as Figure 1E As shown, the lower electrode 30 can be coplanar with the upper surface of the second support pattern 28b, and the second support pattern 28b can be formed as the uppermost support member, so that the surface profiles of the lower electrode 30 and the uppermost support member 28 can be flat or smooth. Figure 2B In detail, if the upper surface of the electrode pattern 30b is higher than the upper surface of the second supporting pattern 28b, the lower electrode 30 may protrude from the upper surface of the second supporting pattern 28b, so that the surface profiles of the lower electrode 30 and the uppermost support 28 may be uneven. Therefore, the contact hole H may be filled with the electrode pattern 30b, and the second supporting pattern 28b may be covered with the residual mask RM without the presence of the residual electrode layer 32.

[0055] Reference Figure 1F , the residual mask RM may be removed from the substrate 10 , thereby exposing the second support pattern 28 b and forming the electrode pattern 30 b as the lower electrode 30 in the contact hole H. Referring to FIG.

[0056] For example, under the condition that the planarization process may not damage the second support pattern 28b, the residual mask RM may be removed from the substrate 10 by the planarization process. For example, a radical dry cleaning (RDC) process may be performed on the residual mask RM using a removal radical, so that the polysilicon of the residual mask RM may be selectively removed relative to the silicon nitride of the second support pattern 28b. That is, the radical may be selected so that the polysilicon of the residual mask RM may be removed without damaging the silicon nitride of the second support pattern 28b.

[0057] For example, the substrate 10 with the residual mask RM may be loaded into the RDC chamber, and the removal source gas may be converted into a source plasma including removal radicals in the RDC chamber. Then, the removal radicals may be selectively guided to the substrate 10, and the residual mask RM may be selectively removed from the substrate 10 without causing any damage to the second support pattern 28b. The removal radicals may be appropriately selected in consideration of the components of the second support pattern 28b and the residual mask RM.

[0058] Therefore, the second supporting pattern 28b may be exposed to the surrounding environment along the entire surface of the substrate 10, and the electrode pattern 30b may be formed as a lower electrode 30, and the upper surface of the lower electrode 30 may be coplanar with the upper surface of the second supporting pattern 28b. The lower electrode 30 may be arranged through the second supporting pattern 28b and may contact the interconnection 16 in the contact hole H in the cell region C1.

[0059] Specifically, the second support pattern 28b may not be damaged in the dry etch-back process, the wet etch process using LPSPM as an etchant, and the RDC process for forming the lower electrode layer 30a into the lower electrode 30, so that the height of the second support pattern 28b may remain unchanged when the lower electrode 30 is formed. Therefore, the second support pattern 28b may have the same thickness as the second support layer 28a. In the present example embodiment, since the second support pattern 28b may be formed as the uppermost support for supporting the lower electrode 30 in subsequent processes, the height of the lower electrode 30 may be determined by the thickness of the second support pattern 28b. Therefore, regardless of the sequential processing of the dry etch-back process, the wet etch process using LPSPM as an etchant, and the RDC process, the lower electrode 30 may still be formed to be sufficiently high.

[0060] 1G, the second support pattern 28b may be partially removed from the substrate 10 to form a plurality of upper openings through which the second mold pattern 26 may be exposed. Then, the second mold pattern 26 may be removed from the substrate 10 through the upper openings by an etching process.

[0061] For example, a first etching mask may be formed on the second support pattern 28b, and a dry etching process may be performed on the second support pattern 28b by using the first etching mask. Thus, the second support pattern 28b may be formed as a second support member 28 having an upper opening through which the second molding pattern 26 may be exposed. Figure 1G One such opening through the second support 28 is shown in the core region C2 of FIG. 1 , in which the second molding pattern 26 is removed.

[0062] The shape of the upper opening may be changed according to the configuration of the lower electrode 30. For example, the upper opening may be shaped as a cylindrical or rectangular tube. Specifically, since the core region C2 may be opened by the first etching mask, most of the second support pattern 28b in the core region C2 may be removed from the substrate 10, and most of the second mold pattern 26 in the core region C2 may be exposed to the surrounding environment. Therefore, a plurality of relatively small-sized upper openings may be formed in the cell region C1, and a relatively large-sized upper opening may be formed in the core region C2. Subsequent etching processing may be performed on the second mold pattern 26 through the upper openings in the cell region C1 and the core region C2.

[0063] Therefore, between a pair of lower electrodes 30 around the upper opening, the second support member 28 may be partially cut off, and the pair of lower electrodes 30 around the upper opening may be disconnected and separated from each other. On the contrary, the lower electrodes away from the upper opening may be connected to each other and may be supported by the second support member 28. That is, the lower electrodes 30 away from the upper opening may be connected to each other via the second support member 28, and the upper portions of the lower electrodes 30 may be supported by the second support member 28.

[0064] Since the second mold pattern 26 under the second support members 28 may be removed from the substrate 10 in a subsequent etching process, the lower electrode 30 may be supported only by the second support members 28. Therefore, the number and configuration of the second support members 28 may vary depending on the supporting force required to sufficiently support the lower electrode 30.

[0065] Then, a wet etching process may be performed on the second mold pattern 26 through the upper opening, thereby removing the second mold pattern 26 from the substrate 10. Since the lower electrode 30 may be sufficiently supported by the second support member 28, the lower electrode 30 may be prevented from being tilted despite the removal of the second mold pattern 26. That is, although the second mold pattern 26 may be removed from the substrate 10, the lower electrode 30 may still be maintained vertically relative to the substrate 10 by the second support member 28.

[0066] In the present exemplary embodiment, since the second mold pattern 26 may include an oxide, a wet etching process for removing the second mold pattern 26 may be performed by using a horseshoe crab amebocyte lysate (LAL) aqueous solution as an etchant. The LAL aqueous solution may be hydrogen fluoride (HF), ammonium fluoride (NH 4 F) and a mixture of deionized water.

[0067] Therefore, the top portion of the lower electrode 30 may be supported by the second support member 28, and the lower portion of the lower electrode 30 may be supported by the first support pattern 24b and the first mold pattern 22, and the upper space US may be provided between the first support pattern 24b and the second support member 28. Therefore, the upper side of the lower electrode 30 may be exposed to the upper space US, and the upper surface of the lower electrode 30 may be coplanar with the upper surface of the second support member 28.

[0068] Reference Figure 1H , the first support pattern 24b may be partially removed from the substrate 10, thereby forming a plurality of lower openings through which the first mold pattern 22 may be exposed. Then, the first mold pattern 22 may be removed from the substrate 10 through the lower openings by an etching process.

[0069] For example, a second etch mask may be formed on the second support member 28 and the lower electrode 30 so that each upper portion may be connected to the second etch mask, so that the first support pattern 24b may be exposed through the upper opening and the second etch mask. The first support pattern 24b may be wet-etched using the second etch mask to form a lower opening through which the first mold pattern 22 may be exposed. Specifically, the second etch mask may be formed only in the cell region C1, and most of the core region C2 may be exposed like the first etch mask. Therefore, the first support pattern 24b may be formed as a first support member 24 having each lower opening in the cell region C1, and most of the first support pattern 24b may be removed from the core region C2. In the same manner as the second mold pattern 26, the first mold pattern 22 may be removed from the substrate 10 by a wet etch process using an LAL aqueous solution as an etchant.

[0070] Therefore, the first support 24 may be spaced apart from the etch stopper 18, and the lower space LS may be provided between the first support 24 and the etch stopper 18. The lower electrodes 30 except for the lower openings may be connected to each other by the first support 24 at the middle sidewall, so that the middle portion of each lower electrode 30 may be supported by the first support 24. That is, the upper portion of each lower electrode 30 may be supported by the second support 28, and the middle portion of each lower electrode 30 may be supported by the first support 24. Therefore, although the first and second mold patterns 22 and 26 are removed, the tilting of each lower electrode 30 may be prevented.

[0071] In addition, in the same manner that the upper side of each lower electrode 30 may be exposed to the upper space US, the lower side of each lower electrode 30 may also be exposed to the lower space LS.

[0072] Therefore, a plurality of cylindrical lower electrodes 30 may be arranged in a matrix shape on the substrate 10, and the top portion and the middle portion of each of the cylindrical lower electrodes 30 may be supported by the first support 24 and the second support 28. Therefore, although the aspect ratio of the cylindrical shape is high, the lower electrode 30 may be sufficiently prevented from tilting. The upper space US and the lower space SL may be communicated with the surrounding environment through the upper opening and the lower opening.

[0073] Reference Fig. 1I , a dielectric layer 40 may be formed along a surface of each lower electrode 30. In the present example embodiment, the dielectric layer 40 may be formed on top surfaces of each lower electrode 30 and each second support member 28, and on side surfaces of each lower electrode 30 that may be exposed to the upper space US and the lower space LS.

[0074] A dielectric material may be supplied into the upper space US and the lower space LS through the upper opening and the lower opening, and then the dielectric material may be deposited on the top surface of each lower electrode 30 and each second support 28, and on the side surface of each lower electrode 30, thereby forming a dielectric layer 40 on the top surface and the side surface of each lower electrode 30 and on the top surface of each second support 28. The dielectric layer 40 may include, for example, any one of oxide, nitride, and oxynitride.

[0075] Specifically, the dielectric layer 40 may be formed only in the cell region C1, and the dielectric layer may not be formed in the core region C2. Therefore, the etch stopper 18 in the core region C2 may be exposed to the surrounding environment.

[0076] Reference Figure 1J , an upper electrode 50 may be formed on the dielectric layer 40 .

[0077] For example, the conductive material may be deposited by a deposition process such as a CVD process onto the dielectric layer 40. In the deposition process, the conductive material may also be supplied into the upper space US and the lower space LS through the upper and lower openings and through the open core region C2.

[0078] Therefore, the conductive layer may be formed to a uniform thickness on the dielectric layer 40 while filling the upper space US and the lower space LS, thereby forming the upper electrode 50. In the present example embodiment, the upper electrode 50 may be the same conductive material as the lower electrode 30.

[0079] In this case, the lower electrode 30 and the upper electrode 50 may face each other in the medium of the dielectric layer 40 at the top and side surfaces of the lower electrode 30 , and thus the capacitor 90 may be separately disposed at the top and side surfaces of the lower electrode 30 .

[0080] Since the second support member 28 can be formed of the second support layer 28a without any substantial height reduction, and the top surface of the lower electrode 30 can be coplanar with the top surface of the second support member 28, the lower electrode 30 can be formed as high as possible. Therefore, the upper space US and the lower space LS can also be formed as high as possible, and as a result, the size of the facing surface between the upper electrode 50 and the lower electrode 30 in the upper space US and the lower space LS can be increased. Therefore, the capacitance of the capacitor 90 can be increased in proportion to the height of the lower electrode 30.

[0081] According to an example embodiment of the method of forming a capacitor 90 of a semiconductor device, in the etch-back process and wet etching process for forming the lower electrode 30 and the RDC process for removing the residual mask RM, the second support pattern 28b can have sufficient etching selectivity relative to the conductive material and the polysilicon, so that no substantial damage to the second support pattern 28b occurs in the etch-back process, the wet etching process and the RDC process. Therefore, in the etch-back process, the wet etching process and the RDC process, the thickness of the second support layer 28a can remain unchanged, so the height of the second support layer 28a can be as high as possible. Since the height of the lower electrode 30 can vary according to the height of the uppermost support member, the height of the lower electrode 30 can be formed to be as high as possible, thereby increasing the capacitance of the capacitor 90.

[0082] According to a typical process for forming a lower electrode, that is, when the height of the second support layer is not kept constant, the uppermost support layer is partially removed by an etch-back process during the formation of the contact hole and by a node separation process during the formation of the lower electrode in the contact hole, so that the thickness of the uppermost support member is reduced. On the contrary, according to the present exemplary embodiment, the node separation process for forming the lower electrode 30 can be performed under the condition that the second support pattern 28b can be covered by the residual mask RM, so that the second support pattern 28b can be fully protected from the node separation process. Therefore, despite the node separation process, the thickness of the second support pattern 28b can still remain unchanged. In addition, the residual mask RM can be removed from the uppermost support pattern 28b by the RDC process without damaging the second support pattern 28b, so that the second support pattern 28b can also be protected from the RDC process. Therefore, despite the RDC process, the thickness of the second support pattern 28b can still remain unchanged.

[0083] Because the uppermost support member can support the top portion of the lower electrode 30, the height of the lower electrode 30 can be determined by the height of the uppermost support member. Therefore, since in some embodiments, no reduction in the thickness of the second support pattern 28b occurs, for example, the thickness of the second support pattern 28b remains constant until the residual mask RM is removed, no reduction in the height of the lower electrode 30 occurs, for example, the lower electrode 30 can have a maximum height. Therefore, the capacitance of the capacitor 90 having the lower electrode 30 in the semiconductor device can be maximized.

[0084] Although the present exemplary embodiment discloses that the upper surface of the lower electrode 30 can be coplanar with the upper surface of the uppermost support member 28, it is also possible to increase the height of the lower electrode 30 to the same length as the protrusion height simply by controlling the etching rate of the lower electrode layer 30a so that the lower electrode 30 protrudes above the uppermost support member 28 to reach the protrusion height.

[0085] FIG. 2A to FIG. 2C are cross-sectional views showing stages of an improved method of forming a capacitor according to the first example embodiment.

[0086] Reference Figure 2A , by referring to Figures 1A to 1E The process described in detail is the same, the lower electrode layer 30a can be formed into the electrode pattern 30b by a dry etch-back process, and the residual electrode layer 32 can be removed from the second residual mask M4 by a wet etch process using LPSPM as an etchant. Specifically, the dry etch-back process can be controlled in such a way that the upper surface of the electrode pattern 30b can be higher than the upper surface of the second support pattern 28b. Therefore, the contact hole H can be filled with the electrode pattern 30b, the upper surface of the electrode pattern 30b can be higher than the upper surface of the second support pattern 28b, and the electrode pattern 30b can be defined by the first residual mask M3 in the cell region C1.

[0087] Reference Figure 2B , can be used in conjunction with the reference Figure 1F The residual mask RM is removed from the second support pattern 28b in the same RDC process described in detail, and the electrode pattern 30b can be formed as a protruding lower electrode 35, which can, for example, protrude from above the second support pattern 28b to a protruding height h. Therefore, the height of the second support pattern 28b can remain unchanged during the RDC process, and the second support pattern 28b can also have the same thickness as the second support layer 28a. Therefore, the second support pattern 28b and the protruding lower electrode 35 can be arranged in the unit area C1, and the second support pattern 28b can be arranged in the core area C2. Therefore, the surface profile of the unit area C1 can be uneven, and the surface profile of the core area C2 can be flat, for example, can be flat.

[0088] The protrusion height h can be controlled according to device requirements and processing conditions. Specifically, the protrusion height h can be formed as high as possible as long as the focus margin of the subsequent photolithography process does not deteriorate. The height of the lower electrode 35 can be increased as much as the protrusion height h, thereby increasing the capacitance of the capacitor 90.

[0089] Reference Figure 2C , a dielectric layer 40 may be formed on the top and side surfaces of the protruding lower electrode 35 and the top surface of the second support member 28, and an upper electrode 50 may be formed on the dielectric layer 40 and in the upper space US and the lower space LS in such a manner that the upper space US and the lower space LS may be formed with reference to Figure 1G to Figure 1J The same process as described in detail is filled with the upper electrode 50. Therefore, the capacitance of the capacitor 90 having the protruding lower electrode 35, the dielectric layer 40, and the upper electrode 50 can be increased due to the protruding height h of the protruding lower electrode 35.

[0090] FIG. 3A to FIG. 3D Cross-sectional views showing stages of another improved method of forming a capacitor according to the first example embodiment are shown.

[0091] Reference Figure 3A , you can refer to Figures 1A to 1C The same process described in detail forms the lower electrode layer 30a on the entire surface of the substrate 10 in such a manner that the mask pattern M may be covered by the lower electrode layer 30a. The mask pattern M may include a first mask pattern M1 in the cell region C1 of the substrate 10 and a second mask pattern M2 in the core region C2 of the substrate 10.

[0092] Reference Figure 3B , the lower electrode layer 30a may be partially removed from the substrate 10 in such a manner that the first mask pattern M1 surrounding the contact hole H and the second mask pattern M2 covering the core area C2 of the substrate 10 may be exposed. Thus, the lower electrode layer 30a may be formed into electrode patterns 30b that may be separated by the contact hole H.

[0093] Specifically, the lower electrode layer 30a may be removed to an amount that the mask pattern M may be exposed, so the electrode pattern 30b may be sufficiently higher than the second support pattern 28b. That is, the electrode pattern 30b may fill the contact hole H in the cell region C1 and may be higher than the second support pattern 28b, while the first mask pattern M1 surrounding the electrode pattern 30b and the second mask pattern M2 covering the core region C2 may be exposed. The electrode pattern 30b may be lower than the mask pattern M.

[0094] Various etching processes may be performed on the lower electrode layer 30a as long as the mask pattern M may be exposed. Therefore, any etching process for etching the conductive material may be allowed to remove the lower electrode layer 30a as long as the mask pattern M may be exposed without substantial loss of the mask pattern M.

[0095] For example, a wet etching process may be performed on the lower electrode layer 30a using LPSPM as an etchant in such a manner that the lower electrode layer 30a may be selectively removed from the mask pattern M without any substantial removal of the mask pattern M. Therefore, although the wet etching process uses LPSPM as an etchant, the mask pattern M may have the same thickness.

[0096] On the contrary, the lower electrode layer 30a may be firstly subjected to a dry etch-back process until the mask pattern M may be exposed, and then the lower electrode layer 30a may be subjected to a wet etch-back process using LPSPM as an etchant until the lower electrode layer 30a may be sufficiently separated through the contact hole H and the electrode pattern 30b may be formed. In this case, the mask pattern M may be partially removed by the dry etch-back process and may be formed as a residual mask RM, which may be the same as the reference EM. Figure 2A Substantially the same construction as described in detail.

[0097] Although the lower electrode layer 30a may be removed by the dry etch-back process, the second support pattern 28b may be sufficiently protected in the dry etch-back process by the residual mask RM. Therefore, by sequentially performing the dry etch-back process and the wet etch process using the LPSPM as an etchant, node separation of the lower electrode layer 30a may be efficiently performed without any substantial loss of the mask pattern M.

[0098] Reference Figure 3C , the mask pattern M may be removed from the second supporting pattern 28 b and thus the second supporting pattern 28 b may be exposed.

[0099] For example, a radical dry cleaning (RDC) process may be performed on the mask pattern M using a removal radical in such a manner that the mask pattern M may be selectively removed relative to the second support pattern 28 b. In this example embodiment, the mask pattern M may include polysilicon and the second support pattern 28 b may include silicon nitride, so that only the polysilicon of the mask pattern M may be removed without causing any loss to the silicon nitride of the second support pattern 28 b. The RDC process may be similar to the reference Figure 1F The process described in detail is substantially the same process. Therefore, any further detailed description of the RDC process will be omitted. Therefore, the height of the second support pattern 28b can remain unchanged during the RDC process, and the second support pattern 28b can also have the same thickness as the second support layer 28a.

[0100] Reference Figure 3D The electrode pattern 30 b may be planarized to be substantially coplanar with the second support pattern 28 b , and the support pattern 28 b may have substantially the same thickness as the support layer 28 a , thereby forming the lower electrode 30 in the contact hole H.

[0101] For example, chemical mechanical polishing (CMP) can be performed on the electrode pattern 30b by using a slurry having a sufficiently low polishing property for the second support pattern 28b and a sufficiently high polishing property for the electrode pattern 30b. However, an etch-back process can also be used to remove the upper portion of the electrode pattern 30b, as long as the second support pattern 28b can be sufficiently resistant to the etch-back process.

[0102] According to a typical CMP process for forming the lower electrode, the lower electrode layer is formed on the second support pattern 28b, and therefore the second support pattern 28b is inevitably damaged in the CMP process. However, since the electrode pattern 30b of the present exemplary embodiment can be sufficiently higher than the second support pattern 28b, the appropriate polishing conditions and polishing liquid of the CMP can make the electrode pattern 30b coplanar with the second support pattern 28b without any substantial loss or damage to the second support pattern 28b. Therefore, the lower electrode 30 can be coplanar with the second support pattern 28b, and the second support pattern 28b can have substantially the same thickness as the second support layer 28a, because any substantial loss or damage to the second support pattern 28b does not occur in the CMP process for forming the lower electrode 30.

[0103] Thereafter, the dielectric layer 40 and the upper electrode 50 can be connected by contacting the reference Figure 1G to Figure 1J The same process described in detail is then repeated to form capacitor 90 on substrate 10 .

[0104] When the lower electrode layer 30a may be formed into the lower electrode 30 by an etching process, the second support pattern 28b may be sufficiently protected from the etching process by the mask pattern M. That is, the lower electrode 30 may be formed in the contact hole H without any damage to the uppermost support pattern, so that the lower electrode 30 may be formed as high as possible corresponding to the uppermost support pattern, and the thickness or height of the uppermost support pattern may not be reduced when the lower electrode 30 is formed. Therefore, although the size of the semiconductor memory device is reduced, the capacitor 90 may have sufficient capacitance.

[0105] The above process for forming the capacitor may be modified so as to eliminate void or seam defects in the lower electrode 30. Since the aspect ratio of the contact hole H tends to increase due to the reduction in the gap distance between the adjacent interconnects 16 and the thickness of the mask pattern M, void defects or seam defects may occur in the lower electrode layer 30a. Therefore, the above process for forming the capacitor may be modified so as to eliminate void defects and / or seam defects, as described below with reference to 4A to 4F described.

[0106] 4A to 4F are cross-sectional views showing stages in still another improved method of forming a capacitor according to the first exemplary embodiment.

[0107] Reference Figure 4A , you can refer to Figures 1A to 1C The lower electrode layer 31a is formed on the entire surface of the substrate 10 by the same process as described in detail. Specifically, due to the large aspect ratio of the contact hole H, various deposition defects may occur in the lower electrode layer 31a. For example, due to the overhang of the lower electrode layer at the upper portion of the contact hole H, a void defect may occur in the lower electrode layer 31a. In addition, when the lower electrode layer 31a is not sufficiently formed at the boundary area between the contact hole H and the mask pattern M and between the contact hole H and the first mold pattern 22 and the second mold pattern 26, a tiny stripe-shaped vacant space may appear at the boundary area, thereby forming a seam defect in the lower electrode layer 31a.

[0108] Reference Figure 4B If any deposition defect occurs, the lower electrode layer 31a may be partially removed from the substrate 10 by an etching process using the first mask pattern M1 and the second mask pattern M2 as etching masks, thereby forming a first electrode pattern 31b separated by the contact hole H and a preliminary residual mask PRM covering the second support pattern 28b. For example, reference may be performed Figure 1D The dry etch-back process described in detail allows the lower electrode layer 31 a and the mask pattern M to be removed until the deposition defects D can be exposed.

[0109] Thus, the first electrode pattern 31b may be formed in the contact hole H and may be defined by the preliminary residual mask PRM, and the deposition defect D may be exposed at the upper portion. The first mask pattern M1 may be formed as the first preliminary residual mask PM3 in the cell region C1, and the second mask pattern M2 may be formed as the second preliminary residual mask PM4 in the core region C2. The preliminary residual mask PRM may include the first preliminary residual mask PM3 and the second preliminary residual mask PM4, and may have a thickness less than that of the mask pattern M.

[0110] Since the mask pattern M can be used as an etching mask for the dry etch-back process, the second support pattern 28b can be fully protected from the dry etch-back process by the preliminary residual mask PRM, and the upper surface of the first electrode pattern 31b can be lower than the upper surface of the preliminary residual mask PRM. Figure 1D In detail, at the boundary region between the cell region C1 and the core region C2, the residual electrode layer 32 may also be formed on the sidewall of the second preliminary residual mask PM4. Specifically, the empty space of the deposition defect D may be formed as a recess R of the first electrode pattern 31b, which may be recessed from the top surface of the first electrode pattern 31b.

[0111] Reference Figure 4C , an additional conductive layer 33a may be formed on the first electrode pattern 31b and the preliminary residual mask PRM to a sufficient thickness to fill the recess R of the first electrode pattern 31b. For example, the additional conductive layer 33a may include the same conductive material as the lower electrode layer 31a and may be formed by the same deposition process as the lower electrode layer 31a.

[0112] Therefore, the additional conductive layer 33a may be formed along the surface profile of the first electrode pattern 31b having the recess and defined by the preliminary residual mask PRM, and thus the first electrode pattern 31b and the preliminary residual mask PRM may be completely covered by the additional conductive layer 33a.

[0113] Reference Figure 4D , a dry etch back process may be performed on the additional conductive layer 33a and the preliminary residual mask PRM until the upper surface of the first electrode pattern 31b may be exposed. Therefore, the additional conductive layer 33a may be formed into a second electrode pattern 33b filling the recess R, and the preliminary residual mask PRM may be slightly reduced. Therefore, the first electrode pattern 31b and the second electrode pattern 33b may be formed into an electrode pattern 36b filling the contact hole H.

[0114] For example, the additional conductive layer 33a and the preliminary residual mask PRM may be simultaneously removed from the substrate 10 by a dry etch-back process. Therefore, the additional conductive layer 33a may be separated by the contact hole H and may be formed into a second electrode pattern 33b, which may fill the contact hole H defined by the preliminary residual mask PRM. Therefore, the recess R of the first electrode pattern 31b may be filled with the second electrode pattern 33b.

[0115] In this example embodiment, the lower electrode layer 31a and the mask pattern M can be partially removed from the substrate 10 by a first dry etch-back treatment, and the additional conductive layer 33a and the preliminary residual mask PRM can be partially removed from the substrate 10 by a second dry etch-back treatment, so that the first electrode pattern 31b can be formed by the first dry etch-back treatment, and the second electrode pattern 33b can be formed by the second dry etch-back treatment.

[0116] Specifically, the second support pattern 28b can be protected from the first dry etch-back process by the mask pattern M, and the second support pattern 28b can also be protected from the second dry etch-back process by the preliminary residual mask PRM. Therefore, the second support pattern 28b is not damaged in the first dry etch-back process and the second dry etch-back process, and the thickness reduction of the second support pattern 28b can be fully prevented in the first dry etch-back process and the second dry etch-back process.

[0117] Specifically, since the second preliminary residual mask PM4 can be formed to be thicker than the first preliminary residual mask PM3, in the second dry etch-back process, at the boundary region between the cell region C1 and the core region C2, some of the additional conductive layer 33a can remain on the sidewall of the second preliminary residual mask PM4, so that some of the additional conductive layer 33a can remain on the sidewall of the second preliminary residual mask PM4, and the residual electrode layer 32 can be further grown by the additional conductive layer 33a at the boundary region. In this case, considering the further removal in the subsequent etching process for removing the residual electrode layer 32, the second dry etch-back process can be controlled in such a way that the upper surface of the electrode pattern 36b can be higher than the upper surface of the second support pattern 28b. Therefore, according to the amount of further removal of the electrode pattern 36b, the upper surface of the second electrode pattern 33b can be equal to or higher than the upper surface of the first electrode pattern 31b.

[0118] Although the present exemplary embodiment discloses that the formation of an additional conductive layer and the additional dry etch-back treatment of the additional conductive layer can be performed sequentially to remove the deposition defects D of the lower electrode layer 31a, it is also disclosed that: according to the configuration and distribution of the deposition defects D in the lower electrode layer 31a, the further formation of another additional conductive layer and the further dry etch-back treatment of another additional conductive layer can be repeated to remove the deposition defects D.

[0119] Since the number of repetitions of further forming another additional conductive layer and further dry etching back for the another additional conductive layer may be increased, the constituent layers of the electrode pattern 36 b may also be added in the contact hole H. Therefore, although the present exemplary embodiment discloses that the electrode pattern 36 b may include the first electrode pattern 31 b and the second electrode pattern 33 b, a third electrode pattern or more electrode patterns may also be included in the electrode pattern 36 b.

[0120] Reference Figure 4E , can be obtained by referring to Figure 1E The substantially same process described above removes the residual electrode layer 32 from the second preliminary residual mask PM4. For example, a wet etching process may be performed on the electrode pattern 36 b and the residual electrode layer 32 in such a manner that the residual electrode layer 32 can be selectively removed from the second preliminary residual mask PM4. Specifically, since the residual mask RM may include polysilicon, LPSPM may be used as an etchant for the wet etching process. That is, by selectively etching the conductive material relative to the polysilicon, the residual electrode layer 32 may be removed from the substrate 10 together with the top portion of the electrode pattern 36 b.

[0121] Since the top portion of the electrode pattern 36b can also be removed from the substrate 10 in the wet etching process, the thickness or height of the electrode pattern 36b can be slightly reduced due to the wet etching process. In addition, the top portion of the preliminary residual mask PRM can be removed from the substrate 10 in the wet etching process, and the thickness or height of the preliminary residual mask PRM can be slightly reduced, thereby forming a residual mask RM.

[0122] In the present exemplary embodiment, the wet etching process may be controlled in such a manner that the upper surface of the electrode pattern 36b may be equal to or higher than the upper surface of the second support pattern 28b. When the upper surface of the electrode pattern 36b has the same horizontal height as the upper surface of the second support pattern 28b, the lower electrode 36 may be coplanar with the upper surface of the second support pattern 28b, which in the present exemplary embodiment may be formed as the uppermost support member, so that the surface profiles of the lower electrode 30 and the uppermost support member 28 may be flat or level.

[0123] On the contrary, when the upper surface of the electrode pattern 36b is higher than the upper surface of the second support pattern 28b, the lower electrode 36 may protrude from the upper surface of the second support pattern 28b, which may be the uppermost support in the present exemplary embodiment, so that the surface profiles of the lower electrode 36 and the uppermost support pattern 28b may be uneven, such as FIG. 2A to FIG. 2C shown.

[0124] Therefore, the contact hole H may be filled with the electrode pattern 36b and the second supporting pattern 28b may be covered with the residual mask RM. The second supporting pattern 28b in the cell region C1 may be covered with the first residual mask M3 and the second supporting pattern 28b in the core region C2 may be covered with the second residual mask M4.

[0125] Reference Figure 4F , the residual mask RM may be removed from the substrate 10 , thereby exposing the second support pattern 28 b and forming the electrode pattern 36 b as the lower electrode 36 in the contact hole H.

[0126] In reference Figure 1F Under the condition that the second support pattern 28b may not be damaged in the planarization process described in detail, the residual mask RM may be removed from the substrate 10 by the planarization process. For example, the residual mask RM may be subjected to an RDC process using a removal radical in such a manner that the polysilicon of the residual mask RM may be selectively removed relative to the silicon nitride of the second support pattern 28b.

[0127] Therefore, the second supporting pattern 28b may be exposed to the surrounding environment along the entire surface of the substrate 10, and the lower electrode 36 may be disposed in the cell region C1 through the second supporting pattern 28b. The lower electrode 36 may contact the interconnection 16 in the contact hole H.

[0128] Specifically, when the lower electrode layer 31a and the additional conductive layer 33a can be formed into the lower electrode 36, the second support pattern 28b can be substantially not damaged, so that the height of the second support pattern 28b can be unchanged during the formation of the lower electrode 36. Therefore, the second support pattern 28b can also have the same thickness as the second support layer 28a.

[0129] In addition, since the deposition defects D in the lower electrode layer 31 a may be sufficiently removed by the additional conductive layer 33 a , the lower electrode 36 may be free of deposition defects, and the operational reliability of the capacitor 90 having the lower electrode 36 may be improved.

[0130] Specifically, although the etch-back process, the wet etching process using LPSPM as an etchant, and the RDC process are repeated, the thickness or height of the second supporting pattern 28 b is not reduced, and the thickness or height of the lower electrode 36 in the cell region C1 may be maximized.

[0131] Thereafter, the dielectric layer 40 and the upper electrode 50 can be connected by contacting the reference Figure 1G and Figure 1J The same process as described in detail is formed to form a capacitor 90 on the substrate 10. By repeatedly depositing a conductive layer and dry-etching back the conductive layer without damaging the second support pattern 28b, deposition defects of the lower electrode 36 can be eliminated, thereby increasing the capacitance and operational reliability of the capacitor 90.

[0132] FIG. 5A to FIG. 5C are cross-sectional views showing stages in a method of forming a capacitor for a semiconductor device according to a second example embodiment.

[0133] Reference Figure 5A , the lower electrode layer 30a can be formed on the entire surface of the substrate 10, and the mask pattern M can be formed by Figures 1A to 1C The same process as described in detail is performed while being covered with the lower electrode layer 30a.

[0134] Reference Figure 5B , the lower electrode layer 30a may be partially removed from the substrate 10 by an etching process, thereby forming an electrode pattern 30b that may be separated by the contact hole H. For example, a wet etching process may be performed on the lower electrode layer 30a using LPSPM as an etchant, and the lower electrode layer 30a may be removed more than the mask pattern M, thereby forming an electrode pattern 30b that may be disposed in the contact hole H.

[0135] Since polysilicon may have a high etching selectivity with respect to conductive metal in LPSPM, the lower electrode layer 30a including the conductive metal may be removed more than the mask pattern M including polysilicon. Therefore, the lower electrode layer 30a may be etched away from the substrate 10 without substantial etching of the mask pattern M.

[0136] Only by controlling the end point of the wet etching process, the relative height of the electrode pattern 30b with respect to the second support pattern 28b may be changed. In the present example embodiment, the upper surface of the electrode pattern 30b may be equal to or higher than the upper surface of the second support pattern 28b.

[0137] When the upper surface of the electrode pattern 30b has the same level as the upper surface of the second support pattern 28b, Figure 5C The lower electrode 30 in the embodiment may be coplanar with the upper surface of the electrode pattern 28b, so that the surface profiles of the lower electrode 30 and the second support pattern 28b may be flat or level. On the contrary, when the upper surface of the electrode pattern 30b may be higher than the upper surface of the second support pattern 28b, the lower electrode 36 may protrude from the upper surface of the second support pattern 28b, so that the surface profiles of the lower electrode 36 and the second support pattern 28b may be uneven, such as FIG. 2A to FIG. 2C shown.

[0138] Reference Figure 5C , the mask pattern M may be removed from the substrate 10 , thereby exposing the second support pattern 28 b and forming the electrode pattern 30 b as the lower electrode 30 in the contact hole H.

[0139] In reference Figure 1F In the planarization process described in detail, the mask pattern M can be removed from the substrate 10 by the planarization process under the condition that the second support pattern 28b can be not damaged. For example, the mask pattern M can be subjected to the RDC process using the removal radical in such a way that the polysilicon of the mask pattern M can be selectively removed relative to the silicon nitride of the second support pattern 28b. Therefore, the height of the second support pattern 28b can remain unchanged during the RDC process, and the second support pattern 28b can also have the same thickness as the second support layer 28a.

[0140] Thereafter, the dielectric layer 40 and the upper electrode 50 can be connected by contacting the reference Figures 1G to 1J The same process as described in detail is formed, thereby forming a capacitor 90 on the substrate 10. The lower electrode layer 30a can be formed into an electrode pattern 30b by an etching process without damaging the second support pattern 28b, thereby preventing the thickness or height of the uppermost support from being reduced in the formation process of the lower electrode. Therefore, although the critical dimension (CD) of the semiconductor device can be reduced, the lower electrode 30 can also be formed as high as possible, and the capacitance of the capacitor 90 can be sufficiently increased.

[0141] FIG. 6A to FIG. 6D are cross-sectional views showing stages in a method of forming a capacitor for a semiconductor device according to a third example embodiment.

[0142] Reference Fig. 6A , the lower electrode layer 30a can be formed on the entire surface of the substrate 10, and can be Figures 1A to 1C The mask pattern M is covered with the lower electrode layer 30a by the same process as described in detail.

[0143] Reference Figure 6B , the lower electrode layer 30a and the mask pattern M may be planarized until the top surface of the lower electrode layer 30a and the top surface of the mask pattern M may be coplanar with each other. Therefore, the lower electrode layer 30a may be formed into a preliminary electrode pattern 30c that may remain only in the contact hole H, and in the cell region C1 and the core region C2, the mask pattern M may be formed into a residual mask RM that may cover the second support pattern 28b.

[0144] For example, a chemical mechanical polishing (CMP) process may be performed along the cell region C1 and the core region C2 of the substrate 10 in such a manner that the lower electrode layer 30a and the mask pattern M may be simultaneously removed from the substrate 10 and the lower electrode layer 30a and the mask pattern M may have the same level. Therefore, the CMP process may be performed by using a polishing liquid, by which the lower electrode layer 30a and the mask pattern M may be simultaneously polished and removed from the substrate 10. In this case, the upper surface of the preliminary electrode pattern 30c and the upper surface of the residual mask RM may be sufficiently higher than the upper surface of the second support pattern 28b, thereby preventing the second support from being damaged during the CMP process.

[0145] Since the CMP process can be performed faster than the subsequent processing of the preliminary electrode pattern 30c and the residual mask RM, the preliminary electrode pattern 30c and the residual mask RM can be formed to a thickness as small as possible in a short time as long as the second support pattern 28b is not damaged in the CMP process. Therefore, since the preliminary electrode pattern 30c and the residual mask RM can be sufficiently reduced in the CMP process, the processing time for forming the electrode pattern 30b and the processing time for removing the residual mask RM can be reduced. Fig.6D The total processing time of the lower electrode 30 in the embodiment can be reduced by the CMP process.

[0146] Therefore, the preliminary electrode pattern 30c and the residual mask RM can be planarized in such a way that the upper surfaces of the preliminary electrode pattern 30c and the residual mask RM can be as close as possible to the upper surface of the second support pattern 28b as long as the second support pattern 28b is not damaged during the CMP process, thereby reducing the processing time for subsequent processing of the preliminary electrode pattern 30c and the residual mask RM.

[0147] Reference Figure 6C , an upper portion of the preliminary electrode pattern 30c may be removed from the substrate 10, thereby forming an electrode pattern 30b in the contact hole H. The second support pattern 28b may still be covered by the residual mask RM.

[0148] For example, by wet etching using LPSPM as an etchant, the upper portion of the preliminary electrode pattern 30c can be selectively removed from the substrate 10 relative to the residual mask RM. Therefore, the upper surface of the electrode pattern 30b can be lower than the upper surface of the residual mask RM, and the contact hole H can be filled with the electrode pattern 30b.

[0149] In this case, the relative height of the electrode pattern 30b with respect to the second support pattern 28b can be changed only by controlling the end point of the wet etching process.The upper surface of the electrode pattern 30b may be equal to or higher than the upper surface of the second support pattern 28b.

[0150] In the present example embodiment, the upper surface of the electrode pattern 30b may have the same horizontal height as the upper surface of the second support pattern 28b, and the lower electrode 30 may be coplanar with the upper surface of the second support pattern 28b. On the contrary, when the upper surface of the electrode pattern 36b may be higher than the upper surface of the second support pattern 28b, the lower electrode 30 may protrude from the upper surface of the second support pattern 28b, so that the surface profiles of the lower electrode 30 and the second support pattern 28b may be uneven, such as FIG. 2A to FIG. 2C shown.

[0151] Reference Fig.6D, the residual mask RM may be removed from the substrate 10 , thereby exposing the second support pattern 28 b and forming the electrode pattern 30 b as the lower electrode 30 in the contact hole H. Referring to FIG.

[0152] For example, the RDC treatment can be performed on the residual mask RM using a removal radical in such a manner that the polysilicon of the residual mask RM can be selectively removed relative to the silicon nitride of the second support pattern 28b. Therefore, the second support pattern 28b can be exposed to the surrounding environment along the entire surface of the substrate 10, and the lower electrode 30 can be arranged in the cell area C1 through the second support pattern 28b. The lower electrode 30 can contact the interconnect 16 in the contact hole H. Specifically, the second support pattern 28b is not substantially damaged during the RDC treatment, so the height of the second support pattern 28b can be substantially unchanged during the RDC treatment. Therefore, the second support pattern 28b can also have the same thickness as the second support layer 28a. The RDC treatment can be performed with the same thickness as the reference pattern 28b. Figure 1F Therefore, any detailed description of the RDC process is omitted in this exemplary embodiment. Figure 1G to Figure 1J The same process described in detail is used to form dielectric layer 40 and upper electrode 50 to form capacitor 90 on substrate 10.

[0153] The lower electrode layer 30a and the mask pattern M can be planarized simultaneously by the CMP process in such a way that the upper surface of the preliminary electrode pattern 30c and the upper surface of the residual mask RM can be as close as possible to the upper surface of the second support pattern 28b, as long as the second support pattern 28b is not damaged in the CMP process, thereby reducing the etching time of the wet etching process for the preliminary electrode pattern 30c and the cleaning time of the RDC process for the residual mask RM. Therefore, since the process time for forming the lower electrode 30 is reduced, the total process time for forming the capacitor can be substantially reduced.

[0154] 7A to 7C are cross-sectional views showing stages in a modified method of forming a capacitor according to the third example embodiment.

[0155] Reference Fig. 7A , the lower electrode layer 30a can be formed on the entire surface of the substrate 10 in such a manner that: Fig. 6A and Figure 6B The process described is the same, the mask pattern M can be covered by the lower electrode layer 30a and the lower electrode layer 30a and the mask pattern M can be planarized until the top surface of the lower electrode layer 30a and the top surface of the mask pattern M can be coplanar with each other, thereby forming a preliminary electrode pattern 30c that can be retained only in the contact hole H and a residual mask RM that can cover the second support pattern 28b in the cell area C1 and the core area C2.

[0156] For example, the lower electrode layer 30a and the mask pattern M may be removed by a first CMP process having a first polishing rate, thereby forming a preliminary electrode pattern 30c and a residual mask RM. The first polishing rate of the first CMP process may be greater than the second polishing rate of the second CMP process, which will be referred to below. Figure 7C Therefore, through the relatively fast first CMP process, the process time for forming the preliminary electrode pattern 30c and the residual mask RM can be substantially reduced.

[0157] Reference Figure 7B , the residual mask RM may be removed from the substrate 10 , thereby exposing the second supporting pattern 28 b and the preliminary electrode pattern 30 c , so that the preliminary electrode pattern 30 c may protrude from the second supporting pattern 28 b .

[0158] For example, the RDC treatment can be performed on the residual mask RM using the removal radical in such a manner that the polysilicon of the residual mask RM can be selectively removed relative to the silicon nitride of the second support pattern 28b and the conductive material of the preliminary electrode pattern 30c. Therefore, the preliminary electrode pattern 30c and the second support pattern 28b can be exposed to the surrounding environment along the entire surface of the substrate 10. Specifically, the preliminary electrode pattern 30c and the second support pattern 28b will not be damaged during the RDC treatment, and therefore, the height of the second support pattern 28b can remain substantially unchanged during the RDC treatment. Therefore, the second support pattern 28b can also have the same thickness as the second support layer 28a. The RDC treatment can be performed with the same thickness as the reference electrode pattern 30c. Figure 1F Therefore, any detailed description about the RDC process is omitted in the present exemplary embodiment. Therefore, the preliminary electrode patterns 30c may be arranged in a matrix shape in the cell region C1 while protruding from the second support pattern 28b.

[0159] Reference Figure 7C , an upper portion of the preliminary electrode pattern 30c may be removed from the substrate 10, thereby forming the lower electrode 30. When the preliminary electrode pattern 30c excessively protrudes from the second support pattern 28b, a focus error may occur in a subsequent photolithography process for forming a dielectric layer on the lower electrode 30.

[0160] For example, the upper portion of the preliminary electrode pattern 30c may be selectively removed from the substrate 10 relative to the second support pattern 28b by a wet etching process using LPSPM as an etchant, as shown in FIG. Figure 1EIn this case, the relative height of the lower electrode 30 relative to the second support pattern 28b can be changed only by controlling the end point of the wet etching process. In this example embodiment, the upper surface of the electrode pattern 30b may have the same horizontal height as the upper surface of the second support pattern 28b, and the lower electrode 30 may be coplanar with the upper surface of the second support pattern 28b.

[0161] However, when the upper surface of the preliminary electrode pattern 30c is higher than the upper surface of the second support pattern 28b, the lower electrode 30 may protrude from the upper surface of the second support pattern 28b, and the surface profiles of the lower electrode 30 and the second support pattern 28b may be uneven, such as FIG. 2A to FIG. 2C The protrusion of the lower electrode 30 may be permitted under the condition that the focus margin of a subsequent photolithography process for forming a dielectric layer on the lower electrode 30 does not deteriorate.

[0162] In a modified example embodiment, the upper portion of the preliminary electrode pattern 30c may be removed by a second CMP process having a second polishing rate less than the first polishing rate. The second support pattern 28b may be used as a polishing stopper for the second CMP process. Therefore, the preliminary electrode pattern 30c may be formed as a lower electrode 30 that may be coplanar with the second support pattern 28b.

[0163] The second CMP process can be performed by using such a polishing liquid so that the second support pattern 28b can be sufficiently resistant to the polishing liquid, and the preliminary electrode pattern 30c can be sufficiently well polished by the polishing liquid. In addition, the second CMP can be performed at a sufficiently low polishing rate so that the loss or damage to the second support pattern 28b can be sufficiently prevented in the second CMP process. Therefore, the height of the second support pattern 28b can be unchanged during the formation of the lower electrode 30, and the second support pattern 28b can have substantially the same thickness or height as the second support layer 28a. Therefore, the thickness or height of the lower electrode 30 can be maximized in the unit area C1.

[0164] Thereafter, the dielectric layer 40 and the upper electrode 50 can be connected by contacting the reference Figure 1G to Figure 1J The same process described in detail is then repeated to form capacitor 90 on substrate 10 .

[0165] FIG. 8A to FIG. 8B Cross-sectional views showing stages in another improved method of forming a capacitor according to a third example embodiment are shown.

[0166] Reference Fig. 8A , the lower electrode layer 30a can be formed on the entire surface of the substrate 10 in such a manner that the mask pattern M can be formed by Figures 1A to 1CThe lower electrode layer 30a and the mask pattern M may be planarized by the same process described in detail while being covered by the lower electrode layer 30a until the top surface of the lower electrode layer 30a and the top surface of the mask pattern M may be coplanar with each other, thereby forming an electrode pattern 30b filling the contact hole H and a residual mask RM covering the second support pattern 28b in the cell region C1 and the core region C2.

[0167] For example, the lower electrode layer 30a and the mask pattern M may be removed by a first CMP process at a first polishing rate, referring to Fig. 7A This process is described in detail, thereby forming the electrode pattern 30b and the residual mask RM.

[0168] In the first CMP process, the first polishing liquid may be provided to the lower electrode layer 30a, and the lower electrode 30a and the mask pattern M may be polished at a first polishing rate. Therefore, by the first CMP process having a relatively high polishing rate, the processing time for forming the electrode pattern 30b and the residual mask RM may be substantially reduced. The electrode pattern 30b may fill the contact hole H, and the upper surface of the electrode pattern 30b may be coplanar with the upper surface of the residual mask RM. The second support pattern 28b may still be covered by the residual mask RM in the cell region C1 and the core region C2. Specifically, only by controlling the first polishing liquid and polishing conditions of the first CMP process, the upper surface of the electrode pattern 30b and the upper surface of the residual mask RM may be substantially higher than the upper surface of the second support pattern 28b.

[0169] Specifically, although the first polishing rate of the first CMP process may be relatively high, since the residual mask RM may have a sufficient thickness and may cover the second supporting patterns 28b, the second supporting patterns 28b may be sufficiently protected in the first CMP process.

[0170] Reference Figure 8B , the electrode pattern 30b and the upper portion of the residual mask RM may be simultaneously removed by the second CMP process at a second polishing rate that is lower than the first polishing rate.

[0171] A second polishing liquid (the second support pattern 28b may be sufficient to resist the second polishing liquid) may be provided onto the electrode pattern 30b and the residual mask RM, and a second CMP process may be relatively slowly performed on the electrode pattern 30b and the residual mask RM at a second polishing rate.

[0172] Therefore, the residual mask RM can be removed from the second supporting pattern 28b without causing any substantial damage or loss to the second supporting pattern 28b, and the upper portion of the electrode pattern 30b can be removed in such a manner that the upper surface of the electrode pattern 30b is coplanar with the top surface of the second supporting pattern 28b, thereby forming a lower electrode 30 in the contact hole H that can be coplanar with the second supporting pattern 28b, and the height of the second supporting pattern 28b can remain unchanged during the CMP process, and the second supporting pattern 28b can have the same thickness as the second supporting layer 28a.

[0173] According to the polishing characteristics of the first CMP process and the second CMP process, the first polishing liquid may be the same as or different from the second polishing liquid. In the present exemplary embodiment, the first polishing liquid may have the same components as the second polishing liquid. In this case, the second CMP process may be continuously performed after the first CMP process only by reducing the first polishing rate to the second polishing rate.

[0174] Since the first CMP process for forming the electrode pattern 30b and the residual mask RM can be performed relatively quickly, and the second support pattern 28b can be protected by the residual mask RM during the first CMP process, and the second CMP process for forming the lower electrode 30 can be performed relatively slowly without substantially damaging the second support pattern 28b, the lower electrode 30 can be effectively formed in the contact hole H without causing any damage to the second support pattern 28b.

[0175] Thereafter, the dielectric layer 40 and the upper electrode 50 can be connected by contacting the reference Figure 1G to Figure 1J The same process described in detail is then repeated to form capacitor 90 on substrate 10 .

[0176] 9A to 9D are cross-sectional views showing stages in a method of forming a capacitor for a semiconductor device according to a fourth example embodiment.

[0177] Reference Fig.9A , by referring to Figure 1A and 1BThe same process described above can partially remove the first mold layer 22a and the second mold layer 26a and the first support layer 24a and the second support layer 28a from the substrate 10, thereby forming a contact hole H in the cell region C1 of the substrate 10, and the interconnection 16 can be exposed through the contact hole H. Therefore, the first mold layer 22a and the second mold layer 26a can be formed into the first mold pattern 22 and the second mold pattern 26, respectively, and the first support layer 24a and the second support layer 28a can be formed into the first support pattern 24b and the second support pattern 28b, respectively. Specifically, the first mold layer 22a and the second mold layer 26a can include an oxide that does not contain boron (B) to prevent the first mold pattern 22 and the second mold pattern 26 from being removed in a subsequent process for removing the mask pattern M.

[0178] In the present example embodiment, the composition of the first mold pattern 22 and the second mold pattern 26 may be selected to have a sufficient etching selectivity with respect to the polysilicon of the mask pattern M, so that the first mold pattern 22 and the second mold pattern 26 may include an oxide that does not contain boron (B). Therefore, when the mask pattern M includes other materials besides polysilicon, the composition of the first mold pattern 22 and the second mold pattern 26 may also vary according to the material of the mask pattern M.

[0179] Reference Fig. 9B , the mask pattern M may be removed from the substrate 10 in a manner that does not damage the second supporting pattern 28 b.

[0180] For example, the mask pattern M may be removed from the substrate 10 by a planarization process, by which the second support pattern 28b is not damaged, as shown in FIG. Figure 1F In the present example embodiment, the RDC treatment can be performed on the residual mask RM using the removal radical in such a manner that the polysilicon of the residual mask RM can be selectively removed relative to the silicon nitride of the second support pattern 28b. Therefore, the second support pattern 28b can be exposed to the surrounding environment along the entire surface of the substrate 10, and the interconnection 16 can be exposed through the contact hole H.

[0181] The first mold pattern 22 and the second mold pattern 26 may be exposed in the contact hole H, and thus the first mold pattern 22 and the second mold pattern 26 may also be subjected to the RDC treatment. However, the removal radicals of the RDC treatment may selectively react with the polysilicon, and the oxides of the first mold pattern 22 and the second mold pattern 26 may not react with the removal radicals. Specifically, the boron-based oxide may react with the removal radicals used to remove the polysilicon in the RDC treatment, and thus the first mold pattern 22 and the second mold pattern 26 may include an oxide that does not contain boron (B). Therefore, the mask pattern M may be removed from the substrate 10 without substantially damaging the first support pattern 24b and the second support pattern 28b as well as the first mold pattern 22 and the second mold pattern 26. Specifically, despite the RDC treatment of removing the mask pattern M, the thickness of the second support pattern 28b may still remain unchanged, Fig.9D The lower electrode 30 in the embodiment can still be formed as high as possible.

[0182] Reference Fig. 9C , a lower electrode layer 30a may be formed on the substrate 10 to a sufficient thickness to fill the contact hole H and cover the second support pattern 28b. For example, a conductive material may be deposited on the substrate 10 to a sufficient thickness to fill the contact hole H by a chemical vapor deposition (CVD) process, thereby forming the lower electrode layer 30a in contact with the interconnection 16. The CVD process for forming the lower electrode layer 30a may be the same as that described in reference to FIG. Figure 1C The CVD process described is the same.

[0183] Specifically, since the lower electrode layer 30a can be formed on the substrate 10 after removing the mask pattern M, deposition defects (e.g., void defects and / or seam defects) can be substantially reduced, for example, compared to forming the lower electrode layer through a mask. Since the mask pattern M may not be located on the second support pattern 28b, the aspect ratio of the contact hole H can be reduced compared to the aspect ratio generated when the mask pattern M is located on the second support pattern 28b. Therefore, since the aspect ratio of the contact hole H is reduced, deposition defects in the lower electrode layer 30a can be reduced.

[0184] Reference Fig.9D The lower electrode layer 30a may be partially removed from the substrate 10 with an etch selectivity relative to the second support pattern 28b. Portions of the lower electrode layer 30a may remain only in the contact hole H, thereby forming the lower electrode 30 contacting the interconnection 16 in the contact hole H.

[0185] Specifically, the removal process of the lower electrode layer 30a can be mainly performed on the lower electrode layer 30a without damaging the second support pattern 28b. Therefore, the height or thickness of the second support pattern 28b can be substantially unchanged during the planarization process. Therefore, the lower electrode 30 can be formed into a configuration in which the upper surface of the lower electrode 30 can be coplanar with the upper surface of the second support pattern 28b.

[0186] For example, the CMP treatment can be performed on the lower electrode layer 30a by using such a polishing liquid: the second support pattern 28b can be sufficiently resistant to the polishing liquid, and the lower electrode layer 30a can be sufficiently well polished by the polishing liquid. Therefore, the lower electrode layer 30a can be formed into a lower electrode 30 that can fill the contact hole H and is coplanar with the second support pattern 28b. Since the second support pattern 28b is not damaged or lost during the CMP treatment, the second support pattern 28b can have substantially the same thickness as the second support layer 28a. Therefore, the height reduction of the lower electrode 30 caused by the reduction in the thickness of the second support pattern 28b can be fully prevented.

[0187] In addition, the lower electrode layer 30a may also be removed by an etch-back process as long as the second support pattern 28b is not damaged during the etch-back process.

[0188] In addition, a wet etching process may be performed on the lower electrode layer 30a using LPSPM as an etchant until the upper surface of the second support pattern 28b can be exposed. In the wet etching process using LPSPM as an etchant, the conductive material of the lower electrode layer 30a may be etched away from the substrate 10 with a high etching selectivity relative to the second support pattern 28b until the upper surface of the second support pattern 28b can be exposed. That is, the second support pattern 28b may be used as an etching stopper for the wet etching process using LPSPM as an etchant.

[0189] Therefore, the lower electrode 30 may be formed in the contact hole H in such a configuration that the upper surface of the lower electrode 30 may be coplanar with the upper surface of the second support pattern 28b. Since the second support pattern 28b is not damaged or lost during the formation process of the lower electrode 30, the height reduction of the lower electrode 30 caused by the reduction in the thickness of the second support pattern 28b can be fully prevented.

[0190] Thereafter, the dielectric layer 40 and the upper electrode 50 can be connected by contacting the reference Figure 1G to Figure 1J The same process described in detail is then repeated to form capacitor 90 on substrate 10 .

[0191] Since the mask pattern M can be removed from the substrate without substantially damaging the second support pattern 28b, and the first mold pattern 22 and the second mold pattern 26 and the lower electrode layer 30a can be formed as the lower electrode 30 without substantially damaging the second support pattern 28b, the height or thickness of the second support pattern 28b can be unchanged in the removal process of the mask pattern M and the node separation process of the lower electrode layer 30a. Therefore, since the height of the lower electrode 30 can be determined by the second support pattern 28b, the second support pattern 28b can be formed as the uppermost support member in the subsequent process, so despite the removal process of the mask pattern M and the node separation process of the lower electrode layer 30, the height of the lower electrode 30 can still be formed as high as possible.

[0192] Fig.10 It shows that FIG. 2A to FIG. 2C The plan view of the semiconductor device of the capacitor shown, Fig.11 is along Fig.10 A cross-sectional view taken along line AA in FIG.

[0193] Reference Fig.10 and Fig.11 , a semiconductor device 500 according to example embodiments may include a substrate 100, a memory cell structure 200 disposed on the substrate 100, an interconnection 300 connected to the memory cell structure, and a charge storage structure (i.e., a capacitor 400) connected to the interconnection and selectively storing charges. The capacitor 400 may include a lower electrode 410 that may be connected to the interconnection 300 and may be supported by at least one support 415, a dielectric layer 420 covering a surface of the lower electrode 410 and an upper surface of the support 415, and an upper electrode 430 located on the dielectric layer 420. Specifically, the lower electrode 410 may protrude from the support 415.

[0194] For example, the substrate 100 may include a semiconductor substrate on which a plurality of thin film transistors (TFTs) for a flat panel display device may be arranged, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon on insulator (SOI) substrate, a germanium on insulator (GOI) substrate, and a glass substrate.

[0195] The substrate 100 may include an active region 102 on which a plurality of conductive structures (e.g., gate electrodes) may be disposed, and a field region defining the active region 102. A device isolation layer 110 may be disposed on the field region, and thus, conductive structures on adjacent active regions 102 may be electrically isolated from each other by the device isolation layer 110.

[0196] In this example embodiment, the active region 102 may be tilted at an inclination angle ( Fig.10), and the plurality of active regions 102 may be arranged with the same gap distance in the first direction I and the second direction II. The inclined arrangement of the active regions 102 may increase the cell density of the substrate 100 and have a sufficient gap distance between adjacent active regions 102.

[0197] In the present example embodiment, a pair of gate lines may intersect a single active region 102 in a first direction I, and a single bit line may intersect a single active region 102 in a second direction II, so that a plurality of word lines WL of the semiconductor device 500 may extend in the first direction I, and a plurality of bit lines BL of the semiconductor device 500 may extend in the second direction II. The bit line BL may intersect the active region 102 at a central portion, and the word line WL may intersect the active region 102 between the central portion and the end portion. Therefore, a pair of word lines WL and a single bit line BL may intersect each other at a single active region 102.

[0198] Reference Fig.11 , the memory cell structure 200 may include a buried gate 210 and a junction region 220, the top portion of the buried gate 210 may be located below the top surface of the substrate 100, and the top portion of the junction region 220 may be located above the top portion of the buried gate 210. The gate trench may be disposed in the cell region along the first direction I, so the gate trench may alternately intersect the active region 102 and the device isolation layer 110 with each other in the first direction I. The buried gate 210 may be arranged in the gate trench and may be disposed as a word line WL in the first direction I.

[0199] For example, the buried gate 210 may include a gate insulating layer on the bottom and side surfaces of the gate trench, a gate conductive layer on the gate insulating layer and filling a lower portion of the gate trench, and a gate capping pattern on the gate conductive layer and filling an upper portion of the gate trench.

[0200] A pair of buried gates may be located in a single active region 102, and portions of the active region 102 on which the buried gates are not placed may be provided as junction regions 220. Since a pair of word lines WL that may be spaced apart by a gap distance may intersect the single active region 102, the junction region 220 may be provided at a central portion and both end portions of the active region 102. That is, the central portion and both end portions may be provided as the junction region 220 in the single active region 102. In the present example embodiment, the central portion of the active region 102 may be recessed to a certain depth and may be provided as a first junction 222, and both end portions of the active region 102 may have the same horizontal height as the top surface of the substrate 100, and may be provided as a pair of second junctions 224.

[0201] Some impurities may be implanted into the junction region 220 , and a source S and a drain D may be provided in each active region 102 , so a buried gate and the source S and the drain D may be provided as a unit transistor. That is, a pair of unit transistors may be provided at a single active region 102 .

[0202] The first junction 222 may be recessed downward from the top surface of the substrate 100 so that the top portion of the first junction 222 may be lower than the top surface of the device isolation layer 110. The bit line contact 310 may electrically connect the first junction 222, and the bit line BL may be connected to the first junction 222 via the bit line contact 310.

[0203] The second junction 224 may have the same surface level as the device isolation layer 110, and thus the surface level of the second junction 224 may be higher than the surface level of the first junction 222. The storage contact 320 may be connected to the second junction 224, and the capacitor 400 may be electrically connected to the second junction 224 via the storage contact 320. Therefore, the semiconductor device 500 may include the buried gate 210 in the cell region of the substrate 100 and the source S and the drain D at the junction region 220 as a buried channel array transistor (BCAT) structure.

[0204] The interconnect 300 may include a bit line contact 310 in contact with the bit line BL and a storage contact 320 in contact with the capacitor 400. In the present example embodiment, the bit line contact 310 may be provided as a direct contact (DC) that is in direct contact with the bit line BL in the same insulating interlayer 390, and the storage contact 320 may be provided as a buried contact (BC) that is buried in the insulating interlayer 390 and contacts the capacitor 400 through the insulating interlayer 390.

[0205] The bit line BL may extend in the second direction II and may be simultaneously connected to a plurality of first junctions 222, which may be arranged in a row along the second direction II. The plurality of bit lines BL may be arranged at the same gap distance in the first direction I. Thus, a pair of second junctions 224 may be located at both sides of each bit line BL.

[0206] In the present example embodiment, the bit line BL may be provided as a gate bit line (GBL), wherein a top surface of the bit line BL may be coplanar with a bottom surface of a peripheral gate structure (not shown). The peripheral gate structure may be arranged in a core region or a peripheral region of the substrate 100 .

[0207] The storage contact 320 may be connected to the capacitor 400 and the second junction 224. A plurality of storage contacts 320 may be arranged in a matrix shape between each bit line along the first direction I and the second direction II.

[0208] The storage contacts 320 may be electrically isolated from each other by the insulating interlayer 390, and the capacitor 400 may be disposed on the insulating interlayer 390. The storage contact 320 may contact the second junction 224 through the insulating interlayer 390, and the upper surface of the storage contact 320 may be coplanar with the upper surface of the insulating interlayer 390. Therefore, the storage contact 320 may contact the lower electrode 410 of the capacitor 400, and the lower electrode 410 of the capacitor 400 may be disposed on the insulating interlayer 390. A connection pad may be further provided between the storage contact 320 and the capacitor 400 to increase the contact area between the storage contact 320 and the capacitor 400.

[0209] The capacitor 400 may be connected to the memory cell structure 200, and charges may be selectively charged to or discharged from the capacitor 400. In the present example embodiment, the capacitor 400 may include: a plurality of lower electrodes 410, which may be respectively connected to the interconnection 300 and may be supported by at least one support 415; a dielectric layer 420, which covers surfaces of the lower electrodes 410 and upper portions of the support 415; and an upper electrode 430, which is located on the dielectric layer 420.

[0210] In the present example embodiment, the lower electrode 410, the support member 415, the dielectric layer 420, and the upper electrode 430 may be formed in the same manner as the reference electrode 410. FIG. 2A to FIG. 2C Formed by the same process described above, capacitor 400 may include capacitor 90 in which the lower electrode may protrude from uppermost support member 28 .

[0211] Therefore, the support member 415 may include an upper support member 415a supporting the top portion of the lower electrode 410 and a lower support member 415b supporting the middle portion of the lower electrode 410. In addition, the upper electrode 430 may be arranged in the upper space US and the lower space LS and on the lower electrode 410, so that in the upper space US and the lower space LS, the upper electrode 430 may face the side surfaces of the lower electrode 410 and the upper surface of the lower electrode 410, thereby increasing the capacitance of the capacitor 400. Specifically, the lower electrode 410 may protrude from the top surface of the upper support member 415a to a protrusion height h, so that the height of the lower electrode 410 may be increased to be as high as the protrusion height h.

[0212] In this case, as long as the focus margin of the subsequent photolithography process does not deteriorate, the protrusion height h can be formed as high as possible. Therefore, the capacitance of the capacitor 400 can be increased according to the height increase of the lower electrode 410. Therefore, the lower electrode 410 can protrude from the uppermost support member 415, and due to the protrusion height h of the lower electrode 410, the capacitance of the capacitor 400 can also be increased. In addition, the node separation process for forming the lower electrode 410 and the RDC process for removing the mask pattern M can be performed under the condition that the uppermost support member 415 can be fully protected. Therefore, in the node separation process and the RDC process, the thickness of the uppermost support member 415 can remain unchanged. Therefore, since the thickness of the uppermost support member 415 is not reduced, the lower electrode 410 can be formed as high as possible, thereby fully increasing the capacitance of the capacitor 400.

[0213] By summarizing and reviewing, when the lower electrode of the capacitor of the DRAM device is formed to be as high as possible, in the etching process for forming the lower electrode pattern, the support pattern for supporting the lower electrode pattern can be partially removed from the substrate. As a result, due to the partial removal of the support pattern, the total height of the lower electrode can be limited to a specific height.

[0214] In contrast, example embodiments provide a method for manufacturing a semiconductor device in which a lower electrode of a capacitor is formed without damaging a support pattern. That is, according to example embodiments, a lower electrode for a capacitor of a semiconductor device can be formed without causing substantial damage to the uppermost support pattern, thereby preventing the thickness of the uppermost support member for supporting the top portion of the lower electrode from being reduced. Since the height of the lower electrode varies according to the thickness of the uppermost support member, the height of the lower electrode can also be formed to be high enough to fully increase the capacitance of the capacitor. For example, by controlling only the dry etch-back process, the lower electrode can be formed to be higher than the uppermost support member, so that the lower electrode can protrude from the uppermost support member. Therefore, the height of the lower electrode can be increased to be as high as the protruding height, and the capacitance of the capacitor can be increased due to the increase in the height of the lower electrode.

[0215] That is, according to an embodiment, before removing the mask pattern, a lower electrode layer is formed on the substrate. That is, the mask pattern for forming the contact hole may be covered by the lower electrode layer. Then, the lower electrode layer is formed as the lower electrode in the contact hole by a dry etch-back process and a wet etch process using LPSPM as an etchant, and then the mask pattern is removed from the support pattern by an RDC process. Therefore, in the dry etch-back process, the wet etch process using LPSPM as an etchant, and the RDC process, no substantial damage is caused to the support pattern because the support pattern is covered by the mask pattern before the node separation process is completed.

[0216] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art when filing this application, unless otherwise specifically noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: sequentially forming a mold layer, a support layer, and a mask pattern on an entire surface of a substrate, the substrate having a cell region defined by a core region, and a lower conductive structure and at least one interconnection contacting the lower conductive structure being located on the cell region of the substrate below the mold layer; partially removing the support layer and the mold layer by an etching process using the mask pattern as an etching mask to form a mold pattern and a support pattern on the mold pattern, so that a contact hole is formed through the support pattern and the mold pattern to expose the at least one interconnection in the cell region; forming a lower electrode layer on the mask pattern to fill the contact hole; forming a lower electrode of the capacitor in the contact hole by partially removing the lower electrode layer and removing the mask pattern so that the lower electrode is supported by the support pattern and contacts the interconnection, the support pattern having the same thickness as the support layer, Wherein, forming the lower electrode comprises: forming the electrode pattern in the contact hole and the residual mask on the support pattern by partially removing the lower electrode layer and the mask pattern from the substrate through a dry etch-back process; and The residual mask is removed from the support pattern by a radical dry cleaning process, thereby exposing the support pattern and forming the electrode pattern as a lower electrode in the contact hole.

2. The method of claim 1, wherein: The electrode pattern is formed to be higher than the support pattern and lower than the residual mask.

3. The method of claim 2, wherein: The electrode pattern is further removed by a wet etching process using a low peroxide sulfuric acid-hydrogen peroxide mixture as an etchant.

4. The method of claim 1, wherein: The electrode pattern is formed to be equal to or higher than the support pattern.

5. The method of claim 4, after removing the residual mask from the substrate, further comprising: The electrode pattern higher than the support pattern is planarized by chemical mechanical polishing until the electrode pattern is coplanar with the support pattern.

6. The method of claim 1, wherein: Forming the electrode pattern and the residual mask includes: forming a preliminary residual mask on the first electrode pattern in the contact hole and the support pattern by partially removing the lower electrode layer and the mask pattern from the substrate through a dry etch-back process and forming at least one recess on the top surface of the first electrode pattern; forming an additional conductive layer on the first electrode pattern and the preliminary residual mask so that the at least one recess is filled with the additional conductive layer; and The second electrode pattern in the contact hole and the residual mask on the support pattern are formed by dry etching, so that the additional conductive layer and the preliminary residual mask are partially removed from the substrate, and the first electrode pattern and the second electrode pattern filling the at least one recess located on the first electrode pattern constitute the electrode pattern.

7. A method for manufacturing a semiconductor device, the method comprising: sequentially forming a mold layer, a support layer, and a mask pattern on an entire surface of a substrate, the substrate having a cell region defined by a core region, and a lower conductive structure and at least one interconnection contacting the lower conductive structure being located on the cell region of the substrate below the mold layer; partially removing the support layer and the mold layer by an etching process using the mask pattern as an etching mask to form a mold pattern and a support pattern on the mold pattern, so that a contact hole is formed through the support pattern and the mold pattern to expose the at least one interconnection in the cell region; forming a lower electrode layer on the mask pattern to fill the contact hole; forming a lower electrode of the capacitor in the contact hole by partially removing the lower electrode layer and removing the mask pattern so that the lower electrode is supported by the support pattern and contacts the interconnection, the support pattern having the same thickness as the support layer, Wherein, forming the lower electrode in the contact hole comprises: partially removing the lower electrode layer by a wet etching process so that the lower electrode layer is separated by the contact hole, thereby forming an electrode pattern in the contact hole, while the support pattern is covered by the mask pattern; and The mask pattern is removed from the support pattern by a radical dry cleaning process.

8. The method of claim 7, wherein: The wet etching process is performed by using a low peroxide sulfuric acid-hydrogen peroxide mixture as an etchant.

9. The method of claim 8, wherein: The electrode pattern is formed to be equal to or higher than the support pattern.

10. The method of claim 9, after removing the mask pattern from the substrate, the method further comprises: The electrode pattern higher than the support pattern is planarized by chemical mechanical polishing until the electrode pattern is coplanar with the support pattern.

11. A method for manufacturing a semiconductor device, the method comprising: sequentially forming a mold layer, a support layer, and a mask pattern on an entire surface of a substrate, the substrate having a cell region defined by a core region, and a lower conductive structure and at least one interconnection contacting the lower conductive structure being located on the cell region of the substrate below the mold layer; partially removing the support layer and the mold layer by an etching process using the mask pattern as an etching mask to form a mold pattern and a support pattern on the mold pattern, so that a contact hole is formed through the support pattern and the mold pattern to expose the at least one interconnection in the cell region; forming a lower electrode layer on the mask pattern to fill the contact hole; forming a lower electrode of the capacitor in the contact hole by partially removing the lower electrode layer and removing the mask pattern so that the lower electrode is supported by the support pattern and contacts the interconnection, the support pattern having the same thickness as the support layer, Wherein, forming the lower electrode in the contact hole comprises: By planarizing the lower electrode layer and the mask pattern, a preliminary electrode pattern in the contact hole and a residual mask on the support pattern are formed simultaneously, so that the upper surface of the preliminary electrode pattern is coplanar with the upper surface of the residual mask, and The residual mask is removed from the support pattern by a radical dry cleaning process to expose the support pattern.

12. The method of claim 11, wherein: The lower electrode layer and the mask pattern are planarized at a first polishing rate through a first chemical mechanical polishing process.

13. The method according to claim 12, before removing the residual mask, further comprising: The preliminary electrode pattern is partially removed to form an electrode pattern in the contact hole so that an upper surface of the electrode pattern is coplanar with an upper surface of the support pattern.

14. The method of claim 13, wherein: The preliminary electrode pattern is removed by a wet etching process using a low peroxide sulfuric acid-hydrogen peroxide mixture as an etchant.

15. The method of claim 12, wherein: The residual mask is removed from the support pattern together with the preliminary electrode pattern by a second chemical mechanical polishing process at a second polishing rate less than the first polishing rate until the support pattern is exposed, thereby forming a lower electrode coplanar with the support pattern.

16. The method according to claim 11, after removing the residual mask to expose the support pattern, the method further comprises: The preliminary electrode pattern is partially removed in such a manner that an upper surface of the lower electrode is coplanar with the support pattern to form a lower electrode pattern in the contact hole.

17. The method of claim 16, wherein: The preliminary electrode pattern is partially removed by a wet etching process using a low peroxide sulfuric acid-hydrogen peroxide mixture as an etchant.

18. The method of claim 16, wherein: The preliminary electrode pattern is partially removed by a chemical mechanical polishing process using the support pattern as a polishing stopper.

19. A method for manufacturing a semiconductor device, the method comprising: sequentially forming a mold layer not containing boron, a support layer, and a mask pattern on the entire surface of a substrate, the substrate having a cell region defined by a core region, and at least one lower conductive structure and at least one interconnection contacting the at least one lower conductive structure located on the cell region of the substrate below the mold layer; partially removing the support layer and the mold layer by an etching process using a mask pattern as an etching mask to form a mold pattern and a support pattern on the mold pattern, so that a contact hole is formed through the support pattern and the mold pattern, and the interconnection is exposed through the contact hole in the cell region; removing the mask pattern from the support pattern by a free radical dry cleaning process; forming a lower electrode layer on the support pattern to fill the contact hole; as well as By partially removing the lower electrode layer, a lower electrode of a capacitor contacting the interconnection in the contact hole is formed.

20. The method of claim 19, wherein: The lower electrode layer is partially removed by a wet etching process using a low-peroxide sulfuric acid-hydrogen peroxide mixture as an etchant so that an upper surface of the lower electrode is coplanar with an upper surface of the support pattern.

21. The method of claim 19, wherein: The lower electrode layer is partially removed by a chemical mechanical polishing process using a polishing liquid, the support pattern is sufficient to resist the polishing liquid, and the lower electrode layer is sufficiently polished by the polishing liquid.

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