Vertical field effect transistor with two-dimensional channel structure

Abstract

The present invention can provide a vertical field effect transistor, which includes: a first source / drain region; a channel structure, which protrudes upward from the first source / drain region and is configured to serve as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at least on one side of the channel structure, the channel structure including one or two first parts and one or more second parts, the one or two first parts extending in a first direction, and the one or more second parts being connected to a corresponding one or more of the one or two first parts and extending in a second direction, the second direction being different from the first direction; a gate structure, which horizontally surrounds the channel structure; and a second source / drain region, which is upward on the channel structure.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This non-provisional application claims priority to U.S. Provisional Patent Application No. 62 / 610,650 filed on December 27, 2017 and U.S. Non-provisional Patent Application No. 16 / 128,995 filed in the U.S. Patent and Trademark Office on September 12, 2018, as well as all rights derived from the U.S. Provisional Patent Application and the U.S. Non-provisional Patent Application based on 35 U.S.C119, and the contents of the U.S. Provisional Patent Application and the U.S. Non-provisional Patent Application are all incorporated into this application for reference. Technical Field

[0003] Some exemplary embodiments of the inventive concepts disclosed herein relate to vertical field effect transistors, and more particularly, to vertical field effect transistors (VFETs) having a two-dimensional (2D) channel structure. Background Art

[0004] Vertical field effect transistors (VFETs) have been extensively studied as a promising candidate for a fin field effect transistor (FinFET) replacement and / or a horizontal nanosheet field effect transistor (HNS FET) replacement due to enhanced scalability and lower middle-of-line (MOL) capacitance and / or relatively low contact resistance in transistor structures. In addition, VFETs have design freedom in terms of their channel length. Therefore, VFETs can be designed to not have the so-called short channel effect.

[0005] Figure 1 A conceptual perspective cross-sectional view of a VFET is shown. Figure 1 , VFETs have relatively short channel widths compared to other devices (e.g., FinFETs and HNSFETs). For example, when a FinFET used to implement a 1X inverter standard cell has a channel width of 300nm, a VFET used to implement the same 1X inverter standard cell may have a channel width of 220nm. As a result, VFETs tend to have relatively poor current drivability. Therefore, it is desirable to have a VFET structure that has a relatively wide channel width compared to other device architectures (e.g., FinFETs and HNS FETs) and therefore exhibits improved performance. Summary of the invention

[0006] Some exemplary embodiments of the inventive concept provide a vertical field effect transistor (VFET) having an increased effective channel width.

[0007] Some exemplary embodiments of the inventive concepts provide a VFET having a two-dimensional (2D) channel structure.

[0008] Some exemplary embodiments of the inventive concepts provide VFETs with improved electrical performance.

[0009] According to an exemplary embodiment of the inventive concept, a VFET may include: a first source / drain region; a channel structure protruding upward from the first source / drain region and configured to function as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at least on one side of the channel structure, the channel structure including one or two first portions and one or more second portions, the one or two first portions extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or two first portions and extending in a second direction, the second direction being different from the first direction; a gate structure horizontally surrounding the channel structure; and a second source / drain region upward on the channel structure.

[0010] According to an exemplary embodiment of the inventive concept, a VFET may include: a substrate including a first source / drain region; a channel structure protruding from the first source / drain region and configured to function as a channel, the channel structure having a two-dimensional shape in a plan view, the channel structure having an opening at least on one side of the channel structure, a gate structure horizontally surrounding the channel structure; and a second source / drain region located on the channel structure.

[0011] According to an exemplary embodiment of the inventive concept, a VFET may include: a substrate including a first source / drain region; a channel structure protruding vertically from the first source / drain region of the substrate and configured to function as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at least on one side of the channel structure, the channel structure including two or more first portions and at least one second portion, the two or more first portions extending in a first direction, the at least one second portion connecting the two or more first portions; a gate structure horizontally surrounding the channel structure; and a second source / drain region located on the channel structure, the second source / drain region facing the first source / drain region and the channel structure being vertically sandwiched between the second source / drain region and the first source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other features and advantages of the present invention will become more apparent by describing in detail some exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0013] Figure 1 A conceptual perspective cutaway view of a vertical field effect transistor (VFET) is shown.

[0014] Figure 2A is a perspective view of a 1X inverter standard cell implemented by a VFET according to conventional technology.

[0015] Figure 2B is a perspective view of a 1X inverter standard cell implemented by a VFET according to an exemplary embodiment of the inventive concept.

[0016] Figure 3 yes Figure 2A A plan view of a one-dimensional (1D) channel structure of a VFET is shown.

[0017] FIG. 4A to FIG. 4E is a plan view of an example of a two-dimensional (2D) channel structure of a VFET according to some exemplary embodiments of the inventive concept.

[0018] Figure 5 It shows that Figure 2A and Figure 3 The VFET with a one-dimensional channel structure shown in FIG. Figure 2B and Figure 4A FIG. 1 is a graph showing the alternating current (AC) performance comparison results between VFETs having two-dimensional channel structures.

[0019] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H and Fig.6I is used to explain the formation of an exemplary embodiment according to the concept of the present invention Figure 2B A perspective view of the method of showing the channel structure. DETAILED DESCRIPTION

[0020] It should be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0021] The term "and / or" as used herein includes any and all combinations of one or more of the related listed items. When an expression such as "at least one of..." is located after a series of elements, it modifies the elements of the entire series rather than the individual elements in the series. Thus, for example, "at least one of A, B, or C" and "A, B, and / or C" both mean A, B, C, or any combination of A, B, C. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which the exemplary embodiments belong. It should also be understood that terms (such as those defined in a commonly used dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and unless explicitly defined herein, should not be interpreted as having an idealized or overly formal meaning.

[0022] Hereinafter, some exemplary embodiments of the inventive concept will be explained with reference to the accompanying drawings.

[0023] Figure 2A is a perspective view of a 1X inverter standard cell implemented by a vertical field effect transistor (VFET) according to conventional technology. Figure 2B is a perspective view of a 1X inverter standard cell implemented by a VFET according to an exemplary embodiment of the inventive concept.

[0024] Reference Figure 2A, according to the conventional technology, the 1X inverter standard cell 200a includes an N-type metal oxide semiconductor (NMOS) VFET 200N and a P-type metal oxide semiconductor (PMOS) VFET 200P. The NMOS VFET 200N includes a first source / drain region 230a, a channel structure 250a, and a gate structure 270. For the sake of convenience of explanation, the gate insulating layer and the second source / drain region of the NMOS VFET 200N are not specifically shown. The PMOS VFET 200P includes a first source / drain region 230b, a channel structure 250b, and a gate structure 270. For the sake of convenience of explanation, the gate insulating layer and the second source / drain region of the PMOS VFET 200P are not specifically shown. The first source / drain regions 230a and 230b may be formed in the semiconductor substrate 210. In some cases, each of the first source / drain regions 230a and 230b may be disposed at a bottom portion of a fin protruding from the semiconductor substrate 210. The channel structures 250a and 250b may be provided by a fin protruding from the semiconductor substrate 210. For ease of explanation, each of the channel structures 250a and 250b will be interchangeably referred to as a fin.

[0025] Substrate 210 may be a portion of a bulk silicon wafer. Substrate 210 may be a silicon portion of a silicon-on-insulator (SOI) wafer. Substrate 210 may include materials other than silicon, including but not limited to Ge, SiGe, SiC, GeP, GeN, InGaAs, GaAs, InSb, InAs, GaSb, and InP. Substrate 210 may refer to a semiconductor layer epitaxially grown on a base substrate.

[0026] Reference Figure 2A , first source / drain regions 230a and 230b are disposed in the substrate 210. The first source / drain region 230a may be doped with n-type impurities (e.g., phosphorus P or arsenic As) and used as the source or drain of the NMOS VFET 200N. The first source / drain region 230b may be doped with p-type impurities (e.g., boron B) and used as the source or drain of the PMOS VFET 200P.

[0027] The second source / drain regions (not shown) of the NMOS VFET 200N and the PMOS VFET 200P may be disposed at upper portions of the channel structures 250a and 250b, respectively, or may be disposed on the channel structures 250a and 250b, respectively. For example, the second source / drain regions may be epitaxially grown on the channel structures 250a and 250b. In some examples, the first source / drain regions 230a and 230b may be used as source regions, and the second source / drain regions (not shown) may be used as drain regions. In some other examples, the first source / drain regions 230a and 230b may be used as drain regions, and the second source / drain regions (not shown) may be used as source regions.

[0028] As shown in the figure, each of the fins constituting the channel structure of the VFET (e.g., 200N or 200P) is arranged one-dimensionally in a plan view. In other words, each of the fins constituting the channel structure of the VFET (e.g., 200N or 200P) has a linear shape extending in one direction. In addition, the two fins constituting the channel region of the VFET are spaced apart from each other. Conventional technology has been illustrated using examples in which each of the VFETs includes a channel structure formed by two fins. However, examples of conventional technology are not limited thereto. In some other examples of conventional technology, the channel structure of the VFET may include more than two fins (e.g., three fins).

[0029] Reference Figure 2B , a 1X inverter standard cell 200b according to an exemplary embodiment of the inventive concept includes an NMOS VFET 200N' and a PMOS VFET 200P'. The NMOS VFET 200N' includes a first source / drain region 230a', a channel structure 250a', and a gate structure 270'. For the sake of illustration, the gate insulating layer and the second source / drain region of the NMOS VFET 200N' are not specifically shown. The PMOS VFET 200P' includes a first source / drain region 230b', a channel structure 250b', and a gate structure 270'. For the sake of illustration, the gate insulating layer and the second source / drain region of the PMOS VFET 200P' are not specifically shown.

[0030] picture Figure 2A 2 , substrate 210' may be part of a bulk silicon wafer. Substrate 210' may be a silicon portion of a silicon-on-insulator (SOI) wafer. Substrate 210' may include materials other than silicon, including but not limited to Ge, SiGe, SiC, GeP, GeN, InGaAs, GaAs, InSb, InAs, GaSb, and InP. Substrate 210' may refer to a semiconductor layer epitaxially grown on a base substrate.

[0031] The first source / drain regions 230a' and 230b' may be formed in the semiconductor substrate 210'. In some cases, each of the first source / drain regions 230a' and 230b' may be disposed at a bottom portion of a fin protruding from the semiconductor substrate 210'. According to some exemplary embodiments, each of the first source / drain regions 230a' and 230b' may be formed at a bottom portion of a fin protruding from the semiconductor substrate 210'. The first source / drain region 230a' may be doped with n-type impurities (e.g., phosphorus P or arsenic As) and used as a source or drain of the NMOS VFET 200N'. The first source / drain region 230b' may be doped with p-type impurities (e.g., boron B) and used as a source or drain of the PMOS VFET 200P'.

[0032] Each of the second source / drain region (not shown) of the NMOS VFET 200N' and the second source / drain region (not shown) of the PMOS VFET 200P' may be disposed at an upper portion of the fin protruding from the substrate 210'. In some exemplary embodiments of the inventive concept, the second source / drain region (not shown) of the NMOS VFET 200N' and the second source / drain region (not shown) of the PMOS VFET 200P' may be disposed on the channel structures (e.g., fins) 250a' and 250b', respectively. In some examples, the first source / drain regions 230a' and 230b' may be used as source regions, and the second source / drain region (not shown) may be used as drain regions. In some other examples, the first source / drain regions 230a' and 230b' may be used as drain regions, and the second source / drain region (not shown) may be used as source regions.

[0033] The second source / drain region (not shown) of the NMOS VFET 200N' and the second source / drain region (not shown) of the PMOS VFET 200P' may protrude vertically over the gate structure 270'.

[0034] The gate structure 270 ′ may horizontally surround the channel structures 250 a ′ and 250 b , respectively.

[0035] Each of the channel structures 250a' and 250b' may be provided by a fin protruding from the semiconductor substrate 210'. Therefore, for ease of explanation, each of the channel structures 250a' and 250b' will be interchangeably referred to as a fin. Figure 2B, the channel structure (e.g., 250a' or 250b') of the VFET (e.g., 200N' or 200P') is provided by a fin protruding upward from a first source / drain region (e.g., 230a' or 230b') and has a two-dimensional (2D) shape in a plan view. In addition, the two-dimensional shape of the channel structure has an opening at least on one side of the channel structure. The channel structure (e.g., 250a' or 250b') may include (1) one or two first portions and (2) one or more second portions, the one or two first portions extending in a first direction, the one or more second portions connected to corresponding one or more of the one or two first portions and extending in a second direction, the second direction being different from the first direction. For example, the channel structure may have a Π shape.

[0036] For example, Figure 2B The channel structure (250a' or 250b') shown can be realized with Figure 2A The one-dimensional (1D) channel structures (250a and 250b) shown have an effective channel width W that is 25% larger than eff , as summarized in Table 1 below.

[0037] Figure 2A VFET shown Figure 2B VFET shown Fin pitch(nm) 40 40 Fin width(nm) 6 6 Fin shape ||(one-dimensional) Π(2D) <![CDATA[W length (nm)]]> 50 / 50 50 / 34 / 50 <![CDATA[W eff (nm)]]> (50+50+6+6)×2＝224 (50+44+6+6)×2+34×2＝280

[0038] Table 1

[0039] Table 1 assumes a situation where the pitch between fins is 40 nm and the width of the fin is 6 nm.

[0040] According to this design rule, Figure 2A Each of the channel structures (or fins) 250a and 250b is horizontally surrounded by a gate structure 270. Therefore, the effective channel width of one fin is 50+50+6+6=112nm. Figure 2A The total effective channel width W achieved by the two one-dimensional channel structures shown is eff It is 112×2=224nm.

[0041] According to the same design rules, Figure 2B The channel structure 250 a ′ or 250 b ′ shown has a two-dimensional structure in a plan view, and is horizontally surrounded by the gate structure 270 ′. Figure 2B The channel structure (or fin) 250a' or 250b' shown corresponds to the Figure 2A The structure shown is that two one-dimensional fin portions are connected to each other by a connecting fin portion. Therefore, the effective channel width of each of the two one-dimensional fin portions is (50+44+6+6)×2=212nm, and the effective channel width of the connecting fin portion is 34×2=68nm. Therefore, Figure 2B The total effective channel width W achieved by the two-dimensional channel structure showneff is 212+68=280nm. Since the effective channel width is large, Figure 2B The VFET with a two-dimensional channel structure shown in FIG. Figure 2A The VFET having the one-dimensional channel structure shown may exhibit improved alternating current (AC) electrical characteristics and / or direct current (DC) electrical characteristics compared to FETs.

[0042] Reference Figure 2A and Figure 2B , Figure 2B The VFET shown (for example, a VFET having a Π-shaped two-dimensional channel structure) has a Figure 2A The VFET shown (e.g., a VFET having a one-dimensional channel structure) has an effective channel width of approximately 25%. Figure 2B The VFET shown is Figure 2A The VFET shown exhibits improved DC characteristics (e.g., current drivability) compared to the VFET shown. For example, Figure 2B The NMOS VFET with a two-dimensional channel structure shown in FIG. Figure 2A The NMOS VFET with a one-dimensional channel structure shown has 25% greater current drivability and Figure 2B The PMOS VFET with a two-dimensional channel structure shown in FIG. Figure 2A The PMOS VFET with a one-dimensional channel structure has a 19% greater current drivability. Figure 2A Compared with the VFET with a one-dimensional channel structure shown in Figure 2B The VFET with the two-dimensional channel structure shown can also exhibit improved AC performance. Figure 5 The improvement of AC performance of VFETs with two-dimensional channel structures is described.

[0043] although Figure 2B The channel structures 250a' and 250b' are shown to have a Π shape, however exemplary embodiments of the inventive concept are not limited thereto. The channel structure may have any shape as long as it has a two-dimensional shape in a plan view and has an opening at one side of the channel structure.

[0044] Figure 3 yes Figure 2A A plan view of a one-dimensional channel structure of a VFET shown in FIG. In the present disclosure, a one-dimensional channel structure refers to a channel structure in which each portion is arranged in a one-dimensional form (for example, arranged in a line shape) in a plan view. Figure 3, the one-dimensional channel structure includes two fins that protrude from the substrate and are each arranged in a straight line shape in one direction. A VFET employing such a one-dimensional channel structure has relatively poor current drivability compared to, for example, fin field-effect transistor (FinFET) alternatives and / or horizontal nanosheet field-effect transistor (HNS FET) alternatives.

[0045] FIG. 4A to FIG. 4E is a plan view of an example of a two-dimensional (2D) channel structure of a VFET according to some exemplary embodiments of the inventive concept. In the present disclosure, a two-dimensional channel structure refers to a channel structure having a two-dimensional shape in a plan view. Figure 4A shows Figure 2B an example of the two-dimensional channel structure (e.g., Π shape) of the VFET shown; Figure 4B shows an example in which the two-dimensional channel structure has an H shape; Figure 4C shows an example in which the two-dimensional channel structure has a [] shape; Figure 4D shows an example in which the two-dimensional channel structure has a modified Π shape (or mouth shape, with an opening in a part of one side of the mouth shape); and Figure 4E shows an example in which the two-dimensional channel structure has a mouth shape.

[0046] Employing FIG. 4A to FIG. 4E one of the two-dimensional channel structures shown, a VFET can have a relatively wide channel width compared to Figure 3 the one-dimensional channel structure shown, and thus can exhibit improved current drivability compared to a VFET employing a one-dimensional channel structure.

[0047] According to some exemplary embodiments of the inventive concept (e.g., FIG. 4A to FIG. 4D ), the two-dimensional channel structure can have an opening at one side and can include a first part and at least one second part, the first part extending in a first direction, the at least one second part being connected to the first part and extending in a second direction, the second direction being different from the first direction. FIG. 4A to FIG. 4D respectively show two-dimensional channel structures having a Π shape, an H shape, a [] shape, and a modified Π shape. However, the exemplary embodiments of the inventive concept are not limited thereto. In some exemplary embodiments, the channel structure can have an X shape, a Z shape, a [] shape, or an E shape. The [] shape and the E shape can be regarded as modified examples of the Π shape.

[0048] According to some exemplary embodiments, the two-dimensional shape of each of the channel structures 250a' and 250b' having an opening at one side may include two or more first portions and at least one second portion, the two or more first portions extending in a first direction, and the at least one second portion connecting the two or more first portions. The number of the two or more first portions may be two, and the number of the at least one second portion may be one. For example, the channel structures 250a' and 250b' may have a Π shape. The number of the two or more first portions may be three, and the number of the at least one second portion may be one. For example, the channel structures 250a' and 250b' may have an E shape. The number of the two or more first portions may be three, and the number of the at least one second portion may be two. For example, the channel structures 250a' and 250b' may have shape.

[0049] Figure 4E A two-dimensional channel structure having a mouth shape is shown as an exemplary two-dimensional channel structure having a closed shape (without an opening at one side). In this case, the gate structure may have a first portion and a second portion, the first portion horizontally covering the inside of the channel structure, and the second portion horizontally covering the outside of the channel structure. Therefore, the gate voltage can only be applied to the second portion of the gate structure and cannot be applied to the first portion of the gate structure. This is because the channel structure does not have an opening at one side of its two-dimensional structure, and therefore the first portion and the second portion of the gate structure are physically separated from each other.

[0050] Figure 5 It shows that Figure 2A and Figure 3 The VFET with a one-dimensional channel structure shown in FIG. Figure 2B and Figure 4A The graph shows the AC performance comparison results between VFETs with two-dimensional channel structures. Figure 5 , Figure 2B and Figure 4A The VFET (an example having a two-dimensional channel structure) shown is relative to Figure 2A and Figure 3 The comparative VFET (an example having a one-dimensional channel structure) shown shows an approximately 6% improvement in AC performance. dd At the data point, Figure 2B The VFET is shown relative to Figure 2A The comparative VFET shown shows approximately 11% performance improvement in AC performance. Figure 2B and Figure 4A The VFET with a two-dimensional channel structure shown in FIG. Figure 2A and Figure 3Compared with the VFET with a one-dimensional channel structure shown in FIG. 1 , the VFET can also exhibit improved DC characteristics, as shown in the above connection. Figure 2A and Figure 2B described.

[0051] According to some exemplary embodiments of the present disclosure, a VFET may be provided with a channel structure with an increased effective channel width. Therefore, a VFET with improved direct current characteristics (eg, current drivability) may be obtained.

[0052] According to some exemplary embodiments of the present disclosure, the VFET may be provided with a two-dimensional channel structure having an opening on one side and a gate structure horizontally surrounding the channel structure. Therefore, a first portion of the gate structure covering the inside of the two-dimensional channel structure is connected to a second portion of the gate structure covering the outside of the two-dimensional channel structure. Therefore, a gate voltage may be applied to both the first portion of the gate structure and the second portion of the gate structure.

[0053] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H and Fig.6I is used to explain the formation of an exemplary embodiment according to the concept of the present invention Figure 2B A perspective view of the method of showing the channel structure.

[0054] Reference Fig. 6A , a stack formed of insulating layers may be deposited on a semiconductor substrate 600. The semiconductor substrate 600 may be a portion of a bulk silicon wafer. The semiconductor substrate 600 may be a silicon portion of a silicon-on-insulator (SOI) wafer. The semiconductor substrate 600 may include materials other than silicon, including but not limited to Ge, SiGe, SiC, GeP, GeN, InGaAs, GaAs, InSb, InAs, GaSb, and InP. The semiconductor substrate 600 may refer to a semiconductor layer epitaxially grown on a base substrate.

[0055] The stack formed by the insulating layer may include a first insulating layer 601, a second insulating layer 602, a third insulating layer 603, a fourth insulating layer 604, a fifth insulating layer 605, a sixth insulating layer 606, and a seventh insulating layer 607. The first insulating layer 601, the third insulating layer 603, and the sixth insulating layer 606 may include the same material or materials having an etching selectivity comparable to each other. In some exemplary embodiments, the second insulating layer 602 and the fourth insulating layer 604 may include an oxide material (e.g., SiO 2 ) or silicon carbide materials and have comparable etching selectivities to each other.

[0056] A mandrel mask pattern 610 (interchangeably referred to as a mandrel layer) may be formed on the seventh insulating layer 607. The mandrel mask pattern 610 may be formed using a photolithography process (eg, an extreme ultraviolet (UV) photolithography process). The mandrel mask pattern 610 may include a photoresist material.

[0057] The seventh insulating layer 607 may have a high etching selectivity to the underlying sixth insulating layer 606. In some exemplary embodiments, the fifth insulating layer 605 may include a hard mask material (e.g., a silsesquioxane material or a silanol material), the sixth insulating layer 606 may include a nitride, and the seventh insulating layer 607 may include an organic layer formed of a spin-on organic hard-mask (SOH) material. The SOH material may be a Si-based material or a carbon-based material.

[0058] Reference Figure 6B , the seventh insulating layer 606 may be etched using the mandrel mask pattern 610 as a mask to form the mandrel 607a. The etching may be performed using, for example, reactive ion etching. After the mandrel mask pattern 610 is removed using, for example, an ashing process, the mandrel 607a may remain on the seventh insulating layer 606.

[0059] Reference Figure 6C , a spacer layer 620 may be conformally formed on the mandrel 607a and the fifth insulating layer 605 using a chemical vapor deposition or atomic layer deposition process. The spacer layer 620 may include a silicon nitride material or a silicon oxide material.

[0060] Next, the spacer layer 620 may be etched to leave spacers 620a around the mandrel 607a, as shown in FIG. Fig.6D shown.

[0061] Reference Fig. 6E , the mandrel 607 a may be removed using, for example, a wet etch that can selectively remove the mandrel 607 a while leaving the spacer 620 a on the fifth insulating layer 605 .

[0062] Although not specifically shown in a separate figure, the fifth and sixth insulating layers 605 and 606 may be etched using the spacer 620a as a mask to form a hard mask pattern. Next, the second, third, and fourth insulating layers 602, 603, and 604 may be etched using the hard mask pattern as a mask.

[0063] Then, the hard mask pattern may be removed to leave the intermediate structure IS including the second insulation layer pattern 602a, the third insulation layer pattern 603a and the fourth insulation layer pattern 604a, as shown in FIG. Fig. 6F shown.

[0064] Afterwards, a fin cutting mask layer may be formed on the intermediate structure IS including the second insulation layer pattern 602a, the third insulation layer pattern 603a, and the fourth insulation layer pattern 604a. In some exemplary embodiments, the fin cutting mask layer may include a first mask layer and a second mask layer. In addition, the first mask layer may be deposited so that the top surface of the first mask layer is higher than the top surface of the intermediate pattern IS, and then the first mask layer may be planarized (e.g., etched back) to facilitate the subsequent photolithography process. A second mask layer may be deposited on the first mask layer.

[0065] Reference Figure 6G The fin-cut mask layer (e.g., a stack formed by the first mask layer and the second mask layer) may be patterned to form a fin-cut mask pattern 630P (e.g., a stack formed by the first mask pattern 630a and the second mask pattern 630b). The fin-cut mask pattern 630P may have openings at regions where the underlying fin structure is exposed and to be cut.

[0066] Reference Figure 6H , the first insulating layer 601, the second insulating layer 602, the third insulating layer 603, and the fourth insulating layer 604 may be etched using the fin cutting mask pattern 630P as a mask to form a stack pattern including a first insulating layer pattern 601a, a second insulating layer pattern 602a, and a third insulating layer pattern 603a. During this process, the semiconductor substrate 600 may also be etched to a certain depth to form a fin structure 600f, which protrudes from the semiconductor substrate 600 and is separated from each other. In some example embodiments, the fourth insulating layer pattern 604a may be removed.

[0067] Once the insulating layers (eg, the first insulating layer 601, the second insulating layer 602, the third insulating layer 603, and the fourth insulating layer 604) on the fin structure 600f are removed, a semiconductor substrate 600 having the fin structure 600f can be formed. Figure 2B Or the channel structure shown in 4A has a two-dimensional shape.

[0068] Then, you can Fig.6I Bottom source / drain regions 640a and 640b and a gate structure 650 are formed as shown in FIG.

[0069] In some exemplary embodiments, the bottom source / drain regions 640a and 640b may be formed by: (1) using ion implantation; or (2) by etching the semiconductor substrate 600 to form a recess and epitaxially growing a doped semiconductor structure to fill the recess. The gate structure 650 may be formed to surround the fin structure 600f in plan view.

[0070] Although not specifically shown using a separate figure, to complete the manufacture of the VFET, a top source / drain region may be formed on the fin structure 600f or at a top portion of the fin structure 600f, respectively. The top source / drain region may be epitaxially grown on the fin structure 600f, respectively, or may be formed by introducing impurities (e.g., n-type conductivity impurities or p-type conductivity impurities) on a top portion of the fin structure 600f, respectively.

[0071] The above is an illustration of the exemplary embodiments and should not be considered as limiting the exemplary embodiments. Although several exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments as defined by the claims.

Claims

1. A vertical field effect transistor, characterized in that: include: a first source / drain region; a channel structure protruding upward from the first source / drain region and configured to function as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side of the channel structure, the channel structure including one or two first portions and one or more second portions, the one or two first portions extending in a first direction, and the one or more second portions connected to corresponding one or more of the one or two first portions and extending in a second direction, the second direction being different from the first direction; a gate structure horizontally surrounding the channel structure in a completely surrounding manner in a plan view; and A second source / drain region is disposed upwardly on the channel structure.

2. The vertical field effect transistor according to claim 1, characterized in that: The second source / drain region and the channel structure are disposed in a fin structure, which is a protruding portion of a substrate.

3. The vertical field effect transistor according to claim 2, characterized in that: The first source / drain region is disposed in the substrate.

4. The vertical field effect transistor according to claim 2, characterized in that: The first source / drain region is disposed in the fin structure.

5. The vertical field effect transistor according to claim 1, characterized in that: The second source / drain region protrudes vertically over the gate structure.

6. The vertical field effect transistor according to claim 1, characterized in that: The channel structure has at least one of a Π shape, an H shape, a [] shape, an X shape, or a Z shape.

7. A vertical field effect transistor, characterized in that: include: a substrate including a first source / drain region; a channel structure protruding from the first source / drain region and configured to function as a channel, the channel structure having a two-dimensional shape in a plan view, the channel structure having an opening at least on one side of the channel structure, a gate structure horizontally surrounding the channel structure in a completely surrounding manner in a plan view; and The second source / drain region is located on the channel structure.

8. The vertical field effect transistor according to claim 7, characterized in that: The channel structure is disposed in a fin structure, which is a protruding portion of the substrate.

9. The vertical field effect transistor according to claim 8, characterized in that: The second source / drain region is disposed in the fin structure.

10. The vertical field effect transistor according to claim 7, characterized in that: The second source / drain region protrudes vertically over the gate structure.

11. The vertical field effect transistor according to claim 7, characterized in that: The channel structure includes a first portion extending in a first direction and at least one second portion connected to the first portion and extending in a second direction different from the first direction.

12. A vertical field effect transistor, characterized in that: include: a first source / drain region included in the substrate; a channel structure protruding vertically from the first source / drain region of the substrate and configured to function as a channel, the channel structure having a two-dimensional structure in a plan view, the channel structure having an opening at at least one side of the channel structure, the channel structure including two or more first portions and at least one second portion, the two or more first portions extending in a first direction, the at least one second portion connecting the two or more first portions; a gate structure horizontally surrounding the channel structure in a completely surrounding manner in a plan view; and A second source / drain region is located on the channel structure, the second source / drain region faces the first source / drain region and the channel structure is vertically sandwiched between the second source / drain region and the first source / drain region.

13. The vertical field effect transistor according to claim 12, characterized in that: The channel structure is disposed in a fin structure, which is a protruding portion of the substrate.

14. The vertical field effect transistor according to claim 13, characterized in that: The second source / drain region is disposed in the fin structure.

15. The vertical field effect transistor according to claim 12, characterized in that: The second source / drain region protrudes vertically over the gate structure.

16. The vertical field effect transistor according to claim 12, characterized in that: The number of the two or more first parts is two, and the number of the at least one second part is one.

17. The vertical field effect transistor according to claim 12, characterized in that: The number of the two or more first parts is three, and the number of the at least one second part is one.

18. The vertical field effect transistor according to claim 12, characterized in that: The number of the two or more first portions is three, and the number of the at least one second portion is two.

19. The vertical field effect transistor according to claim 12, characterized in that: The channel structure has a Π shape, an H shape, an E shape or At least one of the shapes.

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