Semiconductor device and manufacturing method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor device structure having a vertically stacked complementary field effect transistor (CFET). The CFET is formed by bonding two substrates on which a semiconductor stack is formed. Bonding structures are formed between the semiconductor stacks using wafer bonding techniques. Embodiments of the present disclosure enable flexibility in selecting different N / P channel characteristics, provide a simple way to form N / P channel isolation structures, and reduce potential leakage paths and defects in stacking CFETs. The embodiment of the invention also relates to a semiconductor device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking brings new challenges.

[0003] In pursuit of higher device density, higher performance and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field effect transistors (FETs), including nanosheet FETs. In nanosheet FETs, all sides of the channel are surrounded by gate electrodes, which allows for more complete depletion in the channel and results in less short channel effects and better gate control. As transistor dimensions continue to shrink, further improvements in nanosheet FETs are needed. Summary of the invention

[0004] Some embodiments of the present application provide a method for manufacturing a semiconductor device, including: forming a first semiconductor stack on a first substrate; forming a second semiconductor stack on a second substrate; bonding the second substrate to the first substrate so that the second semiconductor stack is stacked above the first semiconductor stack; removing the second substrate; patterning the first semiconductor stack and the second semiconductor stack to form a fin structure; and forming a first transistor and a second transistor from the fin structure, wherein the first transistor includes a first source / drain region disposed across a portion of the first semiconductor stack, and the second transistor includes a second source / drain region disposed across a portion of the second semiconductor stack.

[0005] Some other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a fin structure above a first substrate, wherein the fin structure includes: a first semiconductor channel layer having a first crystal orientation; a second semiconductor channel layer having a second crystal orientation; and a bonding structure located between the first semiconductor channel layer and the second semiconductor channel layer; forming a sacrificial gate structure above the fin structure; etching the fin structure on opposite sides of the fin structure; forming a first source / drain region in contact with the first semiconductor channel layer; depositing a first contact etch stop layer (CESL) above the first source / drain region; depositing a first interlayer dielectric (ILD) layer on the first contact etch stop layer; forming a second source / drain region in contact with the second semiconductor channel layer; depositing a second contact etch stop layer above the second source / drain region; and depositing a second interlayer dielectric layer on the second contact etch stop layer.

[0006] Some other embodiments of the present application provide a semiconductor device, including: a first channel layer; a first gate dielectric layer surrounding the first channel layer; a first gate electrode layer disposed on the first gate dielectric layer; a first source / drain region in contact with the first channel layer; a second channel layer disposed below the first channel layer and aligned with the first channel layer; a second gate dielectric layer surrounding the second channel layer; a second gate electrode layer disposed on the second gate dielectric layer; a second source / drain region in contact with the second channel layer; and a bonding structure disposed between the first channel layer and the second channel layer and aligned with the first channel layer and the second channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0009] FIG. 2A to FIG. 2B , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4E , FIG. 5A to FIG. 5B to FIG. 10A to FIG. 10B and FIG. 11A to FIG. 11C Semiconductor devices during various stages of fabrication according to some embodiments of the present disclosure are schematically illustrated.

[0010] FIG. 12A to FIG. 12B and FIG. 13A to FIG. 13BA semiconductor device according to another embodiment of the present disclosure is schematically shown.

[0011] FIG. 14A to FIG. 14B and Figures 15 to 18 A semiconductor device according to another embodiment of the present disclosure is schematically illustrated. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "over," "top," "upper," and the like may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] Although embodiments of the present disclosure are discussed with respect to nanosheet channel FETs, implementations of some aspects of embodiments of the present disclosure may be used in other processes and / or other devices, such as planar FETs, fin FETs, horizontal all-around gate (HGAA) FETs, vertical all-around gate (VGAA) FETs, and other suitable devices. A person of ordinary skill in the art will readily appreciate other modifications that may be considered within the scope of the embodiments of the present disclosure. In the case of a all-around gate (GAA) transistor structure, the GAA transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

[0015] Embodiments of the present disclosure provide a semiconductor device structure with vertically stacked complementary field effect transistors (CFETs). Each CFET is formed by vertically stacking a first nanosheet FET (e.g., an n-channel FET) on a second nanosheet FET (e.g., a p-channel FET). The first nanosheet FET is formed by a first channel stack including one or more first semiconductor channel layers separated from a sacrificial semiconductor layer. The second nanosheet FET is formed by a second channel stack including one or more second semiconductor channel layers separated from a sacrificial semiconductor layer. In some embodiments, the first channel stack and the second channel stack are epitaxially grown from two different substrates. A bonding layer may be deposited above the first channel stack and the second channel stack. The two substrates are bonded using wafer bonding technology. A bonding structure is formed by a bonding layer. The first channel stack and the second channel stack are stacked together and separated by a bonding structure. The bonding structure and the channel stack form a combined complementary FET (cCFET). By applying wafer bonding technology in the CFET integration process, the embodiments of the present disclosure provide the flexibility of selecting different N / P channel characteristics, provide a simple way to form N / P channel isolation structures, and reduce potential leakage paths and defects in stacked CFETs.

[0016] Figure 1 is a schematic flow chart of a method 100 for manufacturing a semiconductor device according to an embodiment of the present disclosure. In particular, the method 100 uses a substrate bonding technique to form a channel stack for a vertically stacked CFET.

[0017] FIG. 2A to FIG. 2B , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4E , FIG. 5A to FIG. 5B to FIG. 10A to FIG. 10B and FIG. 11A to FIG. 11C The semiconductor device 200 is schematically shown during various stages of manufacture according to some embodiments of the present disclosure. The semiconductor device 200 can be formed using the method 100. It should be understood that the semiconductor device 200 can be formed using the method 100. FIG. 2A to FIG. 2B , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4E , FIG. 5A to FIG. 5B to FIG. 10A to FIG. 10B and FIG. 11A to FIG. 11C Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the present disclosure. The order of operations / processes is not limiting and may be interchanged. Semiconductor device 200 includes a stacked CFET having a top device stacked above a bottom device. The top device and the corresponding bottom device may be complementary field effect transistors with aligned channels.

[0018] In operation 102, a first channel stack 204a for a bottom device of the semiconductor device 200 is deposited on a first substrate 202a, such as Figure 2A As shown in FIG. 1 , a second channel stack 204 b for a top device of the semiconductor device 200 is deposited on the second substrate 202 b, as shown in FIG. Figure 2B as shown in . Figure 2A and Figure 2B 2 are cross-sectional views of the first substrate 202a and the second substrate 202b, respectively.

[0019] like Figure 2A As shown in , the first channel stack 204a is formed above the first substrate 202a. The first substrate 202a can be a semiconductor substrate configured to have a semiconductor device formed thereon. The first substrate 202a may include a single crystal semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In some embodiments, the first substrate 202a is made of silicon. In some embodiments, the first substrate 202a is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer. In some embodiments, the first substrate 202a may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, boron for an n-type field effect transistor (NFET) and phosphorus for a p-type field effect transistor (PFET).

[0020] The first channel stack 204a includes semiconductor layers made of different materials to facilitate the formation of nanosheet channels in multi-gate devices, such as nanosheet channel FETs. In some embodiments, the channel stack 204a includes a first semiconductor layer 206a and a second semiconductor layer 208a. The first semiconductor layer 206a and the second semiconductor layer 208a are arranged alternately. The first semiconductor layer 206a and the second semiconductor layer 208a are made of semiconductor materials with different etching selectivities and / or oxidation rates. In some embodiments, the first semiconductor layer 206a can be made of Si, and the second semiconductor layer 208a can be made of SiGe. Optionally, in some embodiments, any one of the semiconductor layers 206a, 208a can be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0021] The first semiconductor layer 206a or their portions may form nanosheet channels of the semiconductor device 200 in a later manufacturing stage. The term nanosheet is used herein to refer to any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions of circular and substantially circular cross-sections, as well as beam-shaped or strip-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanosheet channels of the semiconductor device 200 may be surrounded by a gate electrode. The semiconductor device 200 may include a nanosheet transistor. A nanosheet transistor may refer to a nanowire transistor, a full-ring gate (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 206a to define one or more channels of the semiconductor device 200 is further discussed below.

[0022] The first semiconductor layer 206a and the second semiconductor layer 208a are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the channel stack 204a can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0023] As discussed, the semiconductor device 200 to be formed includes a complementary FET (CFET), in which two or more nanosheet FETs are stacked vertically on top of each other. In some embodiments, the first semiconductor layer 206a can define a channel of a first FET, such as an n-type FET (N-FET). Alternatively, the first semiconductor layer 206a can define a channel of a p-type FET (P-FET). The thickness of the first semiconductor layer 206a is selected based on device performance considerations. In some embodiments, each of the first semiconductor layers 206a has a thickness ranging from about 3 nanometers (nm) to about 10nm. The second semiconductor layer 208a can be eventually removed and used to define a spacing for a gate stack to be formed therein. Each of the second semiconductor layers 208a can have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 206a, depending on device performance considerations. In some embodiments, each of the second semiconductor layers 208a has a thickness equal to the thickness of the first semiconductor layer 206a.

[0024] like Figure 2A As shown in FIG, the first channel stack 204a starts with a bottommost second semiconductor layer 208ba and ends with a topmost second semiconductor layer 208ta. The bottommost second semiconductor layer 208ba grows from the top surface 202ta of the first substrate 202a.

[0025] Although the two first semiconductor layers 206a and the three second semiconductor layers 208a are arranged alternately, as shown in FIG. Figure 2A , but it is understood that any number of first semiconductor layers 206 a and second semiconductor layers 208 a may be formed in the first channel stack 204 a , depending on the predetermined number of nanosheet channels required for each FET of the semiconductor device 200 .

[0026] After forming the first channel stack 204a, a bonding layer 210a is deposited over the top second semiconductor layer 208ta of the first channel stack 204a. The bonding layer 210a may include one or more suitable material layers to bond with the second channel stack 204b deposited on the substrate 202b and provide isolation between the first channel stack 204a and the second channel stack 204b. In some embodiments, the bonding layer 210a includes one or more dielectric layers. For example, the bonding layer 210a may include silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxide, silicon nitride, high-k dielectric materials such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), compounds thereof, composites thereof, combinations thereof, etc. The bonding layer 210a may be formed by a suitable deposition method, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), spin coating, etc.

[0027] like Figure 2B As shown in , a second channel stack 204b is formed over a second substrate 202b. The second substrate 202b may be a semiconductor substrate. The second substrate 202b may be formed of a material similar to the first substrate 202a. In some embodiments, the first substrate 202a may have a first crystal orientation, and the second substrate 202b may have a second crystal orientation. The first crystal orientation and the second crystal orientation may be different. As discussed below, the crystal orientations of the first substrate 202a and the second substrate 202b may be selected to achieve optimized mobility in a subsequently formed channel.

[0028] The second channel stack 204b includes semiconductor layers made of different materials to facilitate the formation of nanosheet channels in multi-gate devices, such as nanosheet channel FETs. In some embodiments, the second channel stack 204b includes a third semiconductor layer 206b and a fourth semiconductor layer 208b. The third semiconductor layer 206b and the fourth semiconductor layer 208b are arranged alternately. The third semiconductor layer 206b and the fourth semiconductor layer 208b are made of semiconductor materials having different etching selectivities and / or oxidation rates. In some embodiments, the third semiconductor layer 206b can be made of silicon, Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, and the fourth semiconductor layer 208b can be made of SiGe. In some embodiments, the second semiconductor layer 208a and the fourth semiconductor layer 208b can have similar compositions.

[0029] The third semiconductor layer 206b, or portions thereof, may form nanosheet channels of the semiconductor device 200 at a later stage of fabrication. The use of the third semiconductor layer 206b to define one or more channels of the semiconductor device 200 is discussed further below.

[0030] The third semiconductor layer 206b and the fourth semiconductor layer 208b are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the channel stack 204b can be implemented by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0031] As discussed above, the semiconductor device 200 to be formed includes a complementary FET (CFET), in which two or more nanosheet FETs are stacked vertically on top of each other. In some embodiments, the third semiconductor layer 206b can define a channel of a second FET, such as a p-type FET (P-FET). Alternatively, the third semiconductor layer 206b can define a channel of an n-type FET (N-FET). The thickness of the third semiconductor layer 206b is selected based on device performance considerations. In some embodiments, each of the third semiconductor layers 206b has a thickness ranging from about 3 nanometers (nm) to about 10nm. The fourth semiconductor layer 208b can be eventually removed and used to define the spacing for the gate stack to be formed therein. Each of the fourth semiconductor layers 208b can have a thickness equal to, less than, or greater than the thickness of the third semiconductor layer 206b, depending on device performance considerations. In some embodiments, each of the fourth semiconductor layers 208b has a thickness equal to the thickness of the third semiconductor layer 206b.

[0032] like Figure 2BAs shown in , the second channel stack 204b starts with the bottommost fourth semiconductor layer 208bb and ends with the topmost fourth semiconductor layer 208tb. The bottommost fourth semiconductor layer 208bb grows from the top surface 202tb of the second substrate 202b. As discussed below, unlike the other fourth semiconductor layers 208b used as sacrificial layers to define the spacing between the channels, the bottommost fourth semiconductor layer 208bb is used as an etch stop layer during subsequent processes, and the thickness of the bottommost fourth semiconductor layer 208bb is different from that of the other fourth semiconductor layers 208b. For example, the bottommost fourth semiconductor layer 208bb is thicker than the other fourth semiconductor layers 208b. In some embodiments, the bottommost fourth semiconductor layer 208bb has a thickness ranging between about 10nm and about 20nm.

[0033] Although the two third semiconductor layers 206b and the three fourth semiconductor layers 208b are arranged alternately, as shown in FIG. Figure 2B , but it is understood that any number of third semiconductor layers 206 b and fourth semiconductor layers 208 b may be formed in the second channel stack 204 b , depending on the predetermined number of nanosheet channels required for each FET of the semiconductor device 200 .

[0034] After forming the second channel stack 204b, a bonding layer 210b is deposited above the topmost fourth semiconductor layer 208tb of the second channel stack 204b. The bonding layer 210b is configured to bond with the first substrate 202a via the bonding layer 210a. Similar to the bonding layer 210a, the bonding layer 210b may include one or more suitable material layers to bond with the first bonding layer 210a and provide isolation between the first channel stack 204a and the second channel stack 204b. In some embodiments, the bonding layer 210b includes one or more dielectric layers. For example, the bonding layer 210b may include silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxide, silicon nitride, high-k dielectric materials such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), compounds thereof, composite materials thereof, combinations thereof, etc. The bonding layer 210b may be formed by a suitable deposition method, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), spin coating, etc.

[0035] In some embodiments, the bonding layers 210a, 210b may be symmetrically formed of the same material and substantially the same thickness. In other embodiments, the bonding layers 210a, 210b may be asymmetrically formed of different materials and / or different thicknesses to achieve desired performance or processing efficiency.

[0036] As discussed above, the first semiconductor layer 206a and the second semiconductor layer 208a are formed by epitaxial growth from the top surface 202ta of the first substrate 202a. Therefore, the semiconductor layers 206a, 208a have the same crystal orientation as the first substrate 202a. Similarly, the semiconductor layers 206b, 208b have the same crystal orientation as the second substrate 202b. Because at least a portion of the semiconductor layers 206a, 206b eventually becomes a channel in a subsequently formed FET, the crystal orientation of the channel region can be selected to have an optimized mobility for the corresponding FET. For example, in silicon, electrons have the maximum mobility in the {100} plane family, while holes have the maximum mobility in the {110} plane family. Because N-FETs use electrons as carriers, N-FETs can be manufactured on substrates with a (100) top surface to achieve maximum mobility. Because P-FETs use holes as carriers, P-FETs can be manufactured on substrates with a (110) top surface to achieve maximum mobility.

[0037] In some embodiments, the first substrate 202a and the second substrate 202b are selected to achieve maximum mobility for the corresponding FET to be formed thereon. In particular, the first substrate 202a and the second substrate 202b are selected to have different crystal orientations so that the mobility of both the N-FET and the P-FET can be adjusted or optimized according to the circuit design. In some embodiments, the first substrate 202a has a first crystal orientation and the second substrate 202b has a second crystal orientation. The first crystal orientation is selected to achieve the desired mobility in the channel for the first type of device (such as an N-FET or a P-FET). The second crystal orientation is selected to achieve the desired mobility in the channel for the second type of device (such as a P-FET or an N-FET). In some embodiments, the top surface 202ta of the first substrate 202a is located on the (100) plane. The top surface 202tb of the second substrate 202b is located on the (110) plane.

[0038] In operation 104, the first substrate 202a and the second substrate 202b are bonded together. Figure 3A as shown in . Figure 3A is a schematic cross-sectional view of the semiconductor device 200. The first substrate 202a and the second substrate 202b may be bonded by stitching the bonding layers 210a, 210b together using a suitable substrate bonding technique.

[0039] In some embodiments, the first substrate 202a and the second substrate 202b can be bonded using a direct bonding process, such as dielectric to dielectric bonding. In some embodiments, surface cleaning is performed to remove particles, contaminants, and native oxides from the surfaces of the first substrate 202a and the second substrate 202b. The surface cleaning process may include one or more cleaning methods, such as low temperature cleaning, mechanical wiping and scrubbing, etching in gas, plasma or liquid, ultrasonic and megasonic cleaning, laser cleaning, etc.

[0040] In some embodiments, before performing the bonding operation, the first substrate 202a and the second substrate 202b may be positioned relative to each other such that the intended channel orientations in the first channel stack 204a and the second channel stack 204b are aligned with each other.

[0041] Subsequently, the bonding layer 210a of the first substrate 202a and the bonding layer 210b of the second substrate 202b are placed in physical contact under appropriate bonding pressure and temperature to form a bonding structure 212 therebetween. The first channel stack 204a, the bonding structure 212 and the second channel stack 204b form a complementary channel stack 214.

[0042] In some embodiments, an optional anneal may be performed to enhance the bonding strength in the bonding structure 212 between the first substrate 202a and the second substrate 202b. In some embodiments, the anneal may be performed at a temperature between about 250°C and about 400°C for a time period between about 0.5 hours and about 4 hours.

[0043] The junction structure 212 has a top surface 212t in contact with the topmost fourth semiconductor layer 208b and a bottom surface 212b in contact with the topmost second semiconductor layer 208a. In some embodiments, the junction structure 212 may have a thickness T1 ranging between about 5nm and about 30nm from the top surface 212t to the bottom surface 212b. If the junction structure 212 is thicker than 30nm, the complementary channel stack 214 may be too high, thereby producing a high aspect ratio in the following etching process. If the junction structure 212 is thinner than 5nm, it may be difficult to control the thickness of the junction structure 212, or the thickness of the subsequent dielectric layer between the source / drain regions, so that the source / drain structures of the top device and the bottom device are merged.

[0044] In operation 106, a thinning process is performed to remove the second substrate 202b, such as Figure 3B as shown in . Figure 3B2 is a schematic cross-sectional view of the semiconductor device 200. In some embodiments, the thinning process may be performed by a backside grinding process and a subsequent etching process to selectively remove the second substrate 202b from the complementary channel stack 214. During the etching of the second substrate 202b, the bottom fourth semiconductor layer 208bb is used as an etching stop layer. After removing the second substrate 202b, a subsequent etching process is performed to remove the bottom fourth semiconductor layer 208bb so that the third semiconductor layer 206b is exposed, as shown in FIG. Figure 3B as shown in .

[0045] In operation 108, a fin structure 216 is formed from the channel stack 204, such as FIG. 4A to FIG. 4B as shown in . FIG. 4A to FIG. 4B is a cross-sectional view of the semiconductor device 200 after operation 108 . Figure 4A is along Figure 4B Schematic cross-sectional view along line 4A-4A in FIG. Figure 4B is along Figure 4A Schematic cross-sectional view of line 4B-4B in FIG. Each fin structure 216 has an upper portion including a complementary channel stack 214 and a well portion 218 formed by substrate 202a.

[0046] The fin structure 216 can be manufactured using a suitable process including a double patterning or multiple patterning process. Typically, the double patterning or multiple patterning process combines lithography and self-alignment processes, allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and then the remaining spacers or mandrels can be used to pattern the fin structure 216 by etching the complementary channel stack 214 and the substrate 202a. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0047] The fin structure 216 is formed along the direction of the channel so that part of the fin structure 216 becomes the channel of the subsequently formed FET. As discussed above, because the first channel stack 204a and the second channel stack 204b are epitaxially grown from different substrates 202a, 202b, the semiconductor layers in the channel stacks 204a, 204b can have the same or different crystal orientations. Therefore, by selecting different crystal orientations of the substrates 202a, 202b, the crystal orientation in the channel of the N-FET and the crystal orientation in the channel of the P-FET can have various combinations. In addition, the alignment between the first channel stack 204a and the second channel stack 204b can be adjusted to have various combinations of channel directions.

[0048] Figure 4C and Figure 4D is along Figure 4A Schematic cross-sectional view of the line 4C-4C and the line 4D-4D in FIG. Figure 4C and Figure 4D Schematically illustrates an exemplary crystal orientation and channel direction of a stacked CFET in a semiconductor device 200. The channel in the bottom FET is formed in the first semiconductor layer 206a along the fin structure 216. The channel in the top FET is formed in the third semiconductor layer 206b along the fin structure 216. In some embodiments, the bottom FET is an N-FET and the top FET is a P-FET. In some embodiments, the channel of the bottom FET (N-FET) is formed by the semiconductor layer 206a grown from the (100) plane, and the sidewalls of the fin structure 216 are cut along the (110) plane so that the channel is formed along the (110) plane. <110> direction to achieve maximum mobility, such as Figure 4C In some embodiments, the channel of the top FET (P-FET) is formed by the semiconductor layer 206b grown from the (100) plane, and the sidewall of the fin structure 216 is cut along the (100) plane so that the channel is <100> Direction formation, such as Figure 4D You can choose Figure 4D , to realize an N-FET nanosheet. Alternatively, the channel direction may be selected to realize a P-FET nanosheet. For example, according to another embodiment of the present disclosure, for the semiconductor device 200a, the channel of the P-FET may be formed by the semiconductor layer 206 grown from the (110) plane, and the sidewall of the fin structure 216 is cut along the (100) plane so that the channel is along the (110) plane. <110> Direction formation, such as Figure 4E as shown in .

[0049] Alternatively, the top FET may be an N-FET and the bottom FET may be a P-FET, and the channel directions may be selected differently. In some embodiments, the channel directions may be selected in other combinations to achieve different design objectives.

[0050] In operation 110, an isolation region 220 and a sacrificial gate structure 222 are formed over the fin structure 216, as shown in FIG. FIG. 5A to FIG. 5B as shown in . FIG. 5A to FIG. 5B is a cross-sectional view of the semiconductor device 200 after operation 110 . Figure 5A is along Figure 5B Schematic cross-sectional view along line 5A-5A in FIG. Figure 5B is along Figure 5ASchematic cross-sectional view of line 5B-5B in FIG. An insulating material may be deposited over substrate 202 a to fill the trenches between fin structures 216 . The insulating material may be made of: an oxygen-containing material, such as silicon oxide or fluorine-doped silicate glass (FSG); a nitrogen-containing material, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; a low-k dielectric material; or any suitable dielectric material. The insulating material may be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0051] A planarization operation, such as a chemical mechanical polishing (CMP) process and / or an etch back process, is performed to expose the top of the fin structure 216 from the insulating material. The insulating material may be recessed by removing portions of the insulating material between adjacent fin structures 216 to form isolation regions 220, which may be shallow trench isolations (STIs).

[0052] Sacrificial gate structures 222 are formed over portions of the fin structures 216. Each sacrificial gate structure 222 may include a sacrificial gate dielectric layer 224, a sacrificial gate electrode layer 226, and a mask layer 228. The sacrificial gate dielectric layer 224, the sacrificial gate electrode layer 226, and the mask layer 228 may be formed by sequentially depositing blanket layers of the sacrificial gate dielectric layer 224, the sacrificial gate electrode layer 226, and the mask layer 228, and subsequent patterning and etching processes. For example, the patterning process includes a photolithography process (e.g., photolithography or electron beam lithography), and the photolithography process may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof.

[0053] In operation 112, sidewall spacers 230 are formed on the sidewalls of the sacrificial gate structure 222, such as FIG. 6A to FIG. 6B as shown in . FIG. 6A to FIG. 6B is a cross-sectional view of the semiconductor device 200 . Fig. 6A is along Figure 6B Schematic cross-sectional view along line 6A-6A in FIG. Figure 6B is along Fig. 6A6B-6B in FIG. 6B-6B. The sidewall spacers 230 may be formed by first depositing and then etching back to form a conformal layer of the sidewall spacers 230. For example, the spacer material layer may be conformally disposed on an exposed surface of the semiconductor device 200. The conformal spacer material layer may be formed by an ALD process. Subsequently, an anisotropic etching of the spacer material layer is performed using, for example, RIE. During the anisotropic etching process, a majority of the spacer material layer is removed from horizontal surfaces (such as the top of the fin structure 216), leaving the sidewall spacers 230 on vertical surfaces (such as the sidewalls of the sacrificial gate structure 222). The sidewall spacers 230 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0054] By patterning the sacrificial gate structure 222, the complementary channel stack 214 of the fin structure 216 is partially exposed on opposite sides of the sacrificial gate structure 222 and the sidewall spacers 230. The portion of the fin structure 216 covered by the sacrificial gate structure 222 and the sidewall spacers 230 serves as a channel region for the semiconductor device 200.

[0055] In operation 114, the fin structure 216 partially exposed on opposite sides of the sacrificial gate structure 222 and the sidewall spacer 230 is recessed to form source / drain recesses 232, such as FIG. 6A to FIG. 6B As shown in . The exposed portion of the fin structure 216 is selectively recessed by using one or more suitable etching processes, such as dry etching, wet etching, or a combination thereof. In some embodiments, the exposed portion of the complementary channel stack 214 of the fin structure 216 is removed, thereby exposing a portion of the well portion 218. Fig. 6A As shown in , the exposed portion of the fin structure 216 is recessed to a level at or below a top surface of the isolation region 220 . The recessing process may include an etching process that recesses the exposed portion of the fin structure 216 .

[0056] In operation 116, an internal spacer 234 is formed, such as FIG. 7A to FIG. 7B as shown in . FIG. 7A to FIG. 7B is a cross-sectional view of semiconductor device 200 after operation 116 . Fig. 7A is along Figure 7B Schematic cross-sectional view along line 7A-7A in FIG. Figure 7B is along Fig. 7ASchematic cross-sectional view of line 7B-7B in FIG. The edge portions of the second semiconductor layer 208a and the fourth semiconductor layer 208b of the channel stack 214 are horizontally removed along the X direction. The removal of the edge portions of the second semiconductor layer 208a and the fourth semiconductor layer 208b forms a cavity in the fin structure 216 below the sidewall spacer 230. In some embodiments, portions of the second semiconductor layer 208a and the fourth semiconductor layer 208b are removed by a selective wet etching process. In some embodiments, a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution may be used to remove portions of the second semiconductor layer 208a and the fourth semiconductor layer 208b. Alternatively, a dry etching process may be used. In some embodiments, dry etching using chlorine and / or fluorine-based chemicals may be used to remove edge portions of the fourth semiconductor layer 208b. During the etching process, the second semiconductor layer 208a and the fourth semiconductor layer 208b have a high etching selectivity relative to the dielectric material in the bonding structure 212.

[0057] After removing the edge portions of the second semiconductor layer 208a and the fourth semiconductor layer 208b, a dielectric layer is filled in the cavity to form an inner spacer 234. The inner spacer 234 may be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The inner spacer 234 may be formed by first forming a conformal dielectric layer using a conformal deposition process such as ALD, and then etching to remove portions of the conformal dielectric layer except for the inner spacer 234. The etching process may be primarily isotropic etching or a combination of isotropic etching and anisotropic etching to remove dielectric layers deposited on the sidewalls and the bottom, respectively.

[0058] An inner spacer 234b is formed on an end of the topmost fourth semiconductor layer 208tb. An inner spacer 234a is formed on an end of the topmost second semiconductor layer 208ta. The inner spacers 234b, 234a contact the bonding structure 210 at the top surface 212t and the bottom surface 212b, respectively.

[0059] In operation 118, a first source / drain region 236 and a second source / drain region 244 are formed in the source / drain recess 232, such as FIG. 8A to FIG. 8B as shown in . FIG. 8A to FIG. 8B is a cross-sectional view of the semiconductor device 200 after operation 118 . Fig. 8A is along Figure 8B Schematic cross-sectional view along line 8A-8A in FIG. Figure 8B is along Fig. 8ASchematic cross-sectional view of line 8B-8B in FIG. The first source / drain region 236 is an epitaxial feature grown from the well portion 218 of the fin structure 216 and the exposed semiconductor surface of the first semiconductor layer 206a.

[0060] The first source / drain region 236 may include one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or Si, SiGe, and Ge for p-channel FETs. In some embodiments, the first source / drain region 236 includes one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs. The first source / drain region 236 may be formed from the first semiconductor layer 206a. The first source / drain region 236 may be grown vertically and horizontally to form a facet, which may correspond to a crystal plane of a material for the first semiconductor layer 206a. The first source / drain region 236 may be formed by an epitaxial growth method using CVD, ALD, or MBE.

[0061] The source / drain region 236 is formed in the lower portion of the source / drain recess 232. The upper surface 241 of the source / drain region 236 is positioned above the topmost first semiconductor layer 206a. In some embodiments, the upper surface 241 is positioned within the inner spacer 234a. The dielectric bonding structure 212 disposed between the first channel stack 204a and the second channel stack 204b increases the positioning window of the source / drain region 236, for example, the upper surface 241 can be positioned above the topmost first semiconductor layer 206a and below the top surface 212t of the bonding structure 212 without causing leakage between the first source / drain region 236 and the FET to be formed on the bonding structure 212.

[0062] A first contact etch stop layer (CESL) 238 and a first interlayer dielectric (ILD) layer 240 are formed over the first source / drain region 236. The first CESL 238 may be conformally formed on the exposed surface of the semiconductor device 200. The first CESL 238 covers the first source / drain region 236, the sidewall spacer 230, the isolation region 220, and the exposed surface of the channel stack 204. The first CESL 238 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbide, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, the first ILD layer 240 is formed on the first CESL 238 over the semiconductor device 200. The material for the first ILD layer 240 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials including Si, O, C, and / or H. The first ILD layer 240 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the first ILD layer 240, the semiconductor device 200 may be subjected to a thermal process to anneal the first ILD layer 240.

[0063] In some embodiments, the etch-back process may be performed such that the top surface 242 of the first CESL 238 and the first ILD layer 240 is located below the topmost third semiconductor layer 206 b, such that the third semiconductor layer 206 b is exposed to the source / drain recess 232. In some embodiments, the top surface 242 is positioned within the inner spacer 234 b. The dielectric bonding structure 212 disposed between the first channel stack 204 a and the second channel stack 204 b increases a positioning window for the top surface 242, for example, the top surface 242 may be positioned above the bottom surface 212 b of the bonding structure 212 and below the third semiconductor layer 206 b without causing leakage between FETs to be formed above and below the bonding structure 212.

[0064] The second source / drain region 244 is formed in the source / drain groove 232. The second source / drain region 244 is an epitaxial component grown from the exposed semiconductor surface of the third semiconductor layer 206b. The second source / drain region 244 may include one or more layers of Si, SiGe, Ge for p-channel FET or Si, SiP, SiC and SiCP for n-channel FET. In some embodiments, the second source / drain region 244 includes one or more layers of Si, SiGe, Ge for p-channel FET. The second source / drain region 244 can be grown from the third semiconductor layer 206b. The second source / drain region 244 can grow vertically and horizontally to form a small facet, which can correspond to the crystal plane of the material for the third semiconductor layer 206b. The second source / drain region 244 can be formed by using an epitaxial growth method using CVD, ALD or MBE.

[0065] A second CESL 246 and a second ILD layer 248 are formed over the second source / drain regions 244. The second CESL 246 may be conformally formed on the exposed surface of the semiconductor device 200. The second CESL 246 covers the second source / drain regions 244, the sidewall spacers 230, and the first ILD layer 240. The second CESL 246 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbide, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a second ILD layer 248 is formed on the second CESL 246 over the semiconductor device 200. The material for the second ILD layer 248 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials including Si, O, C, and / or H. The second ILD layer 248 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the second ILD layer 248, the semiconductor device 200 may be subjected to a thermal process to anneal the second ILD layer 248.

[0066] After forming the second ILD layer 248 , a planarization operation, such as CMP, is performed on the semiconductor device 200 to remove a portion of the second ILD layer 248 , exposing the second CESL 246 and the sacrificial gate electrode layer 226 .

[0067] In operation 120, the sacrificial gate structure 222 and the semiconductor layers 208a, 208b are removed. FIG. 9A to FIG. 9B as shown in . FIG. 9A to FIG. 9Bis a cross-sectional view of the semiconductor device 200 after operation 120 . Fig.9A is along Fig. 9B Schematic cross-sectional view along line 9A-9A in FIG. Fig. 9B is along Fig.9A Schematic cross-sectional view of line 9A-9A in FIG. The removal of the sacrificial gate structure 222 forms a gate recess 250 between the sidewall spacers 230 and exposes a portion of the complementary channel stack 214 located below the sacrificial gate structure 222. The sacrificial semiconductor layers 208a, 208b may then be selectively removed to expose the first semiconductor layer 206a and the third semiconductor layer 206b.

[0068] During the removal of the sacrificial gate structure 222, the second ILD layer 248 and the second CESL 246 protect the second source / drain region 244 and the first source / drain region 236. The sacrificial gate structure 222 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 226 can be removed first by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 224, which can also be implemented by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 226, but the sidewall spacers 230, the inner spacers 234, the bonding structure 212, and the second ILD layer 248, the second CESL 246, and the isolation region 220 are not removed.

[0069] The second semiconductor layer 208a and the fourth semiconductor layer 208b are then selectively removed through the gate recess 250. The removal of the semiconductor layers 208a, 208b exposes the inner spacer 234, the semiconductor layers 206a, 206b, and the bonding structure 212 to the gate recess 250. The removal process may be any suitable etching process, such as dry etching, wet etching, or a combination thereof. The etching process may be a selective etching process that removes the semiconductor layers 208a, 208b, but does not remove the sidewall spacers 230, the second CESL 246, the second ILD layer 248, the inner spacer 234, the bonding structure 212, the isolation region 220, and the first semiconductor layer 206.

[0070] In operation 122, a first replacement gate structure 252 and a second replacement gate structure 258 are formed around the first semiconductor layer 206a and the second semiconductor layer 206b, respectively. FIG. 10A to FIG. 10B as shown in . FIG. 10A to FIG. 10B is a cross-sectional view of the semiconductor device 200 after operation 122 . Fig. 10A is along Fig. 10B Schematic cross-sectional view along line 10A-10A in FIG. Fig. 10Bis along Fig. 10A Schematic cross-sectional view along line 10B-10B in FIG.

[0071] The first replacement gate structure 252 includes a first gate dielectric layer 254 formed around the first semiconductor layer 206a and a first gate electrode layer 256 deposited over the first gate dielectric layer 254. The first replacement gate structure 252, the first semiconductor layer 206a, and the first source / drain region 236 form a first transistor 251. The first semiconductor layer 206a is connected between the first source / drain region 236 and serves as a nanosheet channel of the first transistor 251.

[0072] A second replacement gate structure 258 is formed around the third semiconductor layer 206 b. The second replacement gate structure 258 includes a second gate dielectric layer 260 formed around the third semiconductor layer 206 b and a second gate electrode layer 262 deposited over the second gate dielectric layer 260. The second replacement gate structure 258, the third semiconductor layer 206 b, and the second source / drain region 244 form a second transistor 257. The third semiconductor layer 206 b is connected between the second source / drain region 244 and serves as a nanosheet channel of the second transistor 257.

[0073] In some embodiments, the first gate dielectric layer 254 and the second gate dielectric layer 260 are formed simultaneously. The first gate dielectric layer 254 is deposited on the exposed surface of the first semiconductor layer 206a. The second gate dielectric layer 260 is deposited on the exposed surface of the third semiconductor layer 206b. The first gate dielectric layer 254 and the second gate dielectric layer 260 may include the same material as the sacrificial gate dielectric layer 224. In some embodiments, the first gate dielectric layer 254 and the second gate dielectric layer 260 may include a high-k dielectric material. In some embodiments, the first gate dielectric layer 254 and the second gate dielectric layer 260 may be formed by a conformal process. In some embodiments, an oxygen-containing layer or an interfacial layer (not shown) may be formed between the first gate dielectric layer 254 and the first semiconductor layer 206a and between the second gate dielectric layer 260 and the second semiconductor layer 206b, respectively. The oxygen-containing layer, the first gate dielectric layer 254 and the second gate dielectric layer 260 may be formed by any suitable process, such as an ALD process.

[0074] Then, a first gate electrode layer 256 is formed in the gate recess 250 and on the first gate dielectric layer 254. The first gate electrode layer 256 is formed on the first gate dielectric layer 254 to surround the first semiconductor layer 206a. The first gate electrode layer 256 includes one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The first gate electrode layer 256 can be formed by PVD, CVD, ALD, electroplating or other suitable methods. In some embodiments, the first gate electrode layer 256 includes an n-type gate electrode layer, such as TiAlC, TaAlC, TiSiAlC, TiC, TaSiAlC or other suitable materials, and the first gate electrode layer 256 is a gate electrode layer of an NFET.

[0075] In some embodiments, an etch-back process is performed after depositing the first gate electrode layer 256 so that the first replacement gate structure 252 remains at the lower portion of the gate recess 250. In some embodiments, a planarization process, such as a CMP process, may be performed before the etch-back process. In some embodiments, a top surface 252t of the replacement gate structure 252 contacts the bonding structure 212, i.e., the top surface 252t is positioned between the top surface 212t and the bottom surface 212b of the bonding structure 212. The bonding structure 212 prevents leakage between the first replacement gate structure 252 and the second source / drain region 244.

[0076] The second gate electrode layer 262 is formed in the gate groove 250 and on the second gate dielectric layer 260. The second gate electrode layer 262 is formed on the second gate dielectric layer 260 to surround the third semiconductor layer 206b. The second gate electrode layer 262 includes one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The second gate electrode layer 262 can be formed by PVD, CVD, ALD, electroplating or other suitable methods. In some embodiments, the second gate electrode layer 262 includes a p-type gate electrode layer, such as TiN, TaN, TiTaN, TiAlN, WCN, W, Ni, Co or other suitable materials, and the second gate electrode layer 262 is a gate electrode layer of a PFET.

[0077] After depositing the gate electrode layer 262, an etch-back process may be performed to etch the second gate electrode layer 262 and the second gate dielectric layer 260 under the sidewall spacers 230. A self-aligned contact etch layer 264 is deposited over the gate electrode layer 262 for subsequent formation of contact features.

[0078] The first transistor 251 and the second transistor 257 may have different threshold voltages, and a control voltage may be applied together to the gate electrode layers 256 , 262 .

[0079] In operation 124, contact features 268 are formed, such as FIG. 11A to FIG. 11C as shown in . FIG. 11A to FIG. 11C is a cross-sectional view of the semiconductor device 200 after operation 124 . Fig.11A is along Fig. 11B Schematic cross-sectional view along line 11A-11A in FIG. Fig. 11B is along Fig.11A Schematic cross-sectional view along line 11B-11B in FIG. Fig. 11C is along Fig. 11B Schematic cross-sectional view along line 11C-11C in FIG.

[0080] like FIG. 11A to FIG. 11C As shown in , source / drain contact features 268 and gate contact features (not shown) may be formed to be connected to the source / drain regions 244 and the gate electrode layer 262, respectively. In some embodiments, a silicide layer 266 may be formed between the source / drain contact features 268 and the source / drain regions 244. The contact features 268 may be formed of a conductive material, and the conductive material may include one or more of Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN.

[0081] It should be understood that the semiconductor device 200 may undergo further complementary metal oxide semiconductor (CMOS) and / or back-end of line (BEOL) processes to form various components, such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc. The semiconductor device 200 may also include a backside contact (not shown) on the backside of the substrate 202 a by flipping the semiconductor device 200 , removing the substrate 202 a , and selectively connecting the source or drain components / terminals of the first source / drain region 236 and the gate electrode layer 256 .

[0082] The bonding layer over the first channel stack and the second channel stack may include various compositions. For example, the bonding layer may include two or more bonding dielectric layers to improve bonding strength and / or device reliability.

[0083] FIG. 12A to FIG. 12B and FIG. 13A to FIG. 13BSchematically illustrates a semiconductor device 300 according to an embodiment of the present disclosure. The semiconductor device 300 is similar to the semiconductor device 200, except that the semiconductor device 300 is formed by bonding two substrates with a composite bonding layer, such as FIG. 12A to FIG. 12B as shown in .

[0084] exist Fig. 12A and Fig. 12B In the embodiment of the present invention, a first trench stack 204a for a bottom device of a semiconductor device 300 is formed above a first substrate 202a, and a second trench stack 204b for a top device of the semiconductor device 300 is deposited on a second substrate 202b. Multilayer bonding dielectrics 310a, 310b are deposited above the trench stacks 204a, 204b, respectively. Each of the multilayer bonding dielectrics 310a, 310b may include two or more dielectric layers. In some embodiments, the multilayer bonding dielectric 310a may include a first bonding layer 311a and a top bonding layer 312a.

[0085] The first bonding layer 311a is deposited directly over the topmost second semiconductor layer 208ta of the first channel stack 204a. In some embodiments, the first bonding layer 311a may be selected from a dielectric material having a high etching selectivity relative to the second semiconductor layer 208a, so that during the subsequent removal of the second semiconductor layer 208a, the first bonding layer 311a may be used as an etching stop layer. In some embodiments, the first bonding layer 311a may be selected from silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), silicon oxide, silicon nitride, high-k materials, etc.

[0086] The top bonding layer 312a is the topmost layer of the multilayer bonding dielectric 310a. The top bonding layer 312a can be selected from dielectric materials suitable for surface treatments associated with the bonding process. In some embodiments, the top bonding layer 312a is deposited directly above the first bonding layer 311a. In some embodiments, the top bonding layer 312a can be selected from silicon oxide, silicon nitride, silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), high-k materials, etc.

[0087] In other embodiments, one or more intermediate dielectric layers may be disposed between the first bonding layer 311a and the top bonding layer 312a. For example, an intermediate dielectric layer may be deposited between the first bonding layer 311a and the top bonding layer 312a to improve adhesion therebetween.

[0088] In some embodiments, the multilayer bonding layer 310b includes the same composition as the multilayer bonding layer 310a. The multilayer bonding layer 310b includes a first bonding layer 311b and a top bonding layer 312b. The multilayer bonding layers 310a and 310b form a symmetrical bonding structure 313 in the semiconductor device 300, such as FIG. 13A to FIG. 13BThe bonding structure 313 includes first bonding layers 311a, 311b as outer layers facing the transistors 251, 257 and top bonding layers 312a, 312b bonded together as inner layers. The bonding structure 313 may have a thickness T1 ranging between about 5 nm and about 30 nm.

[0089] In some embodiments, the bonding structure 313 may include one or more intermediate dielectric layers between the first bonding layer 311a and the top bonding layer 312a or between the first bonding layer 311b and the top bonding layer 312b. In other embodiments, the multilayer bonding layer 310b may have a different composition than the multilayer bonding layer 310a, and the resulting bonding structure 313 may be asymmetric.

[0090] FIG. 14A to FIG. 14B and Figures 15 to 18 Schematically illustrates a semiconductor device 400 according to another embodiment of the present disclosure. The semiconductor device 400 is similar to the semiconductor device 200, except that the semiconductor device 400 is formed using a sacrificial semiconductor layer adjacent to the bonding layer, such as FIG. 14A to FIG. 14B as shown in .

[0091] exist Fig.14A and Fig. 14B In the embodiment, a first channel stack 204 a for a bottom device of the semiconductor device 400 is formed over a first substrate 202 a , and a second channel stack 204 b for a top device of the semiconductor device 400 is deposited on a second substrate 202 b .

[0092] A sacrificial semiconductor layer 411a is first deposited over the channel stack 204a. A bonding layer 210a or 310a is then deposited over the sacrificial semiconductor layer 411a. The sacrificial semiconductor layer 411a may serve as an etch stop layer to protect the bonding layer 210a / 310a during subsequent processing.

[0093] The sacrificial semiconductor layer 411a may include a semiconductor material having an etching selectivity relative to the semiconductor layers in the channel stacks 204a and 204b. For example, the sacrificial semiconductor layer 411 may include a semiconductor material having an etching selectivity relative to the second semiconductor layer 208a and the fourth semiconductor layer 208b. In some embodiments, the sacrificial semiconductor layer 411a may be formed of the same material as the first semiconductor layer 206a. In some embodiments, the sacrificial semiconductor layer 411a includes epitaxially formed silicon. In other embodiments, the sacrificial semiconductor layer 411a may include SiGe. For example, the sacrificial semiconductor layer 411a, the second semiconductor layer 208a, and the fourth semiconductor layer 208b all include SiGe, and the sacrificial semiconductor layer 411a has a Ge concentration different from the second semiconductor layer 208a and the fourth semiconductor layer 208b, such as a higher Ge concentration. The sacrificial semiconductor layer 411a may have a thickness in the range of about 1nm to about 2nm.

[0094] Similarly, a sacrificial semiconductor layer 411b is first deposited over the channel stack 204b. The bonding layer 210b or 310b is then deposited over the sacrificial semiconductor layer 411b. The sacrificial semiconductor layer 411b may serve as an etch stop layer to protect the bonding layer 210b / 310b during subsequent processing.

[0095] The sacrificial semiconductor layer 411b may include a semiconductor material having an etching selectivity relative to the fourth semiconductor layer 208b. In some embodiments, the sacrificial semiconductor layer 411b may be formed of the same material as the third semiconductor layer 206b. In some embodiments, the sacrificial semiconductor layer 411b includes epitaxially formed silicon or SiGe. The sacrificial semiconductor layer 411b may have a thickness in the range of about 1nm to about 2nm.

[0096] Figures 15 to 18 1 and 13 are schematic cross-sectional views of semiconductor device 400 after operations 112, 116, 126, and 132, respectively. Fig.15 As shown in FIG. 4 , a bonding structure 412 having bonding layers 210a / 310a and 210b / 310b is formed. The bonding structure 412 is sandwiched between sacrificial semiconductor layers 411a and 411b. Fig.16 As shown in FIG. 1 , when forming the inner spacer 234, portions of the sacrificial semiconductor layers 411a, 411b are removed. Therefore, the inner spacers 234a, 234b adjacent to the bonding structure 412 may have a greater thickness along the z-axis than the other inner spacers 234. Fig.17As shown in , the sacrificial semiconductor layers 411a, 411b protect the junction structure 412 by acting as an etch stop layer during the removal of the semiconductor layers 208a, 208b in operation 126. After operation 126, the additional etching process can be removed before forming the replacement gate structure. In some embodiments, the distance Ta between the topmost semiconductor layers 206a, 206b is greater than the distance Tg between adjacent semiconductor layers 206a, 206b in the semiconductor device 400, as shown in FIG. Fig.18 Zhongsuo.

[0097] Various embodiments or examples described herein provide multiple advantages over the prior art. For example, the isolation between the channels of the NFET and PFET is formed by a dielectric bond, thereby avoiding potential leakage paths through the isolation to the source / drain region. By using a bonded structure as isolation, the use of a SiGe layer with a higher concentration of Ge can be avoided, thereby avoiding defects caused by a SiGe layer with a higher Ge concentration. In addition, device performance is improved because the channel orientation of the top device and the bottom device can be independently selected.

[0098] It should be understood that not all advantages are necessarily discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0099] Some embodiments of the present disclosure provide methods, including: forming a first semiconductor stack on a first substrate; forming a second semiconductor stack on a second substrate; bonding the second substrate to the first substrate so that the second semiconductor stack is stacked above the first semiconductor stack; removing the second substrate; patterning the first semiconductor stack and the second semiconductor stack to form a fin structure; and forming a first transistor and a second transistor from the fin structure, wherein the first transistor includes a first source / drain region disposed across a portion of the first semiconductor stack, and the second transistor includes a second source / drain region disposed across a portion of the second semiconductor stack.

[0100] Some embodiments of the present disclosure provide methods, including: forming a fin structure above a first substrate, wherein the fin structure includes: a first semiconductor channel layer having a first crystal orientation; a second semiconductor channel layer having a second crystal orientation; and a bonding structure located between the first semiconductor channel layer and the second semiconductor channel layer; forming a sacrificial gate structure above the fin structure; etching the fin structure on opposite sides of the fin structure; forming a first source / drain region in contact with the first semiconductor channel layer; depositing a first CESL (contact etch stop layer) above the first source / drain region; depositing a first ILD (interlayer dielectric) layer on the first CESL; forming a second source / drain region in contact with the second semiconductor channel layer; depositing a second CESL above the second source / drain region; and depositing a second ILD layer on the second CESL.

[0101] Some embodiments of the present disclosure provide a semiconductor device, including: a first channel layer; a first gate dielectric layer surrounding the first channel layer; a first gate electrode layer disposed on the first gate dielectric layer; a first source / drain region in contact with the first channel layer; a second channel layer disposed below the first channel layer and aligned with the first channel layer; a second gate dielectric layer surrounding the second channel layer; a second gate electrode layer disposed on the second gate dielectric layer; a second source / drain region in contact with the second channel layer; and a bonding structure disposed between the first channel layer and the second channel layer and aligned with the first channel layer and the second channel layer.

[0102] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a first semiconductor stack on a first substrate; forming a second semiconductor stack on a second substrate; bonding the second substrate to the first substrate so that the second semiconductor stack is stacked above the first semiconductor stack; removing the second substrate; patterning the first semiconductor stack and the second semiconductor stack to form a fin structure; and forming a first transistor and a second transistor from the fin structure, wherein the first transistor includes a first source / drain region disposed across a portion of the first semiconductor stack, and the second transistor includes a second source / drain region disposed across a portion of the second semiconductor stack. In some embodiments, the method further comprises: depositing a first dielectric layer over the first semiconductor stack; and depositing a second dielectric layer formed over the second semiconductor stack, wherein bonding the second substrate to the first substrate comprises bonding the first dielectric layer to the second dielectric layer. In some embodiments, forming the first semiconductor stack comprises: alternately depositing two or more first semiconductor layers and two or more second semiconductor layers. In some embodiments, the method further comprises: depositing an etch stop layer on the first semiconductor stack before depositing the first dielectric layer. In some embodiments, the etch stop layer comprises a dielectric material. In some embodiments, the etch stop layer comprises a semiconductor material. In some embodiments, the first substrate has a first crystal orientation and the second substrate has a second crystal orientation different from the first crystal orientation. In some embodiments, the method further comprises: before bonding the first substrate and the second substrate, aligning the first substrate and the second substrate according to the first crystal orientation and the second crystal orientation.

[0103] Some other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a fin structure above a first substrate, wherein the fin structure includes: a first semiconductor channel layer having a first crystal orientation; a second semiconductor channel layer having a second crystal orientation; and a bonding structure located between the first semiconductor channel layer and the second semiconductor channel layer; forming a sacrificial gate structure above the fin structure; etching the fin structure on opposite sides of the fin structure; forming a first source / drain region in contact with the first semiconductor channel layer; depositing a first contact etch stop layer (CESL) above the first source / drain region; depositing a first interlayer dielectric (ILD) layer on the first contact etch stop layer; forming a second source / drain region in contact with the second semiconductor channel layer; depositing a second contact etch stop layer above the second source / drain region; and depositing a second interlayer dielectric layer on the second contact etch stop layer. In some embodiments, forming the fin structure includes: depositing the first semiconductor channel layer on the first substrate, wherein the first substrate has the first crystal orientation; depositing a first bonding layer above the first semiconductor channel layer; forming the second semiconductor channel layer on a second substrate having the second crystal orientation; depositing a second bonding layer above the second semiconductor channel layer; and bonding the first bonding layer and the second bonding layer to form the bonding structure. In some embodiments, the method further includes: aligning the first substrate and the second substrate according to the first crystal orientation and the second crystal orientation before bonding the first bonding layer and the second bonding layer. In some embodiments, the first bonding layer includes a dielectric layer. In some embodiments, the method further includes: depositing an etch stop layer above the first semiconductor channel layer, wherein the first bonding layer is deposited on the etch stop layer. In some embodiments, the etch stop layer includes a dielectric material. In some embodiments, the etch stop layer includes silicon.

[0104] Some other embodiments of the present application provide a semiconductor device, comprising: a first channel layer; a first gate dielectric layer surrounding the first channel layer; a first gate electrode layer disposed on the first gate dielectric layer; a first source / drain region in contact with the first channel layer; a second channel layer disposed below the first channel layer and aligned with the first channel layer; a second gate dielectric layer surrounding the second channel layer; a second gate electrode layer disposed on the second gate dielectric layer; a second source / drain region in contact with the second channel layer; and a bonding structure disposed between the first channel layer and the second channel layer and aligned with the first channel layer and the second channel layer. In some embodiments, the bonding structure comprises: a first dielectric bonding layer; and a second dielectric bonding layer bonded to the first dielectric bonding layer by dielectric-to-dielectric direct bonding. In some embodiments, the first channel layer has a first crystal orientation, and the second channel layer has a second crystal orientation. In some embodiments, the bonding structure further comprises: a third dielectric layer facing the first channel layer; and a fourth dielectric layer facing the second channel layer. In some embodiments, the first channel layer has a first crystal orientation and the second channel layer has a second crystal orientation.

[0105] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first semiconductor stack on a first substrate; forming a second semiconductor stack on a second substrate; bonding the second substrate to the first substrate such that the second semiconductor stack is stacked above the first semiconductor stack; removing the second substrate; patterning the first semiconductor stack and the second semiconductor stack to form a fin structure; as well as A first transistor and a second transistor are formed from the fin structure, wherein the first transistor includes a first source / drain region disposed across a portion of the first semiconductor stack and the second transistor includes a second source / drain region disposed across a portion of the second semiconductor stack.

2. The method according to claim 1, further comprising: depositing a first dielectric layer over the first semiconductor stack; as well as A second dielectric layer is deposited over the second semiconductor stack, wherein bonding the second substrate to the first substrate includes bonding the first dielectric layer to the second dielectric layer.

3. The method according to claim 2, wherein: Forming the first semiconductor stack includes: Two or more first semiconductor layers and two or more second semiconductor layers are alternately deposited.

4. The method according to claim 3, further comprising: Prior to depositing the first dielectric layer, an etch stop layer is deposited on the first semiconductor stack.

5. The method according to claim 4, wherein: The etch stop layer includes a dielectric material.

6. The method according to claim 4, wherein: The etch stop layer includes a semiconductor material.

7. The method according to claim 1, wherein: The first substrate has a first crystal orientation, and the second substrate has a second crystal orientation different from the first crystal orientation.

8. The method according to claim 7, further comprising: Before bonding the first substrate and the second substrate, the first substrate and the second substrate are aligned according to the first crystal orientation and the second crystal orientation.

9. A method for manufacturing a semiconductor device, comprising: A fin structure is formed on the first substrate, wherein the fin structure comprises: a first semiconductor channel layer having a first crystal orientation; a second semiconductor channel layer having a second crystal orientation; and a bonding structure located between the first semiconductor channel layer and the second semiconductor channel layer; forming a sacrificial gate structure over the fin structure; etching the fin structure on opposite sides of the fin structure; forming a first source / drain region in contact with the first semiconductor channel layer; depositing a first contact etch stop layer (CESL) over the first source / drain region; depositing a first interlayer dielectric (ILD) layer on the first contact etch stop layer; forming a second source / drain region in contact with the second semiconductor channel layer; depositing a second contact etch stop layer over the second source / drain region; and A second interlayer dielectric layer is deposited on the second contact etch stop layer.

10. A semiconductor device comprising: a first channel layer; a first gate dielectric layer surrounding the first channel layer; a first gate electrode layer, disposed on the first gate dielectric layer; a first source / drain region, in contact with the first channel layer; a second channel layer disposed below the first channel layer and aligned with the first channel layer; a second gate dielectric layer surrounding the second channel layer; a second gate electrode layer, disposed on the second gate dielectric layer; a second source / drain region, in contact with the second channel layer; as well as A bonding structure is disposed between and aligned with the first channel layer and the second channel layer.

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