Package-free diode and its processing technology

Abstract

A package-free diode and its processing technology; the diode includes an insulating hard heat dissipation substrate, an insulating thermally conductive adhesive, a diode chip and a conductive alloy layer; the lower surface of the insulating hard heat dissipation substrate is adhered and fixed to the upper surface of the diode chip by the insulating thermally conductive adhesive; the diode chip includes a silicon wafer substrate, the lower surface of which is doped with a first impurity to form an N+ region, and doped with a second impurity to form a P+ region, and the N+ region and the P+ region are arranged at intervals; the N+ region and the P+ region are on the same side and the surfaces of both are provided with metal electrodes, and the surfaces of the metal electrodes are formed with a conductive alloy layer. The present invention can reduce material costs and labor costs by greatly simplifying the packaging, and can reduce the processing cost by up to 30%, and can improve the production efficiency per unit time.

Description

Technical Field

[0001] The invention relates to the field of diode processing and manufacturing, and in particular to a package-free diode and a processing technology thereof. Background Art

[0002] Diodes are widely used in various circuits. It can be said that wherever there is a circuit, there are diodes. Using their unidirectional conduction characteristics, AC is converted into DC, so that the terminal components of the circuit can obtain stable DC input. The existing manufacturing method of rectifier diodes is to use N-type (111) crystal orientation single crystal silicon wafers as the basic material, perform boron doping on the upper surface of the silicon wafer to form a flat P region, and then perform phosphorus diffusion on the lower surface to form a flat N region, and then perform photolithography, metallization, alloying and other processes to finally form the PN structure and electrode metal of the diode to make a rectifier diode chip (also known as "grain" in the industry). Finally, the final diode product is made through the packaging process. The traditional packaging process usually includes frame assembly, solder paste, grain assembly, welding combination, cleaning, injection molding epoxy molding, curing, degumming, cutting ribs and bending feet, reflow soldering, electroplating, annealing, testing, laser printing, and packaging.

[0003] The shortcomings of the above prior art include:

[0004] 1. Since the PN junction is formed by the process of diffusion on both sides of the chip, it is not conducive to the miniaturization of the product;

[0005] Second, there are electrodes and lead frames on both sides of the chip, which further increases the thickness and the complexity of the circuit connection process. In addition, in the subsequent packaging process, the chip cannot directly contact the outer heat sink, and the heat dissipation effect will also be affected;

[0006] 3. There are too many steps in the packaging process, which leads to waste of resources, increased costs, and long production cycles. In addition, too many steps also increase the probability of processing errors.

[0007] Therefore, how to solve the above-mentioned deficiencies in the prior art has become a subject to be studied and solved by the present invention. Summary of the invention

[0008] The purpose of the present invention is to provide a packaging-free diode and a processing technology thereof.

[0009] In order to achieve the above object, the technical solution adopted by the present invention is:

[0010] A package-free diode; comprising, from top to bottom, an insulating hard heat dissipation substrate, an insulating thermal conductive adhesive, a diode chip and a conductive alloy layer;

[0011] The lower surface of the insulating hard heat dissipation substrate is adhered and fixed to the upper surface of the diode chip through the insulating thermal conductive adhesive;

[0012] The diode chip comprises an N-type or P-type silicon wafer substrate with a crystal orientation of <111>, a lower surface of which is doped with a first impurity to form an N+ region, and doped with a second impurity to form a P+ region, and the N+ region and the P+ region are arranged alternately; the N+ region and the P+ region are formed on the same side of the silicon wafer substrate, and metal electrodes are provided on the surfaces of both, so that the two metal electrodes are located on the same side of the silicon wafer substrate;

[0013] Wherein, the surfaces of the two metal electrodes are formed with the conductive alloy layer by melting the solder paste.

[0014] The relevant contents in the above technical solution are explained as follows:

[0015] 1. In the above scheme, the insulating rigid heat dissipation substrate is a ceramic substrate, and a silicon carbide substrate or other substrates with the same or similar functions may also be selected. The ceramic substrate is preferred because the expansion coefficient of the ceramic substrate is closest to that of silicon, which can reduce packaging stress.

[0016] 2. In the above solution, the first impurity doping is phosphorus impurity doping or arsenic impurity doping, and the second impurity doping is boron impurity doping or gallium impurity doping.

[0017] 3. In the above solution, the silicon wafer substrate is of N-type (111) crystal orientation, a groove is opened in the edge area of ​​the P+ region, and the groove is filled with a glass passivation layer.

[0018] 4. In the above solution, the silicon wafer substrate is of P-type (111) crystal orientation, a groove is formed at the edge of the N+ region, and the groove is filled with a glass passivation layer.

[0019] 5. In the above solution, the number of the N+ region and the number of the P+ region are at least one.

[0020] 6. In the above scheme, the N+ region and the P+ region are arranged in parallel and spaced apart in the horizontal direction, or one of the N+ region and the P+ region is surrounded by the other in the horizontal direction.

[0021] To achieve the above object, another technical solution adopted by the present invention is:

[0022] A processing technology for a package-free diode; based on the diode according to claim 1, the process comprises the following steps:

[0023] Step 1: Apply insulating thermal conductive adhesive to the upper surface of the diode chip, i.e., the non-welding surface, and attach an insulating hard heat dissipation substrate through the insulating thermal conductive adhesive;

[0024] Step 2: high temperature baking to solidify the glue, the baking temperature is 150±10℃, and the baking time is 0.5±0.1h;

[0025] Step 3: Print solder paste on the surfaces of the two electrodes, and melt the solder paste in a tunnel furnace to form a conductive alloy layer with the metal electrodes.

[0026] The relevant contents in the above technical solution are explained as follows:

[0027] 1. In the above scheme, between step 1 and step 2, each electrode is shielded by a stencil, and a second insulating thermal conductive adhesive is partially printed on the lower surface of the diode chip.

[0028] 2. In the above scheme, in step 4, after cooling, a layer of blue film is attached to the upper surface of the insulating rigid heat dissipation substrate, and then the wafer is cut into several individual grains by a wafer-specific cutting machine.

[0029] 3. In the above scheme, in step 5, the blue film carrying products are loaded on the automatic testing machine, all of which are subjected to electrical testing. The finished products that pass the test are laser printed, and the qualified products are loaded into the carrier tape and heat-sealed on the surface.

[0030] 4. In the above scheme, the insulating hard heat dissipation substrate is a ceramic substrate with a thickness of 0.3-0.6 mm, a thermal conductivity of 100-300 W / mK, and a linear thermal expansion coefficient of 2.4-4.8 10 -6 / K, insulation strength is 10~20 kV / mm, volume resistivity is greater than 10 10 Ω.m.

[0031] 5. In the above scheme, the thickness of the insulating thermal conductive adhesive is 0.02~0.05mm, the thermal conductivity is 1~3W / mK, the insulation strength is 10~20 kV / mm, and the volume resistivity is less than 10 15 Ω.m, tensile modulus at 25℃ is 5000~10000N / mm 2 , tensile modulus at 200°C is 50~200 N / mm 2 .

[0032] 6. In the above solution, the thickness of the second insulating thermally conductive adhesive is 0.02~0.05mm, the thermal conductivity is 1~3W / mK, the insulation strength is 10~20 kV / mm, and the volume resistivity is less than 10 15 Ω.m, tensile modulus at 25℃ is 5000~10000N / mm 2 , tensile modulus at 200°C is 50~200 N / mm 2 .

[0033] The working principle and advantages of the present invention are as follows:

[0034] The invention discloses a package-free diode; it comprises an insulating hard heat dissipation substrate, an insulating thermally conductive adhesive, a diode chip and a conductive alloy layer; the lower surface of the insulating hard heat dissipation substrate is adhered and fixed to the upper surface of the diode chip by the insulating thermally conductive adhesive; the diode chip comprises a silicon wafer substrate, the lower surface of which is doped with a first impurity to form an N+ region, and doped with a second impurity to form a P+ region, and the N+ region and the P+ region are arranged at intervals; the N+ region and the P+ region are on the same side and the surfaces of both are provided with metal electrodes, and the surfaces of the metal electrodes are formed with a conductive alloy layer.

[0035] Compared with the prior art, the advantages of the present invention include:

[0036] 1. The N+ region and P+ region of the diode chip are located on the same side of the silicon wafer substrate, and the PN junction is formed by the same-side diffusion process of the chip, which is conducive to the miniaturization of the product and can ensure high reliability quality;

[0037] Second, there is no need to set electrodes and lead frames on both sides of the chip, which reduces the complexity of the circuit connection process. During the packaging process, the chip can directly contact the outer heat sink, greatly improving the heat dissipation effect;

[0038] 3. The combination of printing technology can eliminate the conventional copper leads, greatly simplifying the process and saving costs; at the same time, due to the increase in integration, the size of the device can be greatly reduced;

[0039] 4. It can be directly applied to the circuit after being mounted on an insulating hard heat dissipation substrate, eliminating epoxy, reducing thermal resistance and improving heat dissipation performance;

[0040] 5. Use 20~40um shallow trenches, combined with polysilicon passivation composite film layer and glass passivation to protect the PN junction. The process is simple, the chemical consumption is small, the forward power consumption is low, the manufacturing cost is low but the quality is high;

[0041] 6. The U-shaped PN junction is formed by selective diffusion, which increases the effective area of ​​the PN junction and significantly reduces the power consumption of the diode when used in the circuit;

[0042] 7. The structure is suitable for common rectifier diodes, fast recovery diodes, TVS protection diodes, voltage regulator diodes, etc.

[0043] In summary, the present invention breaks the traditional diode packaging structure and process, and makes the diode packaging process simpler and more effective under the premise of ensuring the heat dissipation and insulation performance of the diode. It is not only conducive to reducing the processing cost of large-scale diode semiconductor devices, but also reduces the energy consumption of the client, and is more conducive to reducing the waste of resources (eliminating the consumption of materials such as resin, solder, copper leads, etc.), and contributing to environmental protection.

[0044] Compared with the traditional diode packaging structure and process, the present invention can reduce material costs and labor costs by greatly simplifying the packaging, thereby reducing the processing cost by up to 30%, and improving the production efficiency per unit time. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Attached Figure 1 It is a three-dimensional diagram of the first embodiment of the present invention;

[0046] Attached Figure 2 This is a schematic diagram of the structure of Embodiment 1 of the present invention;

[0047] Attached Figure 3 It is a bottom schematic diagram of the first embodiment of the present invention;

[0048] Attached Figure 4 This is a decomposed exploded view of the first embodiment of the present invention;

[0049] Attached Figure 5 This is a schematic diagram of the structure of a diode chip according to an embodiment of the present invention;

[0050] Attached Figure 6 It is a three-dimensional diagram of the second embodiment of the present invention;

[0051] Attached Figure 7 It is a bottom schematic diagram of the second embodiment of the present invention;

[0052] Attached Figure 8 It is a three-dimensional diagram of the third embodiment of the present invention;

[0053] Attached Fig. 9 This is a bottom schematic diagram of Embodiment 3 of the present invention.

[0054] In the above figures: 1. Insulating hard heat dissipation substrate; 2. Insulating thermally conductive adhesive; 3. Diode chip; 4. Second insulating thermally conductive adhesive; 5. Silicon wafer substrate; 6. N+ region; 7. P+ region; 8. Groove; 9. Glass passivation layer; 10. Electrode; d. Distance; 11. Conductive alloy layer. DETAILED DESCRIPTION

[0055] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0056] Embodiment 1: See attached Figures 1 to 5 As shown, a package-free diode comprises, from top to bottom, an insulating hard heat dissipation substrate 1, an insulating thermally conductive adhesive 2, a diode chip 3, a second insulating thermally conductive adhesive 4, and a conductive alloy layer 11.

[0057] The lower surface of the insulating hard heat dissipation substrate 1 is adhered and fixed to the upper surface of the diode chip 3 through the insulating thermal conductive adhesive 2. The insulating hard heat dissipation substrate 1 is preferably a ceramic substrate, because the expansion coefficient of the ceramic substrate is closest to that of silicon, which can reduce packaging stress. Silicon carbide substrates or other substrates with the same or similar functions can also be selected.

[0058] like Figure 5 As shown, the diode chip 3 includes a silicon wafer substrate 5, the lower surface of which is doped with a first impurity to form an N+ region 6, and doped with a second impurity to form a P+ region 7, and the N+ region 6 and the P+ region 7 are arranged at intervals; the N+ region 6 and the P+ region 7 are formed on the same side of the silicon wafer substrate 5, and the surfaces of both are formed by depositing a metal layer to form a metal electrode 10, so that the two metal electrodes 10 are located on the same side of the silicon wafer substrate 5; the second insulating thermally conductive adhesive 4 is applied to the lower surface of the diode chip 3, and each of the metal electrodes 10 is exposed. Through the provision of the second insulating thermally conductive adhesive 4, the future diode can be insulated from the PCB board after assembly. Among them, the surfaces of the two metal electrodes 10 are formed with the conductive alloy layer 11 by melting the solder paste.

[0059] The first impurity doping is phosphorus impurity doping or arsenic impurity doping, and the second impurity doping is boron impurity doping or gallium impurity doping. The doping concentration of the surface of the N+ region 6 is at least 10 21 atm / cm 3 , the diffusion depth is 30~50μm; the doping concentration of the surface of the P+ region 7 is at least 10 21 atm / cm 3 , the diffusion depth is 50~70μm.

[0060] The silicon wafer substrate 5 is of N-type <111> crystal orientation, and a groove 8 is formed in the edge region of the P+ region 7. Alternatively, the silicon wafer substrate 5 is of P-type <111> crystal orientation, and a groove 8 is formed in the edge region of the N+ region 6.

[0061] The depth of the groove 8 is 20-40 μm; the groove 8 is filled with glass glue with a thickness of 25-35 μm, and a glass passivation layer 9 is formed by high-temperature sintering.

[0062] The number of the N+ region 6 and the number of the P+ region 7 are both one, and they are arranged in parallel and spaced apart in the horizontal direction. The distance d between the N+ region 6 and the P+ region 7 is 200-300um. The reason for selecting this distance parameter is that the distance design between the N+ region 6 and the P+ region 7 must ensure a certain range. When an external electric field is applied, the space charge region of the diode PN junction will expand outward. If the distance between the N+ region 6 and the P+ region 7 is too close, the space charge region will not be widened enough, and the diode will break down prematurely and fail to meet the designed voltage requirements. If it is too wide, it will lead to an increase in size and waste of materials.

[0063] The processing technology of the diode of the present invention comprises the following steps:

[0064] Step 1: Apply insulating thermally conductive adhesive 2 on the upper surface of the diode chip 3 , ie, the non-soldering surface, and attach the insulating hard heat dissipation substrate 1 through the insulating thermally conductive adhesive 2 .

[0065] Step 2: shield each electrode 10 through a screen plate, and partially print the second insulating thermal conductive adhesive 4 on the lower surface of the diode chip 3.

[0066] Step 3: High temperature baking to solidify the adhesive, the baking temperature is 150±10℃, and the baking time is 0.5±0.1h. The wafer processing is now completed.

[0067] Step 4: Print solder paste on the surfaces of the two electrodes 10 , and melt the solder paste in a tunnel furnace to form a conductive alloy layer 11 (ie, solder ball) with the metal electrode 10 .

[0068] Step 5: After cooling, a layer of blue film is attached to the upper surface of the insulating rigid heat dissipation substrate 1, and then the wafer is cut into several individual grains according to the size designed by the manufacturer by a wafer-specific cutting machine, that is, it is cut into several diode chips 3. The blue film is a PVC film with a certain degree of adhesion, which is a universal carrier for wafer cutting and is removed after step 5 is completed.

[0069] Step 6: Load the blue film carrying products on the automatic testing machine, and all of them are tested for electrical properties. The finished products that pass the test are laser printed, and the qualified products are loaded into the carrier tape and heat-sealed on the surface. The selection and use of the automatic testing machine and the specific methods of electrical testing are all conventional technologies, so they are not repeated here.

[0070] The insulating rigid heat dissipation substrate 1 is a ceramic substrate with a thickness of 0.3-0.6 mm, a thermal conductivity of 100-300 W / mK, and a linear thermal expansion coefficient of 2.4-4.8 (10 -6 / K), insulation strength is 10~20 kV / mm, volume resistivity is greater than 10 10Ω.m, AN3170 model can be selected in practical applications. The ceramic substrate has high thermal conductivity and high insulation properties, and can improve the strength of the product, help protect the diode chip 3, and ensure the heat dissipation and insulation of the diode chip 3.

[0071] The thickness of the insulating thermal conductive adhesive 2 is 0.02-0.05 mm, the thermal conductivity is 1-3 W / mK, the insulation strength is 10-20 kV / mm, and the volume resistivity is less than 10 15 Ω.m, tensile modulus at 25℃ is 5000~10000N / mm 2 (psi), tensile modulus at 200°C is 50~200 N / mm 2 (psi), 282-EN model is available.

[0072] The thickness of the second insulating thermally conductive adhesive 4 is 0.02-0.05 mm, the thermal conductivity is 1-3 W / mK, the insulation strength is 10-20 kV / mm, and the volume resistivity is less than 10 15 Ω.m, tensile modulus at 25℃ is 5000~10000N / mm 2 (psi), tensile modulus at 200°C is 50~200 N / mm 2 (psi), 282-EN model is available.

[0073] The technical details of step 4 "forming a conductive alloy layer 11 by printing solder paste on the surface and melting the solder paste in a tunnel furnace" are not repeated here because the technology is an existing technology and can be mastered and flexibly used by those skilled in the art.

[0074] Embodiment 2: See attached Figures 6 and 7 As shown, a package-free diode is shown; the difference from the first embodiment is that the number of the N+ region 6 and the number of the P+ region 7 are both multiple, and one is surrounded by the other in the horizontal direction. The other parts are the same as the first embodiment, so they are not repeated.

[0075] Embodiment 3: See attached Figures 8 and 9 As shown, a package-free diode is shown; the difference from the first embodiment is that the number of the N+ region 6 and the P+ region 7 are both multiple, and they are arranged in parallel and spaced in the horizontal direction. The other parts are the same as the first embodiment, so they are not repeated.

[0076] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A package-free diode; characterized in that: From top to bottom, it includes an insulating hard heat dissipation substrate, an insulating thermal conductive adhesive, a diode chip, and a conductive alloy layer; The lower surface of the insulating hard heat dissipation substrate is adhered and fixed to the upper surface of the diode chip through the insulating thermal conductive adhesive; the thickness of the insulating thermal conductive adhesive is 0.02-0.05 mm; The diode chip comprises a silicon wafer substrate, a lower surface of which is doped with a first impurity to form an N+ region, and doped with a second impurity to form a P+ region, and the N+ region and the P+ region are arranged at intervals; the N+ region and the P+ region are formed on the same side of the silicon wafer substrate, and metal electrodes are provided on the surfaces of both, so that the two metal electrodes are located on the same side of the silicon wafer substrate; Wherein, the surfaces of the two metal electrodes are formed with the conductive alloy layer by melting the solder paste; The N+ region and the P+ region are arranged in parallel and spaced apart in the horizontal direction, or one of the N+ region and the P+ region is surrounded by the other in the horizontal direction; the distance d between the N+ region and the P+ region is 200-300 um; The diffusion depth of the surface of the N+ region is 30-50 μm; the diffusion depth of the surface of the P+ region is 50-70 μm; the first impurity doping is phosphorus impurity doping or arsenic impurity doping, and the second impurity doping is boron impurity doping or gallium impurity doping; The insulating rigid heat dissipation substrate is a ceramic substrate with a thickness of 0.3-0.6 mm; It also includes a second insulating thermally conductive adhesive, which is applied to the lower surface of the diode chip and exposes each of the metal electrodes; the thickness of the second insulating thermally conductive adhesive is 0.02-0.05 mm; The processing technology of package-free diode includes the following steps: Step 1: Apply insulating thermal conductive adhesive to the upper surface of the diode chip, i.e., the non-welding surface, and attach an insulating hard heat dissipation substrate through the insulating thermal conductive adhesive; Step 2: high temperature baking to solidify the glue, the baking temperature is 150±10℃, and the baking time is 0.5±0.1h; Step 3: printing solder paste on the surfaces of the two electrodes, and melting the solder paste in a tunnel furnace to form a conductive alloy layer with the metal electrode; Wherein, between step 1 and step 2, each electrode is shielded by a screen plate, and a second insulating thermal conductive adhesive is partially printed on the lower surface of the diode chip.

2. The diode according to claim 1, characterized in that: The silicon wafer substrate is of N-type <111> crystal orientation, a groove is opened in the edge area of ​​the P+ region, and the groove is filled with a glass passivation layer.

3. The diode according to claim 1, characterized in that: The silicon wafer substrate is of P-type <111> crystal orientation, and a groove is opened in the edge area of ​​the N+ region, and the groove is filled with a glass passivation layer.

4. The diode according to claim 1, characterized in that: Step 4: After cooling, a layer of blue film is attached to the upper surface of the insulating rigid heat dissipation substrate, and then the wafer is cut into several individual grains by a wafer-specific cutting machine; Step 5: The blue film carrying products are loaded onto the automatic testing machine and all are subjected to electrical testing. The finished products that pass the test are laser printed, and the qualified products are loaded into the carrier tape and heat-sealed on the surface.

Images