Resistor-less power amplifier

Abstract

The present invention relates to a power amplifier circuit, which comprises a current source, a power control circuit, a current mirror and an output circuit. The current source circuit comprises a first transistor and a second transistor. The source of the first transistor is connected to the drain of the second transistor, and the gate of the first transistor is connected to the source through the second transistor. The power control circuit is connected to the gate of the second transistor. The current mirror circuit is connected to the gate of the first transistor and the source of the second transistor. The output circuit is connected to the current mirror circuit.

Description

Technical Field

[0001] The present invention relates to a power amplifier, and more particularly, to a bias circuit for a power amplifier. Background Art

[0002] A power amplifier is used in a circuit in a wireless transceiver that amplifies a signal to be transmitted. The power amplifier may be powered by a power supply circuit, such as a current source (or current sink) connected to a current mirror. When the power amplifier is used in a mobile device (e.g., a cell phone, a tablet computer, or a notebook), it may be desirable for the power amplifier and the power supply circuit to have relatively low power consumption. In order to accurately control or reduce the current applied to the power amplifier, a relatively large resistor (e.g., in the kilo-ohm (k-ohm) to mega-ohm (M-ohm) range) may be used. However, a larger resistor may increase the chip / die area, which may hinder the miniaturization of the chip / die. Summary of the invention

[0003] According to one aspect of the present invention, a power amplifier circuit includes a current source, a power control circuit, a current mirror and an output circuit. The current source circuit includes a first transistor and a second transistor. The source of the first transistor is connected to the drain of the second transistor, and the gate of the first transistor is connected to the source through the second transistor. The power control circuit is connected to the gate of the second transistor. The current mirror circuit is connected to the gate of the first transistor and the source of the second transistor. The output circuit is connected to the current mirror circuit.

[0004] According to another aspect of the present invention, a power amplifier circuit includes a current source circuit, a current mirror, a power control circuit, and an output circuit. The power control circuit includes a first transistor and a second transistor. The first transistor has a drain connected to a first voltage input, a gate connected to ground, and a source connected to the gate of the second transistor. The current mirror circuit has a first node connected to the current source circuit and a second node connected to the source of the second transistor. The output circuit is connected to the current mirror circuit.

[0005] According to another aspect of the present invention, a power amplifier circuit includes a current source circuit, a current mirror circuit, a power control circuit and an output circuit. The current source circuit is configured to generate a first current. The current mirror circuit is connected to the current source and configured to generate a second current in response to the first current. The power control circuit is connected to the current source circuit and the current mirror circuit and configured to receive a first voltage. The output circuit is connected to the current mirror circuit and configured to generate a third current. The third current changes in response to the first voltage.

[0006] According to another aspect of the present invention, a wireless communication system includes a GaAs power amplifier and a GaN transistor. The GaAs power amplifier has an input terminal configured to receive a first signal and an output terminal configured to output an amplified signal. The GaN transistor has a source connected to the output terminal of the power amplifier and a gate connected to ground. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a schematic diagram illustrating a power amplifier according to some embodiments of the present invention.

[0008] Figure 1B and Figure 1C Describe some embodiments of the present invention Figure 1A Simulation results of the power amplifier shown in .

[0009] Figure 2A is a schematic diagram illustrating a power amplifier according to some embodiments of the present invention.

[0010] Figure 2B and Figure 2C Describe some embodiments of the present invention Figure 2A Simulation results of the power amplifier shown in .

[0011] Figure 3 is a schematic diagram illustrating a power amplifier according to some embodiments of the present invention.

[0012] Figure 4 is a block diagram of a multi-chip module (MCM) according to some embodiments of the present invention.

[0013] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. The present invention can be easily understood based on the following detailed description made in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0014] Although described with particular reference to portable transceivers, the circuits and methods for biasing gallium arsenide (GaAs) power amplifiers (also referred to as GaAs bias circuits) may be implemented in any GaAs device where bias current and voltage need to be provided. In addition, the circuits described below may be fabricated using an integrated bipolar-field effect transistor (BIFET) process that exploits the lower voltage of field effect transistors. In addition, in specific embodiments, the transistors described below include bipolar junction transistors (referred to as BJTs) fabricated using a process referred to as a BIFET process or a BiHEMT process, including heterojunction bipolar junction transistors (referred to as HBTs) and field effect transistors (referred to as FETs) or phantom high electron mobility transistors (referred to as pHEMTs).

[0015] As used herein, reference to a gate, source, drain or other component of a transistor or other circuit component being connected to the gate, source, drain or other component of another transistor or other circuit component refers to a direct connection or to a connection with another circuit component (such as a transistor) placed therebetween.

[0016] Figure 1A is a schematic diagram illustrating a power amplifier 100 according to some embodiments of the present invention. The power amplifier 100 includes a power control circuit 110, a current source circuit 120, an enable circuit 130, a current mirror circuit 140, and an output circuit 150. The power amplifier 100 further includes a transistor T133, a capacitor C11, a capacitor C12, and an inductor L11.

[0017] The power control circuit 110 includes transistors T111 and T112. The drain of transistor T111 is connected to the input voltage V11, the gate of transistor T111 is connected to ground (i.e., ground voltage), and the source of transistor T111 is connected to the drain of transistor T112. The gate of transistor T112 is connected to ground, and the source of transistor T112 is connected to the current source circuit 120. In some embodiments, the number of transistors of the power control circuit 110 can be adjusted depending on the design specifications. For example, the power control circuit 110 can include one transistor or more than two transistors connected in series. For example, in one or more embodiments, transistor T111 can be omitted.

[0018] In some embodiments, transistors T111 and T112 are depletion mode (D-mode) phantom high electron mobility transistors (pHEMTs), and thus transistors T111 and T112 can limit the voltage of the input terminal of the current source circuit (e.g., the gate of transistor T121) to a predetermined voltage. For example, if the pinch-off voltage of each of transistors T111 and T112 is 1V, the voltage of the input terminal of the current source circuit 120 can be limited to about 1V. In some embodiments, the power control circuit 110 can also be referred to as a "voltage limiting circuit" or a "voltage limiter." In addition, the power control circuit 110 can be configured to limit the current I11 provided to the input terminal of the current source circuit 120 to less than about 0.1μA (e.g., less than about 0.095μA, less than about 0.090μA, less than about 0.085μA, or less).

[0019] The current source circuit 120 includes transistors T121, T122, T123, and T124. The gate of transistor T121 is connected to the source of transistor T112, the source of transistor T121 is connected to the collector of transistor T141 (described below), and the drain of transistor T121 is connected to the source of transistor T122. The gate of transistor T122 is connected to the collector of transistor T141, and the drain of transistor T122 is connected to the source of transistor T123. The gate of transistor T123 is connected to the collector of transistor T141 and to the gate of transistor T133, and the drain of transistor T123 is connected to the source of transistor T124. The gate of transistor T124 is connected to the source of transistor T123, and the drain of transistor T124 is connected to the power supply V13 (or power supply). In some embodiments, transistors T121, T122, T123, and T124 are D-mode pHEMTs.

[0020] Transistors T121, T122, T123 and T124 are configured to determine or set the current I12 of the current source circuit 120. In some embodiments, transistors T121 and T122 can be replaced by larger resistors to accurately control or reduce the current I12. However, such larger resistors can occupy a larger area of ​​the chip / die, which can hinder the miniaturization of the chip / die. By using transistors T121 and T122 to replace the larger resistor, the total area of ​​the chip / die can be reduced. In addition, the size of the transistors T121 and T122 can adjust the equivalent resistance thereof, which can increase design flexibility. In some embodiments, the input voltage V11 is provided to the gate of the transistor T121 through transistors T11 and T112 to control the transistor T121 as a voltage-controlled resistor (or variable resistor) so that the current source circuit 120 can be used as a voltage-controlled current source.

[0021] The enabling circuit 130 includes transistors T131 and T132. The drain of the transistor T131 is connected to the enabling input voltage V12, which can start the power amplifier 100. The gate of the transistor T131 is connected to the base of the transistor T141, and the source of the transistor T131 is connected to the gate of the transistor T132. The source of the transistor T132 is connected to the base of the transistor T145, and the drain of the transistor T132 is connected to the source of the transistor T133. In some embodiments, the transistor T131 is a D-mode pHEMT and can be used as a voltage limiter to limit the voltage of the gate of the transistor T132 to a predetermined voltage.

[0022] The current mirror circuit 140 includes transistors T141, T142, T143, T144, T145 and T146. The collector of transistor T141 is connected to the current source circuit 120 (e.g., connected to the source of transistor T121), the base of transistor T141 is connected to the enabling circuit 130 (e.g., connected to the gate of transistor T131) and the emitter of transistor T141 is connected to ground. The source and gate of transistor T142 are connected to the base of transistor T141, and the drain of transistor T142 is connected to the source of transistor T143. The gate of transistor T143 is connected to the gate and source of transistor T142, and the drain of transistor T143 is connected to the source of transistor T144. The drain of transistor T144 is connected to the emitter of transistor T145. The gates of transistors T142, T143 and T144 are connected to the gate of transistor T146. The base of transistor T145 is connected to the enabling circuit 130 (e.g., connected to the source of transistor T132) and the collector of transistor T145 is connected to the power supply V13. The drain of transistor T146 is connected to the drain of transistor T144 and the emitter of transistor T145, and the source of transistor T146 is connected to the output circuit 150 (e.g., the base of transistor T151).

[0023] The current mirror circuit 140 is connected to the current source circuit 120 and the enabling circuit 130 to generate a current I13 based on the current I12 of the current source circuit 120. In some embodiments, the value of the current I13 is substantially equal to a predetermined ratio of the value of the current I12. In some embodiments, transistors T142, T143, and T144 and transistor T146 may act as two ballast resistors to limit the amount of current I13 and compensate for temperature changes of the power amplifier 100. In some embodiments, transistors T142, T143, and T144 may be replaced by larger resistors, and transistor T146 may be replaced by another larger resistor. However, such larger resistors may occupy a larger area of ​​the chip / die, which may hinder the miniaturization of the chip / die. By replacing the larger resistors with transistors T142, T143, T144, and T146, the total area of ​​the chip / die may be reduced. In addition, adjusting the sizes of transistors T142 , T143 , T144 , and T146 may adjust their equivalent resistances, which may increase design flexibility.

[0024] The output circuit 150 includes a transistor T151. The base of the transistor T151 is connected to the current mirror circuit 140 (e.g., to the source of the transistor T146), and is configured to receive the current I13 from the current mirror circuit 140 to set the direct current (DC) bias of the output circuit 150. The emitter of the transistor T151 is connected to ground, and the collector of the transistor T151 is connected to the capacitor C12 and to the power supply V14 (or power supply) through the inductor L11. The base of the transistor T151 is further configured to receive a high-frequency signal (e.g., a radio frequency signal) from the input terminal Vin and output an amplified signal at the output terminal (e.g., the collector of the transistor T151) of the power circuit 150. In some embodiments, the (optional) capacitor C11 is connected between the base of the transistor T151 and the input terminal Vin to block the DC current (e.g., I13). In some embodiments, the output circuit 150 may include a plurality of transistors (e.g., a plurality of transistors connected in a parallel arrangement) to increase the power and heat dissipation of the power amplifier 100.

[0025] Figure 1B Describe some embodiments of the present invention Figure 1A The simulation results of the power amplifier 100 are shown in FIG. Figure 1B , the x-axis represents the voltage (V) of the input voltage V11 and the y-axis represents the current I14 of the output circuit 150. Figure 1B, when the voltage of the input voltage V11 increases from about 0 V to about 1.8 V or to about 2.0 V, the current I14 of the output circuit 150 increases from 0 milliamperes (mA) to about 45 mA. Because the current I14 of the output circuit 150 can be adjusted based on the voltage of the input voltage V11, the power amplifier 100 can include multiple power levels to comply with the specifications of a multi-band communication device.

[0026] Figure 1C Describe some embodiments of the present invention Figure 1A The simulation results of the power amplifier 100 are shown in FIG. Figure 1C In FIG. 1 , the x-axis represents the temperature of the power amplifier 100 (in degrees Celsius (° C.)), and the y-axis represents the current I14 of the output circuit 150. Figure 1C As shown in FIG. 1 , when the temperature of the power amplifier 100 increases from approximately −55° C. to approximately 125° C., the deviation of the current I14 of the output circuit 150 is less than approximately 3 mA (eg, less than approximately 2.9 mA, or less than approximately 2.8 mA, or less than approximately 2.7 mA).

[0027] Figure 2A 2 is a schematic diagram illustrating a power amplifier 200 according to some embodiments of the present invention. The power amplifier 200 includes a power control circuit 210, a current source circuit 220, a current mirror circuit 230, and an output circuit 240. The power amplifier 200 further includes a transistor T251 and a transistor T252.

[0028] The power control circuit 210 includes transistors T211 and T212. The drain of transistor T211 is connected to the input voltage V21, the gate of transistor T211 is connected to ground and the source of transistor T211 is connected to the gate of transistor T212. The source of transistor T212 is connected to the current source circuit 230 (e.g., connected to the drain of transistor T233 and the drain of transistor T234), and the drain of transistor T212 is connected to the emitter of transistor T252. In some embodiments, transistor T211 is a D-mode pHEMT, and therefore it can be used as a voltage limiter to limit the voltage of the gate of transistor T212 to a predetermined voltage. In some embodiments, when operating in a linear region (or ohmic region), transistor T212 can be used as a variable resistor.

[0029] The current source circuit 220 includes transistors T221, T222, T223 and T224. The gates of transistors T221, T222 and T223 are connected to the current mirror circuit 230 (e.g., connected to the collector of transistor T231). The source of transistor T221 is connected to the collector of transistor T231, and the drain of transistor T221 is connected to the source of transistor T222. The drain of transistor T222 is connected to the source of transistor T223 and the gate of transistor T224. The drain of transistor T223 is connected to the source of transistor T224 and the gate of transistor T251. The drain of transistor T224 is connected to the power supply V22 (or power supply). In some embodiments, transistors T221, T222, T223 and T224 are D-mode pHEMTs.

[0030] Transistors T221, T222, T223, and T224 are configured to determine or set the current I21 of the current source circuit 220. In some embodiments, transistors T221 and T222 can be replaced by larger resistors to accurately control or reduce the current I21. However, such larger resistors can occupy a larger area of ​​the chip / die, which can hinder the miniaturization of the chip / die. By using transistors T221 and T222 to replace the larger resistor, the total area of ​​the chip / die can be reduced. In addition, adjusting the size of transistors T221 and T222 can adjust their equivalent resistance, which can increase design flexibility.

[0031] The current mirror circuit 230 includes transistors T231, T232, T233 and T234. The collector of transistor T231 is connected to the current source circuit 220, the base of transistor T231 is connected to the source and gate of transistor T232, the gate of transistor T233 and the gate of transistor T234, and the emitter of transistor T231 is connected to ground. The drain of transistor T232 is connected to the source of transistor T233. The drain of transistor T233 is connected to the power control circuit 210 (for example, connected to the source of transistor T212) and the drain of transistor T234. The source of transistor T234 is connected to the output circuit 240 (for example, connected to the base of transistor T241).

[0032] The current mirror circuit 230 is connected to the current source circuit 220 and the power control circuit 210, and generates a current I22 based on the current I21 of the current source circuit 220. In some embodiments, the value of the current I22 is substantially equal to a predetermined ratio of the value of the current I21. In some embodiments, transistors T232 and T233 and transistor T234 can act as two ballast resistors to limit the amount of current I22 and compensate for the temperature change of the power amplifier 200. In some embodiments, transistors T232 and T233 can be replaced by larger resistors, and transistor T234 can be replaced by another larger resistor. However, such a larger resistor can occupy a large area of ​​the chip / die, which can hinder the miniaturization of the chip / die. By using transistors T232, T233 and T234 to replace the larger resistor, the total area of ​​the chip / die can be reduced. In addition, adjusting the size of transistors T232, T233 and T234 can adjust its equivalent resistance, which can increase design flexibility.

[0033] The output circuit 240 includes a transistor T241. The base of the transistor T241 is connected to the current mirror circuit 230 (e.g., connected to the source of the transistor T234), and is configured to receive the current I22 from the current mirror circuit 230 to set the DC bias of the output circuit 240. The emitter of the transistor T241 is connected to ground, and the collector of the transistor T241 is connected to the power supply V23 (or power supply). In some embodiments, the base of the transistor T241 is further configured to receive a high-frequency signal (e.g., a radio frequency signal) and output an amplified signal at the output end of the power circuit 240 (e.g., the collector of the transistor T241). In some embodiments, the output circuit 240 may include a plurality of transistors (e.g., a plurality of transistors connected in a parallel arrangement) to increase the power and heat dissipation of the power amplifier 200.

[0034] Figure 2B Describe some embodiments of the present invention Figure 2A The simulation results of the power amplifier 200 are shown in FIG. Figure 2B , the x-axis represents the voltage (V) of the input voltage V21 and the y-axis represents the current I23 of the output circuit 240. Figure 2B , when the voltage of the input voltage V21 increases from 0 V to about 0.8 V, the current I23 of the output circuit 240 increases from 0 mA to about 41 mA. Because the current I23 of the output circuit 240 can be adjusted based on the voltage of the input voltage V21, the power amplifier 200 can include multiple power levels to meet the specifications of multi-band communication equipment.

[0035] Figure 2C Describe some embodiments of the present invention Figure 2A The simulation results of the power amplifier 200 are shown in FIG. Figure 2C In FIG. 2 , the x-axis represents the temperature (° C.) of the power amplifier 200 and the y-axis represents the current I23 of the output circuit 240. Figure 2C As shown in , when the temperature of the power amplifier 200 increases from about -55°C to about 125°C, the deviation of the current I23 of the output circuit 240 is less than about 3mA (e.g., less than about 2.9mA, less than about 2.8mA, or less than about 2.7mA).

[0036] Figure 3 is a schematic diagram illustrating a power amplifier 300 according to some embodiments of the present invention. Figure 1A 1 and 100, and the differences therebetween include the following: in addition to the power control circuit 110, the power amplifier 300 further includes a power control circuit 310; and Figure 1A Compared with the current source circuit 120 in FIG. 1 , the current source circuit 320 further includes transistors T321 and T322 .

[0037] The power control circuit 310 includes transistors T311 and T312. The drain of transistor T311 is connected to the input voltage V31, the gate of transistor T311 is connected to ground and the source of transistor T311 is connected to the drain of transistor T312. The gate of transistor T312 is connected to ground, and the source of transistor T312 is connected to the current source circuit 320 (e.g., connected to the gate of transistor T322). In some embodiments, the number of transistors of the power control circuit 310 can be adjusted depending on the design specification. For example, the power control circuit 310 can include one transistor or more than two transistors connected in series. In some embodiments, the power control circuit 310 is the same as the power control circuit 110. Alternatively, the power control circuit 310 may be different from the power control circuit 110. In some embodiments, transistors T311 and T312 are D-mode pHEMTs, and therefore transistors T311 and T312 can limit the voltage of the gate of transistor T322 to a predetermined voltage. For example, the power control circuit 310 may be referred to as a "voltage limiting circuit" or a "voltage limiter."

[0038] The gate of transistor T321 is connected to the gates of transistors T133, T122 and T123, the source of transistor T321 is connected to the drains of transistors T322 and T122 and the drain of transistor T321 is connected to the source of transistor T123. The source of transistor T322 is connected to the source of transistor T121.

[0039] In some embodiments, the two sets of power control circuits 110 and 310 can implement 2-bit power level control. For example, when the voltages of the input voltages V11 and V31 are both high, the current source 320 operates in a high power mode. When the voltage of the input voltage V31 is high and the voltage of the input voltage V11 is low, the current source 320 operates in an intermediate power mode (assuming that the size of the transistor T322 is larger than the size of the transistor T121). When the voltage of the input voltage V31 is low and the voltage of the input voltage V11 is high, the current source 320 operates in a low power mode (assuming that the size of the transistor T322 is larger than the size of the transistor T121). When the voltages of the input voltages V11 and V31 are both low, the current source 320 is turned off. According to Figure 3 In the embodiment shown in , multiple power level modes can be realized by adding power control circuit 310, which will meet the specifications of multi-band communication devices. In some embodiments, the power amplifier may include more than two sets of power control circuits to realize more control modes.

[0040] Figure 4 is a block diagram of a multi-chip module (MCM) 400 according to some embodiments of the present invention. The MCM 400 includes a power amplifier 410 and a gallium nitride (GaN) transistor T410 connected in series with the power amplifier 410. In some embodiments, the MCM 400 is a wireless communication system or a part of a wireless communication system.

[0041] In some embodiments, the power amplifier 410 may be Figure 1A , 2A Any of the power amplifiers 100, 200 and 300 in and 3 or any other GaAs or SiGe power amplifier. The gate of the GaN transistor T410 is connected to ground, and the source of the GaN transistor T410 is connected to the output terminal of the power amplifier 410. The drain of the GaN transistor T410 is connected to the power supply V41 (or power supply) through the inductor L41, and is connected to the output terminal Vout through the capacitor C41. The capacitor C42 is connected between the power supply V41 and ground. In some embodiments, the GaN transistor is a HEMT.

[0042] The power amplifier is configured to provide a DC bias for the GaN transistor T410, and thus an additional bias circuit (e.g., a power supply, a power control circuit, and the like) can be omitted. The power amplifier 410 also provides a driver stage for the GaN transistor T410, and thus an additional driver stage can be omitted. In addition, a negative voltage generator for biasing the GaN transistor T410 can be omitted. In addition, because the power amplifier 410 includes a temperature compensation circuit, an additional temperature compensation circuit can be omitted for the GaN transistor T410. Therefore, according to Figure 4In the embodiment, by connecting the GaN transistor T410 in series with the power amplifier 410, the process of designing the MCM module 400 can be simplified and the manufacturing cost can be reduced.

[0043] As used herein, the singular terms "a," "an," and "the" may include plural references unless the context clearly dictates otherwise.

[0044] In addition, amounts, ratios and other numerical values ​​are sometimes presented herein in a range format. It should be understood that such a range format is used for convenience and brevity and should be flexibly interpreted to include not only the numerical values ​​explicitly specified as the range limits, but also all individual numerical values ​​or sub-ranges encompassed within the range, as if each numerical value and sub-range were explicitly specified.

[0045] As used herein and not otherwise defined, the terms "substantially," "essentially," "approximately," and "about" are used to describe and take into account minor variations. When used in conjunction with an event or circumstance, the terms may encompass situations where the event or circumstance definitely occurs as well as situations where the event or circumstance closely approximates to occurring. For example, when used in conjunction with a numerical value, the terms may encompass a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values ​​may be considered to be “substantially” or “approximately” the same or equal if the difference between them is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).

[0046] Although the present invention has been described and illustrated with reference to specific embodiments of the present invention, these descriptions and illustrations do not limit the present invention. It is clearly understood by those skilled in the art that various changes can be made and equivalent elements can be substituted in the embodiments without departing from the true spirit and scope of the present invention as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the artistic reproduction and the actual equipment in the present invention. There may be other embodiments of the present invention that are not specifically described. The description and drawings should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific situations, materials, material compositions, methods or processes to the goals, spirits and scopes of the present invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the present invention.

Claims

1. A power amplifier circuit, comprising: a current source circuit comprising a first transistor and a second transistor, a source of the first transistor being connected to a drain of the second transistor and a gate of the first transistor being connected to a source of the second transistor; a power control circuit connected to the gate of the second transistor; a current mirror circuit connected to the gate of the first transistor and the source of the second transistor; as well as output circuit, which is connected to the current mirror circuit, The power control circuit is configured to receive a first voltage input and is configured to control a current of the output circuit based on the first voltage input.

2. The power amplifier circuit of claim 1 , wherein the power control circuit comprises a third transistor, and the third transistor comprises a drain connected to the first voltage input, a gate connected to ground, and a source connected to the gate of the second transistor.

3. A power amplifier circuit according to claim 2, wherein the power control circuit further includes a fourth transistor between the third transistor and the first voltage input, and the fourth transistor includes a drain connected to the first voltage input, a gate connected to ground, and a source connected to the drain of the third transistor.

4. The power amplifier circuit of claim 1 , wherein the current source circuit further comprises a third transistor and a fourth transistor, and the third transistor comprises a source connected to the drain of the first transistor, a gate connected to the source of the first transistor, and a drain connected to the first voltage input.

5. The power amplifier circuit of claim 1 further comprising an enabling circuit, wherein The enabling circuit includes a third transistor and a fourth transistor; a drain of the third transistor connected to the first voltage input, a gate of the third transistor connected to the current mirror circuit, and a source of the third transistor connected to the gate of the fourth transistor; and A source of the fourth transistor is connected to the current mirror circuit, and a drain of the fourth transistor is connected to the gate of the first transistor.

6. The power amplifier circuit of claim 5, further comprising a fifth transistor, wherein the fifth transistor comprises a drain connected to a second voltage input, a gate connected to the gate of the first transistor, and a source connected to the drain of the fourth transistor.

7. The power amplifier circuit according to claim 5, wherein The current mirror circuit further includes a fifth transistor and a sixth transistor; a collector of the fifth transistor is connected to the source of the second transistor, a base of the fifth transistor is connected to the emitter of the sixth transistor, and an emitter of the fifth transistor is connected to the output circuit; and The emitter of the sixth transistor is connected to the output circuit, the base of the sixth transistor is connected to the source of the fourth transistor, and the collector of the sixth transistor is connected to a second voltage input.

8. The power amplifier circuit according to claim 7, wherein The current mirror circuit further includes a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; a drain of the seventh transistor connected to the emitter of the sixth transistor, a gate of the seventh transistor connected to the base of the fifth transistor, and a source of the seventh transistor connected to the drain of the eighth transistor; The gate of the eighth transistor is connected to the base of the fifth transistor, and the source of the eighth transistor is connected to the drain of the ninth transistor; The gate and source of the ninth transistor are connected to the base of the fifth transistor; and A gate of the tenth transistor is connected to the base of the fifth transistor, a drain of the tenth transistor is connected to the emitter of the sixth transistor, and a source of the tenth transistor is connected to the output circuit.

9. A power amplifier circuit, comprising: a current source circuit configured to generate a first current; a current mirror circuit connected to the current source circuit and configured to generate a second current in response to the first current; a power control circuit connected to the current source circuit and the current mirror circuit and configured to receive a first voltage; as well as an output circuit connected to the current mirror circuit and configured to generate a third current, wherein the third current varies in response to the first voltage, in: The current source circuit includes a first transistor and a second transistor; The source of the first transistor is connected to the drain of the second transistor, and the gate of the first transistor is connected to the source of the second transistor; as well as A gate of the second transistor is connected to receive the first voltage. 10 . The power amplifier circuit of claim 9 , wherein when the first voltage increases from 0 V to 2 V, the third current increases from 0 mA to 45 mA. 11 . The power amplifier circuit of claim 9 , wherein when the first voltage increases from 0 V to 0.8 V, the third current increases from 0 mA to 41 mA.

12. The power amplifier circuit of claim 9, wherein the power control circuit comprises a third transistor, and the third transistor comprises a drain connected to receive the first voltage, a gate connected to ground, and a source connected to the gate of the second transistor.

13. The power amplifier circuit according to claim 9, wherein The power control circuit includes a third transistor and a fourth transistor; a drain of the third transistor connected to the source of the fourth transistor, a gate of the third transistor connected to ground, and a source of the third transistor connected to the gate of the second transistor; and A drain of the fourth transistor is connected to receive the first voltage, and a gate of the fourth transistor is connected to ground.

14. The power amplifier circuit of claim 9, wherein a resistance value of the second transistor varies in response to the first voltage.

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