Forming an epitaxial structure in a fin field effect transistor

Abstract

Embodiments of the present invention disclose forming an epitaxial structure in a fin field-effect transistor. In one embodiment, a method of forming source / drain members in a FinFET device includes: providing a fin formed over a substrate and a gate structure formed over the fin; forming a groove adjacent to the gate structure in the fin; forming a first epitaxial layer in the groove; forming a second epitaxial layer over the first epitaxial layer; and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, and one or both of the first epitaxial layer and the third epitaxial layer contain a second element different from the first element. One or both of the first epitaxial layer and the third epitaxial layer may be formed by a plasma deposition process.

Description

Technical Field

[0001] Embodiments of the present invention relate to forming an epitaxial structure in a fin field effect transistor. Background Art

[0002] The integrated circuit (IC) industry has experienced tremendous growth. Technological advances in IC materials and design have produced multiple generations of ICs, with each generation having smaller and more complex circuits than the previous one. During the evolution of ICs, the functional density (i.e., the number of interconnect devices per chip area) has generally increased, while the geometric size (i.e., the smallest component (or line) that can be produced using the process) has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing related costs.

[0003] This scaling also increases the complexity of processing and manufacturing ICs. For example, while many current IC applications desire three-dimensional fin field effect transistors (FinFETs), their reduced component size also poses challenges in device manufacturing. In one instance, the shortened channel length can result in a reduced barrier to the diffusion of active dopant species from the source / drain components, which can degrade device performance. Thus, improvements in this field are needed. Summary of the Invention

[0004] An embodiment of the present invention relates to a device including: a fin over a substrate; a gate structure over the fin; and an epitaxial source / drain component over the fin and adjacent to the gate structure, wherein the epitaxial source / drain component includes a first layer, a second layer over the first layer, and a third layer over the second layer, wherein the second layer is doped with a first dopant, and wherein at least one of the first layer and the third layer is doped with a second dopant different from the first dopant.

[0005] An embodiment of the present invention relates to a method including: forming a fin over a substrate; forming a gate structure over the fin; removing a portion of the fin adjacent to the gate structure to form a recess; forming a source / drain component in the recess, wherein the forming of the source / drain component includes: depositing a film including a first element in the recess, wherein the first element in the bottom portion of the film diffuses into the top portion of the recess; substantially removing the top portion of the film; performing a first annealing process on the bottom portion of the film to form a first epitaxial layer; forming a second epitaxial layer over the first epitaxial layer; and forming a third epitaxial layer over the second epitaxial layer, wherein the second epitaxial layer and the third epitaxial layer include a second element different from the first element; and performing a second annealing process on the source / drain component.

[0006] One embodiment of the present invention relates to a method, which includes: providing a semiconductor device including fins formed over a substrate and a gate structure formed over the fins; forming a groove having a first surface adjacent to the gate structure in the fins; and forming source / drain members in the groove, wherein the forming of the source / drain members includes: forming a first epitaxial layer in the groove; forming a second epitaxial layer over the first epitaxial layer, wherein the second epitaxial layer is doped with a first element; and forming a third epitaxial layer over the second epitaxial layer; wherein one or both of the forming of the first epitaxial layer and the forming of the third epitaxial layer includes depositing a film including a second element different from the first element such that the second element in the bottom portion of the film diffuses into one or both of the first surface of the groove and the top surface of the second epitaxial layer to form the first epitaxial layer and the third epitaxial layer, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of brevity of discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0008] Figure 1A and 1B FIG. 1 is a flow chart illustrating an exemplary method for manufacturing a fin field effect transistor (FinFET) device in accordance with various aspects of the present disclosure.

[0009] Figure 2 FIG. 2 is a three-dimensional perspective view of an exemplary FinFET device in accordance with various aspects of the present disclosure.

[0010] Figure 3A 、 4A FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A and 15A are partial cross-sectional views of an exemplary FinFET device along line AA' at different steps of an exemplary manufacturing method in accordance with various aspects of the present disclosure. Figure 2 FIGS. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B and 15B are corresponding to FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A and 15A, respectively, and are partial cross-sectional views of an exemplary FinFET device along line BB' at different steps of an exemplary manufacturing method in accordance with various aspects of the present disclosure.

[0011] Figure 3B 、 4B FIGS. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B and 15B are corresponding to FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A and 15A, respectively, and are partial cross-sectional views of an exemplary FinFET device along line BB' at different steps of an exemplary manufacturing method in accordance with various aspects of the present disclosure. Figure 3A 、 4A FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A and 15A and are partial cross-sectional views of an exemplary FinFET device along line AA' at different steps of an exemplary manufacturing method in accordance with various aspects of the present disclosure. Figure 2Partial cross-sectional view of an exemplary FinFET device along line BB'.

[0012] Figure 16A , 16B , 17A and 17B are partial cross-sectional views of an exemplary FinFET device along line AA' according to various aspects of embodiments of the present disclosure. Figure 2 Partial cross-sectional view of an exemplary FinFET device along line AA'. Detailed Description

[0013] The following disclosure provides many different embodiments or examples for implementing different components of embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify embodiments of the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component are not in direct contact.

[0014] In addition, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself specify a relationship between the various embodiments and / or configurations discussed. Further, in the following embodiments of the present disclosure, a component being formed on, connected to, and / or coupled to another component may include embodiments in which the components are formed in direct contact, and may also include embodiments in which additional components may be formed to sandwich the components such that the components are not in direct contact. In addition, spatially relative terms, such as "below", "above", "horizontal", "vertical", "above", "over", "below", "beneath", "upward", "downward", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used for convenience in relation to one component of an embodiment of the present disclosure to another component. Spatially relative terms are intended to cover different orientations of devices including the components. Furthermore, when a number or a range of numbers is described using "about", "approximately" and similar words, the term is intended to cover numbers within + / - 10% of the described number, unless otherwise specified. For example, the term "about 5 nm" covers dimensions in the range from 4.5 nm to 5.5 nm.

[0015] Embodiments of the present disclosure generally relate to methods of manufacturing semiconductor devices, and more particularly to methods for forming epitaxial source / drain components in fin field-effect transistor (FinFET) devices. The FinFET devices can be, for example, complementary metal-oxide-semiconductor (CMOS) devices, which include p-type metal-oxide-semiconductor (PMOS) FinFET devices and n-type metal-oxide-semiconductor (NMOS) FinFET devices. Although the methods provided herein can also be applied to fabricating planar transistor devices, the following disclosure continues with FinFET examples for illustrative purposes. Although FinFETs have enabled devices to be fabricated with reduced component sizes, there are still many challenges in improving device performance. For example, a shortened channel length can reduce the barrier to the diffusion and outgassing of active dopant species from the source / drain components, resulting in increased resistance and / or other short-channel effects (SCEs), such as drain-induced barrier lowering (DIBL). Accordingly, embodiments of the present disclosure provide methods for controlling the diffusion of active dopant species in the epitaxial source / drain components of FinFET devices.

[0016] Figure 1A and 1B FIG. 6 shows a flowchart of a method 100 for manufacturing a FinFET device in accordance with some aspects of embodiments of the present disclosure. However, it should be understood that the present application is not limited to a particular type of device. Additional steps can be provided before, during, and after the processing methods provided herein, and some of the described steps can be replaced, eliminated, or moved for additional embodiments of the present disclosure.

[0017] Regarding Figures 2 to 17B the cross-sectional view of the exemplary FinFET device 200 depicted in FIG. 6, the processing steps of the method 100 shown in FIG. 6 are described. Figures 1A to 1B FIG. 6 Figure 2 FIG. 7 shows a partial cross-sectional view of a portion of the exemplary FinFET device 200 in a three-dimensional perspective view. Figure 3A 、 4A 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are partial cross-sectional views of the FinFET device 200 taken along the direction AA' of subsequent processing steps of the method 100. Specifically, Figure 2 FIGS. 5A Figure 8A 、 9A 13A, and 14A depict in detail the region 202 of the FinFET device 200. Figure 3B 、 4B 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B are respectively corresponding to Figure 3A 、 4A, the subsequent processing steps of 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A after passing through method 100 along Figure 2 Partial cross-sectional view of FinFET device 200 taken along direction BB' of Figure 16A and 16B Illustrate parts of FinFET device 200 corresponding to Figure 10A and 14A respectively. Figure 17A and 17B are partial cross-sectional views of FinFET device 200 after additional manufacturing steps of method 100 corresponding to Figure 10A and 14A respectively.

[0018] In operation 102 and referring to Figure 2 , 3A and 3B, method 100 ( Figure 1A ) forms generally parallel fins 210 over substrate 206. In the depicted embodiment, two separate regions (first region 202 and second region 204) are provided on substrate 206, but as shown in Figure 2 they may or may not be adjacent to each other. First region 202 may provide NMOS devices and is thus referred to as the NMOS region, and second region 204 may provide PMOS devices and is thus referred to as the PMOS region. As shown in Figure 3A (and subsequent views taken along line AA' of Figure 2 ), first region 202 and second region 204 are depicted side by side for comparison purposes. The fins 210 in both first region 202 and second region 204 are separated by isolation region 208 formed over substrate 206. Each of regions 202 and 204 may include any number of fins 210, but four parallel fins are shown in each of the regions in Figure 2 . Additionally, in various embodiments, regions 202 and 204 may include different numbers of fins 210.

[0019] In many embodiments, the substrate 206 is a semiconductor substrate (e.g., a semiconductor wafer). In some embodiments, the substrate 206 comprises silicon. Alternatively, the substrate 206 comprises other elemental semiconductors, such as germanium; or compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; and alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The substrate 206 may comprise a silicon-on-insulator (SOI) substrate, strained / stressed for performance enhancement, comprising an epitaxial region, comprising isolation regions, comprising doped regions, comprising one or more semiconductor devices (e.g., planar transistors or multi-gate transistors, such as FinFETs) or portions thereof, comprising conductive and / or non-conductive layers, and / or comprising other suitable components and layers.

[0020] In some embodiments, the isolation member 208 comprises, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other suitable dielectric materials, or combinations thereof. The isolation member 208 may comprise different structures, such as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or a local oxidation of silicon (LOCOS) structure.

[0021] The fins 210 may be formed by any suitable process. In some embodiments, forming the fins 210 also results in the formation of the isolation member 208. In an exemplary embodiment, the process may comprise the following steps: one or more processes for patterning a hard mask layer (not shown) over the substrate 206, a process for etching trenches in the substrate 206 not covered by the patterned hard mask layer (e.g., a dry etching and / or a wet etching process), and a process for filling the trenches with one or more insulating materials to form the isolation member 208 (e.g., a chemical vapor deposition process and / or a spin-on glass process). The hard mask layer may be silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, other suitable materials, or combinations thereof and may be formed by any suitable method, such as thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, and / or other suitable methods. The hard mask layer (not shown) may be patterned using one or more lithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the generation of patterns having, for example, a pitch smaller than that which can be obtained otherwise using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate 206 and patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels become the patterned hard mask layer.

[0022] The trenches may be partially filled such that the substrate 206 remaining between the trenches forms fins 210. Alternatively, forming the fins 210 may include: completely filling the trenches with an insulating material; planarizing the top surface of the filled trenches using a polishing process such as chemical mechanical polishing / planarization (CMP) to remove any excess insulating material; and selectively growing one or more layers of epitaxial semiconductor material over the exposed substrate 206, thereby forming the fins 210, wherein the isolation members 208 are placed between the fins 210. The epitaxial semiconductor material may be, for example, silicon, germanium, silicon germanium, other suitable materials, or combinations thereof. In some embodiments, the filled trenches may have a multi-layer structure, such as a thermal oxide liner filled with silicon nitride or silicon oxide. Thus, the fins 210 formed by the embodiments provided herein may include the same material as the substrate 206, or alternatively, they may include one or more layers of epitaxially grown semiconductor material over the substrate 206. In the depicted embodiment, the fins 210 include the same material as the substrate 206.

[0023] At operation 104 and referring to Figure 3A , method 100 ( Figure 1A ) forms a gate structure 212 over the fins 210. In the depicted embodiment, the gate structure 212 is a dummy gate structure that is partially subjected to a high-k metal gate (HK MG) replacement process after performing a high thermal budget process. The dummy gate structure 212 may include a dummy gate electrode 214 (e.g., including polysilicon) and a hard mask layer 216 over the dummy gate electrode 214. In various embodiments, the dummy gate structure 212 may include additional layers, such as an interface layer, a gate dielectric layer, a capping layer, a diffusion / barrier layer, a conductive layer, other suitable layers, and / or combinations thereof. The dummy gate structure 212 may be formed by a series of deposition and etching processes. During a subsequent HK MG process, the dummy gate electrode 214 may be replaced with multiple metal layers to form a conductive electrode, while the dummy gate dielectric layer may be replaced with a high-k gate dielectric layer.

[0024] In some embodiments, the hard mask layer 216 is formed over the dummy gate electrode 214 by a suitable process to accommodate various processes during the implementation of method 100. The hard mask layer 216 may be a single layer or may include multiple layers, each of which may be any suitable material, such as silicon oxide, silicon nitride, titanium nitride, silicon oxynitride, silicon carbide, carbon silicon oxide, or other suitable materials.

[0025] Referring to Figure 4A and 4B, a spacer material layer 220 and 222 can be formed over the dummy gate structure 212 and the fin 210. Layer 220 can form an offset spacer along the sidewalls of the dummy gate structure 212, while layer 222 can form a main spacer adjacent to the offset spacer. The spacer materials 220 and 222 can be similar or different and can each comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, spin-on glass (SOG), low-k materials, tetraethyl orthosilicate (TEOS), plasma enhanced oxide (PE oxide), high aspect ratio process (HARP) formed oxide, other dielectric materials, or combinations thereof. In some embodiments, each of the spacer materials 220 and 222 can include a plurality of material layers. The spacer materials 220 and 222 can be formed by any suitable deposition process such as CVD, PVD, ALD, and / or other suitable processes.

[0026] In operation 106, method 100 ( Figure 1A ) removes a portion of the fin 210 in the NMOS region 202 (or alternatively, in the PMOS region 204). Referring to Figure 5A and 5B , removing a portion of the fin 210 in the NMOS region 202 (or PMOS region 204) includes a series of deposition and patterning processes such as forming a bottom layer 226 (and spacer material layer 222) over the fin 210, forming an intermediate layer 228 over the bottom layer 226, and forming a photoresist layer 230 over the intermediate layer 228. The bottom layer 226 can be a bottom anti-reflective coating (BARC), and the intermediate layer 228 can include a material different from the bottom layer 226 and can comprise a dielectric material such as silicon oxide, silicon nitride, titanium nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and / or other suitable materials. The photoresist layer 230 can comprise any suitable photosensitive material and can be a positive photoresist material (i.e., the exposed areas are removed by a subsequent developing process) or a negative photoresist material (i.e., the unexposed areas are removed by a subsequent developing process).

[0027] In the depicted embodiment ( Figure 5A) In [the process], the photoresist layer 230 is patterned using any suitable lithography process to expose the NMOS region 202 for subsequent etching processes. Subsequently, the intermediate layer 228, the bottom layer 226, and the spacer material layers 220 and 222 can be etched in sequence. The etching process can be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the wet etching process implements an etching solution that includes potassium hydroxide (KOH), ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), tetramethylammonium hydroxide (TMAH), other suitable wet etching solutions, or a combination thereof. In some embodiments, the dry etching process employs an etching gas that includes a fluorine-containing etching gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), an oxygen-containing gas, a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, helium, other suitable gases, and / or a plasma or a combination thereof. In an exemplary embodiment, the etching process is a dry etching process. In the depicted embodiment, the spacer material layers 220 and 222 are anisotropically etched such that a portion of each of the spacer material layers 220 and 222 remains along the sidewalls of the dummy gate structure 212 to form gate spacers.

[0028] Reference Figure 6A and 6B , a portion of the fin 210 in the NMOS region 202 can be subsequently removed to form a groove (i.e., trench) 232 in the fin 210. In the depicted embodiment, the trench 232 is formed in the source / drain region of the fin 210 via a series of etching processes. Each etching process can be a dry etching process, a wet etching process, or a combination thereof as described in detail above. In an exemplary embodiment, the etching process is a dry etching process and is implemented in multiple cycles to form the trench 232. After the series of etching processes, method 100 can remove the bottom layer 226 and the intermediate layer 228 from the PMOS region 204.

[0029] Method 100 then forms source / drain components in the trench 232 as described in detail below. At operation 108 and with reference to Figure 7A and 7B , method 100 ( Figure 1A ) forms a film 234 on the top surface of the trench 232. In the depicted embodiment, before forming the film 234, the top surface of the trench 232 is subjected to a clean / strip process. The clean / strip process can implement a mixture of sulfuric acid and hydrogen peroxide (sulfuric acid hydrogen peroxide mixture or SPM) at a high temperature of about 150 degrees Celsius to about 180 degrees Celsius for about 30 seconds to about 60 seconds.

[0030] In many embodiments, the composition of the film 234 is uniform and includes a first element 240. The first element 240 can be any suitable element, including arsenic, carbon, phosphorus, boron, germanium, indium, other suitable elements, and / or combinations thereof. In one exemplary embodiment, the first element 240 is arsenic. In another exemplary embodiment, the first element 240 is carbon. The film 234 can be formed by any suitable process, including plasma deposition, CVD, PVD, ALD, plasma-assisted CVD (PE-CVD), and / or other suitable processes. In one instance, the material in the bottom portion of the film 234 can penetrate or diffuse into the top surface of the underlying fin 210 in the trench 232. In the depicted embodiment, the film 234 is formed by a plasma deposition process, the details of which are discussed below.

[0031] In many embodiments, operation 108 implements a gas mixture that includes a precursor gas of the first element 240 and one or more carrier gases above the top surface of the trench 232. For embodiments in which the first element 240 is arsenic, the precursor gas can be AsH3. The carrier gas can be any suitable gas, including hydrogen, helium, argon, xenon, other suitable gases, or combinations thereof. In one exemplary embodiment, the gas mixture includes AsH3, hydrogen, and helium. In another exemplary embodiment, the gas mixture includes AsH3, hydrogen, and argon. In yet another exemplary embodiment, the gas mixture includes AsH3, hydrogen, and xenon. The concentration of AsH3 in the gas mixture can be less than about 10%.

[0032] The implementation of the gas mixture can be affected by several operating parameters, including the tilt bias voltage, the power of the radio frequency (RF) source, the dose or concentration of the precursor gas relative to (each) carrier gas, the flow rate of the gas mixture, and the duration of the deposition. In the depicted embodiment, the bias voltage is about 2 kV, the RF power is from about 500 W to about 1500 W, the dose of the precursor gas is from about 1×10^16 to about 4×10^21, the flow rate is from about 90 scm (standard cubic meters) to about 150 scm or from about 5 mT (millitorr) to about 100 millitorr, and the duration of the deposition is less than about 150 ms.

[0033] After operation 108, refer to Figure 8A and 8B Method 100 ( Figure 1A)Operation 110 is performed, during which the top portion 258 of the film 234 is removed by a cleaning process. In the depicted embodiment, operation 110 is performed by applying a cleaning solvent 256 (e.g., SPM) at a high temperature of about 150 degrees Celsius to about 180 degrees Celsius for about 30 seconds to about 120 seconds. In many embodiments, the cleaning process is performed such that it selectively removes only the top portion 258 of the film 234, leaving the bottom portion of the film 234 that has penetrated the top surface of the trench 232 (i.e., the fin 210). On the one hand, if the temperature is higher than about 180 degrees Celsius and / or if the cleaning process is performed for longer than about 60 seconds, then the bottom portion of the film 234 that has penetrated the top surface of the trench 232 may be accidentally removed, leaving an insufficient amount of the first element 240 for subsequent formation of a semiconductor layer (e.g., the first layer 260 described below). On the other hand, if the temperature is lower than about 150 degrees Celsius and / or if the cleaning process is performed for shorter than about 30 seconds, then an excessive amount of the film 234 may remain above the top surface of the trench 232, thereby hindering the formation of the semiconductor layer during a subsequent annealing process (e.g., operation 112 described below). In some embodiments, the spacer material layer 222 is removed after the cleaning process in operation 108.

[0034] Subsequently, in operation 112, method 100 ( Figure 1A ) applies a first annealing process to the remaining portion of the film 234. In an exemplary embodiment, operation 112 is performed at a temperature of about 900 degrees Celsius to about 1050 degrees Celsius for from about 1 second to 2 seconds. In many embodiments, referring to Figure 9A and 9B , operation 112 causes the first element 240 to react with the composition of the fin 210 in the trench 232 to form the first layer 260. In many embodiments, the first annealing process is performed at a temperature within the range described above such that sufficient thermal energy is supplied to activate the dopant species (e.g., the first element 240) and / or repair the crystal structure of the first layer 260. However, if the temperature is too high or the annealing time is too long (i.e., longer than about 2 seconds), then the resulting electrical properties of the first layer 260 may be impaired.

[0035] In many embodiments, the first layer 260 comprises an epitaxial semiconductor material doped with a first element (i.e., dopant species) 240. The epitaxial semiconductor material can be any suitable material, including single-element semiconductor materials such as silicon (Si) or germanium (Ge); compound semiconductor materials such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs); or semiconductor alloys such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP). In an exemplary embodiment, the first element 240 is arsenic, and the epitaxial semiconductor material is silicon. In another exemplary embodiment, the first element 240 is carbon, and the epitaxial semiconductor material is silicon germanium.

[0036] In an alternative embodiment, a first layer 260 is formed directly above the trench 232 of the fin 210 by epitaxially growing a semiconductor material (e.g., silicon, silicon germanium, etc.) while in-situ introducing a first element 240. In one such instance, a selective epitaxial growth (SEG) process is performed to grow the first layer 260, during which the first element 240 can be introduced by adding a doping species to the source material of the SEG process. The SEG process can be implemented using CVD techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low pressure CVD (LP-CVD), and / or PE-CVD), molecular beam epitaxy, other suitable SEG processes, or a combination thereof. The SEG process can use gas precursors (e.g., silicon-containing gases such as SiH4 and / or germanium-containing gases such as GeH4) and / or liquid precursors, which interact with the composition of the fin 210 to form the first layer 260. Any suitable process (e.g., in-situ doping process, ion implantation process, diffusion process, or a combination thereof) can be implemented to introduce the first element 240 into the first layer 260 during the SEG process. In yet another alternative embodiment, the first layer 260 is formed directly by a suitable deposition process (e.g., ALD). After the epitaxial growth and doping processes, one or more annealing processes can be performed to activate the first element 240 in the first layer 260. The annealing process can include rapid thermal annealing (RTA), laser annealing process, and / or other suitable annealing processes.

[0037] Reference Figure 10A and 10B , at operations 114 and 116, method 100 ( Figure 1B ) forms a second layer 236 above the first layer 260 and a third layer 238 above the second layer 236. In many embodiments, the second layer 236 and the third layer 238 each include an epitaxially grown semiconductor material doped with a second element (i.e., doping species) 242. It should be understood that the second layer 236 and the third layer 238 can include the same epitaxially grown semiconductor material, but can contain different concentrations of the second element 242. For example, the concentration of the second element 242 in the second layer 236 can be greater than the concentration of the second element 242 in the third layer 238. The epitaxially grown semiconductor material of the second layer 236 and the third layer 238 can be any suitable material, including single element semiconductor materials such as silicon (Si) or germanium (Ge); compound semiconductor materials such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs); or semiconductor alloys such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP). The second element 242 can be any suitable element, including phosphorus, boron, arsenic, carbon, germanium, indium, other suitable elements, and / or a combination thereof.

[0038] In the depicted embodiment, the first layer 260, the second layer 236, and the third layer 238 comprise the same epitaxially grown semiconductor material. In one such instance, the first layer 260, the second layer 236, and the third layer 238 all comprise silicon. In another such instance, the first layer 260, the second layer 236, and the third layer 238 all comprise silicon germanium. However, in many embodiments, the first element 240 is different from the second element 242 and has a higher atomic weight (i.e., higher atomic number) than the second element 242. For embodiments in which the epitaxially grown material is silicon, the first element 240 is arsenic and the second element 242 is phosphorus. For embodiments in which the epitaxially grown material is silicon germanium, the first element 240 is carbon and the second element 242 is boron.

[0039] The method of forming the second layer 236 and the third layer 238 may be similar to the method discussed above with respect to forming the first layer 260. In one instance, the second layer 236 and the third layer 238 may each be formed by a plasma deposition process (e.g., operation 108) using a gas mixture comprising a precursor material for the second element 242, followed by a cleaning process (e.g., operation 110) and an annealing process (e.g., operation 112). In another instance, the second layer 236 and the third layer 238 may each be formed by epitaxially growing a semiconductor material using a deposition process (e.g., SEG) and in-situ doping the second element 242 during epitaxial growth, followed by one or more annealing processes (e.g., RTA, laser annealing, etc.).

[0040] As an alternative to operations 108, 110, 112, 114, and 116, method 100 may implement operations 118, 120, 122, and 124 as depicted in Figure 1A and 1B In operations 118 and 120, method 100 ( Figure 1A ) forms the first layer 260 in the trench 232 and then forms the second layer 236 above the first layer 260 ( Figure 11A and 11B)。In the depicted embodiment, each of the first layer 260 and the third layer 236 comprises an epitaxially grown semiconductor material doped with a second element (i.e., dopant species) 242. The epitaxially grown semiconductor materials of the first layer 260 and the second layer 236 may be similar to the materials discussed above and may be a single-element semiconductor material such as silicon (Si) or germanium (Ge); a compound semiconductor material such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs); or a semiconductor alloy such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP). In many embodiments, the first layer 260 and the second layer 236 comprise the same epitaxially grown semiconductor material; however, the concentration of the second element 242 is different between the two semiconductor layers. In one example, the concentration of the second element 242 in the second layer 236 is higher than the concentration of the second element 242 in the first layer 260. The second element 242 has been discussed in detail above and may be any suitable element, including phosphorus, boron, arsenic, carbon, germanium, indium, other suitable elements, and / or combinations thereof. In an exemplary embodiment, the epitaxially grown semiconductor material is silicon and the second element 242 is phosphorus. In another exemplary embodiment, the epitaxially grown semiconductor material is silicon germanium and the second element 242 is boron.

[0041] The first layer 260 and the second layer 236 may be formed using any suitable method as discussed above. In an exemplary embodiment, the first layer 260 and the second layer 236 are each formed by epitaxially growing a semiconductor material and in-situ introducing the second element 242 during the epitaxial growth process. In one such example, an SEG process is performed to grow the first layer 260 and the second layer 236, during which the second element 242 may be introduced by adding a dopant species to a source material of the SEG process. SEG may be implemented using CVD deposition techniques such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low pressure CVD (LP-CVD), and / or PE-CVD, molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The SEG process may use gas precursors such as silicon-containing gases such as SiH4 and / or germanium-containing gases such as GeH4 and / or liquid precursors which interact with the composition of the trenches 232 of the fin 210 to form the first layer 260 and, in a subsequent process, form the second layer 236 over the first layer 260. Any suitable process such as an in-situ doping process, an ion implantation process, a diffusion process, or combinations thereof may be implemented to introduce the second element 242 into the epitaxial growth process. In yet another alternative embodiment, the first layer 260 and the second layer 236 are each formed by a suitable deposition process such as ALD. After the epitaxial growth and doping processes, one or more annealing processes may be performed to activate the second element 242 in the semiconductor layers. The annealing process may include rapid thermal annealing (RTA), laser annealing processes, and / or other suitable annealing processes.

[0042] At operation 122, method 100( Figure 1B ) deposits film 246 above the top surface of the second layer 236( Figure 12A and 12B ). In many embodiments, the composition of film 246 is uniform and includes a first element 240. The first element 240 has been discussed in detail above and may include arsenic, carbon, phosphorus, boron, germanium, indium, other suitable elements, and / or combinations thereof. In one exemplary embodiment, the first element 240 is arsenic. In another exemplary embodiment, the first element 240 is carbon.

[0043] In the depicted embodiment, film 246 is formed by a plasma deposition process that has been discussed in detail above. Briefly, the plasma deposition process implements a gas mixture that includes a precursor gas for the first element 240 and one or more carrier gases above the top surface of the second layer 236. For embodiments in which the first element 240 is arsenic, the precursor gas may be AsH3, and the carrier gas may include hydrogen, helium, argon, and / or xenon. In many embodiments, the concentration of AsH3 in the gas mixture may be less than about 10%. In the depicted embodiment, the plasma deposition process is implemented using: a bias of about 2 kV; an RF power of about 500 W to about 1500 W; a dose of the precursor gas of about 1×10^16 to about 4×10^21; a flow rate of about 90 sccm to about 150 sccm or about 5 mTorr to about 100 mTorr; and a deposition duration of less than about 150 ms.

[0044] After the plasma deposition process, referring to Figure 13A and 13B , method 100( Figure 1B ) implements operation 124, during which the top portion 262 of film 246 is removed by a cleaning process similar to operation 110 discussed above. In the depicted embodiment, operation 124 is implemented by applying a cleaning solvent 256 (e.g., SPM) at a high temperature of about 150 degrees Celsius to about 180 degrees Celsius for about 30 seconds to about 60 seconds.

[0045] Subsequently, at operation 126, method 100( Figure 1B)Apply a second annealing process, which can be implemented at a temperature from about 1000 degrees Celsius to about 1200 degrees Celsius for less than about 10 ms (milliseconds). The second annealing process is designed to activate a first element 240 (i.e., a doping species) formed in or above the top surface of the second layer 236 to enhance device performance. On the one hand, if the temperature of the second annealing process is higher than about 1200 degrees Celsius, then the dopant profile of the first element 240 has been changed by overheating. On the other hand, if the temperature of the second annealing process is lower than about 1000 degrees Celsius, then the first element 240 may not be sufficiently activated to achieve the desired device performance. The rapid annealing time achieves the desired heat for activating the first element 240 while minimizing the thermal budget of the underlying second layer 236. In some embodiments, refer to Figure 10A and 10B , and perform operation 126 to activate a doping species (e.g., a second element 242) present in the source / drain members of the FinFET device 200. In some embodiments, refer to Figure 14A and 14B , and operation 126 causes the first element 240 to react with the composition of the second layer 236 to form a third layer 238.

[0046] In many embodiments, the third layer 238 comprises an epitaxial semiconductor material doped with a first element (i.e., a doping species) 240. The epitaxial semiconductor material in the third layer 238 can be any suitable material, including single-element semiconductor materials such as silicon (Si) or germanium (Ge); compound semiconductor materials such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs); or semiconductor alloys such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP). In the depicted embodiment, the epitaxial semiconductor material in the third layer 238 is the same as the epitaxial semiconductor materials in the first layer 260 and the second layer 236; however, both the first layer 260 and the second layer 236 include a second element (i.e., a doping species) 242, while the third layer 238 includes the first element 240. In an exemplary embodiment, the first element 240 and the second element 242 as discussed above are different elements, and the first element 240 has an atomic weight (i.e., atomic number) greater than that of the second element 242. In one such example, the first element 240 is arsenic, the second element 242 is phosphorus, and the epitaxial semiconductor material is silicon. In another such example, the first element 240 is carbon, the second element 242 is boron, and the epitaxial semiconductor material is silicon germanium.

[0047] In an alternative embodiment, a third layer 238 is formed directly above the top surface of the second layer 236 by epitaxially growing a semiconductor material (e.g., silicon, silicon germanium, etc.) while in-situ introducing a first element 240. In one such example, a SEG process is performed to grow the third layer 238, during which the first element 240 is introduced as discussed in detail above. Any suitable process (e.g., an in-situ doping process, an ion implantation process, a diffusion process, or a combination thereof) can be implemented to introduce the first element 240 into the third layer 238. In yet another alternative embodiment, the third layer 238 is formed by a suitable deposition process (e.g., ALD). After the epitaxial growth and doping processes, one or more annealing processes can be performed to activate the first element 240 in the third layer 238. The annealing process can include rapid thermal annealing (RTA), a laser annealing process, and / or other suitable annealing processes.

[0048] As Figure 15A and 15B illustrated in, method 100 can provide yet another embodiment including a first layer 260 formed in trench 232 of fin 210 comprising epitaxial semiconductor material doped with a first element 240; a second layer 236 formed above the first layer 260 comprising the same epitaxial semiconductor material as the first layer 260 but doped with a second element 242; and a third layer 238 comprising the same epitaxial semiconductor material as the first layer 260 and doped with the first element 240. In one example, the epitaxial semiconductor material can be silicon, the first element 240 can be arsenic, and the second element 242 can be phosphorus. In another example, the epitaxial semiconductor material can be silicon germanium, the first element 240 can be carbon, and the second element 242 can be boron. The first layer 260, the second layer 236, and the third layer 238 can each be formed using any of the methods discussed above. Specifically, the first layer 260 and the third layer 238 can each be formed using a plasma deposition process (e.g., operations 108 and 122), followed by a cleaning process as detailed above (e.g., operations 110 and 124) and a subsequent annealing process (e.g., operations 112 and 126).

[0049] In an exemplary embodiment, with reference to the depiction of Figure 10A a portion of Figure 16A, Method 100 forms a source / drain member 270 that includes a first layer 260 (i.e., the lower layer 260), a second layer 236 (i.e., the middle layer 236), and a third layer 238 (i.e., the upper layer 238). Among them, the first layer 260 includes epitaxially grown semiconductor material doped with a first element (i.e., a doping species) 240, and each of the second layer 236 and the third layer 238 includes the same epitaxially grown semiconductor material doped with a second element (i.e., a doping species) 242 different from the first element 240. As provided herein, the first element 240 has a higher atomic weight (i.e., a higher atomic number) than the second element 242. Specifically, the epitaxially grown semiconductor material can be silicon, the first element 240 can be arsenic, and the second element 242 can be phosphorus. Alternatively, the epitaxially grown semiconductor material can be silicon germanium, the first element 240 can be carbon, and the second element 242 can be boron. In the depicted embodiment, the second layer 236 is embedded within the first layer 260 such that the second layer 236 is physically separated from the fin 210 by a distance 266. In many embodiments, the second element 242 diffuses from the second layer 236 after a thermal annealing process (e.g., operation 126). The loss of the second element 242 into other components of the FinFET device 200 can result in increased device resistance in the source / drain regions and short-channel effects, such as DIBL discussed above. When the first layer 260 includes a different doping species (i.e., the first element 240), the diffusion of the second element 242 in the second layer 236 from the source / drain member 270 is prevented. Thus, in many embodiments, the diffusion distance of the second element 242 achieved by operation 126 (i.e., the second annealing process) is shortened by a distance 266, and the distance 266 is the thickness of the first layer 260 as shown in Figure 16A . In one such instance, the distance 266 is from about 2 nm (nanometers) to about 10 nm. On the one hand, if the distance 266 is less than about 2 nm, then an undesirable distribution of the doping species is produced, and the performance of the source / drain member 270 can be degraded. On the other hand, if the distance 266 is greater than about 10 nm, then a high risk of current leakage (i.e., short-channel effect) is prevalent.

[0050] In another exemplary embodiment, referring to the portion depicted in Figure 14A of Figure 16B , Method 100 forms a source / drain member 270 that includes a first layer 260, a second layer 236, and a third layer 238. Each of the first layer 260 and the second layer 236 includes epitaxially grown semiconductor material doped with a second element (i.e., a doping species) 242, and the third layer 238 includes the same epitaxially grown semiconductor material doped with a first element (i.e., a doping species) 240. Similar to Figure 16AIn the embodiment depicted, the epitaxially grown semiconductor material can be silicon, the first element 240 can be arsenic, and the second element 242 can be phosphorus. Alternatively, the epitaxially grown semiconductor material can be silicon germanium, the first element 240 can be carbon, and the second element 242 can be boron. In the present example, due to the inclusion of the first dopant 240, the third layer 238 acts as a barrier layer to prevent the upward diffusion of the second element 242 and the diffusion from the source / drain member 270.

[0051] Subsequently, at operation 128, the method 100 ( Figure 1B ) performs additional fabrication steps on the FinFET device 200. Referring to Figure 17A and 17B , operation 128 can include replacing the dummy gate structure 212 with a high-k metal gate structure in a gate replacement process, which includes forming a high-k gate dielectric layer (not shown) over the fin 210 and forming a metal gate electrode 218 over the high-k gate dielectric layer. The high-k metal gate structure can include additional layers, e.g., a capping layer, an interface layer, a diffusion layer, a barrier layer, a hard mask layer, or a combination thereof. The metal gate electrode 218 can include multiple metal layers (e.g., a bulk conductive layer, a work function layer, etc.). In some embodiments, replacing the dummy gate structure 212 includes several procedures. For example, the gate replacement process can include: depositing a contact etch stop layer CESL 250 over the source / drain member 270; depositing and planarizing an ILD layer 252 around the source / drain member 270 and the dummy gate structure 212; removing the dummy gate electrode 214 via a series of patterning and etching procedures to form a trench (not shown); and forming a high-k metal gate structure in the trench. Additionally, the metal contact member 254 can also be formed over the source / drain member 270 via a series of patterning, etching, and deposition procedures.

[0052] The FinFET device 200 formed according to various embodiments provided herein may be included in a microprocessor, a memory, and / or other integrated circuit devices. In some embodiments, the FinFET device 200 may be a part of an IC chip, a system-on-chip (SoC), or a part thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, metal-oxide semiconductor field-effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. Additional components may be added to the FinFET device 200 through subsequent processing steps. For example, various vertical interconnect components (such as contacts and / or vias) and / or horizontal interconnect components (such as lines) and multi-level interconnect components (such as metal layers and interlayer dielectrics) may be formed above the substrate 206, which are configured to connect various components or structures of the FinFET 200. The various interconnect components may implement various conductive materials, including aluminum, aluminum alloys (such as aluminum / silicon / copper alloys), copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, other suitable metals, or combinations thereof. The metal silicides may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof.

[0053] Although not intended to be limiting, one or more embodiments of the present disclosure provide improvements to semiconductor devices and methods of manufacturing the same. For example, embodiments of the present disclosure provide a method of reducing the diffusion of a primary dopant species from a source / drain component in a FinFET device by introducing a secondary dopant species in at least a portion of the source / drain component. Specifically, by implementing a plasma deposition process, a semiconductor layer including the secondary dopant species may be formed as a diffusion barrier layer that separates a semiconductor layer doped with the primary dopant species from the surrounding components of the device (such as fins, gates, etc.). Thus, embodiments of the present disclosure ensure that a desired concentration of the primary dopant species can be maintained within the source / drain component, and potential short-channel effects can be minimized in the FinFET device.

[0054] Accordingly, the present disclosure provides many different embodiments of a metal gate in a semiconductor device and a method of manufacturing the same. In one aspect, embodiments of the present disclosure provide a device that includes a fin above a substrate, a gate structure above the fin, and an epitaxial source / drain component above the fin and adjacent to the gate structure. In some embodiments, the epitaxial source / drain component includes a first layer, a second layer above the first layer, and a third layer above the second layer, where the second layer is doped with a first dopant, and where at least one of the first layer and the third layer is doped with a second dopant different from the first dopant. In some embodiments, both the first layer and the third layer are doped with the second dopant.

[0055] In some embodiments, the first layer is doped with a second dopant, and the second layer is physically separated from the fin. In other embodiments, the separation distance between the second layer and the fin is between about 2 nanometers and about 10 nanometers. In further embodiments, the diffusion distance of the first dopant in the second layer is less than the separation distance.

[0056] In some embodiments, the second dopant has an atomic weight greater than that of the first dopant. In further embodiments, the first dopant is phosphorus and the second dopant is arsenic.

[0057] In another aspect, embodiments of the present disclosure provide a method that includes: forming a fin over a substrate; forming a gate structure over the fin; removing a portion of the fin adjacent to the gate structure to form a recess (i.e., a trench); forming source / drain components in the recess; and performing a second annealing process on the source / drain components. In some embodiments, forming the source / drain components includes: depositing a film containing a first element in the recess, wherein the first element in the bottom portion of the film diffuses into the top surface of the recess; substantially removing the top portion of the film; performing a first annealing process on the bottom portion of the film to form a first epitaxial layer; forming a second epitaxial layer over the first epitaxial layer; and forming a third epitaxial layer over the second epitaxial layer. In some embodiments, the second epitaxial layer and the third epitaxial layer contain a second element different from the first element.

[0058] In some embodiments, substantially removing the top portion of the film includes exposing the film to a mixture of sulfuric acid and hydrogen peroxide at a temperature between about 150 degrees Celsius and about 180 degrees Celsius for a duration between about 30 seconds and about 65 seconds.

[0059] In some embodiments, performing the first annealing process is carried out at a temperature between about 900 degrees Celsius and about 1000 degrees Celsius for a duration between about 1 second and about 2 seconds.

[0060] In some embodiments, performing the second annealing process is carried out at a temperature between about 1000 degrees Celsius and about 1200 degrees Celsius for a duration less than about 10 milliseconds.

[0061] In some embodiments, depositing the film includes exposing the top surface of the recess to a dose of plasma containing the first element and a carrier gas, the carrier gas having hydrogen, helium, or a combination thereof. In further embodiments, the first element is arsenic and the second element is phosphorus. In some embodiments, the first element is boron and the second element is carbon.

[0062] In another aspect, embodiments of the present disclosure provide a method that includes: providing a semiconductor device that includes fins formed over a substrate and a gate structure formed over the fins; forming a groove having a first surface adjacent to the gate structure in the fins; and forming source / drain members in the groove. In some embodiments, forming the source / drain members includes: forming a first epitaxial layer in the groove; forming a second epitaxial layer over the first epitaxial layer; and forming a third epitaxial layer over the second epitaxial layer. In some embodiments, the second epitaxial layer is doped with a first element. In further embodiments, forming one or both of the first epitaxial layer and the third epitaxial layer includes depositing a film that includes a second element different from the first element such that the second element in a bottom portion of the film diffuses into one or both of the first surface of the groove and the top surface of the second epitaxial layer to form the first epitaxial layer and the third epitaxial layer, respectively.

[0063] In some embodiments, depositing the film includes performing a plasma deposition process. In further embodiments, depositing the film includes implementing a dose of plasma that includes the first element and a carrier gas that has hydrogen, helium, or a combination thereof. In other embodiments, depositing the film includes performing an atomic layer deposition process.

[0064] In some embodiments, forming one or both of the first epitaxial layer and the third epitaxial layer further includes substantially removing a top portion of the film and performing a first annealing process on the film at a temperature between about 900 degrees Celsius and about 1000 degrees Celsius for a duration between about 1 second and about 2 seconds. In some embodiments, removing the top portion includes exposing the film to a mixture of sulfuric acid and hydrogen peroxide at a temperature between about 150 degrees Celsius and about 180 degrees Celsius for a duration between about 30 seconds and about 65 seconds.

[0065] In some embodiments, forming one or both of the first epitaxial layer and the third epitaxial layer further includes performing a second annealing process after the execution of the first annealing process, wherein the second annealing process is implemented at a temperature between about 1000 degrees Celsius and about 1200 degrees Celsius for a duration of less than about 10 milliseconds.

[0066] In yet another aspect, embodiments of the present disclosure provide a method that includes: forming fins over a substrate; forming a gate structure over the fins; removing a portion of the fins adjacent to the gate structure to form a recess; and forming source / drain components in the recess. In some embodiments, forming the source / drain components includes: forming a first epitaxial layer in the recess; forming a second epitaxial layer over the first epitaxial layer; forming a third epitaxial layer over the second epitaxial layer; and doping each of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer with a first doping species or a second doping species different from the first doping species such that the second epitaxial layer includes the first doping species and at least one of the first epitaxial layer and the third epitaxial layer includes the second doping species.

[0067] In some embodiments, doping is performed while forming the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer. In some embodiments, both the first epitaxial layer and the third epitaxial layer are doped with the second doping species. In some embodiments, the first epitaxial layer is doped with the second doping species and the third epitaxial layer is doped with the first doping species. In further embodiments, the method further includes doping the first epitaxial layer with the first doping species and doping the third epitaxial layer with the second doping species.

[0068] In some embodiments, the first doping species is phosphorus and the second doping species is arsenic. In some embodiments, the first doping species is boron and the second doping species is carbon.

[0069] The foregoing has outlined features of several embodiments so that those of ordinary skill in the art may better understand aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can readily use the embodiments of the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments described herein. Those of ordinary skill in the art should also understand that these equivalent constructs do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

[0070] Symbol Explanation

[0071] 100 Method

[0072] 102 Operation

[0073] 104 Operation

[0074] 106 Operation

[0075] 108 Operation

[0076] 110 Operation

[0077] 112 Operation

[0078] 114 Operation

[0079] 116 Operation

[0080] 118 Operation

[0081] 120 Operation

[0082] 122 Operation

[0083] 124 Operation

[0084] 126 Operation

[0085] 128 Operation

[0086] 200 Fin Field-Effect Transistor (FinFET) Device

[0087] 202 First Region

[0088] 204 Second Region

[0089] 206 Substrate

[0090] 208 Isolation Region

[0091] 210 Fin

[0092] 212 Gate Structure

[0093] 214Dummy Gate Electrode

[0094] 216 Hard Mask Layer

[0095] 218 Metal Gate Electrode

[0096] 220 Spacer Material / Spacer Material Layer

[0097] 222 Spacer Material / Spacer Material Layer

[0098] 226 Bottom Layer

[0099] 228 Intermediate Layer

[0100] 230 Photoresist Layer

[0101] 232 Groove / Trench

[0102] 234 Film

[0103] 236 Second Layer / Intermediate Layer

[0104] 238 Third Layer / Upper Layer

[0105] 240 First Element

[0106] 242 Second Element

[0107] 246 film

[0108] 250 Contact Etch Stop Layer CESL

[0109] 252 ILD layer

[0110] 254 Metal contact member

[0111] 256 Cleaning solvent

[0112] 258 Top part

[0113] 260 First layer / Lower layer

[0114] 262 Top part

[0115] 266 Distance

[0116] 270 Source / drain member

Claims

1. A method, comprising: Forming fins above a substrate; Forming a gate structure above the fins; Removing a portion of the fins adjacent to the gate structure to form a groove; Forming source / drain members in the groove, wherein forming the source / drain members comprises: Depositing a film containing a first element in the groove, wherein the first element in a portion of the film penetrates the bottom and sidewall surfaces of the groove to form a diffusion layer; Removing a top portion of the film to expose the bottom and sidewall surfaces of the groove; Thereafter, performing a first annealing process on the diffusion layer to form a first epitaxial layer; Forming a second epitaxial layer above the first epitaxial layer such that the second epitaxial layer contacts the bottom and sidewall surfaces of the groove; and Forming a third epitaxial layer above the second epitaxial layer, wherein the second epitaxial layer and the third epitaxial layer contain a second element different from the first element, wherein both the first element and the second element have the same conductivity type and are both n-type dopants, and wherein the concentration of the second element in the second epitaxial layer is greater than the concentration of the second element in the third epitaxial layer; and Performing a second annealing process on the source / drain members.

2. The method according to claim 1, wherein removing the top portion of the film comprises exposing the film to a mixture of sulfuric acid and hydrogen peroxide at a temperature between about 150 degrees Celsius and about 180 degrees Celsius for a duration between about 30 seconds and about 65 seconds.

3. The method according to claim 1, wherein performing the first annealing process is carried out at a temperature between about 900 degrees Celsius and about 1000 degrees Celsius for a duration between about 1 second and about 2 seconds.

4. The method according to claim 1, wherein performing the second annealing process is carried out at a temperature between about 1000 degrees Celsius and about 1200 degrees Celsius for a duration of less than about 10 milliseconds.

5. The method according to claim 1, wherein depositing the film comprises exposing the bottom and sidewall surfaces of the groove to a dose of plasma containing the first element and a carrier gas, wherein the carrier gas comprises hydrogen, helium, or a combination thereof.

6. The method according to claim 5, wherein the first element is arsenic and the second element is phosphorus.

7. The method according to claim 1, wherein forming the second epitaxial layer or the third epitaxial layer comprises performing an in-situ epitaxial process.

8. A method, comprising: Performing a first etching process on a top portion of fins disposed above a semiconductor substrate to form trenches in the fins; Forming a material layer containing a first element in the trenches, wherein a portion of the material layer diffuses into the fins to form a buried layer below the bottom and sidewall surfaces of the trenches; Performing a second etching process to remove a top portion of the material layer above the buried layer; After performing the second etching process, performing a first annealing treatment on the buried layer; Form a first epitaxial semiconductor layer containing a second element on the annealed buried layer, wherein the first element and the second element have the same conductivity type, and wherein the first element is arsenic; Form a second epitaxial semiconductor layer containing the second element above the first epitaxial semiconductor layer; And Perform a second annealing process on the first epitaxial semiconductor layer and the second epitaxial semiconductor layer, wherein the concentration of the second element in the first epitaxial semiconductor layer is greater than the concentration of the second element in the second epitaxial semiconductor layer.

9. The method according to claim 8, wherein forming the first epitaxial semiconductor layer and the second epitaxial semiconductor layer each comprises forming a silicon-containing epitaxial semiconductor layer doped with phosphorus.

10. The method according to claim 8, wherein forming the material layer comprises performing a plasma deposition process, and wherein forming the first epitaxial semiconductor layer or the second epitaxial semiconductor layer comprises performing a selective epitaxial growth process.

11. The method according to claim 8, wherein forming the material layer comprises performing an atomic layer deposition process, and wherein forming the first epitaxial semiconductor layer or the second epitaxial semiconductor layer comprises performing a selective epitaxial growth process.

12. The method according to claim 8, wherein performing the second etching process comprises treating the material layer with a cleaning mixture, and wherein the cleaning mixture comprises sulfuric acid and hydrogen peroxide.

13. The method according to claim 8, wherein the second annealing process is performed at a higher temperature than the first annealing process.

14. A method, comprising: Recessing a semiconductor fin disposed above a substrate; Depositing a dopant-containing layer above the recessed semiconductor fin, wherein a first portion of the dopant-containing layer is embedded below the bottom and sidewall surfaces of the recessed semiconductor fin, and wherein the dopant-containing layer comprises a first dopant; Removing a second portion of the dopant-containing layer disposed above the first portion, thereby exposing the bottom and sidewall surfaces of the recessed semiconductor fin; After removing the second portion, annealing the first portion of the dopant-containing layer; After annealing the first portion, depositing a first epitaxial layer on the first portion of the dopant-containing layer; Depositing a second epitaxial layer above the first epitaxial layer to form a source / drain (S / D) component, wherein the first epitaxial layer and the second epitaxial layer comprise a second dopant different from the first dopant, and wherein the second dopant has the same conductivity type as the first dopant; and Annealing the first epitaxial layer and the second epitaxial layer, wherein the concentration of the second dopant in the first epitaxial layer is greater than the concentration of the second dopant in the second epitaxial layer.

15. The method according to claim 14, wherein annealing the first portion of the dopant-containing layer forms an epitaxial silicon-containing semiconductor layer doped with the first dopant.

16. The method according to claim 14, wherein depositing the dopant-containing layer comprises performing a plasma deposition process, and wherein depositing the first epitaxial layer or the second epitaxial layer comprises performing an in-situ epitaxial process.

17. The method according to claim 1, wherein removing the top portion of the film comprises cleaning the film with a sulfuric acid and hydrogen peroxide mixture (SPM).

18. The method according to claim 12, wherein treating the material layer with the cleaning mixture is performed at a temperature of from about 150 degrees Celsius to about 180 degrees Celsius.

19. The method according to claim 14, wherein the first dopant is arsenic and the second dopant is phosphorus.

20. The method according to claim 14, wherein depositing the first epitaxial layer causes the first epitaxial layer to have a first concentration of the second dopant, wherein depositing the second epitaxial layer causes the second epitaxial layer to have a second concentration of the second dopant, and wherein the first concentration is higher than the second concentration.

21. A semiconductor device, comprising: a fin above a substrate; a gate structure above the fin; and an epitaxial source / drain member adjacent to the gate structure, wherein the epitaxial source / drain member comprises a first layer in the fin, a second layer above the first layer, and a third layer above the second layer, wherein the second layer and the third layer are doped with a first dopant, and wherein the concentration of the first dopant in the second layer is greater than the concentration of the first dopant in the third layer, wherein the first layer is doped with a second dopant different from the first dopant, and the first dopant and the second dopant have the same conductivity type.

22. The semiconductor device according to claim 21, wherein the first layer, the second layer, and the third layer have the same semiconductor material.

23. The semiconductor device according to claim 22, wherein the second dopant has a higher atomic weight than the first dopant.

24. The semiconductor device according to claim 21, wherein the first layer separates the second layer from the fin.

25. The semiconductor device according to claim 24, wherein the diffusion distance of the first dopant in the second layer is less than the thickness of the first layer.

26. The semiconductor device according to claim 22, wherein the first dopant is boron and the second dopant is carbon.

27. The semiconductor device according to claim 22, wherein the first dopant is phosphorus and the second dopant is arsenic.

28. A semiconductor device, comprising: a semiconductor layer disposed above a substrate; a metal gate stack disposed above a channel region of the semiconductor layer; and A source / drain component adjacent to the metal gate stack, wherein the source / drain component includes a first epitaxial layer disposed in the semiconductor layer, a second epitaxial layer disposed above the first epitaxial layer, and a third epitaxial layer disposed above the second epitaxial layer, wherein the second epitaxial layer and the third epitaxial layer are doped with a first dopant, and wherein the concentration of the first dopant in the second epitaxial layer is greater than the concentration of the first dopant in the third epitaxial layer. Wherein the first epitaxial layer is doped with a second dopant different from the first dopant, and the first dopant and the second dopant have the same conductivity type.

29. The semiconductor device according to claim 28, wherein the first epitaxial layer physically separates the second epitaxial layer from the semiconductor layer.

30. The semiconductor device according to claim 29, wherein the second dopant has a higher atomic weight than the first dopant.

31. The semiconductor device according to claim 29, wherein the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer have the same semiconductor material.

32. The semiconductor device according to claim 28, wherein the first epitaxial layer is configured in a U shape.

33. The semiconductor device according to claim 28, wherein the first epitaxial layer is embedded in the top portion of the semiconductor layer.

34. The semiconductor device according to claim 28, wherein the first dopant is phosphorus and the second dopant is arsenic.

35. A device comprising: A fin above a semiconductor substrate; A gate structure above the fin; And An epitaxial source / drain component adjacent to the gate structure, wherein the epitaxial source / drain component includes a first layer in the fin, a second layer surrounded by the first layer, and a third layer above the second layer, wherein the first layer is doped with a first dopant at a first concentration, and wherein the second layer and the third layer are doped with a second dopant having a higher atomic weight than the first dopant, and the first dopant and the second dopant have the same conductivity type. Wherein the concentration of the second dopant in the second layer is greater than the concentration of the second dopant in the third layer.

36. The device according to claim 35, wherein the first layer physically separates the second layer from the fin.

37. The device according to claim 36, wherein the spacing distance between the second layer and the fin is between about 2 nanometers and about 10 nanometers.

38. The device according to claim 35, wherein the third layer contacts both the first layer and the second layer.

39. The device according to claim 35, wherein both the first dopant and the second dopant have an n conductivity type, wherein the first dopant is phosphorus, and wherein the second dopant is arsenic.

40. The device according to claim 35, wherein both the first dopant and the second dopant have a p conductivity type, wherein the first dopant is boron, and wherein the second dopant is carbon.

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