Semiconductor light emitting device and method for manufacturing the same

Abstract

A semiconductor light emitting device and a method for manufacturing the semiconductor light emitting device are provided. The semiconductor light emitting device includes: a light emitting structure including a plurality of semiconductor layers and configured to generate light and emit the light to the outside of the light emitting structure; a transparent electrode layer arranged on the light emitting structure; a transparent protective layer arranged on the transparent electrode layer; a distributed Bragg reflector layer arranged on the transparent protective layer and covering at least a portion of the transparent electrode layer; and at least one electrode pad connected to the transparent electrode layer through a hole or a via.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0025091 filed on March 2, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Apparatuses and methods according to exemplary embodiments of the inventive concept relate to a semiconductor light emitting device. Background Art

[0004] Semiconductor light-emitting devices are considered to be the next generation of light sources, which have advantages over traditional light sources such as long life, low power consumption, fast response time, and environmental friendliness. Therefore, semiconductor light-emitting devices have become prominent as important light sources in various products such as backlights of display devices. Summary of the invention

[0005] Example embodiments provide a semiconductor light emitting device having improved luminous flux and increased reliability. Example embodiments also provide a method of manufacturing the semiconductor light emitting device.

[0006] According to example embodiments, a semiconductor light emitting device is provided, which may include: a light emitting structure including a plurality of semiconductor layers and configured to generate light and emit the light to the outside of the light emitting structure; a transparent electrode layer disposed on the light emitting structure; a transparent protective layer disposed on the transparent electrode layer; a distributed Bragg reflector (DBR) layer disposed on the transparent protective layer and covering at least a portion of the transparent electrode layer; and at least one electrode pad connected to the transparent electrode layer through a hole or a via.

[0007] According to example embodiments, a semiconductor light emitting device is provided, which may include: a light emitting structure including a plurality of semiconductor layers and configured to generate light and emit the light to the outside of the light emitting structure; a transparent electrode layer arranged on the light emitting structure; a transparent protective layer arranged on the transparent electrode layer; an insulating layer arranged on the transparent protective layer and covering at least a portion of the transparent electrode layer; and at least one electrode pad connected to the transparent electrode layer through a hole or a via, wherein the refractive index of the transparent protective layer is lower than the refractive index of the insulating layer, wherein the hole or the via includes a first inner wall and a second inner wall connected to each other, the first inner wall and the second inner wall having different inclination angles relative to an upper surface of the transparent electrode layer, and wherein the first inner wall is surrounded by the insulating layer, and the second inner wall is surrounded by the transparent protective layer.

[0008] According to example embodiments, a method for manufacturing a semiconductor light emitting device is provided, the method may include: forming a light emitting structure including a plurality of semiconductor layers on a substrate; forming a transparent electrode layer, a transparent protective layer, and an insulating layer in order on the light emitting structure; forming a hole or a via through the insulating layer and the transparent protective layer to expose some portions of the transparent electrode layer; and forming an electrode pad on the insulating layer so that the electrode pad is connected to the transparent electrode layer through the hole or the via. Here, the step of forming the hole or the via includes: a first step of removing a portion of the insulating layer so that the surface of the transparent protective layer is exposed in the hole or the via; and a second step of removing a portion of the transparent protective layer so that the transparent electrode layer is exposed in the hole or the via. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a plan view schematically illustrating a semiconductor light emitting device according to an example embodiment;

[0011] Figure 2 It is along Figure 1 A cross-sectional view taken along line II';

[0012] Figure 3 yes Figure 2 an enlarged partial cross-sectional view of portion “A” of FIG.

[0013] FIG. 4A to FIG. 4C is a cross-sectional view illustrating a process of forming a hole in a method of manufacturing a semiconductor light emitting device according to an example embodiment;

[0014] Figure 5 yes Figure 4C An enlarged partial cross-sectional view of the portion indicated by "C";

[0015] FIG. 6A to FIG. 6C is a cross-sectional view illustrating a process of forming a hole in a method of manufacturing a semiconductor light emitting device according to an example embodiment;

[0016] Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 and Fig.19 is a plan view illustrating a method of manufacturing a semiconductor light emitting device according to an example embodiment;

[0017] Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 and Fig. 20 is a cross-sectional view illustrating a method of manufacturing a semiconductor light emitting device according to example embodiments; and

[0018] Fig.21 is a cross-sectional view schematically illustrating an example in which a semiconductor light emitting device according to example embodiments is applied to a package. DETAILED DESCRIPTION

[0019] Hereinafter, various example embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this description will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the figures, the size and relative size of layers and regions may be exaggerated for clarity.

[0020] It should be understood that when an element or layer is referred to as being "located "above" another element or layer, "located "above" another element or layer, "located "on" another element or layer, "connected to" or "bonded to" another element or layer, it may be directly located above, directly located on, directly located on, directly connected to or directly bonded to another element or layer, or there may be intermediate elements or layers. In contrast, when an element is referred to as being "directly located "above", "directly located "on", "directly located "on", "directly connected to" or "directly bonded to" another element or layer, there are no intermediate elements or layers. The same reference numerals always refer to the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] It should be understood that, although the terms first, second, third, fourth, etc. can be used herein to describe multiple elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another region, layer or part. Therefore, without departing from the concept of the present invention, the first element, component, region, layer (e.g., semiconductor layer of the first conductivity type) or part discussed below can be referred to as the second element, component, region, layer (e.g., semiconductor layer of the second conductivity type) or part, and vice versa.

[0022] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0023] Figure 1 is a plan view schematically showing a semiconductor light emitting device according to an example embodiment, Figure 2 It is along Figure 1A cross-sectional view taken along line II'.

[0024] First, refer to Figure 1 and Figure 2 An example of a semiconductor light emitting device 10 according to an example embodiment is described.

[0025] Reference Figure 1 and Figure 2 The semiconductor light emitting device 10 according to example embodiments may include a substrate 105 , a light emitting structure 110 , a transparent electrode layer 140 , a first transparent protective layer 135 (also referred to as a 'transparent protective layer'), a first insulating layer 130 (also referred to as an 'insulating layer'), and a reflective electrode layer 144 .

[0026] The semiconductor light emitting device 10 may further include a second insulating layer 150 , a first connection electrode 155 n , a second connection electrode 155 p , a first electrode pad 165 n , a second electrode pad 165 p , a first solder column 170 n , and a second solder column 170 p .

[0027] The substrate 105 may have a front surface 105s1 and a rear surface 105s2 opposite to the front surface 105s1. The substrate 105 may be a substrate for growing a semiconductor, and may be made of a material such as sapphire, Si, SiC, MgAl 2 O 4 、MgO、LiAlO 2 、LiGaO 2 Sapphire may be a crystal having electrical insulating properties and Hexa-Rhombo R3c symmetry, and may be used as a substrate for growing nitride semiconductors.

[0028] Throughout the description, terms such as "front side" and "rear side" are used to distinguish between relative positions of components, and the technical idea is not limited to these terms. Terms such as "front surface", "rear surface", etc. can be replaced by other terms such as "first surface", "second surface", etc. or terms such as "upper surface", "lower surface", etc., and are used to explain the components of the present disclosure. Therefore, the front surface 105s1 and the rear surface 105s2 of the substrate 105 can be replaced by the upper surface 105s1 and the lower surface 105s2 of the substrate 105, or the first surface 105s1 and the second surface 150s2 of the substrate 105, respectively.

[0029] The light emitting structure 110 may be arranged on the front surface 105 s 1 of the substrate 105 .

[0030] In one example, the front surface 105s1 of the substrate 105 may be formed to have an irregular structure (or a concave-convex structure), and the irregular structure may improve the crystallinity and luminous efficiency of the semiconductor layer constituting the light emitting structure 110. In the current embodiment, the irregular structure of the front surface 105s1 of the substrate 105 is shown as having a dome-shaped convex shape, but the inventive concept is not limited thereto. For example, the irregular structure of the front surface 105s1 of the substrate 105 may have various other shapes such as a square or a triangle. In addition, the irregular structure of the front surface 105s1 of the substrate 105 may be selectively formed and may be omitted.

[0031] In one example, according to example embodiments, the substrate 105 may be removed later. For example, the substrate 105 may be provided as a growth substrate for growing the light emitting structure 110, and then, may be removed by a separation process. Here, the substrate 105 may be separated from the light emitting structure 110 by a laser lift-off (LLO) method, a chemical lift-off (CLO) method, or the like.

[0032] Although not shown, a buffer layer may be further provided on the front surface 105s1 of the substrate 105. The buffer layer for alleviating lattice defects of the semiconductor layer grown on the substrate 105 may be formed of an undoped semiconductor layer formed of a nitride or the like. Undoped GaN, AlN, InGaN, or the like may be applied to the buffer layer, and here, the undoped GaN, AlN, or InGaN may be grown to tens to hundreds of angstroms at a low temperature of 500° C. to 600° C. Here, undoped means that the semiconductor layer has not been intentionally subjected to an impurity doping process. However, according to example embodiments, such a buffer layer is not necessary and may be omitted.

[0033] The light emitting structure 110 may include a first conductive type semiconductor layer 115 , an active layer 120 , and a second conductive type semiconductor layer 125 .

[0034] The first conductive type semiconductor layer 115 may be grown from the front surface 105s1 of the substrate 105. The first conductive type semiconductor layer 115 may be formed of a semiconductor doped with n-type impurities, or may be an n-type nitride semiconductor layer.

[0035] like Figure 1 As shown, the first conductive type semiconductor layer 115 has a first edge S1, a second edge S2, a third edge S3, and a fourth edge S4. Therefore, the first edge S1 and the third edge S3 may be opposite to each other, and the second edge S2 and the fourth edge S4 may be opposite to each other.

[0036] The second conductive type semiconductor layer 125 may be formed of a semiconductor doped with p-type impurities, and may be a p-type nitride semiconductor layer.

[0037] In another example embodiment, the first conductivity type semiconductor layer 115 and the second conductivity type semiconductor layer 125 may be stacked so that their positions are interchangeable. The first conductivity type semiconductor layer 115 and the second conductivity type semiconductor layer 125 may have an empirical formula of Al x In y Ga (1-x-y) N, where 0≤x<1, 0≤y<1, and 0≤x+y<1, and, for example, materials such as GaN, AlGaN, InGaN, and AlInGaN correspond thereto.

[0038] The active layer 120 may be interposed between the semiconductor layer 115 of the first conductivity type and the semiconductor layer 125 of the second conductivity type. When the semiconductor light emitting device 10 operates, the active layer 120 may emit light having a predetermined energy according to the recombination of electrons and holes. The active layer 120 may include a material having a narrower energy band gap than the energy band gaps of the semiconductor layer 115 of the first conductivity type and the semiconductor layer 125 of the second conductivity type. For example, when the semiconductor layer 115 of the first conductivity type and the semiconductor layer 125 of the second conductivity type are GaN-based compound semiconductors, the active layer 120 may include an InGaN-based compound semiconductor having a narrower energy band gap than the energy band gap of GaN. In addition, the active layer 120 may have a multiple quantum well (MQW) structure in which quantum well layers and quantum barrier layers are alternately stacked, for example, an InGaN / GaN structure. However, the inventive concept is not limited thereto, and the active layer 120 may have a single quantum well (SQW) structure.

[0039] The light emitting structure 110 may include a recessed region E in which portions of the second conductive type semiconductor layer 125, the active layer 120, and the first conductive type semiconductor layer 115 are etched, and a mesa region M around the recessed region E. In the drawings, a marking letter "B" may indicate a boundary B between the recessed region E and the mesa region M. A top surface of the mesa region M may be higher than a top surface of the recessed region E. In one example, the mesa region M may gradually narrow upward. Therefore, the mesa region M may have an inclined side surface.

[0040] In one example, a portion of a top surface of the recess region E may be defined as a first contact region CT1. In one example, at least a portion of a top surface of the mesa region M may be defined as a second contact region CT2.

[0041] The mesa region M may be spaced apart from the first to fourth edges S1 to S4 , and the recessed region E may be disposed between the mesa region M and the first to fourth edges S1 to S4 . In addition, circular recessed regions E spaced apart from each other may also be arranged in the middle portion of the light emitting structure 110 .

[0042] The transparent electrode layer 140 may be disposed on the second conductive type semiconductor layer 125 of the light emitting structure 110. The transparent electrode layer 140 may be disposed in the second contact region CT2 of the second conductive type semiconductor layer 125, and the transparent electrode layer 140 may be electrically connected to the second conductive type semiconductor layer 125. The transparent electrode layer 140 serves to disperse current injected from the outside on an upper surface of the second conductive type semiconductor layer 125.

[0043] The first insulating layer 130 may be arranged on the transparent electrode layer 140. The first insulating layer 130 may cover a portion of the first conductivity type semiconductor layer 115 and a portion of the second conductivity type semiconductor layer 125. The first insulating layer 130 may include a plurality of holes PD located in the mesa region M. The first insulating layer 130 may partially cover the transparent electrode layer 140 in the mesa region M. In the current embodiment, it is shown that the plurality of holes PD are arranged in a hexagonal close packed (HCP) lattice pattern, but the inventive concept is not limited thereto. For example, the plurality of holes PD may be arranged in various forms such as a rectangular grid form. It is shown that the plurality of holes PD have a circular cross section, but the inventive concept is not limited thereto. For example, the plurality of holes PD may have a polygonal or annular cross section.

[0044] For example, the transparent electrode layer 140 may include indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), In 4 Sn 3 O 12 and Zn (1-x) Mg x At least one selected from among zinc magnesium oxide (ZMO), zinc magnesium oxide (ZMO), where 0≤x≤1. The thickness of the transparent electrode layer 140 may be in the range of 1 nm to 5 nm, but is not limited thereto.

[0045] For example, the first insulating layer 130 may include a layer made of SiO 2 、SiN、SiO x N y 、TiO 2 、Si 3 N 4 、Al 2 O 3 、TiN、AlN、ZrO 2 、TiAlN、TiSiN、HfO、NbO 2 、TaO 2 and MgF 2 At least one selected from the group consisting of.

[0046] In example embodiments, the first insulating layer 130 may have a multilayer structure in which a plurality of insulating films having different refractive indexes are alternately stacked, and may be provided as a distributed Bragg reflector (DBR). The multilayer structure may be a structure in which a first insulating film having a first refractive index and a second refractive index different from the first refractive index and a second insulating film are alternately stacked.

[0047] In another example embodiment, the first insulating layer 130 may be formed of a material having a refractive index lower than that of the second conductive type semiconductor layer 125 and may form an omnidirectional reflector (ODR) together with the reflective electrode layer 144 disposed thereon and in contact therewith.

[0048] The first insulating layer 130 may be used alone or in combination with the reflective electrode layer 144 as a reflective structure to increase reflectivity of light emitted from the active layer 120 , and light extraction efficiency may be significantly improved.

[0049] In the current embodiment, the first transparent protective layer 135 may be disposed between the transparent electrode layer 140 and the first insulating layer 130. The first transparent protective layer 135 employed in the current embodiment may be a process for forming the plurality of holes PD in the first insulating layer 130 (which will be referred to below). FIG. 4A to FIG. 4C and FIG. 6A to FIG. 6C In the embodiment described above, the physical influence (e.g., plasma damage) applied to the second conductive type semiconductor layer 125 (e.g., p-type GaN layer) is reduced. Therefore, the degradation of the electrical characteristics (Vr or Ir) due to the leakage current of the semiconductor light emitting device 10 can be prevented.

[0050] The first transparent protective layer 135 may be formed of an insulating material having a refractive index equal to or lower than that of the second conductive type semiconductor layer 125 to enhance the total reflection characteristics. When the first insulating layer 130 has a multilayer structure of a plurality of insulating films, the first transparent protective layer 135 may have a refractive index lower than at least that of the insulating film arranged closest to the first transparent protective layer 135 among the plurality of insulating films. In one example, the first transparent protective layer 135 may be formed of a material having a refractive index equal to or lower than that of the material of the first insulating layer 130. For example, the first transparent protective layer 135 may include SiO 2 and MgF 2 At least one of. In example embodiments, although the first insulating layer 130 is designed with a DBR structure, the first insulating layer may be designed to be thinner to prevent cracking in the folding region located at the edge of the mesa region to improve reliability. The thickness of the first transparent protective layer 135 may be in the range of 10nm to 200nm, but is not limited thereto.

[0051] The first transparent protective layer 135 may include the same material as at least a portion of the first insulating layer 130. For example, when the first insulating layer 130 is made of SiO 2 When the DBR of the film is formed, the first transparent protective layer 135 can be made of SiO 2 Although the first transparent protective layer 135 is formed of the same material as at least a portion of the first insulating layer 130, it is not required to have a high film quality such as an insulating film of a DBR, and therefore, the first insulating layer 130 and the first transparent protective layer 135 may be formed by different processes. The interface of the first transparent protective layer 135 with respect to the first insulating layer 130 may be visually distinguished (e.g., TEM photograph).

[0052] The reflective electrode layer 144 may be disposed on the first insulating layer 130 to be electrically connected to the transparent electrode layer 140 through the plurality of holes PD. For example, the reflective electrode layer 144 may include Ag, Cr, Ni, Ti, Al, Rh, Ru, Au, or any combination thereof.

[0053] In addition, the bonding electrode layer 142 may be disposed between the first insulating layer 130 and the reflective electrode layer 144. The bonding electrode layer 142 may contact the transparent electrode layer 140 through the plurality of holes PD. The bonding electrode layer 142 may improve bonding performance between the reflective electrode layer 144 and the first insulating layer 130.

[0054] For example, the bonding electrode layer 142 may be formed of a material similar to that of the transparent electrode layer 140. For example, the bonding electrode layer 142 may include a material made of ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, In 4 Sn 3 O 12 and Zn (1-x) Mg x At least one selected from the group consisting of O(0≤x≤1).

[0055] The second transparent protective layer 138 may cover the upper surface and the side surface of the reflective electrode layer 144 to protect the reflective electrode layer 144. The second transparent protective layer 138 may cover the side surface of the bonding electrode layer 142. By forming the second transparent protective layer 138, the adhesive property (or bonding characteristic) of the reflective electrode layer 144 may be improved, and the migration of the metal element forming the reflective electrode layer 144 may be suppressed.

[0056] The second transparent protective layer 138 may be formed of a transparent conductive material or a transparent insulating material. The transparent conductive material may include ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, In 4 Sn 3 O 12 and Zn (1-x) Mgx O (0≤x≤1), or includes a conductive polymer. The transparent insulating material may include SiO 2 、SiN、TiO 2 、HfO、NbO 2 、TaO 2 At least one selected from the group consisting of and MgF2.

[0057] The second insulating layer 150 may be disposed on the second transparent protection layer 138 and the first insulating layer 130 .

[0058] Refer to the detailed Figure 2 Part "A" Figure 3 In the case where the second transparent protective layer 138 is formed of a transparent insulating material, a first opening OPa exposing the first contact region CT1 of the first conductive type semiconductor layer 115 and a second opening OPb exposing the third contact region CT3 of the reflective electrode layer 144 may be formed by passing through the first insulating layer 130 and the second insulating layer 150. The first opening OPa may be located in the recessed region E, and the second opening OPb may be located in the mesa region M.

[0059] The first connection electrode 155n may be disposed on the second insulating layer 150 and extend to the first contact region CT1 of the first conductive type semiconductor layer 115 through the first opening OPa to be electrically connected to the first conductive type semiconductor layer 115. The first connection electrode 155n may contact the first contact region CT1 of the first conductive type semiconductor layer 115. In one example, in order to improve the contact resistance characteristics between the first connection electrode 155n and the first contact region CT1 of the first conductive type semiconductor layer 115, a conductive buffer layer may be disposed between the first connection electrode 155n and the first contact region CT1 of the first conductive type semiconductor layer 115.

[0060] The second connection electrode 155p may be disposed on the second insulating layer 150 and extend to the third contact region CT3 of the reflective electrode layer 144 through the second opening OPb to be electrically connected to the reflective electrode layer 144. Therefore, the second connection electrode 155p may be electrically connected to the second conductive type semiconductor layer 125 through the reflective electrode layer 144.

[0061] Alternatively, in the case where the second transparent protective layer 138 is formed of a transparent conductive material, a second opening OPb passing through the second insulating layer 150 may be formed such that a contact region of the second transparent protective layer 138 is exposed. The second connection electrode 155p may be disposed on the second insulating layer 150 and may be connected to the second transparent protective layer 138 through the second opening OPb to be electrically connected to the reflective electrode layer 144 and the second conductive type semiconductor layer 125.

[0062] The first connection electrode 155n and the second connection electrode 155p may be disposed on the second insulating layer 150, may be formed of the same material, and be separated from each other.

[0063] When viewed from a plane (ie, in a plan view), the first connection electrode 155n may be adjacent to the first edge S1, and the second connection electrode 155p (also referred to as 'connection electrode') may be adjacent to the third edge S3.

[0064] The third insulating layer 160 may include a third opening 160a disposed in the first connection electrode 155n and exposing the fourth contact region CT4 of the first connection electrode 155n and a fourth opening 160b disposed in the second connection electrode 155p and exposing the fifth contact region CT5 of the second connection electrode 155p.

[0065] For example, the first and second connection electrodes 155n and 155p may be formed of a material including one or more of materials such as Al, Au, W, Pt, Si, Ir, Ag, Cu, Ni, and alloys thereof.

[0066] The first electrode pad 165n may be arranged on the fourth contact region CT4 of the first connection electrode 155n, and the second electrode pad 165p may be arranged on the fifth contact region CT5 of the second connection electrode 155p. The first solder column 170n may be arranged on the first electrode pad 165n, and the second solder column 170p may be arranged on the second electrode pad 165p. The first solder column 170n and the second solder column 170p may be formed of a conductive material such as Sn, AuSn, etc.

[0067] A molding portion 172 covering the side surfaces of the first solder pillar 170n and the second solder pillar 170p may be formed. The molding portion 172 may include a material such as TiO 2 、Al 2 O 3 The upper surface of the molding portion 172 may be lower than the upper surfaces of the first solder column 170n and the second solder column 170p.

[0068] In another example, Figure 2 In the semiconductor light emitting device 10 shown, the reflective electrode layer 144 can be directly arranged on the first insulating layer 130 without the bonding electrode layer 142. In addition, the second transparent protective layer 138 can also be omitted as needed. In another example, a capping electrode layer arranged on the reflective electrode layer 144 can also be provided. The capping electrode layer can have a multilayer structure in which Ti and Ni are alternately stacked.

[0069] In the electrode structure adopted in the current embodiment, since the transparent electrode layer 140 in ohmic contact with the second conductive type semiconductor layer 125 is first formed, and the reflective electrode layer 144 is disposed on the first insulating layer 130, it is necessary to pattern the first insulating layer 130 or form a hole PD to connect the reflective electrode layer 144 to the transparent electrode layer 140 so as to inject current into the transparent electrode layer 140.

[0070] This can be done in two ways. FIG. 4A to FIG. 4C ), the first insulating layer 130 may be patterned by an etching process using dry etching after the first insulating layer 130 is completely deposited. FIG. 6A to FIG. 6C ), after forming a photoresist pattern M2 corresponding to the contact area, the first insulating layer 130 may be completely deposited, and the photoresist pattern M2 may be stripped to achieve a desired pattern.

[0071] In one example, if Figure 4A As shown, the first insulating layer 130 may be completely deposited on the first transparent protective layer 135. The first insulating layer 130 may be implemented as a DBR in which two insulating films having different refractive indices are alternately stacked. In this case, a plasma enhanced chemical vapor deposition (PE-CVD) process may be performed, and damage to the interface between the second conductive type semiconductor layer 125 and the transparent electrode layer 140 due to plasma may be mitigated by the first transparent protective layer 135.

[0072] Reference Figure 4B , an etching process such as dry etching may be performed using the photoresist pattern M1 to form a hole. The first insulating layer 130 may be subjected to a first etching process using the reaction and process conditions for etching the DBR structure. As the first etching process, a predetermined over-etching (e.g., 20% to 30%) may be performed to prevent the first insulating layer 130 from remaining. In this case, in the absence of the first transparent protective layer 135, a transparent electrode layer 140 (e.g., 1nm to 5nm) thinner than the first insulating layer 130 such as a DBR (e.g., 1000nm or less) may be etched to be open, so that the interface between the second conductive type semiconductor layer 125 and the transparent electrode layer 140 may be severely damaged to degrade the characteristics of the device. However, damage caused by over-etching in the first etching process may be prevented by the first transparent protective layer 135.

[0073] Then, refer to Figure 4C, the first transparent protective layer 135 exposed to the hole may be etched to expose the transparent electrode layer 140. The second etching process for the first transparent protective layer 135 may be performed under different process conditions (e.g., without plasma or using different etching gases) that cause less physical damage, and undesirable damage or etching to the transparent electrode layer 140 may be minimized by minimizing the over-etching time.

[0074] Since the etching process according to example embodiments is performed as a two-step etching process, the inner wall of the obtained hole may have a unique shape.

[0075] Figure 5 yes Figure 4C An enlarged partial cross-sectional view of portion “C” in FIG.

[0076] Figure 5 The hole shown has a first inner wall surrounded by the first insulating layer 130 and a second inner wall surrounded by the first transparent protective layer 135, and the inclination angle θ1 of the first inner wall and the inclination angle θ2 of the second inner wall may be different from each other. As in the current embodiment, the inclination angle θ1 of the first inner wall may be smaller than the inclination angle θ2 of the second inner wall.

[0077] The second inner wall may extend to a portion of the transparent electrode layer 140. The contact region C1 of the transparent electrode layer 140 connected to the hole may have a lower level than other portions.

[0078] In another example, if Fig. 6A As shown, a photoresist pattern M2 corresponding to the contact area is formed on the first transparent protective layer 135 .

[0079] Next, refer to Figure 6B , the first insulating layer 130 such as a DBR is completely deposited on the first transparent protective layer 135 on which the photoresist pattern M2 is formed. For example, in the case where the first insulating layer 130 is formed using a PE-CVD process, damage to the interface between the second conductive type semiconductor layer 125 and the transparent electrode layer 140 due to plasma can be reduced by the first transparent protective layer 135.

[0080] Then, refer to Figure 6C , in the case of a process of stripping a photoresist pattern, a desired patterning process can be performed without causing physical damage due to plasma or the like.

[0081] By forming the first transparent protective layer 135 on the transparent electrode layer 140 in this manner, physical influences such as ion bombardment or damage to the second conductive type semiconductor layer 125 (e.g., pGaN) located below the transparent electrode layer 140 can be minimized in the process of patterning the first insulating layer 130 (hole formation process), thereby maintaining the reliability of the device.

[0082] In addition, by using a material with a relatively low refractive index (e.g., SiO 2 MgF 2 ) forms a first transparent protective layer 135 to enhance the total reflection characteristics, and the first insulating layer 130 can be designed as a thinner DBR, thereby preventing the first insulating layer 130 from cracking.

[0083] In the semiconductor light emitting device in which the first insulating layer is formed to have a DBR structure, in the case where the transparent protective layer is not applied, the leakage current characteristics (especially, VR) are deteriorated, as shown in Table 1 (i.e., Deterioration of leakage current characteristics (VR)). However, it can be seen that by forming a material having a low refractive index such as MgF 2 The dielectric material of as a transparent protective layer greatly improves the leakage current characteristics (VR, IR), as shown in Table 2 (the levels of leakage current characteristics (VR, IR) are basically the same as those of Ref.).

[0084] [Table 1]

[0085]

[0086]

[0087] [Table 2]

[0088]

[0089] In the following, reference will be made to Figures 7 to 20 A method of manufacturing the semiconductor light emitting device 10 according to example embodiments is described. Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 and Fig.19 is a schematic plan view illustrating a method of manufacturing a semiconductor light emitting device 10 according to an example embodiment, and Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 and Fig. 20 It is along Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 and Fig.19 A cross-sectional view of the area taken along line II'.

[0090] Reference Figure 7 and Figure 8, a light emitting structure 110 may be formed on a substrate 105. The substrate 105 may have a front surface 105s1 and a rear surface 105s2 opposite to the front surface 105s1.

[0091] In one example, a concavo-convex structure may be formed on the front surface 105s1 of the substrate 105. According to example embodiments, forming the concavo-convex structure on the front surface 105s1 of the substrate 105 may be omitted.

[0092] The light emitting structure 110 may be formed on the front surface 105s1 of the substrate 105. The light emitting structure 110 may include a plurality of layers formed using processes such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), etc. For example, the light emitting structure 110 may include a first conductive type semiconductor layer 115, an active layer 120, and a second conductive type semiconductor layer 125 formed in sequence on the front surface 105s1 of the substrate 105. The first conductive type semiconductor layer 115 and the second conductive type semiconductor layer 125 may have different conductive types. For example, the first conductive type semiconductor layer 115 may have n-type conductivity, and the second conductive type semiconductor layer 125 may have p-type conductivity. In addition, a transparent electrode layer 140 may be formed on the light emitting structure 110.

[0093] Reference Fig. 9 and Fig.10 , the transparent electrode layer 140, the second conductive type semiconductor layer 125, the active layer 120, and the first conductive type semiconductor layer 115 may be etched using a photolithography process. Therefore, the light emitting structure 110 may include a recessed area E formed by removing some portions of the second conductive type semiconductor layer 125, the active layer 120, and the first conductive type semiconductor layer 115, and a mesa area (M) therearound. The mesa area M may be defined as an area where the second conductive type semiconductor layer 125, the active layer 120, and the first conductive type semiconductor layer 115 are not etched. The mesa area M may have a protruding shape relative to the recessed area E. The recessed area E may also be referred to as an etching area.

[0094] Reference Fig.11 and Fig.12 , a first transparent protective layer 135 and a first insulating layer 130 having the plurality of holes PD may be formed on the light emitting structure 110 .

[0095] The first transparent protective layer 135 and the first insulating layer 130 are sequentially formed on the transparent electrode layer 140, and the plurality of holes PD may pass through the first insulating layer 130 and the first transparent protective layer 135 to expose some portions of the transparent electrode layer 140. The plurality of holes PD may be located in the mesa region (M). FIG. 4A to FIG. 4C or FIG. 6A to FIG. 6CThe patterning process shown performs this treatment. The first transparent protective layer 135 used in the current embodiment can reduce the physical impact (e.g., plasma damage) applied to the second conductive type semiconductor layer 125 (e.g., p-type GaN layer) during the process, and as a result, the electrical characteristics (Vr or Ir) can be prevented from being degraded due to leakage current.

[0096] Reference Fig.13 and Fig.14 , a bonding electrode layer 142 and a reflective electrode layer 144 may be formed on the first insulating layer 130. The bonding electrode layer 142 and the reflective electrode layer 144 may be formed on the mesa region M and may be formed on a region of the first insulating layer 130.

[0097] Reference Fig.15 and Fig.16 , a second transparent protective layer 138 may be formed on the reflective electrode layer 144. The second transparent protective layer 138 may cover the upper surface and the side surface of the reflective electrode layer 144 and the side surface of the bonding electrode layer 142. The second transparent protective layer 138 may cover a portion of the first insulating layer 130 adjacent to the reflective electrode layer 144. For example, after forming a photoresist pattern exposing a region where the second transparent protective layer 138 is to be formed, the second transparent protective layer 138 may be formed by a physical vapor deposition process such as sputtering.

[0098] Reference Fig.17 and Fig.18 , a second insulating layer 150 may be formed on the first insulating layer 130 and the second transparent protective layer 138 .

[0099] A first opening OPa passing through the first insulating layer 130 and the second insulating layer 150 and exposing a portion of the first conductive type semiconductor layer 115 in the recessed area E and a second opening OPb passing through the second transparent protective layer 138 and the second insulating layer 150 and exposing a portion of the reflective electrode layer 144 of the mesa area M may be formed.

[0100] The surface of the first conductive type semiconductor layer 115 exposed through the first opening OPa may be referred to as a first contact region CT1, and the surface of the reflective electrode layer 144 exposed through the second opening OPb may be referred to as a third contact region CT3.

[0101] Reference Fig.19 and Fig. 20 , a first connection electrode 155 n and a second connection electrode 155 p may be formed on the substrate 105 having the second insulating layer 150 .

[0102] The formation of the first connection electrode 155n and the second connection electrode 155p may include forming a conductive material layer on the substrate 105 having the second insulating layer 150 and etching a portion of the conductive material layer using a photolithography process. Since the first connection electrode 155n and the second connection electrode 155p are formed by the same process, they may be formed of the same material. The first connection electrode 155n and the second connection electrode 155p may have the same thickness.

[0103] The first connection electrode 155n may be electrically connected to the first contact region CT1 of the first conductive type semiconductor layer 115. The second connection electrode 155p may be electrically connected to the third contact region CT3 of the reflective electrode layer 144.

[0104] Return to reference Figure 1 and Figure 2 , a third insulating layer 160 having a third opening 160 a and a fourth opening 160 b may be formed on the substrate 105 having the first connection electrode 155 n and the second connection electrode 155 p .

[0105] The third opening 160 a of the third insulating layer 160 may expose a portion of the first connection electrode 155 n , and the fourth opening 160 b of the third insulating layer 160 may expose a portion of the second connection electrode 155 p .

[0106] A partial region of the first connection electrode 155n exposed through the third opening 160a of the third insulating layer 160 may be referred to as a fourth contact region CT4, and a partial region of the second connection electrode 155p exposed through the fourth opening 160b of the third insulating layer 160 may be referred to as a fifth contact region CT5.

[0107] The first electrode pad 165n and the second electrode pad 165p may be formed on the substrate 105 having the third insulating layer 160. The first electrode pad 165n may be formed on the fourth contact region CT4 of the first connection electrode 155n, and the second electrode pad 165p may be formed on the fifth contact region CT5 of the second connection electrode 155p. The first electrode pad 165n and the second electrode pad 165p may be under bump metallization (UBM). In one example, the amount and arrangement of the first electrode pad 165n and the second electrode pad 165p may vary.

[0108] The first solder column 170n and the second solder column 170p may be formed on the substrate 105 having the first and second electrode pads 165n and 165p. The first solder column 170n may be formed on the first electrode pad 165n, and the second solder column 170p may be formed on the second electrode pad 165p.

[0109] A molding portion 172 covering side surfaces of the first and second solder pillars 170n and 170p may be formed.

[0110] The semiconductor light emitting device 10 can be commercialized as a package. Fig.21 An example in which the above-described semiconductor light emitting device 10 is applied to a package is described. Fig.21 is a cross-sectional view schematically illustrating an example in which a semiconductor light emitting device according to example embodiments is applied to a package.

[0111] Reference Fig.21 The semiconductor light emitting device package 1000 may include a semiconductor light emitting device 1001 as a light source, a package body 1002, a pair of lead frames 1010, and a sealant 1005. Here, the semiconductor light emitting device 1001 may be Figure 1 and Figure 2 The semiconductor light emitting device 10 is shown in FIG. 1 , and a description thereof may be omitted.

[0112] The semiconductor light emitting device 1001 may be mounted on a lead frame 1010 and electrically connected to the lead frame 1010 .

[0113] The pair of lead frames 1010 may include a first lead frame 1012 and a second lead frame 1014. The semiconductor light emitting device 1001 may be soldered by first solder posts and second solder posts ( Figure 2 170n and 170p) are connected to the first lead frame 1012 and the second lead frame 1014.

[0114] The package body 1002 may include a reflective cup to improve light reflection efficiency and light extraction efficiency. In the reflective cup, a sealant 1005 formed of a transparent material may be formed to encapsulate the semiconductor light emitting device 1001. The sealant 1005 may include a wavelength conversion material such as a phosphor or a quantum dot.

[0115] According to example embodiments of the technical ideas, a semiconductor light emitting device having improved luminous flux and improved reliability may be provided.

[0116] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope defined by the appended claims.

Claims

1. A semiconductor light emitting device, comprising: a light emitting structure including a plurality of semiconductor layers and configured to generate light and emit the light to the outside of the light emitting structure; a transparent electrode layer, which is arranged on the light emitting structure; a transparent protective layer, arranged on the transparent electrode layer; a distributed Bragg reflector layer, which is arranged on the transparent protective layer and covers at least a portion of the transparent electrode layer; as well as at least one electrode pad connected to the transparent electrode layer through a hole or a via, The hole or via comprises a first inner wall and a second inner wall, the first inner wall and the second inner wall are connected to each other and have different inclination angles relative to the upper surface of the transparent electrode layer. wherein the first inner wall is surrounded by the distributed Bragg reflector layer, and the second inner wall is surrounded by the transparent protective layer, and The second inner wall extends to a surface of the transparent electrode layer that is exposed by removing or etching a portion of the transparent electrode layer, and the surface is thus lower than an upper surface of the transparent electrode layer on which the transparent protective layer is arranged.

2. The semiconductor light emitting device according to claim 1, wherein: The distributed Bragg reflector layer includes a plurality of films having different refractive indices.

3. The semiconductor light emitting device according to claim 2, wherein: The distributed Bragg reflector layer comprises SiO2, SiN, SiO x N y , TiO2, Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN, TiSiN, HfO, NbO2, TaO2 and MgF2.

4. The semiconductor light emitting device according to claim 3, wherein: The transparent protective layer includes at least one of SiO2 and MgF2.

5. The semiconductor light emitting device according to claim 4, wherein: The thickness of the transparent protective layer ranges from 10 nm to 200 nm.

6. The semiconductor light emitting device according to claim 4, wherein: The transparent protective layer includes a material having a refractive index lower than a refractive index of a material forming at least one of the plurality of films forming the distributed Bragg reflector layer, which is arranged closest to the transparent protective layer.

7. The semiconductor light emitting device according to claim 6, wherein: The material forming the distributed Bragg reflector layer has a lower refractive index than a first conductive type semiconductor layer forming the light emitting structure and arranged under the transparent electrode layer.

8. The semiconductor light emitting device according to claim 1, wherein: The thickness of the transparent electrode layer ranges from 1 nm to 5 nm.

9. The semiconductor light emitting device according to claim 1, wherein: The transparent electrode layer is configured to inject current received from the electrode pad into the light emitting structure to generate light, and Wherein, there is an interface between the transparent electrode layer and the transparent protective layer.

10. The semiconductor light emitting device according to claim 1, wherein: The transparent electrode layer includes indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), gallium indium oxide (GIO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), In4Sn3O 12 and zinc magnesium oxide (Zn (1-x) Mg x O) selected from at least one, where 0≤x≤1.

11. The semiconductor light emitting device according to claim 1 , further comprising a reflective electrode layer disposed on the distributed Bragg reflector layer, in, The reflective electrode layer is configured to receive current from the electrode pad, and includes Ag, Cr, Ni, Ti, Al, Rh, Ru, Au, or a combination thereof.

12. The semiconductor light emitting device according to claim 11, wherein: The distributed Bragg reflector layer and the reflective electrode layer form an omnidirectional reflector.

13. A semiconductor light emitting device, comprising: a light emitting structure including a plurality of semiconductor layers and configured to generate light and emit the light to the outside of the light emitting structure; a transparent electrode layer, which is arranged on the light emitting structure; a transparent protective layer, arranged on the transparent electrode layer; an insulating layer disposed on the transparent protective layer and covering at least a portion of the transparent electrode layer; as well as at least one electrode pad connected to the transparent electrode layer through a hole or a via, Wherein, the refractive index of the transparent protective layer is lower than the refractive index of the insulating layer, The hole or via comprises a first inner wall and a second inner wall, the first inner wall and the second inner wall are connected to each other and have different inclination angles relative to the upper surface of the transparent electrode layer. wherein the first inner wall is surrounded by the insulating layer, and the second inner wall is surrounded by the transparent protective layer, and The second inner wall extends to a surface of the transparent electrode layer that is exposed by removing or etching a portion of the transparent electrode layer, and the surface is thus lower than an upper surface of the transparent electrode layer on which the transparent protective layer is arranged.

14. The semiconductor light emitting device according to claim 13, wherein: The insulating layer includes SiO 2 , and the transparent protective layer includes MgF 2 .

15. A semiconductor light emitting device, comprising: a light emitting structure configured to generate light and emit the light to the outside of the light emitting structure, and including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer in the recessed region and the mesa region; wherein, in the recessed region, the semiconductor layer of the first conductivity type is connected to the first electrode pad, and in the mesa region, the semiconductor layer of the second conductivity type is connected to the second electrode pad through at least one hole or via, wherein, in the mesa region, a transparent electrode layer, a transparent protective layer, and a distributed Bragg reflector layer are stacked in this order on the second conductivity type semiconductor layer, and the second electrode pad is connected to the transparent electrode layer through a hole or a via, The hole or via comprises a first inner wall and a second inner wall, the first inner wall and the second inner wall are connected to each other and have different inclination angles relative to the upper surface of the transparent electrode layer. wherein the first inner wall is surrounded by the distributed Bragg reflector layer, and the second inner wall is surrounded by the transparent protective layer, and The second inner wall extends to a surface of the transparent electrode layer that is exposed by removing or etching a portion of the transparent electrode layer, and the surface is thus lower than an upper surface of the transparent electrode layer on which the transparent protective layer is arranged.

16. The semiconductor light emitting device according to claim 15, wherein: The distributed Bragg reflector layer includes a plurality of films having different refractive indices, and includes SiO2, SiN, SiO x N y , TiO2, Si3N4, Al2O3, TiN, AlN, ZrO2, TiAlN, TiSiN, HfO, NbO2, TaO2 and MgF2.

17. The semiconductor light emitting device according to claim 15, wherein: The distributed Bragg reflector layer includes a plurality of films having different refractive indices, and The transparent protective layer includes a material having a refractive index lower than a refractive index of a material forming at least one of the plurality of films used to form the distributed Bragg reflector layer and arranged closest to the transparent protective layer.

18. The semiconductor light emitting device according to claim 15, wherein: In the mesa region, a reflective electrode layer is disposed on the distributed Bragg reflector layer and is configured to receive current from the second electrode pad.

19. A method for manufacturing a semiconductor light emitting device, the method comprising: forming a light emitting structure including a plurality of semiconductor layers on a substrate; forming a transparent electrode layer, a transparent protective layer and an insulating layer on the light emitting structure; forming holes or vias through the insulating layer and the transparent protective layer to expose portions of the transparent electrode layer; as well as forming an electrode pad on the insulating layer so that the electrode pad is connected to the transparent electrode layer through the hole or via hole, Wherein, the step of forming the hole or via comprises: The first step is to remove a portion of the insulating layer so that the surface of the transparent protective layer is exposed in the hole or via; and The second step is to remove a portion of the transparent protective layer and a portion of the transparent electrode layer so that the surface of the transparent electrode layer is exposed in the hole or the via hole, and the exposed surface of the transparent electrode layer is lower than the upper surface of the transparent electrode layer on which the transparent protective layer is arranged. The hole or via is formed to include a first inner wall surrounded by the insulating layer and a second inner wall surrounded by the transparent protective layer and the transparent electrode layer, the first inner wall and the second inner wall are connected to each other and have different inclination angles relative to the upper surface of the transparent electrode layer.

20. The method according to claim 19, wherein: The first step of removing a portion of the insulating layer and the second step of removing a portion of the transparent protective layer and a portion of the transparent electrode layer are performed by etching.

21. The method according to claim 20, wherein: The first step and the second step use different etching gases for etching.

Images