A submicron heterostructure thin film transistor and transistor manufacturing method

Abstract

The present invention relates to the field of semiconductor technology, and more specifically, to a thin film transistor with a submicron heterostructure and a method for manufacturing the transistor, comprising a substrate and a gate connected to the substrate, the substrate and the gate connected to an insulating layer, the insulating layer connected to an active layer, the active layer connected to a source-drain metal layer, wherein the active layer is a periodic heterostructure formed after a submicron gap layer is covered with a material. The transistor of the present invention can increase the on current of the transistor, reduce the off current of the transistor, and improve the performance of the transistor through gate regulation.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more specifically, to a thin film transistor with a submicron heterostructure and a method for manufacturing the transistor. Background Art

[0002] Thin-film transistors (TFTs) and field-effect transistors (FETs) are the basic units for building functional electronic circuits and exploring transmission physics. In traditional TFTs or FETs, the uniform semiconductor film layer limits the current size, on-off ratio, detection sensitivity, and transmission physics. In this case, improving transistor performance often requires finding new materials, and the potential of the discovered materials is difficult to further improve.

[0003] In recent years, new near-field lithography technology has been reported, through which submicron-level controllable stripe gap structure patterning can be achieved for specific materials. Based on near-field lithography technology, TFTs with submicron heterostructures are developed, and a periodic heterojunction active layer is formed by degenerate materials and non-degenerate materials. Through gate regulation, the on-current of the transistor can be increased and the off-current of the transistor can be reduced. Summary of the invention

[0004] In order to overcome at least one defect of the above-mentioned prior art, the present invention provides a submicron heterostructure thin film transistor and a method for manufacturing the transistor. The transistor has an active layer with a periodic heterojunction. Through gate regulation, the on current of the transistor can be increased, the off current of the transistor can be reduced, and the performance of the transistor can be improved.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: a thin film transistor with a submicron heterostructure, including a substrate and a gate connected to the substrate, the substrate and the gate are connected to an insulating layer, the insulating layer is connected to an active layer, and the active layer is connected to a source and drain metal layer, wherein the active layer is a periodic heterostructure formed after a submicron gap layer covering material.

[0006] In this scheme, the substrate of the thin film transistor is connected to the gate, the insulating layer is connected to the substrate and the gate, the insulating layer is connected to the active layer, the source and drain metal layer is connected to the active layer, the active layer is a periodic heterostructure, and the periodic heterostructure is formed by covering the material with a sub-micron gap layer. Through gate regulation, the on current of the transistor can be increased and the off current of the transistor can be reduced, greatly improving the device performance.

[0007] In one embodiment, the insulating layer is an oxidic insulating layer or a polymer insulating layer.

[0008] In one embodiment, the active layer is a periodic heterostructure formed by a sub-micron gap layer formed of a degenerate material filling and covering a non-degenerate semiconductor material.

[0009] Preferably, the degenerate material includes but is not limited to InSnO, and the non-degenerate semiconductor material includes but is not limited to InGaZnO and GaSnO.

[0010] The source and drain metal layers include but are not limited to Mo and Al, and the material of the substrate includes but is not limited to Si, glass, and a flexible substrate.

[0011] When the substrate is Si, the substrate is directly connected to the insulating layer.

[0012] When the substrate is a glass or flexible substrate, a layer of gate electrode is deposited on the substrate. The gate electrode includes but is not limited to Cr / Au, Al, and Mo.

[0013] The present invention provides a method for manufacturing a thin film transistor with a submicron heterogeneous structure, wherein a degenerate material deposited on a substrate and a gate is patterned to form a submicron gap layer, a layer of non-degenerate semiconductor material is then deposited on the substrate and the gate and patterned, the submicron gap layer is filled with the patterned non-degenerate semiconductor material to form an active layer, and a source and drain metal layer is deposited on the active layer.

[0014] The specific steps include:

[0015] S1: The substrate is cleaned and dried;

[0016] S2: When the substrate is Si, it is directly used as a silicon gate; when the substrate is a glass or flexible substrate, a layer of gate electrode is first deposited on the substrate;

[0017] S3: Spin coating or depositing the insulating layer on the substrate and the gate;

[0018] S4: depositing a degenerate material on the substrate and the gate, and patterning the degenerate material using a near-field photolithography technique to obtain a sub-micron gap stripe structure;

[0019] S5: depositing non-degenerate semiconductor materials on the substrate and the gate, selectively etching a non-degenerate semiconductor pattern structure that fills and covers the degenerate material area, and then evaporating or sputtering a metal layer in a vacuum environment to complete a sub-micron heterostructure thin film transistor.

[0020] Preferably, the channel gap of the submicron gap layer is 200nm-3um, and a non-degenerate semiconductor film is used to fill the channel gap of the submicron gap layer, generating a periodic heterojunction parallel to the source and drain directions with the degenerate material, and establishing a current path between the source and the drain.

[0021] In V G <V THWhen V is 0.04, the electron concentration of the non-degenerate semiconductor film is low, forming a space charge region, inducing a built-in electric field near the degenerate / non-degenerate interface, hindering electron transport, and forming a periodic heterostructure, further reducing the off current; when V G >V TH When the gate is turned on, the carrier concentration in the non-degenerate semiconductor increases, forming an electron transmission channel between the stripes on the sub-micron gap layer, and a periodic heterostructure, further increasing the on-current. Therefore, the source-drain current is mainly achieved by gate-regulating the non-degenerate semiconductor film.

[0022] Compared with the prior art, the present invention has the following characteristics:

[0023] The present invention uses near-field photolithography technology to pattern a degenerate material film to form a submicron gap stripe structure, and then sputters a non-degenerate semiconductor film to fill the gap covering the submicron gap layer to form an active layer, which is applied to the transistor structure to form a submicron-level and periodic degenerate doped heterojunction oxide thin film transistor, which has the characteristics of high switching ratio. Compared with traditional uniform semiconductor thin film transistors, the present invention has submicron-level and periodic degenerate doped heterojunction oxide thin film transistors, which have the characteristics of gate regulating the carrier concentration of the non-degenerate semiconductor film, hindering or connecting the electron transmission between the stripes of the submicron gap layer, and suppressing the off current and increasing the on current through the periodic heterostructure, which can greatly improve the transistor switching ratio, transconductance, and mobility. This scheme verifies the feasibility of making various submicron structures or interfaces in TFTs or FETs, and significantly expands the research scope of multifunctional TFTs or FETs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is the principle of the near-field lithography technology in the embodiment of the present invention.

[0025] Figure 2 1 is a transistor device structure and SEM image in an embodiment of the present invention.

[0026] Figure 3 It is the measurement characteristic of the transistor in the embodiment of the present invention. DETAILED DESCRIPTION

[0027] The drawings are only for illustrative purposes and should not be construed as limiting the present invention. To better illustrate the present embodiment, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the drawings. The positional relationships described in the drawings are only for illustrative purposes and should not be construed as limiting the present invention.

[0028] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, it is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limitations on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0029] Embodiment 1:

[0030] The invention provides a submicron heterostructure thin film transistor, which comprises a substrate and a gate connected to the substrate, the substrate and the gate connected to an insulating layer, the insulating layer connected to an active layer, and the active layer connected to a source-drain metal layer.

[0031] In this embodiment, the active layer is a periodic heterostructure formed by a submicron gap layer formed by a degenerate material filling and covering a non-degenerate semiconductor material. The degenerate material is InSnO, and can also be PEDOT:PSS. As long as the conductivity of the material is high enough, it can be either inorganic or organic.

[0032] The non-degenerate semiconductor material is one of InGaZnO and GaSnO, and may also be C8-BTBT or P3HT, as long as it is a non-degenerate organic semiconductor material.

[0033] The source and drain metal layers are one of Mo and Al, and can also be Au. A suitable S / D electrode is selected according to the work function of the semiconductor material.

[0034] When the material of the substrate is Si, the substrate is directly connected to the insulating layer, and the insulating layer is an oxide insulating layer or a polymer insulating layer.

[0035] When the substrate is a glass or flexible substrate, a gate electrode is deposited on the substrate. The gate electrode is one of Cr / Au, Al, Mo, and can also be Ti. In theory, any metal that can be used as an electrode can be used.

[0036] In this embodiment, a method for manufacturing a thin film transistor with a submicron heterostructure is provided, in which a degenerate material deposited on a substrate and a gate is patterned to form a submicron gap layer, and then a layer of non-degenerate semiconductor material is deposited on the substrate and the gate and patterned, and the submicron gap layer is filled with the patterned non-degenerate semiconductor material to form an active layer, and a source and drain metal layer is deposited on the active layer.

[0037] The method comprises the following steps:

[0038] S1: The substrate is cleaned in acetone, ethanol, and water, and dried with nitrogen;

[0039] S2: When the substrate is Si, it is directly used as a silicon gate; when the substrate is a glass or flexible substrate, a gate electrode with a thickness of 30 to 50 nm is first deposited on the substrate;

[0040] S3: Spin coating or PECVD depositing the insulating layer on the substrate and the gate, wherein the thickness of the insulating layer is 100 to 300 nm;

[0041] S4: Depositing 30nm to 80nm of degenerate material on the substrate and the gate using a DC sputtering method, and patterning the degenerate material using a near-field photolithography technique to obtain a sub-micron gap stripe structure;

[0042] S5: Deposit 40 to 100 nm of non-degenerate semiconductor material on the substrate and the gate, selectively etch out a non-degenerate semiconductor pattern structure that fills and covers the degenerate material area, and then evaporate or sputter 70 to 120 nm of metal in a vacuum environment to complete a submicron heterostructure thin film transistor.

[0043] RF sputtering is used to deposit 40-100nm non-degenerate semiconductor material on the substrate and gate, and non-degenerate semiconductor pattern structures that fill and cover the degenerate material area are selectively etched. Then, 70-120nm metal is evaporated or sputtered in a vacuum environment to complete a submicron heterostructure thin film transistor. The vacuum degree of the vacuum environment is greater than 3.8×10 -3 .

[0044] In this embodiment, the channel gap of the submicron gap layer is 200nm-3um, and a non-degenerate semiconductor film is used to fill the channel gap of the submicron gap layer, generating a periodic heterojunction parallel to the source and drain directions with the degenerate material, and establishing a current path between the source and the drain.

[0045] In V G <V TH When V is 0.04, the electron concentration of the non-degenerate semiconductor film is low, forming a space charge region, inducing a built-in electric field near the degenerate / non-degenerate interface, hindering electron transport, and forming a periodic heterostructure, further reducing the off current; when V G >V TH When the gate is turned on, the carrier concentration in the non-degenerate semiconductor increases, forming an electron transmission channel between the stripes of the sub-micron gap layer, and the periodic heterostructure further increases the on-current. Therefore, the source-drain current is mainly achieved by gate-regulating the non-degenerate semiconductor film.

[0046] The source-drain current is mainly realized by gate regulation of the non-degenerate semiconductor film, so changes in the channel length or the gap distance filled by the non-degenerate semiconductor film will also cause changes in the gate regulation.

[0047] The following is a specific embodiment of the method, and the results are as follows Figure 1 He Ru Figure 2 As shown:

[0048] S1: providing a Si / SiO2 substrate, wherein the thickness of SiO2 is 100 nm, and ultrasonically cleaning the substrate in acetone, ethanol, and water, and drying with nitrogen;

[0049] S2: Sputter 50nm ITO on the substrate and gate by DC sputtering;

[0050] S3: Using near-field lithography technology, ITO is patterned through photolithography, development, and etching to obtain a gap stripe structure of about 200nm to 3um;

[0051] S4: 70nm IGZO is sputtered on the substrate and gate by RF sputtering, and the IGZO pattern structure that fills and covers the ITO area is selectively etched, and then at 3.8×10 -3 100nmAl is deposited by mask evaporation under a vacuum degree of 1000nm as the source and drain to complete the submicron heterostructure thin film transistor.

[0052] like Figure 3 The figure shows the comparison of the transfer characteristics, output characteristics, mobility, etc. of submicron heterostructure thin film transistors with those of ordinary non-submicron heterostructure thin film transistors. It can be seen from the figure that compared with ordinary transistors, the maximum current, switching ratio and mobility of submicron heterostructure transistors are significantly improved.

[0053] Embodiment 2:

[0054] This embodiment provides another method for manufacturing a transistor, comprising the following steps:

[0055] S1: Using a Si substrate, ultrasonically clean the substrate in acetone, ethanol, and water, and blow dry with nitrogen;

[0056] S2: Spin coat 0.2 mol / L ZrO2 solution in a glove box at 4000 rpm / 30 s for 1 to 4 times, anneal at 150 °C for 15 min and continue spin coating, anneal at 400 °C in air for 2 hours after spin coating;

[0057] S3: Sputter 50nm ITO on the substrate and gate by DC sputtering;

[0058] S4: Using near-field lithography technology, ITO is patterned through photolithography, development, and etching to obtain a 1um to 2um gap stripe structure;

[0059] S5: IGZO with a thickness of 70 nm is sputtered on the substrate and the gate by RF sputtering, and the IGZO pattern structure filling and covering the ITO area is selectively etched, and then at 3.8×10 -3 Al with a thickness of 100 nm was evaporated and deposited under a vacuum degree of 100 to complete a submicron heterostructure thin film transistor.

[0060] Embodiment 3:

[0061] This embodiment provides another method for manufacturing a transistor, comprising the following steps:

[0062] S1: providing a Si / SiO2 substrate, wherein the thickness of SiO2 is 100 nm, and ultrasonically cleaning the substrate in acetone, ethanol, and water, and drying with nitrogen;

[0063] S2: Sputter 50nm ITO on the substrate and gate by DC sputtering;

[0064] S3: Using near-field lithography technology, ITO is patterned through photolithography, development, and etching to obtain a gap stripe structure of 200nm to 3um;

[0065] S4: 70nm IGZO is sputtered on the substrate and the gate by RF sputtering, and the IGZO pattern structure filling and covering the ITO area is selectively etched, and then 70nm Mo is RF sputtered as the source and drain to complete the submicron heterostructure thin film transistor.

[0066] Implementation 4:

[0067] This embodiment provides another method for manufacturing a transistor, comprising the following steps:

[0068] S1: providing a glass substrate, ultrasonically cleaning the substrate in acetone, ethanol and water, and drying it with nitrogen;

[0069] S2: Sputter Mo on the substrate and the gate by DC sputtering as the gate;

[0070] S3: Spin coating 0.2 mol / L ZrO2 solution in a glove box at 4000 rpm / 30 s for 1 to 4 times. After each spin coating, anneal at 150°C for 15 min and then continue spin coating. After spin coating, anneal at 400°C in air for 2 hours.

[0071] S4: Using near-field lithography technology, ITO is patterned through photolithography, development, and etching to obtain a gap stripe structure of about 200nm to 3um;

[0072] S5: 70nm IGZO is sputtered on the substrate and gate by RF sputtering, and the IGZO pattern structure that fills and covers the ITO area is selectively etched, and then at 3.8×10 -3100nmAl is deposited by mask evaporation under a vacuum degree of 1000nm as the source and drain to complete the submicron heterostructure thin film transistor.

[0073] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A submicron heterostructure thin film transistor, comprising a substrate and a gate connected to the substrate, wherein the substrate and the gate are connected to an insulating layer, the insulating layer is connected to an active layer, and the active layer is connected to a source and drain metal layer, characterized in that: The active layer is a periodic heterostructure formed by covering the sub-micron gap layer with a material; The active layer is a periodic heterostructure formed by a submicron gap layer formed by a degenerate material filling a non-degenerate semiconductor material and allowing the non-degenerate semiconductor material to cover the degenerate material; the insulating layer is an oxidized insulating layer or a polymer insulating layer.

2. The submicron heterostructure thin film transistor according to claim 1, characterized in that: The degenerate material includes InSnO, and the non-degenerate semiconductor material includes InGaZnO and GaSnO.

3. The submicron heterostructure thin film transistor according to claim 1, characterized in that: The source and drain metal layers include Mo and Al, and the substrate material includes Si, glass, and a flexible substrate.

4. The submicron heterostructure thin film transistor according to claim 3, characterized in that: The substrate is Si, and the substrate is directly connected to the insulating layer.

5. The submicron heterostructure thin film transistor according to claim 3, characterized in that: The substrate is a glass or flexible substrate. A gate electrode is deposited on the substrate. The gate electrode includes Cr / Au, Al, and Mo.

6. A method for manufacturing a submicron heterostructure thin film transistor, characterized in that: Near-field photolithography is used to pattern the degenerate material deposited on the substrate and the gate to form a submicron gap layer, and then a non-degenerate semiconductor layer is deposited on the substrate and the gate and patterned. The degenerate material is covered with the patterned non-degenerate semiconductor layer and the submicron gap layer is filled to form an active layer, and a source and drain metal layer is deposited on the active layer.

7. The method for manufacturing a submicron heterostructure thin film transistor according to claim 6, characterized in that: The following steps are included: S1: The substrate is cleaned and dried; S2: When the substrate is Si, it is directly used as a silicon gate; when the substrate is a glass or flexible substrate, a layer of gate electrode is first deposited on the substrate; S3: Spin coating or depositing an insulating layer on the substrate and the gate; S4: depositing a degenerate material on the substrate and the gate, and patterning the degenerate material using a near-field photolithography technique to obtain a sub-micron gap layer; S5: depositing a non-degenerate semiconductor layer on the substrate and the gate, selectively etching a non-degenerate semiconductor pattern structure filling and covering the degenerate material area, and then evaporating or sputtering a metal layer in a vacuum environment to complete a sub-micron heterostructure thin film transistor.

8. The method for manufacturing a submicron heterostructure thin film transistor according to claim 7, characterized in that: The channel gap of the submicron gap layer is 200nm-1um. The submicron gap layer is filled with a non-degenerate semiconductor layer, and the submicron gap layer formed with the degenerate material generates a periodic heterojunction parallel to the source and drain directions, establishing a current path between the source and the drain.

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