Semiconductor device and method for manufacturing the same
By adopting an alternating stacked structure design in the semiconductor memory device, the semiconductor chips are alternately arranged, and the chip bonding and connection are realized through connecting bumps and bonding layers. This solves the problems of the increase in the size of the semiconductor memory device and the increase in manufacturing costs, and achieves Miniaturization and cost reduction of semiconductor devices.
Patent Information
- Application Number
- CN201810847601.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2018-03-22
- Filing Date
- 2018-07-27
- Publication Date
- 2025-01-21
- Estimated Expiration
- 2038-07-27
AI Technical Summary
As the memory capacity of semiconductor memory devices increases, the number of layers of chips increases, resulting in larger device sizes and higher manufacturing costs, making it difficult to achieve miniaturization and lower cost.
Adopting an alternating layered structure design, multiple semiconductor chips are alternately arranged in the cross direction on the surface of the basic component to form the first layered body and the second layered body, and the chip bonding and connection are realized through connecting bumps and bonding layers. .
Through this structural design, the size of the laminated body can be reduced, the manufacturing cost can be reduced, and the size and cost of the semiconductor device can be reduced.
Smart Images
Figure CN110299364B_ABST
Abstract
Description
[0001] [Related applications]
[0002] This application claims priority based on Japanese Patent Application No. 2018-55029 (filing date: March 22, 2018). This application incorporates the entire contents of the basic application by reference. Technical Field
[0003] Embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art
[0004] For example, there is a semiconductor memory device having a structure in which a plurality of semiconductor memory chips are stacked on a substrate and molded with resin. In such a semiconductor device, as the storage capacity increases, the number of stacked chips increases, thereby increasing the size of the device and the manufacturing cost. Summary of the invention
[0005] Embodiments of the present invention provide a semiconductor device that can be miniaturized and reduced in cost, and a method for manufacturing the same.
[0006] A semiconductor device according to an embodiment of the present invention comprises: a base member; a first laminate including a first semiconductor chip and a second semiconductor chip alternately laminated in a first direction intersecting a surface of the base member; and a second laminate arranged in a second direction along the surface of the base member and arranged in parallel with the first laminate, and including other first semiconductor chips and other second semiconductor chips alternately laminated in the first direction. The first laminate includes the first semiconductor chip at the bottom layer connected to the base member, and the second laminate includes the second semiconductor chip at the bottom layer connected to the base member. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 and Figure 2 It is a schematic diagram showing a semiconductor device according to an embodiment.
[0008] Figure 3 and Figure 4 It is a schematic diagram showing the structure of a semiconductor device according to an embodiment.
[0009] Figures 5 to 8 This is a schematic cross-sectional view showing a semiconductor chip included in the semiconductor device according to the embodiment.
[0010] Figures 9 to 13 It is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.
[0011] Fig.14 and Fig.15 It is a schematic diagram showing the structure of a semiconductor device of a comparative example. DETAILED DESCRIPTION
[0012] Hereinafter, the embodiments will be described with reference to the drawings. The same parts in the drawings are given the same numbers and their detailed description is appropriately omitted, and different parts are described. In addition, the drawings are schematic or conceptual diagrams, and the relationship between the thickness and width of each part, the size ratio between the parts, etc. may not be the same as the actual situation. In addition, even when representing the same part, there is a case where the mutual size or ratio is represented differently depending on the difference in the drawings.
[0013] Furthermore, the configuration and structure of each part are described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X direction, Y direction, and Z direction, respectively. In addition, there is a case where the Z direction is set to the top and the opposite direction is set to the bottom for description.
[0014] Figure 1 and Figure 2 It is a schematic diagram showing a semiconductor device 1 according to an embodiment. Figure 1 is a cross-sectional view showing the structure of the semiconductor device 1, Figure 2 It is a schematic plan view showing the upper surface of the semiconductor device 1 .
[0015] The semiconductor device 1 is, for example, a large-capacity nonvolatile memory device, and includes a base member 10 , a laminate 20A, and a laminate 20B. The laminates 20A and 20B are disposed on the base member 10 .
[0016] The laminated bodies 20A and 20B are arranged in the X direction along the upper surface of the base member 10. The laminated bodies 20A and 20B respectively include a plurality of semiconductor chips CA and a plurality of semiconductor chips CB alternately laminated in a direction intersecting the upper surface of the base member 10, for example, in the Z direction. The laminated bodies 20A and 20B are, for example, resin molded on the base member 10.
[0017] The laminated body 20A includes a semiconductor chip CA located at the bottom layer connected to the base member 10 . The laminated body 20B includes a semiconductor chip CB located at the bottom layer connected to the base member 10 .
[0018] like Figure 1 As shown, the semiconductor device 1 further includes a logic chip 30. The logic chip 30 is connected to the lower surface of the base member 10 via, for example, flip chip bumps (hereinafter, FC bumps 33).
[0019] The base component 10 is, for example, a mounting substrate, and includes connection pads 13, wiring 15, and through-hole contacts 17. The wiring 15 is provided on the upper surface side of the base component 10, and the connection pads 13 are provided on the lower surface side of the base component 10. The through-hole contacts 17 penetrate from the lower surface to the upper surface of the base component 10 to electrically connect the connection pads 13 and the wiring 15.
[0020] The semiconductor chips CA and CB include through-hole contacts 21 and 23, respectively. The through-hole contacts 21 and 23 are provided, for example, so as to penetrate the substrates of the semiconductor chips CA and CB from the back side to the front side. The through-hole contacts 21 and 23 are connected to the functional layers of the semiconductor chips CA and CB, respectively (see Figure 3 The semiconductor chips CA and CB included in the laminated bodies 20A and 20B, respectively, are electrically connected to each other via through-hole contacts 21 and 23.
[0021] like Figure 1 As shown, the semiconductor chips CA and CB at the bottom are electrically connected to the wiring 15 through, for example, connection bumps 43. That is, the connection bumps 43 connect the through-hole contacts 21 and 23 of the semiconductor chips CA and CB at the bottom to the wiring 15, respectively.
[0022] The logic chip 30 is electrically connected to the wiring 15 via the connection pads 13 to which the FC bumps 33 are connected and the through-hole contacts 17. Thus, the laminated body 20A and the logic chip 30 and the laminated body 20B and the logic chip 30 are electrically connected.
[0023] The semiconductor device 1 further includes a connection member, such as a solder bump 50, disposed on the lower surface of the base member 10. The solder bump 50 is provided on the connection pad 13 and is electrically connected to the wiring 15 via the through-hole contact 17. The solder bump 50 is electrically connected to, for example, a wiring 15 different from the wiring 15 connected to the laminated bodies 20A and 20B. The solder bump 50 is connected to, for example, an external circuit, and electrically connects the logic chip 30 to the external circuit.
[0024] like Figure 2 As shown in FIG. 1 , the laminate 20A is arranged so as to overlap with a part of the logic chip 30 when viewed in the Z direction. In addition, the laminate 20B is arranged so as to overlap with another part of the logic chip 30 when viewed in the Z direction.
[0025] For example, the through-hole contacts 21 and 23 of the laminated bodies 20A and 20B are arranged above the logic chip 30. Thus, the laminated bodies 20A and 20B can be connected to the logic chip 30 at the shortest distance.
[0026] Figure 3 and Figure 4 It is a schematic diagram showing the structure of the semiconductor device 1 according to the embodiment. Figure 3It is a schematic diagram showing a partial cross section of the semiconductor device 1 . Figure 4 It is a schematic diagram showing the terminal arrangement of the semiconductor chips CA and CB.
[0027] like Figure 3 As shown, the semiconductor chip CA includes a semiconductor substrate SS, a functional layer FLA, and a bonding layer WBL. In addition, the semiconductor chip CB includes a semiconductor substrate SS, a functional layer FLB, and a bonding layer WBL. In addition, a connection pad 45 or a connection pad 47 is provided on the back side (the side opposite to the functional layer FL) of the semiconductor chips CA and CB, respectively.
[0028] like Figure 3 As shown, semiconductor chips CA and CB are bonded so that their bonding layers WBL face each other. Laminated body 20A has a structure in which laminated chip SC1 formed by bonding semiconductor chips CA and CB is laminated in the Z direction. Laminated body 20B has a structure in which laminated chip SC2 formed by bonding semiconductor chips CA and CB is laminated in the Z direction.
[0029] The stacked chip SC1 is configured to have connection bumps 43 provided on the back surface of the semiconductor chip CA via connection pads 47. Furthermore, the stacked body 20A is configured to connect the back surface of the semiconductor chip CB (the surface on the opposite side to the functional layer FLB) to the back surface of the semiconductor chip CA via the connection bumps 43 and the connection pads 45 and 47.
[0030] The buildup chip SC2 is configured to have connection bumps 43 provided on the back surface of the semiconductor chip CB via connection pads 47. The buildup body 20B is configured to connect the back surface of the semiconductor chip CB and the back surface of the semiconductor chip CA via the connection bumps 43 and the connection pads 45 and 47.
[0031] By bonding the semiconductor chip CA and the semiconductor chip CB via the bonding layer WBL, the size (height) of the laminated bodies 20A and 20B can be reduced compared to the case where all chips are laminated via the connection bumps. Thus, the semiconductor device 1 can be miniaturized.
[0032] in addition, Figure 3 In the embodiment, the through-hole contacts 21 and 23 penetrating the semiconductor chips CA and CB are omitted. In addition, the laminated bodies 20A and 20B are connected to the logic chip 30 and the solder bumps 50 via the connection pads 13 of the base member 10, the wirings 15 and the through-hole contacts 17, respectively.
[0033] like Figure 4As shown, the semiconductor chips CA and CB respectively have data terminals 0 to 7 and command terminals 0 to 3. The data terminals and command terminals of the semiconductor chip CA are, for example, through-hole contacts 21, and the data terminals and command terminals of the semiconductor chip CB are, for example, through-hole contacts 23. The data terminals and command terminals of the semiconductor chips CA and CB are connected to the data terminals and command terminals of the logic chip 30.
[0034] For example, the data terminals and the command terminals are arranged in a row along the outer edges of the semiconductor chips CA and CB. In addition, the semiconductor chips CA and CB are arranged in a manner that their data terminals and command terminals face each other at the shortest distance. The semiconductor chips CA and CB adjacent in the X direction have data terminals and command terminals arranged along the sides facing each other, and are arranged in a manner that their data terminals and command terminals are arranged in the X direction.
[0035] Furthermore, in the semiconductor chip CB bonded on the semiconductor chip CA, the data terminals are arranged at positions connected to the data terminals of the lower layer, and the command terminals are arranged at positions connected to the command terminals of the lower layer. The same is true for the semiconductor chip CA bonded on the semiconductor chip CB.
[0036] In this way, in the laminated bodies 20A and 20B, the data terminals and the command terminals are arranged in specific regions, respectively, so that the connection between the laminated bodies 20A and 20B and the logic chip 30 is facilitated.
[0037] For example, Fig.14 and Fig.15 The semiconductor device 2 shown has a structure in which laminated bodies 20A and 20B are arranged on a base member 10, and a logic chip 30 is arranged on the back side of the base member 10. The laminated bodies 20A and 20B each have a structure in which a laminated chip SC1 is laminated in the Z direction. In addition, the laminated bodies 20A and 20B are connected to the logic chip 30 via the connection pads 13, wirings 15, and through-hole contacts 17 of the base member 10.
[0038] like Fig.15 As shown in FIG. 1 , in the semiconductor device 2, the arrangement of the data terminals and the command terminals arranged along the mutually opposing sides of the adjacent semiconductor chips CA is reversed in the Y direction. Therefore, there is a portion where the data terminals and the command terminals are arranged adjacently in the X direction. Therefore, the wiring connecting the terminals of the laminated bodies 20A and 20B to the terminals of the logic chip 30 is relatively large. Figure 4 The semiconductor device 1 shown becomes more complicated.
[0039] That is, the terminal arrangement of the laminated bodies 20A and 20B cannot be made consistent with the terminal arrangement of the logic chip 30, and, for example, the wiring 15 of the base component 10 must be changed to a pattern that allows mutual connection. In addition, as the logic chip 30, a dedicated chip whose terminal arrangement is changed according to the terminal arrangement of the laminated bodies 20A and 20B must be used. Therefore, the manufacturing cost increases.
[0040] In the semiconductor device 1 of the present embodiment, the data terminals and the command terminals of the laminated bodies 20A and 20B can be arranged according to the terminal arrangement of the logic chip 30 , thereby reducing the manufacturing cost.
[0041] Figures 5 to 8 Schematic cross-sectional view showing semiconductor chips CA and CB included in the semiconductor device 1 of the embodiment. For example, if the semiconductor device 1 is distinguished by whether or not it includes the connection bump 43, the semiconductor device 1 includes four types of semiconductor chips CA1, CA2, CB1, and CB2.
[0042] like Figures 5 to 8 As shown, the bonding layer WBL includes a bonding pad 51 and an insulating film 53. The bonding pad 51 is electrically connected to the functional layer FLA or FLB, for example. The insulating film 53 is, for example, a silicon oxide film, and protects the functional layer FLA or FLB. The functional layers FLA and FLB include, for example, a memory cell array of a NAND memory element and peripheral circuits.
[0043] like Figure 5 and Figure 7 As shown, the semiconductor chips CA1 and CB1 have connection bumps 43 on the back side. Figure 6 and Figure 8 The semiconductor chips CA2 and CB2 shown do not have the connection bumps 43 on the back surface side.
[0044] The stacked body 20A includes a stacked chip SC1 formed by bonding a semiconductor chip CA1 and a semiconductor chip CB2. The stacked body 20B includes a stacked chip SC2 formed by bonding a semiconductor chip CA2 and a semiconductor chip CB1.
[0045] Secondly, refer to Figures 9 to 13 A method for manufacturing the semiconductor device 1 according to the embodiment will be described.
[0046] Figures 9 to 13 1 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device 1 in sequence. Figures 9 to 13 The through-hole contacts 21 and 23 are also omitted.
[0047] like Fig. 9As shown, a wafer 100 including a functional layer FLA and a functional layer FLB is formed. The functional layer FLA and the functional layer FLB are, for example, memory elements formed on a semiconductor substrate SS. The functional layer FLA and the functional layer FLB are alternately arranged along the surface of the semiconductor substrate SS.
[0048] Furthermore, a bonding layer WBL is formed to cover the functional layers FLA and FLB. The bonding layer WBL includes, for example, a bonding pad 51 and an insulating film 53. The bonding pad 51 is a metal layer including, for example, copper. The insulating film 53 is, for example, a silicon oxide film.
[0049] like Fig.10 As shown, a wafer 110 having a connection bump 43 is formed on the back side of a semiconductor substrate SS. The wafer 110 is a wafer 100 having a connection bump 43 formed on the back side of the wafer 100. The connection bump 43 is connected to the back side of the semiconductor substrate SS via, for example, a connection pad 47. The connection bump 43 is formed using, for example, a connection member such as a solder material. The connection pad 47 is a metal layer including, for example, copper. The connection bump 43 is not limited to a solder material, and, for example, a metal material having a lower melting point than the connection pad 47 may also be used.
[0050] In addition, a spacer SA is formed on the back surface of the semiconductor substrate SS. The spacer SA is, for example, a resin member. By arranging the spacer SA, the interval between the stacked chips SC1 or SC2 connected by the connection bumps 43 can be kept fixed (see Figure 1 ).
[0051] like Fig.11 As shown, a wafer 120 having connection pads 45 is formed on the back surface of the semiconductor substrate SS. The connection pads 45 are metal layers including, for example, copper. The wafer 120 is a wafer 100 having connection pads 45 formed on the back surface thereof.
[0052] like Fig.12 As shown, the wafer 110 and the wafer 120 are bonded together. For example, after the bonding layer WBL of the wafer 110 and the bonding layer WBL of the wafer 120 are arranged to face each other, the wafer 110 and the wafer 120 are brought into contact and bonded together by, for example, applying pressure at high temperature.
[0053] At this time, the wafer 110 and the wafer 120 are bonded together by contacting the bonding pads 51 and contacting the insulating films 53. The wafer 110 and the wafer 120 are bonded together so that the functional layers FLA and FLB face each other.
[0054] like Fig.13As shown, the bonded wafer 110 and wafer 120 are cut by, for example, a dicing machine to cut out the stacked chips SC1 and SC2. Thereafter, a stacked body 20A is formed by stacking a plurality of stacked chips SC1 on the base component 10 with the connection bumps 43 interposed therebetween. Similarly, a stacked body 20B is formed by stacking a plurality of stacked chips SC2 with the connection bumps 43 interposed therebetween (see FIG. Figure 1 ).
[0055] In the manufacturing method, the stacked chips SC1 and SC2 can be formed by bonding two wafers 100 in which the functional layers FLA and FLB are alternately arranged in at least one direction of the X direction and the Y direction. Thus, the semiconductor device 1 can be manufactured at low cost. For example, in order to manufacture two types of wafers, a wafer including the functional layer FLA and a wafer including the functional layer FLB, two mask sets must be used, but in the manufacturing method of this embodiment, the stacked chips SC1 and SC2 can be manufactured using one mask set.
[0056] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or gist of the invention, and are included in the invention described in the claims and their equivalents.
[0057] [Explanation of symbols]
[0058] 1, 2: Semiconductor devices
[0059] 10: Basic components
[0060] 13, 45, 47: Connecting pads
[0061] 15: Wiring
[0062] 17, 21, 23: Through-hole contacts
[0063] 20A, 20B: Laminated body
[0064] 30: Logic chip
[0065] 33: FC bump
[0066] 43: Connecting bumps
[0067] 50: Solder bump
[0068] 51: Bonding pad
[0069] 53: Insulation film
[0070] 100, 110, 120: Chip
[0071] CA, CA1, CA2, CB, CB1, CB2: semiconductor chips
[0072] FLA, FLB: Functional layer
[0073] WBL: Joining layer
[0074] SS: Semiconductor substrate
[0075] SA: Spacer
[0076] SC1: Stacked Chip
[0077] SC2: Stacked Chip
Claims
1. A semiconductor device comprising: Basic components; A first layered body including first semiconductor chips and second semiconductor chips alternately layered in a first direction intersecting with a surface of the base member; and a second laminated body arranged in parallel with the first laminated body in a second direction along the surface of the base member, and comprising other first semiconductor chips and other second semiconductor chips alternately laminated in the first direction; and The first laminate includes a first semiconductor chip as a bottom layer connected to the base member; The second laminate includes a second semiconductor chip at the bottom layer connected to the base member; The first semiconductor chip and the second semiconductor chip each include: a semiconductor substrate; a functional layer disposed on the semiconductor substrate; a bonding pad disposed on the functional layer; and a connecting pad disposed on the back side of the semiconductor substrate opposite to the functional layer; The first laminate and the second laminate include: a first bonding portion for bonding the functional layer of the first semiconductor chip to the functional layer of the second semiconductor chip facing each other; and a second bonding portion for bonding the semiconductor substrate of the first semiconductor chip to the semiconductor substrate of the second semiconductor chip facing each other; The first bonding portion includes a portion that directly connects a bonding pad of the first semiconductor chip and a bonding pad of the second semiconductor chip; The second joining portion includes a portion connecting the connection pad of the first semiconductor chip and the connection pad of the second semiconductor chip via a connection member.
2. A semiconductor device comprising: Basic components; A first layered body including first semiconductor chips and second semiconductor chips alternately layered in a first direction intersecting with a surface of the base member; a second laminated body arranged in parallel with the first laminated body in a second direction along the surface of the base member, and including other first semiconductor chips and other second semiconductor chips alternately laminated in the first direction; and a third semiconductor chip electrically connected to the first laminate and the second laminate; and The first laminate includes a first semiconductor chip as a bottom layer connected to the base member; The second laminate includes a second semiconductor chip at the bottom layer connected to the base member; The third semiconductor chip has a command terminal and a data terminal; The first laminate and the second laminate respectively have a first terminal connected to the command terminal and a second terminal connected to the data terminal; The first terminal of the first laminate and the first terminal of the second laminate are arranged side by side in the second direction; The second terminal of the first laminate and the second terminal of the second laminate are arranged side by side in the second direction.
3. The semiconductor device according to claim 2, wherein the first semiconductor chip and the second semiconductor chip each include a semiconductor substrate and a functional layer provided on the semiconductor substrate, The first laminate and the second laminate include: a first bonding portion for bonding a functional layer of the first semiconductor chip to a functional layer of the second semiconductor chip facing each other; and a second bonding portion for bonding a semiconductor substrate of the first semiconductor chip to a semiconductor substrate of the second semiconductor chip facing each other.
4. The semiconductor device according to claim 3, wherein the first semiconductor chip and the second semiconductor chip each have: a bonding pad provided on the functional layer; and a connection pad provided on the back side of the semiconductor substrate opposite to the functional layer; and The first bonding portion includes a portion that directly connects a bonding pad of the first semiconductor chip and a bonding pad of the second semiconductor chip. The second joining portion includes a portion connecting the connection pad of the first semiconductor chip and the connection pad of the second semiconductor chip via a connection member.
5. A method for manufacturing a semiconductor device, comprising forming a first wafer having a first surface and a second surface opposite to the first surface, wherein the first surface includes a first functional layer and a second functional layer arranged alternately with the first functional layer, forming a second wafer having a first surface and a second surface opposite to the first surface, wherein the first surface includes a first functional layer and a second functional layer arranged alternately with the first functional layer, forming a wafer bonded body, wherein the first surface of the first wafer and the first surface of the second wafer are bonded in such a manner that the first functional layer of the first wafer and the second functional layer of the second wafer are bonded, and the second functional layer of the first wafer and the first functional layer of the second wafer are bonded, The chip assembly is divided into a plurality of first stacked chips and a plurality of second stacked chips, wherein the first stacked chips respectively include a first functional layer of the first chip and a second functional layer of the second chip bonded to the first functional layer of the first chip, and the second stacked chips respectively include a first functional layer of the second chip and a second functional layer of the first chip bonded to the first functional layer of the second chip.
6. The method for manufacturing a semiconductor device according to claim 5, wherein forming a first connection pad on the second surface of the first wafer, forming a second connection pad on the second surface of the second chip, The first build-up chip and the second build-up chip have a first substrate which is a part of the first wafer and a second substrate which is a part of the second wafer. A plurality of the first stacked chips are stacked in a manner such that the first connection pads face the second connection pads, and the first connection pads and the second connection pads are connected via a conductor to form a first stacked body. A plurality of the second build-up chips are stacked up so that the first connection pads face the second connection pads, and the first connection pads and the second connection pads are connected via a conductor to form a second build-up body.
7. The method for manufacturing a semiconductor device according to claim 5, wherein a first buildup body including a plurality of the first buildup chips and a second buildup body including a plurality of the second buildup chips are formed on a base member.
Citation Information
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