Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package can include a substrate, a microelectromechanical device disposed on the substrate, an interconnect structure connecting the substrate to the microelectromechanical device, and a metal seal structure surrounding the interconnect structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package and a method for manufacturing the same, and to a semiconductor package comprising a substrate and a microelectromechanical device and a method for manufacturing the same. Background Technology

[0002] In comparative processes for manufacturing packages integrated with microelectromechanical devices (MEMS), specific materials such as LiNbO3 or LiTaO3 can be used. However, integrating packages formed from LiNbO3 or LiTaO3 with other silicon-based packages may be challenging, potentially raising concerns about structural strength and package reliability. Furthermore, the metal interconnect structures of certain comparative packages connecting the MEMS to the substrate may be exposed to the environment, potentially leading to oxidation or contamination of the metal interconnect structures. Summary of the Invention

[0003] According to some embodiments of this disclosure, a semiconductor package may include: a substrate, a microelectromechanical device disposed on the substrate, an interconnect structure connecting the substrate to the microelectromechanical device, and a metal sealing structure surrounding the interconnect structure.

[0004] According to some embodiments of this disclosure, a semiconductor package includes: a substrate having a first surface and a second surface, the second surface opposing the first surface to define an opening; the substrate further including conductive pillars disposed in the opening; a microelectromechanical device (MEMS) disposed on the substrate; an interconnect structure disposed between the substrate and the MEMS; and a sealing structure disposed between the substrate and the MEMS. The semiconductor package further includes: a first conductive pattern disposed on the first surface of the substrate and facing the MEMS; and a second conductive pattern disposed on the second surface of the substrate. The first conductive pattern is electrically connected to the second conductive pattern via the conductive pillars, and the interconnect structure is surrounded by the sealing structure.

[0005] According to some embodiments of this disclosure, a method for manufacturing a semiconductor package includes: providing a substrate, providing a microelectromechanical device (MEMS), and forming an interconnect structure and a sealing structure between the substrate and the MEMS. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of this disclosure can be best understood in the following detailed description. It should be noted that features may not be drawn to scale, and the dimensions of features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 This describes a semiconductor package according to some embodiments of the present disclosure.

[0008] Figure 2 Description of some embodiments according to this disclosure Figure 1 A cross-sectional view of the hermetically sealed structure of a semiconductor package.

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E as well as Figure 3F This invention describes a method for manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0010] Figure 4A Description of some embodiments according to this disclosure Figure 1 A top view of a semiconductor package.

[0011] Figure 4B as well as Figure 4C Description of some embodiments according to this disclosure Figure 4A An enlarged view of the sealing structure.

[0012] Figure 5A This describes a semiconductor package according to some embodiments of the present disclosure.

[0013] Figure 5B This describes a semiconductor package according to some embodiments of the present disclosure.

[0014] Figure 5C This describes a semiconductor package according to some embodiments of the present disclosure.

[0015] Figure 6 This describes a semiconductor package according to some embodiments of the present disclosure.

[0016] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar components. This disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0017] Various embodiments of this disclosure are discussed in detail below. However, it should be understood that the embodiments illustrate many applicable concepts that can be embodied in a wide variety of specific environments. It should be understood that the following disclosure provides many different embodiments or instances of different features implementing various embodiments. Specific examples of components and arrangements are described below for illustrative purposes. Of course, these are merely examples and are not intended to be limiting.

[0018] The embodiments or examples illustrated in the figures below are presented using specific languages. However, it will be understood that the embodiments and examples described are not intended to be limiting. As will be understood by those skilled in the art, any changes and modifications to the disclosed embodiments and any further application of the principles disclosed in this document are within the scope of this disclosure.

[0019] Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for the purposes of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0020] According to at least some embodiments of this disclosure, the substrate is connected to the microelectromechanical device (MEMS) via a metal sealing structure and an interconnect structure. The interconnect structure surrounded by the metal sealing structure provides higher structural strength, improved stress management, and package reliability. The metal sealing structure provides improved hermetic sealing. Because the metal sealing structure can at least partially block ambient humidity, oxidation of the interconnect structure electrically connected to the conductive pillars can be avoided or suppressed. The interconnect structure electrically connected to the conductive pillars can shorten signal transmission paths and reduce signal loss. First and second sealing structures comprising multiple trenches filled with adhesive elements can be implemented and can help prevent solder overflow (e.g., during manufacturing).

[0021] Figure 1 This invention describes a semiconductor package 1 according to some embodiments of the present disclosure. The semiconductor package 1 includes a substrate 10, a microelectromechanical device 20, one or more interconnect structures 82, and a hermetically sealed structure 80.

[0022] Substrate 10 has a surface 101 and a surface 102 opposite to surface 101. Surface 101 of the substrate faces the microelectromechanical device 20. In one or more embodiments, substrate 10 comprises a material such as glass, silicon, or other suitable material. A protective layer (e.g., a passivation layer or photoresist layer) 60 is disposed on surface 102 of substrate 10. In one or more embodiments, protective layer 60 comprises polyimide (PI), a polymer (e.g., polypropylene (PP)), a resin, or other suitable material. Conductive bumps 90 are disposed on protective layer 60. In some embodiments, conductive bumps 90 may be solder balls.

[0023] In some embodiments, substrate 10 includes interconnect structures (e.g., conductive pillars) 88 that pass through substrate 10 to provide an electrical connection between surface 101 and surface 102 of substrate 10. In some embodiments, interconnect structure 88 is a through silicon via (TSV), and substrate 10 comprises silicon material. In some embodiments, interconnect structure 88 is a through glass via (TGV), and substrate 10 comprises glass material. Interconnect structure 88 may comprise copper (Cu) or other suitable metals or alloys. In some embodiments, a portion of protective layer 60 extends into an opening 70 defined by interconnect structure 88.

[0024] The substrate 10 may include a conductive pattern (or conductive pad) 84 disposed on a surface 101 of the substrate 10, and a conductive pattern (or conductive pad) 86 disposed on a surface 102 of the substrate 10. The conductive pattern 84 is electrically connected to the conductive pattern 86 via an interconnect structure 88. The conductive pattern 84 contacts and is electrically connected to the interconnect structure 82. In some embodiments, the conductive patterns 84 and 86 comprise copper or other suitable metals or alloys.

[0025] Microelectromechanical device 20 is disposed on surface 101 of substrate 10 and electrically connected to substrate 10. Microelectromechanical device 20 is electrically connected to conductive pattern 84 of substrate 10 via interconnect structure 82. Microelectromechanical device 20 may include surface acoustic wave (SAW) filter or other semiconductor chip (e.g., other microelectromechanical system (MEMS)). In some embodiments, microelectromechanical device 20 may include LiNbO3 or LiTaO3. Microelectromechanical device 20 has a first surface 201 facing away from substrate 10 and a second surface 202 facing substrate 10 and opposite to the first surface 201.

[0026] Interconnect structure 82 is disposed between microelectromechanical device 20 and substrate 10. Interconnect structure 82 is electrically connected to the active surface of microelectromechanical device 20 and conductive pattern 84 on surface 101 of substrate 10. Interconnect structure 82 may comprise copper or other suitable metals or alloys.

[0027] A sealing structure 80 is disposed between the microelectromechanical device 20 and the substrate 10. The sealing structure 80 surrounds the interconnect structure 82. The sealing structure 80 may comprise copper or other suitable metals or alloys. In some embodiments, the sealing structure 80 may comprise a material similar to or the same as the material of the interconnect structure 82 (e.g., copper). In some embodiments, the sealing structure 80 and the interconnect structure 82 may comprise different materials.

[0028] In some comparative semiconductor packages with microelectromechanical devices (MEMS), the hermetical structure is formed of polymer, and the MEMS are connected to the substrate via a metal layer disposed on the substrate sidewalls. However, the sealing or support capabilities of polymers are relatively weak, which can reduce the reliability of the semiconductor package. Furthermore, because the metal layer is disposed along the substrate sidewalls, the transmission path is relatively long, which may adversely affect signal transmission between the MEMS and the substrate. Additionally, because the metal layer is exposed to the environment, it can be easily oxidized or contaminated.

[0029] According to such Figure 1 In the embodiment shown, the sealing structure 80 comprises metal, which provides improved hermetic sealing, higher structural strength, stress management, and reliability for the semiconductor package 1. Furthermore, the microelectromechanical device 20 is electrically connected to the substrate 10 via an interconnect structure 82 surrounded by the sealing structure 80, which helps prevent oxidation or contamination of the interconnect structure 82. Additionally, the configuration of the interconnect structure 82 shortens the signal transmission path between the microelectromechanical device 20 and the substrate 10, which reduces signal loss and improves the performance of the semiconductor package 1.

[0030] Figure 2 Description of some embodiments according to this disclosure Figure 1 A cross-sectional view of a hermetically sealed structure 80 of a semiconductor package. The hermetically sealed structure 80 includes hermetically sealed structures 80a and 80b (which may also be referred to as sub-hermetically sealed structures) and an adhesive element 95. In some embodiments, hermetically sealed structures 80a and 80b comprise gold (Au), tin (Sn), or other suitable metals or alloys. Hermetically sealed structures 80a and 80b may comprise multiple conductive layers. In some embodiments, the adhesive element 95 comprises tin or other suitable metals.

[0031] Sealing structure 80a is disposed on surface 101 of substrate 10 and faces surface 202 of microelectromechanical device 20. Sealing structure 80b is disposed on surface 202 of microelectromechanical device 20. Sealing structures 80a and 80b are connected to each other via adhesive element 95.

[0032] Figures 3A to 3F A method for manufacturing semiconductor package 1 according to an embodiment of the present invention is described.

[0033] refer to Figure 3A A substrate 10 is provided. In some embodiments, the substrate 10 comprises glass, silicon, or other suitable material. A conductive pattern 84 is disposed on the surface 101 of the substrate 10. In some embodiments, the conductive pattern 84 comprises copper. In other specific instances, the conductive pattern 84 comprises other suitable metals or alloys.

[0034] refer to Figure 3BThe carrier 51 is attached to the surface 101 of the substrate 10. Subsequently, the thickness of the substrate 10 is reduced, for example, by using a polishing operation or other suitable operation. One or more openings 70 are formed through the substrate 10. In some embodiments, the openings 70 can be formed by performing an etching operation (such as deep reactive-ion etching, DRIE) on the surface 102 of the substrate 10.

[0035] refer to Figure 3C Interconnect structures (e.g., conductive pillars) 88 are formed in the openings 70. Each interconnect structure 88 defines an opening. The interconnect structure 88 may contain copper or other suitable metals or alloys. Conductive patterns 86 are formed on the surface 102 of the substrate 10 and contact the interconnect structures 88. In some embodiments, the conductive patterns 86 contain copper or other suitable metals or alloys. Subsequently, a protective layer 60 is formed on the surface 102 of the substrate 10 to cover the conductive patterns 86 and a portion of the interconnect structures 88. A portion of the protective layer 60 fills the openings defined by the interconnect structures 88. Conductive bumps 90 are formed on the protective layer 60 and contact the conductive patterns 86.

[0036] refer to Figure 3D The carrier 52 is attached to the protective layer 60, and the carrier 51 is removed from the substrate 10. A sealing structure 80 and one or more interconnect structures 82 are formed on the conductive pattern 84. In some embodiments, the sealing structure 80 and the interconnect structures are formed by a single process. Alternatively, they can be formed by different processes. In some embodiments, the sealing structure 80 and the interconnect structures 82 may comprise multiple conductive layers.

[0037] refer to Figure 3E A microelectromechanical device 20 having a back surface attached to a carrier 53 is mounted on a sealing structure 80 and an interconnect structure 82. The active surface of the microelectromechanical device 20 is electrically connected to the interconnect structure 82.

[0038] refer to Figure 3F Carriers 53 and 52 were removed to form such Figure 1 The semiconductor package 1 shown is illustrated. In some embodiments, the microelectromechanical device 20 may be attached to the wafer via an adhesive 11. Subsequently, a separation operation can be performed.

[0039] Figure 4A Description of some embodiments according to this disclosure Figure 1 A top view of the semiconductor package 1. For clarity, the interconnect structure 82 and the microelectromechanical device 20 are not shown. Figure 4A As shown, the sealing structure 80 is positioned along the edge of the substrate 10.

[0040] Figure 4B and4C This illustration shows an enlarged view of a portion of a sealing structure 80 according to some embodiments of the present disclosure, the portion being outlined by a dotted rectangle A. (See attached image.) Figure 4B and 4C As shown, the sealing structure 80 may include multiple openings or holes 87, which can help prevent welding material (e.g., contained in...) Figure 2 In the adhesive element 95 shown, overflow occurs during the manufacturing process. In some embodiments, the opening or hole may be circular (e.g., ...). Figure 4B (as shown in the image), square (such as) Figure 4C (as shown in the diagram), rectangular or other suitable shapes. During the bonding operation, the material of the adhesive element 95 melts and is applied between the sealing structures 80a and 80b to connect the sealing structures 80a and 80b. The molten adhesive element 95 may fill multiple openings or holes 87 in the sealing structures 80a and 80b.

[0041] Multiple openings or holes 87 arranged in a high density can define multiple receiving spaces to accommodate the molten adhesive element 95. Due to the receiving spaces of the openings or holes 87, the overflow of welding material (adhesive element 95) can be at least partially prevented.

[0042] Figure 5A This describes a semiconductor package 5a according to some embodiments of the present disclosure. The semiconductor package 5a and... Figure 1 The encapsulation is similar, and the specific differences between them will be described below.

[0043] Semiconductor package 5a includes an encapsulation substrate 10, a sealing structure 80, and an encapsulation structure 40 for microelectromechanical devices 20 and 22. In some embodiments, the material of the encapsulation structure 40 may include, for example, solder resist, PP, PI, epoxy resin, molding compound, or other suitable conductive materials. Furthermore, the interconnect structure 88 of semiconductor package 5a does not define openings (e.g., it is a monolithic post). In some embodiments, semiconductor package 5a includes another microelectromechanical device 22 similar to microelectromechanical device 20. Conductive pattern 84 is omitted in semiconductor package 5a. Conductive pattern 89 is formed in protective layer 60 and contacts conductive pattern 86. Conductive bump 90 contacts conductive pattern 89. In some embodiments, conductive pattern 89 comprises copper or other suitable metals or alloys.

[0044] Figure 5B This describes a semiconductor package 5b according to some embodiments of the present disclosure. The semiconductor package 5b and... Figure 5A The encapsulation is similar, and the specific differences between them will be described below.

[0045] Semiconductor package 5b includes a protective layer 62 disposed on a surface 101 of substrate 10. The protective layer 62 may cover a first portion of conductive pattern 84 and expose a second portion of conductive pattern 84 for electrical connection. In one or more embodiments, the protective layer 62 comprises PI, a polymer, a resin, or other suitable material. An encapsulation structure 40 is disposed on the protective layer 62. The conductive pattern 84 is electrically connected to an interconnect structure 82. In some embodiments, a sealing structure 80' is disposed on the protective layer 62. The sealing structure 80' may comprise a polymer, an insulating material, or other suitable material.

[0046] Figure 5C This describes a semiconductor package 5c according to some embodiments of the present disclosure. The semiconductor package 5c and... Figure 1 The encapsulation is similar, and the specific differences between them will be described below.

[0047] Semiconductor package 5c includes a protective layer 62 disposed on a surface 101 of substrate 10. The protective layer 62 may cover a first portion of conductive pattern 84 and expose a second portion of conductive pattern 84 for electrical interconnection. Interconnect structure 88 defines an opening. A portion of passivation layer 62 fills the opening defined by interconnect structure 88. Interconnect structure 88 contacts conductive patterns 84 and 86.

[0048] Figure 6 This describes a semiconductor package 6 according to some embodiments of the present disclosure. The semiconductor package 6 and... Figure 1 The encapsulation is similar, and the specific differences between them will be described below.

[0049] Semiconductor package 6 includes a protective layer 62 disposed on a surface 101 of substrate 10. The protective layer 62 may cover a first portion of conductive pattern 84 and expose a second portion of conductive pattern 84 for electrical connection. Semiconductor package 6 includes an adhesive 11 (e.g., a separator tape) on microelectromechanical device 20. Microelectromechanical device 20 is connected to conductive pattern 84 via conductive pattern 86 extending along the sidewall of substrate 10. A sealing structure 80 is disposed on protective layer 62.

[0050] As used herein, the terms “approximately,” “generally,” “roughly,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples of events or situations that occurred precisely or very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" or "approximately" the same.

[0051] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators. In the description of some embodiments, the phrase “on” or “above” another component may cover situations where the preceding component is directly on the following component (e.g., in physical contact with the following component), and situations where one or more intermediate components are located between the preceding and following components.

[0052] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations may not be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt specific circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor package comprising: Substrate; Microelectromechanical devices mounted on the substrate; The substrate is electrically connected to the interconnect structure of the microelectromechanical device; as well as A metal sealing structure surrounding and hermetically sealing the interconnect structure, wherein the substrate has a first surface facing the microelectromechanical device (MEMS), and the MEMS has a bottom surface facing the substrate, and the metal sealing structure includes: A first sealing structure disposed on the first surface of the substrate; as well as A second sealing structure disposed on the bottom surface of the microelectromechanical device. The first sealing structure and the second sealing structure are connected to each other, wherein the metal sealing structure does not contact the interconnect structure and is separate from the interconnect structure, wherein the metal sealing structure surrounds and hermetically seals the active surface of the microelectromechanical device.

2. The semiconductor package of claim 1, wherein the first sealing structure and the second sealing structure are connected to each other via an adhesive element, wherein the adhesive element comprises metal.

3. The semiconductor package of claim 2, wherein the first sealing structure and the second sealing structure comprise a plurality of metal conductive layers, and the outer sidewalls of the first sealing structure and the second sealing structure are exposed to air.

4. The semiconductor package of claim 3, wherein the substrate has a second surface opposite to the first surface of the substrate, and the semiconductor package further comprises: A first conductive pattern is disposed on the first surface of the substrate; as well as A second conductive pattern is disposed on the second surface of the substrate. The first conductive pattern is electrically connected to the interconnect structure, wherein the first conductive pattern contacts the interconnect structure but does not contact the metal sealing structure.

5. The semiconductor package of claim 4, further comprising conductive bumps, wherein the second conductive pattern is electrically connected to the first conductive pattern via conductive pillars, wherein the conductive bumps contact the second conductive pattern.

6. The semiconductor package of claim 5, further comprising a first protective layer formed on the second surface of the substrate, wherein the conductive bumps are formed on the first protective layer and exposed to air.

7. The semiconductor package of claim 5, wherein the interconnect structure and the conductive pillar are offset from each other and misaligned in a cross-sectional view.

8. The semiconductor package of claim 2, wherein the metal sealing structure includes a plurality of openings or holes that prevent the adhesive element from overflowing during the manufacturing process.

9. The semiconductor package of claim 4, further comprising a second protective layer disposed on the first surface of the substrate, the second protective layer covering a first portion of the first conductive pattern and exposing a second portion of the first conductive pattern for electrical connection.

10. The semiconductor package of claim 9, wherein the second protective layer is disposed in the metal sealing structure and the interconnect structure, wherein a portion of the second protective layer contacts the sidewall of the metal sealing structure and a portion contacts the sidewall of the interconnect structure.

11. The semiconductor package of claim 1, wherein the first and second sealing structures comprise gold or tin.

12. The semiconductor package of claim 2, wherein the metal sealing structure defines a plurality of holes filled with the adhesive element.

13. A semiconductor package comprising: A substrate having a first surface and a second surface, the second surface being opposite to the first surface to define an opening, the substrate further comprising a conductive post disposed in the opening; Microelectromechanical devices mounted on the substrate; An interconnect structure disposed between the substrate and the microelectromechanical device; A metal sealing structure disposed between the substrate and the microelectromechanical device (MEMS), wherein the metal sealing structure surrounds and hermetically seals the interconnect structure, wherein the substrate has a first surface facing the MEMS, and the MEMS has a bottom surface facing the substrate, and the metal sealing structure includes: A first sealing structure disposed on the first surface of the substrate; and A second sealing structure disposed on the bottom surface of the microelectromechanical device. The first sealing structure and the second sealing structure are connected to each other; A first conductive pattern disposed on the first surface of the substrate and facing the microelectromechanical device; and A second conductive pattern disposed on the second surface of the substrate. The first conductive pattern is electrically connected to the second conductive pattern via the conductive post, and The interconnect structure is surrounded by the metal sealing structure, wherein the metal sealing structure does not contact the interconnect structure and is separate from the interconnect structure, wherein the metal sealing structure surrounds and hermetically seals the active surface of the microelectromechanical device.

14. The semiconductor package of claim 13, wherein the first sealing structure and the second sealing structure are connected to each other via an adhesive element, wherein the adhesive element comprises metal.

15. The semiconductor package of claim 14, wherein the first sealing structure and the second sealing structure comprise a plurality of metal conductive layers, and the outer sidewalls of the first sealing structure and the second sealing structure are exposed to air.

16. The semiconductor package of claim 13, wherein the first conductive pattern is electrically connected to the interconnect structure, wherein the first conductive pattern contacts the interconnect structure but does not contact the metal sealing structure.

17. The semiconductor package of claim 16, further comprising conductive bumps, wherein the conductive bumps contact the second conductive pattern.

18. The semiconductor package of claim 17, further comprising a first protective layer formed on the second surface of the substrate, wherein the conductive bumps are formed on the first protective layer and exposed to air.

19. A method for manufacturing a semiconductor package, comprising: Provide substrate; Provide microelectromechanical devices; An interconnect structure and a metal sealing structure are formed between the substrate and the microelectromechanical device (MEMS), wherein the interconnect structure electrically connects the substrate to the MEMS, wherein the substrate has a first surface facing the MEMS, and the MEMS has a bottom surface facing the substrate. A first sub-sealing structure is formed on the first surface of the substrate; A second sub-sealing structure is formed on the bottom surface of the microelectromechanical device; as well as The first sub-sealing structure and the second sub-sealing structure are connected to each other to form the metal sealing structure, wherein the metal sealing structure does not contact the interconnect structure and is separate from the interconnect structure, wherein the metal sealing structure surrounds and hermetically seals the active surfaces of the interconnect structure and the microelectromechanical device.

20. The method of claim 19, wherein the first sub-sealing structure and the second sub-sealing structure are connected to each other via an adhesive element comprising metal, and the outer sidewalls of the first sub-sealing structure and the second sub-sealing structure are exposed to air.

21. The method according to claim 19, wherein: The substrate has a first surface and a second surface opposite to the first surface. The substrate includes: A first conductive pattern is formed on the first surface of the substrate. An opening is formed within the substrate. A conductive post is formed in the opening, and A second conductive pattern is formed on the second surface of the substrate, and The first conductive pattern is electrically connected to the second conductive pattern via the conductive post, and the interconnect structure is electrically connected to the first conductive pattern, wherein the first conductive pattern contacts the interconnect structure but does not contact the metal sealing structure.

22. The method of claim 21, further comprising forming a first protective layer on the second surface of the substrate, wherein conductive bumps are formed on the first protective layer and exposed to air.

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