Semiconductor device including gate separation region

Abstract

A semiconductor device including a gate separation region is provided. The semiconductor device includes: an isolation region between active regions; an interlayer insulating layer on the isolation region; a gate line structure overlapping the active region, the gate line structure being located on the isolation region and having ends opposite to each other; and a gate separation region on the isolation region, the gate separation region being located between the ends opposite to each other of the gate line structure and between the interlayer insulating layers. The gate separation region includes a gap filling layer and a buffer structure, the buffer structure including a buffer liner, the buffer liner being located between the gap filling layer and the isolation region, between the ends opposite to each other of the gate line structure and the side surface of the gap filling layer, and between the interlayer insulating layer and the side surface of the gap filling layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0048632, entitled “Semiconductor Device Including Gate Separation Region”, filed on April 26, 2018 in the Korean Intellectual Property Office is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments relate to a semiconductor device including a gate separation region. Background Art

[0004] Generally, as the trend toward higher integration in semiconductor devices increases, the area occupied by transistors can be reduced. Therefore, as the size of transistors can be reduced, the process of forming components constituting the transistors (e.g., gates with smaller sizes) becomes increasingly important. Summary of the invention

[0005] An embodiment can be implemented by providing a semiconductor device, which includes: an isolation region between active regions; an interlayer insulating layer on the isolation region; a gate line structure overlapping the active region, the gate line structure being located on the isolation region and having ends opposite to each other; and a gate separation region on the isolation region, the gate separation region being located between the ends opposite to each other of the gate line structure and between the interlayer insulating layers, wherein the gate separation region includes a gap filling layer and a buffer structure, the buffer structure including a buffer liner, the buffer liner being located between the gap filling layer and the isolation region, between the ends opposite to each other of the gate line structure and the side surface of the gap filling layer, and between the interlayer insulating layer and the side surface of the gap filling layer.

[0006] The embodiment can be implemented by providing a semiconductor device, the semiconductor device comprising: a first active region and a second active region, the first active region and the second active region being located on a semiconductor substrate and spaced apart from each other; an isolation region on the semiconductor substrate, the isolation region comprising a region between the first active region and the second active region; a first gate line structure overlapping the first active region and the isolation region; a second gate line structure overlapping the second active region and the isolation region, the second gate line structure having a second end, the second end facing the first end of the first gate line structure on the isolation region; a spacer covering a side surface of the first gate line structure, the spacer being disposed on the first gate line structure The gate line structure of the second gate line is connected to the first gate line structure by a first gate separation region, the first gate line structure extending in a longitudinal direction to cover the side surface of the second gate line structure; and a first gate separation region, located between the first end of the first gate line structure and the second end of the second gate line structure, and between the spacers, wherein the first gate separation region includes a first gap filling layer and a first buffer structure, the dielectric constant of the first buffer structure is smaller than the dielectric constant of the first gap filling layer; the spacer includes: a first spacer portion, covering the side surfaces of the first gate line structure and the second gate line structure; and a second spacer portion, covering the side surface of the first gate separation region, and the thickness of each of the second spacer portions is smaller than the thickness of each of the first spacer portions.

[0007] An embodiment can be implemented by providing a semiconductor device, the semiconductor device comprising: a first active region and a second active region spaced apart from each other; an isolation region comprising a region between the first active region and the second active region; a first transistor comprising: a first channel region in the first active region; a first source / drain region located on both side surfaces of the first channel region and applying compressive stress or tensile stress to the first channel region; and a first gate line structure extending on the first channel region and above the isolation region; a second transistor comprising: a second channel region in the second active region; a second source / drain region located on both side surfaces of the second channel region and applying compressive stress or tensile stress to the second channel region; and a second gate line structure extending on the second channel region and above the isolation region; and a gate separation region on the isolation region and between ends of the first gate line structure and the second gate line structure, wherein the gate separation region comprises a buffer structure and a gap filling layer; and wherein the buffer structure is formed of an insulating material having a dielectric constant lower than that of the gap filling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 shows a perspective view of a semiconductor device according to an embodiment;

[0010] Figure 2 shows a plan view of a semiconductor device according to an embodiment;

[0011] Figure 3 , Figure 4A and Figure 4B sectional views respectively showing exemplary examples of semiconductor devices according to the embodiments;

[0012] Figure 5 A cross-sectional view showing an example of a semiconductor device according to an embodiment;

[0013] Figures 6 to 18 sectional views respectively showing various modified examples of the semiconductor device according to the embodiment;

[0014] Fig.19 A plan view showing a modified example of the semiconductor device according to the embodiment;

[0015] Fig. 20A and Fig. 20B sectional views respectively showing modified examples of the semiconductor device according to the embodiment;

[0016] Figure 21 to Figure 27 sectional views respectively showing various modified examples of the semiconductor device according to the embodiment;

[0017] Fig.28 A cross-sectional view showing a modified example of the semiconductor device according to the embodiment;

[0018] Fig.29 A cross-sectional view showing a modified example of the semiconductor device according to the embodiment;

[0019] Fig.30 A view showing a modified example of the semiconductor device according to the embodiment;

[0020] Fig.31 A cross-sectional view showing a modified example of the semiconductor device according to the embodiment;

[0021] Fig.32 A view showing a modified example of the semiconductor device according to the embodiment;

[0022] Fig.33 A cross-sectional view showing a modified example of the semiconductor device according to the embodiment; and

[0023] Figures 34 to 37B Flowcharts and diagrams illustrating stages in a method of forming a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0024] First, refer to Figure 1 Illustrative examples of semiconductor devices according to embodiments are described. Figure 1 A perspective view of a semiconductor device according to an embodiment is shown.

[0025] refer to Figure 1 , the semiconductor device 1 according to an exemplary embodiment may include a first circuit region C1.

[0026] The semiconductor device 1 according to the exemplary embodiment may include a semiconductor chip, a semiconductor package formed using a single semiconductor chip, a semiconductor package formed using two or more semiconductor chips, or an electronic device formed using such a semiconductor package. In one embodiment, the semiconductor device 1 may include: a first circuit region C1 in which a transistor, etc. are formed.

[0027] Next, we will refer to Figures 2 to 4B An exemplary embodiment of a semiconductor device 1 including a first circuit region C1 is described. Figures 2 to 4B middle, Figure 2 1 shows a plan view of the first circuit region C1 of the semiconductor device 1. Figure 3 Shown along Figure 2 A cross-sectional view of the area cut by line II′ in FIG. Figure 4A Shown along Figure 2 A cross-sectional view of a region taken along line IIa-IIa′ in FIG. Figure 4B Shown along Figure 2 A cross-sectional view of the area cut along line IIb-IIb′ in FIG.

[0028] refer to Figure 2 , Figure 3 , Figure 4A and Figure 4B , a semiconductor substrate 3 may be provided. The semiconductor substrate 3 may be formed of a semiconductor material such as silicon.

[0029] The active regions 9 a and 9 b and the isolation region 6 may be on the semiconductor substrate 3 .

[0030] The active regions 9a and 9b may include a first active region 9a and a second active region 9b. The first active region 9a may include a first lower active region 9a_1 and a first upper active region 9a_2 on the first lower active region 9a_1. The second active region 9b may include a second lower active region 9b_1 and a second upper active region 9b_2 on the second lower active region 9b_1.

[0031] The first lower active region 9a_1 and the second lower active region 9b_1 may protrude from the semiconductor substrate 3 in a vertical direction Z that is perpendicular to the semiconductor substrate 3 (e.g., perpendicular to a flat surface of the semiconductor substrate 3). The first upper active region 9a_2 may protrude from the first lower active region 9a_1 in the vertical direction Z and may be spaced apart from each other. The second upper active region 9b_2 may protrude from the second lower active region 9b_1 in the vertical direction Z and may be spaced apart from each other.

[0032] The isolation region 6 may include: a second isolation region 6b surrounding the side surfaces of the first lower active region 9a_1 and the second lower active region 9b_1 and defining the first lower active region 9a_1 and the second lower active region 9b_1; and a first isolation region 6a overlapping the first lower active region 9a_1 and the second lower active region 9b_1 and covering the side surfaces of the first upper active region 9a_2 on the first lower active region 9a_1 and the second upper active region 9b_2 on the second lower active region 9b_1. The isolation region 6 may include silicon oxide. The first upper active region 9a_2 and the second upper active region 9b_2 may protrude from the first lower active region 9a_1 and the second lower active region 9b_1 in the vertical direction Z and may extend through the first isolation region 6a. For example, the upper surfaces of the first and second active regions 9a_2 and 9b_2 may be located at a height higher than the upper surface of the first isolation region 6a (for example, the upper surfaces of the first and second active regions 9a_2 and 9b_2 may be farther away from the semiconductor substrate 3 than the upper surface of the first isolation region 6a).

[0033] The gate line structures 63a and 63b may be respectively on the first active region 9a and the second active region 9b and the isolation region 6. The gate line structures 63a and 63b may include one or more first gate line structures 63a overlapping the first active region 9a and extending onto the isolation region 6, and one or more second gate line structures 63b overlapping the second active region 9b and extending onto the isolation region 6.

[0034] Referring to the plan view or top view, the first upper active region 9a_2 and the second upper active region 9b_2 may be in the form of a line extending in the first direction X, and the gate line structures 63a and 63b may be in the form of a line extending in the second direction Y perpendicular to the first direction X. The first direction X and the second direction Y may be in a direction parallel to a horizontal portion (e.g., a flat surface) of the semiconductor substrate 3. From the plan view or top view, the first upper active region 9a_2 and the second upper active region 9b_2 may intersect with the gate line structures 63a and 63b.

[0035] In the one or more first gate line structures 63a, when multiple first gate line structures 63a are provided, a portion of the multiple first gate line structures 63a may be a first dummy line structure 63d1 that partially overlaps with the active area 9a, and the remaining portions of the multiple first gate line structures 63a may overlap with the first active area 9a and cross the first active area 9a.

[0036] In the one or more second gate line structures 63b, when multiple second gate line structures 63b are provided, a portion of the multiple second gate line structures 63b may be a second dummy line structure 63d2 that partially overlaps with the active area 9b, and the remaining portions of the multiple second gate line structures 63b may overlap with the second active area 9b and cross the second active area 9b.

[0037] Each of the one or more first gate line structures 63 a may include a first gate electrode line 69 a , and a first gate dielectric 66 a covering a lower surface of the first gate electrode line 69 a and covering a side surface of the first gate electrode line 69 a .

[0038] In one embodiment, each of the one or more first gate line structures 63a may include a first cover line 72a on the first gate electrode line 69a. The first cover line 72a may cover the upper surface of the first gate electrode line 69a and the upper end of the first gate dielectric 66a. The upper end of the first gate dielectric 66a may be below the first cover line 72a (e.g., closer to the semiconductor substrate 3 than the first cover line 72a).

[0039] Each of the one or more second gate line structures 63b may include a second gate electrode line 69b, and a second gate dielectric 66b covering a lower surface of the second gate electrode line 69b and covering a side surface of the second gate electrode line 69b.

[0040] In one embodiment, each of the one or more second gate line structures 63b may include a second cover line 72b on the second gate electrode line 69b. The second cover line 72b may cover an upper surface of the second gate electrode line 69b and an upper end of the second gate dielectric 66b.

[0041] The first gate dielectric 66a and the second gate dielectric 66b may include silicon oxide and / or a high-k dielectric having a dielectric constant higher than that of silicon oxide. The first gate electrode line 69a and the second gate electrode line 69b may be formed of any one or a combination of doped polysilicon, metal nitride (e.g., TiN, TaN, WN, etc.) and metal (e.g., Ti, Ta, W, etc.).

[0042] Depending on the characteristics or types of transistors that can be formed on the first active area 9a and the second active area 9b, the first gate dielectric 66a and the second gate dielectric 66b can be formed of the same material with different thicknesses from each other, or different materials from each other, and the first gate electrode line 69a and the second gate electrode line 69b can be formed of a conductive material having the same work function, or can be formed of a conductive material having different work functions from each other.

[0043] In one embodiment, the first cover wire 72a and the second cover wire 72b may be formed of the same material as each other. In one embodiment, the first cover wire 72a and the second cover wire 72b may be formed of silicon nitride or a silicon nitride-based insulating material. In one embodiment, the first cover wire 72a and the second cover wire 72b may be formed of a metal material such as tungsten, which has a higher conductivity than that of metal nitride to improve the electrical characteristics of the semiconductor device.

[0044] For convenience or to better understand the following content, one first gate line structure 63a that crosses the first active area 9a among the one or more first gate line structures 63a, and one second gate line structure 63b that crosses the second active area 9b among the one or more second gate line structures 63b will be mainly described. In one embodiment, the semiconductor device may include multiple first gate line structures 63a that cross the first active area 9a among the one or more first gate line structures 63a, and multiple second gate line structures 63b that cross the second active area 9b among the one or more second gate line structures 63b.

[0045] The first source / drain region 24a may be on the first active region 9a, and the second source / drain region 24b may be on the second active region 9b. The first source / drain region 24a may include a portion of the first recessed region 21a in the first upper active region 9a_2 filling the first active region 9a. The second source / drain region 24b may include a portion of the second recessed region 21b in the second upper active region 9b_2 filling the second active region 9b. For example, each first source / drain region 24a may have a strip-shaped form on the first lower active region 9a_1 and cross the first upper active region 9a_2. Each second source / drain region 24b may have a strip-shaped form on the second lower active region 9b_1 and cross the second upper active region 9b_2.

[0046] The first channel region CH1 may be formed in the first upper active region 9a_2 located between the first source / drain regions 24a, and the second channel region CH2 may be formed in the second upper active region 9b_2 located between the second source / drain regions 24b. The first gate line structure 63a crossing the first active region 9a may include a portion on the first channel region CH1, and the second gate line structure 63b crossing the second active region 9b may include a portion on the second channel region CH2. In the case where the first gate line structure 63a crossing the first active region 9a is set to be multiple, the first channel region CH1 may be set to be multiple to correspond to the multiple first gate line structures 63a. In the case where the second gate line structure 63b crossing the second active region 9b is set to be multiple, the second channel region CH2 may be set to be multiple to correspond to the multiple second gate line structures 63b.

[0047] In one embodiment, the first source / drain region 24a, the first channel region CH1 in the first upper active region 9a_2 between the first source / drain regions 24a, the first gate dielectric 66a and the first gate electrode line 69a on the first channel region CH1 may constitute a first transistor TR1. The second source / drain region 24b, the second channel region CH2 in the second upper active region 9b_2 between the second source / drain regions 24b, the second gate dielectric 66b and the second gate electrode line 69b on the second channel region CH2 may constitute a second transistor TR2.

[0048] In one embodiment, the first transistor TR1 and the second transistor TR2 may be NMOS transistors or PMOS transistors. In one embodiment, the first transistor TR1 may be an NMOS transistor, and the second transistor TR2 may be a PMOS transistor.

[0049] In one embodiment, when the first and second transistors TR1 and TR2 are NMOS transistors, the first and second source / drain regions 24a and 24b may have N-type conductivity and may be formed of a silicon epitaxial layer capable of imparting tensile stress to the first and second channel regions CH1 and CH2.

[0050] In one embodiment, when the first transistor TR1 and the second transistor TR2 are PMOS transistors, the first source / drain region 24a and the second source / drain region 24b may have P-type conductivity and may be formed of a silicon-germanium SiGe epitaxial layer capable of imparting compressive stress to the first channel region CH1 and the second channel region CH2.

[0051] In one embodiment, when the first transistor TR1 may be an NMOS transistor, the first source / drain region 24a may be formed of a silicon epitaxial layer capable of imparting tensile stress to the first channel region CH1. When the second transistor TR2 is a PMOS transistor, the second source / drain region 24b may be formed of a silicon-germanium SiGe epitaxial layer capable of imparting compressive stress to the second channel region CH2.

[0052] As described above, the first gate line structure 63a may overlap the first active region 9a and may extend onto the isolation region 6, and the second gate line structure 63b may overlap the second active region 9b and may extend onto the isolation region 6. The first gate line structure 63a and the second gate line structure 63b may have ends facing each other on the isolation region 6 between the first active region 9a and the second active region 9b. For example, the first end 63e1 of the first gate line structure 63a may face the second end 63e2 of the second gate line structure 63b on the isolation region 6 between the first active region 9a and the second active region 9b.

[0053] The gate separation region 40 may be located on the isolation region 6 between the first active region 9a and the second active region 9b. In one embodiment, when the first gate line structure 63a is provided in plurality and the second gate line structure 63b is provided in plurality, the gate separation region 40 may be provided in plurality.

[0054] In one embodiment, the gate separation region 40 may have an upper surface coplanar with the upper surfaces of the first gate line structure 63a and the second gate line structure 63b. For example, the gate separation region 40 may have an upper surface coplanar with the upper surfaces of the first cover line 72a and the second cover line 72b of the first gate line structure 63a and the second gate line structure 63b.

[0055] In one embodiment, the gate separation region 40 may impart tensile stress to the first channel region CH1 and the second channel region CH2 to help improve the performance of the first transistor TR1 and the second transistor TR2 .

[0056] The spacer 18 may be on the side surface of the first gate line structure 63a and the second gate line structure 63b, and may extend to the side surface of the gate separation region 40. Therefore, the first gate line structure 63a and the second gate line structure 63b and the gate separation region 40 may be between adjacent spacers 18. Referring to the plan view or the top view, the spacer 18 may be in the form of a line extending in the second direction Y. The spacer 18 may be formed of an insulating material. For example, the spacer 18 may be formed of an insulating material such as SiN, SiCN, SiOCN, etc.

[0057] The spacer 18 may include a first spacer portion 18a covering the side surfaces of the first gate line structure 63a and the second gate line structure 63b, and a second spacer portion 18b covering the side surfaces of the gate separation region 40. In one embodiment, the width of the first spacer portion 18a may be wider than the width of the second spacer portion 18b. For example, the second spacer portion 18b may be narrower than the first spacer portion 18a.

[0058] The first gate dielectric 66a may cover the lower surface of the first gate electrode line 69a, may extend between the first gate electrode line 69a and the spacer 18, and may extend between the first gate electrode line 69a and the gate separation region 40. The second gate dielectric 66b may cover the lower surface of the second gate electrode line 69b, may extend between the second gate electrode line 69b and the spacer 18, and may extend between the second gate electrode line 69b and the gate separation region 40.

[0059] The interlayer insulating layer 27 may be located on the second isolation region 6b of the isolation region 6. On the second isolation region 6b, spacers 18 may be formed between the gate line structures 63a and 63b and the interlayer insulating layer 27, and between the gate separation region 40 and the interlayer insulating layer 27.

[0060] The interlayer insulating layer 27 may be formed as a single layer formed of silicon oxide, or may be formed as a stacked structure including silicon oxide and silicon nitride stacked in sequence. The first contact structure 78a may be on the first source / drain region 24a, and the second contact structure 78b may be on the second source / drain region 24b.

[0061] The first and second capping lines 72a and 72b, the spacer 18, and the gap-filling layer 52 of the gate separation region 40 may act as etching masks in an etching process for forming the first and second contact structures 78a and 78b. Therefore, the first and second contact structures 78a and 78b may be formed by a self-aligned contact process.

[0062] Will refer to Figure 5 Description Reference above Figures 2 to 4B An illustrative example of gate separation region 40 is described. Figure 5 Shown are Figure 2 A cross-sectional view of the area cut by line IIIa-IIIa′ and line IVa-IVa′.

[0063] Reference Figure 5 Together with Figures 2 to 4B The gate separation region 40 may be a gate separation region 40 a including a gap filling layer 52 and a buffer structure. The buffer structure may include a buffer liner 46 covering a bottom surface and a side surface of the gap filling layer 52.

[0064] In the first direction X (ie, in the width direction X of the first and second gate line structures 63 a and 63 b ), the width of each of the first and second gate line structures 63 a and 63 b may be narrower than the width of the gate separation region 40 .

[0065] The buffer liner 46 of the buffer structure can be located between the gap filling layer 52 and the isolation region 6, between the gap filling layer 52 and the second spacer portion 18b of the spacer 18, between the gap filling layer 52 and the first end 63e1 of the first gate line structure 63a, and between the gap filling layer 52 and the second end 63e2 of the second gate line structure 63b.

[0066] In one implementation, the gate separation region 40 a may further include a lower insulating layer 12 a between the buffer liner 46 and the isolation region 6 .

[0067] The buffer liner 46 may be formed of an insulating material having a dielectric constant higher than that of silicon oxide and lower than that of silicon nitride. In the case where the isolation region 6 includes silicon oxide, the dielectric constant of the buffer liner 46 may be higher than the dielectric constant of the silicon oxide of the isolation region 6. The dielectric constant of the buffer liner 46 may be higher than the dielectric constant of the lower insulating layer 12a. The gap filling layer 52 may be formed of an insulating material having a dielectric constant higher than that of the insulating material of the buffer liner 46.

[0068] The buffer liner 46 may be formed of an insulating material having a dielectric constant between about 4 and about 5. The gap-filling layer 52 may be formed of an insulating material having a dielectric constant higher than that of the buffer liner 46 (e.g., an insulating material having a dielectric constant of about 5 or more). For example, the buffer liner 46 may be formed of an insulating material such as SiOCN, SiON, etc., and the gap-filling layer 52 may be formed of an insulating material such as SiN, etc.

[0069] Will refer to Figure 6 Description Reference above Figures 2 to 4B A modified embodiment of the gate separation region 40 is described. Figure 6 Shown by Figure 2 sectional view of the region indicated by line IIIa-IIIa′ in FIG.

[0070] In a modified embodiment, and with reference to Figure 6 Together with Figures 2 to 4B, between the second spacer portions 18b of the spacer 18, the gate separation region 40 may be a gate separation region 40b that can be between the second spacer portions 18b and can extend into the isolation region 6. The gate separation region 40b may include a gap filling layer 52 and a buffer structure, and a buffer liner 46 of the buffer structure covers the bottom surface and side surfaces of the gap filling layer 52. The lower surface of the gate separation region 40b may exist below the lower surface of the spacer 18.

[0071] Reference Figure 7 Description Reference above Figures 2 to 4B Another modified embodiment of the gate separation region 40 is described. Figure 7 Shown by Figure 2 sectional view of the region indicated by line IIIa-IIIa′ in FIG.

[0072] In another modified embodiment, and with reference to Figure 7 Together with Figures 2 to 4B , between the second spacer portions 18b of the spacer 18, the gate separation region 40 may be a gate separation region 40c that can be between the second spacer portions 18b and can extend into the isolation region 6, and the width of the lower portion thereof may be greater than the width of the upper portion. The gate separation region 40c may include a gap filling layer 52 and a buffer structure, and a buffer liner 46 of the buffer structure covers the bottom surface and side surfaces of the gap filling layer 52. The lower surface of the gate separation region 40c may exist below the lower surface of the spacer 18.

[0073] Reference Figure 8 Description Reference above Figures 2 to 4B Another modified embodiment of the gate separation region 40 is described. Figure 8 Shown by Figure 2 A cross-sectional view of the region indicated by line IVa-IVa′ in FIG.

[0074] In another modified embodiment, and with reference to Figure 8 Together with Figures 2 to 4B , between the first end portion 63e1 and the second end portion 63e2 opposite to each other in the first gate line structure 63a and the second gate line structure 63b, the gate separation region 40 may be a gate separation region 40d that can be located between the first end portion 63e1 and the second end portion 63e2 and can extend into the isolation region 6. The gate separation region 40d may include a gap filling layer 52 and a buffer structure, and a buffer liner 46 of the buffer structure covers the bottom surface and the side surface of the gap filling layer 52. The lower surface of the gate separation region 40d may exist below the lower surfaces of the first gate line structure 63a and the second gate line structure 63b.

[0075] Reference Fig. 9 Description Reference above Figures 2 to 4BAnother modified embodiment of the gate separation region 40 is described. Fig. 9 Shown by Figure 2 A cross-sectional view of the region indicated by line IVa-IVa′ in FIG.

[0076] In another modified embodiment, and with reference to Fig. 9 Together with Figures 2 to 4B , between the first end 63e1 and the second end 63e2 opposite to each other in the first gate line structure 63a and the second gate line structure 63b, the gate separation region 40 may be a gate separation region 40e that can be located between the first end 63e1 and the second end 63e2, can extend into the isolation region 6, and the width of the lower portion thereof may be greater than the width of the upper portion. The gate separation region 40e may include a gap filling layer 52 and a buffer structure, and a buffer liner 46 of the buffer structure covers the bottom surface and the side surface of the gap filling layer 52.

[0077] exist Figures 6 to 9 The buffer liner 46 and the gap filling layer 52 described with the same reference numerals in the drawings may be made of Figure 5 The buffer liner 46 and the gap filling layer 52 described in the above are formed of the same material. In one embodiment, the following components denoted by the same reference numerals as the above components may be formed of the same material as the above materials. Therefore, with reference to the components described with the same reference numerals, the description of the components repeatedly referenced after the description of the first-mentioned components can be understood based on the first-mentioned components and can therefore be omitted.

[0078] Will refer to Fig.10 Description Reference above Figures 2 to 4B Another modified embodiment of the gate separation region 40 is described. Fig.10 Shown are Figure 2 2 is a cross-sectional view of the region indicated by lines IIIa-IIIa′ and IVa-IVa′.

[0079] In another modified embodiment, and with reference to Fig.10 Together with Figures 2 to 4B The gate separation region 40 may be a gate separation region 40 f including a buffer structure and a gap filling layer 152 on the buffer structure. The buffer structure may include a lower buffer layer 150 .

[0080] In one implementation, the gate separation region 40 f may further include a lower insulating layer 12 a between the lower buffer layer 150 and the isolation region 6 .

[0081] The lower buffer layer 150 may be formed of an insulating material having better gap filling characteristics and having a lower dielectric constant than the gap filling layer 152. For example, the gap filling layer 152 may be formed of an insulating material such as silicon nitride, etc., and the lower buffer layer 150 may be formed of an insulating material such as silicon oxide, etc. The lower insulating layer 12a may be formed using a flowable oxide.

[0082] Will refer to Fig.11 Description Reference above Figures 2 to 4B Another modified embodiment of the gate separation region 40 is described. Fig.11 Shown are Figure 2 2 is a cross-sectional view of the region indicated by lines IIIa-IIIa′ and IVa-IVa′.

[0083] In another modified embodiment and with reference to Fig.11 Together with Figures 2 to 4B The gate separation region 40 may be a gate separation region 40 g including a buffer structure including a lower buffer layer 150 and a buffer liner 146 , and a gap filling layer 152 .

[0084] The lower buffer layer 150 and the gap filling layer 152 may be sequentially stacked. The buffer liner 146 may be located between the lower buffer layer 150 and the isolation region 6, between the side surface of the lower buffer layer 150 and the interlayer insulating layer 27, between the side surface of the lower buffer layer 150 and the end 63e1 of the first gate line structure 63a and the end 63e2 of the second gate line structure 63b, between the side surface of the gap filling layer 152 and the interlayer insulating layer 27, and between the side surface of the gap filling layer 152 and the end 63e1 of the first gate line structure 63a and the end 63e2 of the second gate line structure 63b.

[0085] The buffer liner 146 may be formed of an insulating material having a dielectric constant lower than that of the gap filling layer 152 and higher than that of the lower buffer layer 150. For example, the lower buffer layer 150 may be formed of silicon oxide or a silicon oxide-based insulating material, the gap filling layer 152 may be formed of silicon nitride, and the buffer liner 146 may be formed of an insulating material having a dielectric constant of about 4 to about 5 (e.g., an insulating material such as SiOCN, SiON, etc.).

[0086] In one implementation, the gate separation region 40 g may further include a lower insulating layer 12 a between the lower buffer layer 150 and the isolation region 6 .

[0087] Will refer to Fig.12 Description Reference above Figures 2 to 4B Another modified embodiment of the gate separation region 40 is described. Fig.12 Shown are Figure 22 is a cross-sectional view of the region indicated by lines IIIa-IIIa′ and IVa-IVa′.

[0088] In another modified embodiment and with reference to Fig.12 Together with Figures 2 to 4B , the gate separation region 40 may be a gate separation region 40h including a lower buffer layer 150, a gap filling layer 152 on the lower buffer layer 150, and a buffer liner 146′ between the buffer layer 150 and the gap filling layer 152 and between the side surface of the gap filling layer 152 and the second spacer portion 18b. The lower buffer layer 150 and the buffer liner 146′ may constitute a buffer structure.

[0089] In one implementation, the gate separation region 40 h may further include a lower insulating layer 12 a between the lower buffer layer 150 and the isolation region 6 .

[0090] Will refer to Fig.13 , Fig.14 and Fig.15 Description Reference above Figures 2 to 4B Various modified examples of the gate separation region 40 are described. Fig.13 , Fig.14 and Fig.15 They are shown respectively by Figure 2 sectional view of the region indicated by line IIIa-IIIa′ in FIG.

[0091] In another modified embodiment and referring to Fig.13 , Fig.14 and Fig.15 Together with Figures 2 to 4B , between the second spacer portions 18b of the spacer 18, the gate separation region 40 may be located between the second spacer portions 18b, may extend into the isolation region 6, and the width of the lower portion thereof may be greater than the width of the upper portion thereof. Fig.13 40i in Fig.14 40j in Fig.15 40k in ).

[0092] In another modified embodiment, reference Fig.13, the gate separation region 40i may include a lower buffer layer 150 and a gap filling layer 152 stacked in sequence. The lower buffer layer 150 may constitute a buffer structure. The gate separation region 40i may include a lower region and an upper region on the lower region. The width of the lower region may be greater than the width of the upper region. The buffer structure (i.e., the lower buffer layer 150) may be located on the upper surface of the gate separation region 40i. The gap filling layer 152 may be located in the upper region of the gate separation region 40i. The lower buffer layer 150 may be formed of a material having good gap filling properties (e.g., a flowable oxide), and the gate separation region 40i may be formed without defects such as seams.

[0093] In another modified embodiment, reference Fig.14 The gate separation region 40j may include a lower buffer layer 150 and a gap filling layer 152 sequentially stacked, and a buffer liner 146' covering the bottom and side surfaces of the lower buffer layer 150 and the side surface of the gap filling layer 152. The lower buffer layer 150 and the buffer liner 146' may constitute a buffer structure.

[0094] In another modified embodiment, reference Fig.15 The gate separation region 40k may include a lower buffer layer 150 and a gap filling layer 152 stacked in sequence, and a buffer liner 146' covering a side surface of the gap filling layer 152 and located between the gap filling layer 152 and the lower buffer layer 150. The lower buffer layer 150 and the buffer liner 146' may constitute a buffer structure.

[0095] Will refer to Fig.16 , Fig.17 and Fig.18 Description Reference above Figures 2 to 4B Various modified examples of the gate separation region 40 are described. Fig.16 , Fig.17 and Fig.18 They are shown respectively by Figure 2 A cross-sectional view of the region indicated by line IVa-IVa′ in FIG.

[0096] In another modified embodiment, and with reference to Fig.16 , Fig.17 and Fig.18 Together with Figures 2 to 4B , between the first end 63e1 and the second end 63e2 opposite to each other in the first gate line structure 63a and the second gate line structure 63b, the gate separation region 40 may be a gate separation region (which may be located between the first end 63e1 and the second end 63e2, may extend into the isolation region 6, and may have a lower portion with a width greater than an upper portion thereof Fig.16 401 in Fig.17 40m in Fig.1840n in).

[0097] In another modified embodiment, reference Fig.16 , the gate separation region 401 may include a buffer structure including a lower buffer layer 150 and a gap-filling layer 152 stacked on the buffer structure.

[0098] In another modified embodiment, reference Fig.17 The gate separation region 40m may include a lower buffer layer 150 and a gap filling layer 152 sequentially stacked, and a buffer liner 146 covering the bottom and side surfaces of the lower buffer layer 150 and the side surface of the gap filling layer 152. The lower buffer layer 150 and the buffer liner 146 may constitute a buffer structure.

[0099] In another modified embodiment, reference Fig.18 The gate separation region 40n may include a lower buffer layer 150 and a gap filling layer 152 stacked in sequence, and a buffer liner 146' between the gap filling layer 152 and the lower buffer layer 150 and covering the side surface of the gap filling layer 152. The lower buffer layer 150 and the buffer liner 146' may constitute a buffer structure.

[0100] Next, we will refer to Fig.19 Modified embodiments of the above-described gate separation region 40 and spacer 18 are described. Fig.19 A semiconductor device ( Figure 1 1) in the plan view of an example of the first circuit region C1. The modified example of the above-mentioned gate separation region 40 and the above-mentioned spacer 18 will be mainly described. Components other than the gate separation region 40 and the spacer 18 will be described with reference to Figures 2 to 4B The components described are substantially the same. Therefore, some components may be omitted from the following description, and some components will be directly referenced.

[0101] Reference Fig.19 , can provide reference Figures 2 to 4B The same active regions 9a and 9b and first and second gate line structures 63a and 63b are described.

[0102] The gate separation region 240 may be between the first gate line structure 63a and the second gate line structure 63b. The spacer 18′ may also cover a portion of the side surface of each gate separation region 240, and may cover the side surfaces of the first gate line structure 63a and the second gate line structure 63b. The extension portion 253 may extend from at least a portion of the gate separation region 240 in the first direction X. The first direction X may be a longitudinal direction of the first upper active region 9a_2 and the second upper active region 9b_2, and a width direction of the first gate line structure 63a and the second gate line structure 63b, as shown in FIG. Figures 2 to 4B described.

[0103] Will refer to Fig. 20A and Fig. 20B Various examples of the gate separation region 240 and the spacer 18 ′ are described. Fig. 20A Shown along Fig.19 A cross-sectional view of a region cut by lines IIIb-IIIb′ and IVb-IVb′ in FIG. Fig. 20B Shown along Fig.19 A cross-sectional view of the area cut along line IV-IV′ in FIG.

[0104] refer to Fig. 20A and Fig. 20B Together with Fig.19 The gate separation region 240 may be a gate separation region 240a between the first end portion 63e1 of the first gate line structure 63a and the second end portion 63e2 of the second gate line structure 63b and including the extension portions 253 connected to each other.

[0105] Each gate separation region 240a may include a gap-filling layer 252, a buffer liner 246 covering the bottom and side surfaces of the gap-filling layer 252 and extending onto the lower surface of the extension portion 253, and a lower insulating layer 12a between the buffer liner 246 and the isolation region 6. The extension portion 253 may extend from an upper region of the gap-filling layer 252 in the first direction X (e.g., in a width direction of the first gate line structure 63a and the second gate line structure 63b) to integrally form the gap-filling layer 252. The buffer liner 246 may be a buffer structure.

[0106] The spacer 18′ may include a first spacer portion 18a′ covering the side surfaces of the first gate line structure 63a and the second gate line structure 63b, and a second spacer portion 18b′ extending from the first spacer portion 18a′ and connected to the first spacer portion 18a′. The thickness of each second spacer portion 18b′ may be less than the thickness of each first spacer portion 18a′. The position of the upper surface of the second spacer portion 18b′ may be lower than the position of the upper surface of the first spacer portion 18a′ (for example, closer to the semiconductor substrate 3 than the upper surface of the first spacer portion 18a′).

[0107] The interlayer insulating layer 27 may be located on the second isolation region 6b of the isolation region 6. On the second isolation region 6b, the spacer 18' may be located between the gate line structures 63a and 63b and the interlayer insulating layer 27, and between the gate separation region 240 and the interlayer insulating layer 27.

[0108] The extension portion 253 may extend from an upper region of the gap-filling layer 252 in the first direction X and may cover the second spacer portion 18 b ′ and the interlayer insulating layer 27 . Thus, the extension portion 253 may overlap the second spacer portion 18 b ′ and the interlayer insulating layer 27 .

[0109] Will refer to Fig.21 , Fig. 22 and Fig.23 Various modification examples of the gate separation region 240 are described. Fig.21 , Fig. 22 and Fig.23 Shown along Fig.19 A cross-sectional view of the area intercepted by line IIIb-IIIb′ and line IVb-IVb′.

[0110] Reference Fig.21 , Fig. 22 and Fig.23 Each of the Fig.19 The gate separation region 240 may be a gate separation region ( Fig.21 240b in Fig. 22 240c in Fig.23 240d).

[0111] In a modified embodiment, reference Fig.21 , each gate separation region 240b may further include a lower insulating layer 12a between a lower buffer layer 250 and the isolation region 6. The lower buffer layer 250 may be a buffer structure.

[0112] In a modified embodiment, reference Fig. 22 Each gate separation region 240c may further include: a buffer liner 246 covering the lower surface and side surface of the lower buffer layer 250, covering the side surface of the gap filling layer 252' and extending to the lower surface of the extension portion 253. Each gate separation region 240c may further include a lower insulating layer 12a between the buffer liner 246 and the isolation region 6. The buffer liner 246 and the lower buffer layer 250 may constitute a buffer structure.

[0113] In a modified embodiment, reference Fig.23Each gate separation region 240d may further include: a buffer liner 246′ between the lower surface of the gap filling layer 252′ and the lower buffer layer 250, covering the side surface of the gap filling layer 252′, and extending to the lower surface of the extension portion 253. The lower buffer layer 250 and the buffer liner 246′ may constitute a buffer structure. Each gate separation region 240d may further include a lower insulating layer 12a between the lower buffer layer 250 and the isolation region 6.

[0114] Will refer to Fig.24 , Fig.25 , Fig.26 and Fig. 27 Various modification examples of the gate separation region 240 are described. Fig.24 , Fig.25 , Fig.26 and Fig. 27 The Fig.19 A cross-sectional view of the area cut along line IIIb-IIIb′ in FIG.

[0115] Refer to Fig.24 , Fig.25 , Fig.26 and Fig. 27 Together with Fig.19 , between the second spacer portions 18b of the spacer 18, the gate separation region 240 may be located between the second spacer portions 18b, may extend into the isolation region 6, and the width of the lower portion thereof may be greater than the width of the upper portion thereof. Fig.24 240e, Fig.25 240f, Fig.26 240g, Fig. 27 240h ​​in the above table).

[0116] In a modified embodiment, reference Fig.24 Each gate separation region 240e may include a gap filling layer 252, an extension portion 253 connected to an upper region of the gap filling layer 252, and a buffer liner 246 covering a bottom surface and a side surface of the gap filling layer 252 and extending between the extension portion 253 and the interlayer insulating layer 27. The buffer liner 246 may be a buffer structure.

[0117] In a modified embodiment, reference Fig.25 Each gate separation region 240f may include a lower buffer layer 250 and a gap-filling layer 252' stacked in sequence, and an extension portion 253 connected to an upper region of the gap-filling layer 252' and extending in the first direction X. The lower buffer layer 250 may be a buffer structure.

[0118] In a modified embodiment, reference Fig.26Each gate separation region 240g may include a lower buffer layer 250 and a gap filling layer 252′ stacked in sequence, and a buffer liner 246, which covers the lower surface and side surfaces of the lower buffer layer 250, covers the side surface of the gap filling layer 252′ and extends to the lower surface of the extension portion 253. The lower buffer layer 250 and the buffer liner 246 may constitute a buffer structure.

[0119] In a modified embodiment, reference Fig. 27 Each gate separation region 240h may include a lower buffer layer 250 and a gap filling layer 252′ stacked in sequence, and a buffer liner 246′ between a lower surface of the gap filling layer 252′ and the lower buffer layer 250, covering a side surface of the gap filling layer 252′ and extending to a lower surface of the extension portion 253. The lower buffer layer 250 and the buffer liner 246′ may constitute a buffer structure.

[0120] In reference Figures 1 to 27 In the described components, the "buffer liner" represented by the same reference numeral or various reference numerals may be formed of the same material as each other. The "gap filling layer" represented by the same reference numeral or various reference numerals may be formed of the same material as each other. The "lower buffer layer" represented by the same reference numeral or various reference numerals may be formed of the same material as each other. For example, referring to Figure 5 The cushioning liner 46 described in reference Fig.11 The described buffer liner 146, reference Fig.12 The cushioning liner 146' described in reference Fig. 20A The cushioning liner 246 described and referenced Fig. 20B The cushioning liner 246 described above may be formed of the same material. Figure 5 The gap filling layer 52 described in reference Fig.11 The gap filling layer 152 described in reference Fig. 20A The described gap-filling layers 252 may be formed of the same material as each other.

[0121] Next, we will refer to Fig.28 Description Reference above Figures 2 to 27 Modified embodiments of the active regions 9a and 9b are described.

[0122] In a modified embodiment, reference Fig.28 The gate separation regions 40 and 240 may be disposed between the first gate line structure 63a and the second gate line structure 63b, and between the end portions 63e1 and 63e2 of the first gate line structure 63a and the second gate line structure 63b that are opposite to each other, as described above with reference to Figures 2 to 27 Same as described.

[0123] The first active region 9a' may include a first lower active region 9a_1, a first upper active region 9a_2 protruding from the first lower active region 9a_1 in the vertical direction Z, and a first floating active region 9a_3 on an upper portion of the first upper active region 9a_2 and spaced apart from the first upper active region 9a_2. The second active region 9b' may include a second lower active region 9b_1, a second upper active region 9b_2 protruding from the second lower active region 9b_1 in the vertical direction Z, and a second floating active region 9b_3 on an upper portion of the active region 9b_2 and spaced apart from the second upper active region 9b_2. The first floating active region 9a_3 may be surrounded by the first gate line structure 63a, and the second floating active region 9b_3 may be surrounded by the second gate line structure 63b.

[0124] Next, refer to Fig.29 , will refer to Figures 2 to 27 Modified examples of the first gate line structure 63 a and the second gate line structure 63 b are described.

[0125] In a modified embodiment, reference Fig.29 Each first gate line structure 63a′ may include a first gate electrode line 69a and a first gate dielectric 66a, the first gate dielectric 66a covering the lower surface of the first gate electrode line 69a and covering the side surface of the first gate electrode line 69a. Each second gate line structure 63b′ may include a second gate electrode line 69b, and a second gate dielectric 66b covering the lower surface of the second gate electrode line 69b and covering the side surface of the second gate electrode line 69b. Therefore, in the modified embodiment, the upper surfaces of the first gate electrode line 69a and the second gate electrode line 69b may be the same as those described above with reference to Figures 1 to 27 The top surfaces of the gate separation regions 40 and 240 are depicted as being coplanar.

[0126] As above reference Figures 1 to 29 As described above, the semiconductor device 1 according to the embodiment may include the first circuit region C1. In one embodiment, the semiconductor device 1 may include other circuit regions together with the first circuit region C1. Fig.30 and Fig.31 An exemplary embodiment of a semiconductor device 1 including a second circuit area C2 together with the above-mentioned first circuit area C1, and reference Fig.32 and Fig.33 An exemplary example of a semiconductor device 1 including a third circuit region C3 together with the above-mentioned first circuit region C1.

[0127] In the following, reference will be made to Fig.30 and Fig.31 as well as Fig.32 and Fig.33 The semiconductor device 1 of the described exemplary embodiment may include a second circuit region ( Fig.30C2 in) or the third circuit area ( Fig.32 C3) together with the above reference Figures 1 to 29 In this case, reference to the first circuit area C1 can be omitted. Figures 1 to 29 The description of the first circuit area C1 described above (eg, components constituting the first circuit area C1 and various modified examples thereof) is described below. Figures 1 to 29 Among the components of the first circuit area C1 described above, the components that are applied to the second circuit area ( Fig.30 C2 in) or the third circuit area ( Fig.32 The components of C3) in the embodiment may be directly referenced, but the detailed description of the components may be omitted.

[0128] First, refer to Fig.30 and Fig.31 , the second circuit area C2 will be described together with the above reference Figures 1 to 29 An exemplary example of the semiconductor device 1 including the first circuit region C1 is described. Fig.30 A perspective view of a semiconductor device 1 according to the embodiment and a plan view of an enlarged portion of the perspective view are shown. Fig.31 Shown are Fig.30 A cross-sectional view of the area cut by line VI-VI′ and line VII-VII′.

[0129] Reference Fig.30 and Fig.31 Together with Figures 1 to 29 , the semiconductor device 1 according to the embodiment may include a second circuit region C2 together with a reference Figures 1 to 29 A first circuit area C1 is described.

[0130] The second circuit area C2 may include a third active area 109 corresponding to the first active area 9a and the second active area 9b of the first circuit area C1. Therefore, among the third active areas 109 adjacent to each other, one of the third active areas 109 may have the same structure as the first active area 9a, and the other of the third active areas 109 may have the same structure as the second active area 9b. For example, each third active area 109 may include a third lower active area 109_1 having the same structure as the first lower active area 9a_1 and a third upper active area 109_2 having the same structure as the first upper active area 9a_2. In one embodiment, the third active area 109 may be defined by an isolation area 6 including a first isolation area 6a and a second isolation area 6b in the same manner as the first active area 9a and the second active area 9b. The second circuit area C2 may include: a third source / drain area 124, which may correspond to the first source / drain area 24a and the second source / drain area 24b of the first circuit area C1.

[0131] The second circuit area C2 may include: a third gate line structure 163, which may correspond to the first gate line structure 63a and the second gate line structure 63b of the first circuit area C1. For example, each third gate line structure 163 may include a third gate electrode line 169 and a third gate dielectric 166, and the third gate dielectric 166 covers the lower surface of the third gate electrode line 169 and covers the side surface of the third gate electrode line 169. In one embodiment, each third gate line structure 163 may include a third cover line 172, and the third cover line 172 covers the upper surface of the third gate electrode line 169 and the upper end of the third gate dielectric 166. The third cover line 172 may be formed of the same material as the first cover line 72a and the second cover line 72b. The second circuit area C2 may include a gate separation area 340, and the gate separation area 340 is between the opposite ends 163e of the third gate line structure 163 on the second isolation area 6b. In order to clearly distinguish components, the gate separation regions 40 and 240 in the first circuit area C1 will be referred to as first gate separation regions 40 and 240 , and the gate separation region 340 in the second circuit area C2 will be referred to as second gate separation region 340 .

[0132] The second circuit region C2 may include spacers 18 corresponding to the spacers 18 of the first circuit region C1. Therefore, in the same manner as in the first circuit region C1, the spacers 18 may include first spacer portions 18a covering side surfaces of the third gate line structures 163 and second spacer portions 18b covering side surfaces of the second gate separation region 340.

[0133] The second gate separation region 340 may have a different structure from the first gate separation regions 40 and 240. For example, the second gate separation region 340 may be formed by a gap filling layer 352 that fills between the end portions 163e opposite to each other in the third gate line structure 163 and between the second spacer portions 18b. The second gate separation region 340 may also include a lower insulating layer 12a between the gap filling layer 352 and the second isolation region 6b. The gap filling layer 352 may be formed of silicon nitride, and the lower insulating layer 12a may be formed of silicon oxide.

[0134] In one embodiment, when the transistor formed in the first circuit area C1 is a PMOS transistor and the transistor formed in the second circuit area C2 is an NMOS transistor, the first gate separation area 40 and 240 and the second gate separation area 340 may jointly include a gap filling layer formed of an insulating material having a dielectric constant of about 5 or more, and the first gate separation area 40 and 240 may further include a buffer structure (e.g., the buffer liner 46 described before the description of the second gate separation area 340). As described above, the buffer liner 46 may be formed of an insulating material having a dielectric constant of about 4 to 5.

[0135] Next, refer to Fig.32 and Fig.33 , it can be described that the third circuit area C3 is included together with the above reference Figures 1 to 29 An illustrative example of the semiconductor device 1 of the first circuit region C1 is described. Fig.32 A part of a plan view and a perspective view of a semiconductor device 1 according to an embodiment is shown. Fig.33 Shown are Fig.32 A cross-sectional view of an area cut along line VIII-VIII′ and line IX-IX′ in FIG.

[0136] refer to Fig.32 and Fig.33 Together with Figures 1 to 29 The semiconductor device 1 according to the embodiment may include a third circuit region C3 together with the above-referenced Figures 1 to 29 In this case, reference will be directly cited and described. Figure 6 and Figure 8 A description of an exemplary example of the first circuit region C1 is described.

[0137] The third circuit region C3 may include fourth active regions 209. Each of the fourth active regions 209 may include a fourth lower active region 209_1 and a fourth upper active region 209_2, the fourth upper active region 209_2 protruding from the fourth lower active region 209_1 in an upward direction Z. The fourth active regions 209 may be defined by the isolation region 6 in the same manner as the first active region 9a and the second active region 9b of the first circuit region C1. The second isolation region 6b of the isolation region 6 may be located between the fourth lower active regions 209_1, and the first isolation region 6a of the isolation region 6 may be located on the fourth lower active region 209_1. In this case, the fourth upper active region 209_2 may extend from the first lower active region 209_1 in an upward direction Z, and may pass through the first isolation region 6a.

[0138] The third circuit region C3 may include a fourth source / drain region 424 , which may correspond to the first source / drain region 24 a and the second source / drain region 24 b of the first circuit region C1 .

[0139] The third circuit region C3 may include a fourth gate line structure 463 having ends 463 e opposite to each other on the second isolation region 6 b of the isolation region 6 between the fourth active regions 209 .

[0140] Each fourth gate line structure 463 may include a fourth gate electrode line 469 and a fourth gate dielectric 466, which covers the lower surface of the fourth gate electrode line 469 and covers the side surface of the fourth gate electrode line 469. In one embodiment, each fourth gate line structure 463 may include a fourth cover line 472, which covers the upper surface of the fourth gate electrode line 469 and the upper end of the fourth gate dielectric 466. The fourth cover line 472 may be formed of the same material as the first cover line 72a and the second cover line 72b.

[0141] The third circuit region C3 may include a gate separation region 440 between opposite ends 463e of the fourth gate line structure 463 on the second isolation region 6b. The gate separation regions 40 and 240 in the first circuit region C1 will be referred to as first gate separation regions 40 and 240, and the gate separation region 440 in the third circuit region C3 will be referred to as a third gate separation region 440.

[0142] The third circuit region C3 may include spacers 18 corresponding to the spacers 18 and 18' of the first circuit region C1. Therefore, the spacer 18 may include a first spacer portion 18a covering a side surface of the fourth gate line structure 463, and a second spacer portion 18b covering a side surface of the third gate separation region 440, as in the first circuit region C1.

[0143] The third gate separation region 440 may be substantially the same as the first gate separation regions 40 and 240 except for the size. For example, the lower surface of the third gate separation region 440 may be located at a lower height than the lower surface of the first gate separation regions 40 and 240. The third gate separation region 440 may have a greater width or a greater planar dimension (e.g., area) than the first gate separation regions 40 and 240. For example, in reference to Figures 1 to 29 Among the various examples of the first gate separation regions 40 and 240 of the first circuit region C1 described above, the first gate separation regions 40 and 240 are reference Figure 6 and Figure 8 The first gate separation region described ( Figure 6 40b and / or Figure 8 In the case of 40d in the figure, the third gate separation region 440 may include a buffer liner 446 and a gap filling layer 452, and the buffer liner 446 may correspond to the first gate separation region ( Figure 6 40b and / or Figure 8 40d) in the buffer liner 46, the gap filling layer 452 may correspond to the first gate separation region ( Figure 6 40b and / or Figure 8 40d) in the gap filling layer 52.

[0144] The thickness of the portion of the buffer liner 446 of the third gate separation region 440 between the gap filling layer 452 and the isolation region 6 in the third circuit region C3 may be thicker than that of the first gate separation region ( Figure 6 40b and / or Figure 8 The first gate separation region (40d) between the gap filling layer 52 and the isolation region 6 Figure 6 40b and / or Figure 8 The thickness of the portion of the buffer liner 46 (40d) in FIG.

[0145] Throughout the specification, terms such as "first", "second", "third", and "fourth" may be used to describe various components. These terms may be used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a "third component" may be referred to as a "second component", and a "second component" may be referred to as a "third component". For example, a third circuit area C3 may be referred to as a second circuit area C2, and a second circuit area C2 may be referred to as a third circuit area C3.

[0146] Next, an illustrative example of a method of forming a semiconductor device according to an embodiment will be described.

[0147] In the following, reference will be made to Figure 2 and Figures 34 to 37B Various examples of methods of forming a semiconductor device according to embodiments are described. Fig.34 A process flow chart of an exemplary method of forming a semiconductor device according to an embodiment is shown, and FIG. 35A to FIG. 37B 1 shows a cross-sectional view of a stage in a method of forming a semiconductor device according to an embodiment. Figures 35A to 37B middle, Fig.35A , Fig.36A and Fig.37A is shown along Figure 2 A cross-sectional view of the region taken along line II′ in FIG. Fig.35B , Fig.36B and Fig.37B is shown along Figure 2 A cross-sectional view of the area cut along line IIIa-IIIa′ in FIG.

[0148] refer to Figure 2 , Fig.34 , Fig.35A and Fig.35B Active regions 9 a and 9 b and isolation region 6 may be formed ( S10 ). Active regions 9 a and 9 b and isolation region 6 may be formed on semiconductor substrate 3 .

[0149] The formation of the isolation region 6 may include, for example, forming a first isolation region 6a defining an active line in a linear shape on the semiconductor substrate 3; forming a second isolation region 6b, which passes through the first isolation region 6a and the active line and extends into the semiconductor substrate 3; and partially etching the first isolation region 6a and the second isolation region 6b to expose the upper area of ​​the remaining active line.

[0150] By forming the second isolation region 6b, the first lower active region 9a_1 and the second lower active region 9b_1 below the remaining active lines can be formed. The active lines remaining on the first lower active region 9a_1 can be defined as the first upper active region 9a_2, and the active lines remaining on the second lower active region 9b_1 can be defined as the second upper active region 9b_2.

[0151] The first lower active region 9a_1 and the first upper active region 9a_2 may constitute a first active region 9a, and the second lower active region 9b_1 and the second upper active region 9b_2 may constitute a second active region 9b. Thus, the active regions 9a and 9b may include a first active region 9a and a second active region 9b.

[0152] The preliminary gate line 15 may be formed on the active regions 9a and 9b and the isolation region 6 (S20). Before forming the preliminary gate line 15, the lower base layer 12 may be formed.

[0153] The formation of the lower base layer 12 and the primary gate line 15 may include: forming an insulating layer and a primary gate layer on the semiconductor substrate 3, wherein the active regions 9a and 9b and the isolation region 6 are formed on the semiconductor substrate 3; and patterning the insulating layer and the primary gate layer into a line shape. Therefore, the insulating layer may be patterned to form the lower base layer 12, and the primary gate layer may be patterned to form the primary gate line 15.

[0154] The spacer 18 may be formed on the side surface of the preliminary gate line 15 (S30). The spacer 18 may be formed of any one of SiN, SiON, and SiCN or a combination thereof.

[0155] Source / Drain Region( Figure 4A 24a and Figure 4B 24b) can be formed on the active regions 9a and 9b. For example, the source / drain region ( Figure 4A 24a and Figure 4B The formation of 24b) in the embodiment may include: performing an etching process using the primary gate line 15 and the spacer 18 as an etching mask; etching the active regions 9a and 9b to form a recessed region ( Figure 4A 21a and Figure 4B 21b); and performing an epitaxial process to form an epitaxial layer filling the recessed region ( Figure 4B 21a and Figure 4A21b).

[0156] Reference Figure 2 , Fig.34 , Fig.36A and Fig.36B , an interlayer insulating layer 27 filled between the preliminary gate lines 15 may be formed. The interlayer insulating layer 27 may be formed of silicon oxide.

[0157] The mask pattern 30 may be formed on the preliminary gate line 15 and the interlayer insulating layer 27, and an etching process using the mask pattern 30 as an etching mask may be performed to form an opening 33 for separating the preliminary gate line 15 on the isolation region 6. When there are a plurality of preliminary gate lines 15 to be separated, the opening 33 may be formed in plurality.

[0158] In one embodiment, the opening 33 may expose the lower base layer 12 .

[0159] In one embodiment, the opening 33 may pass through the lower base layer 12 and extend into the second isolation region 6 b of the isolation region 6 .

[0160] Reference Figure 2 , Fig.34 , Fig.37A and Fig.37B In an exemplary example, while the opening 33 is formed, the thickness of the spacer 18 adjacent to the opening 33 may be reduced.

[0161] A gate separation region 40 for separating the primary gate lines 15 on the isolation region 6 may be formed (S50). For example, the primary gate lines 15 may be etched by a patterning process to form openings ( Fig.36A and Fig.36B 33), can form a covering opening ( Fig.36A and Fig.36B The buffer lining 46 of the inner wall of 33) can form a filling opening ( Fig.36A and Fig.36B 33) of the gap filling layer 52.

[0162] In one implementation, the gate separation region 40 may include the lower insulating layer 12 a remaining under the buffer liner 46 , and the gap-filling layer 52 and the buffer liner 46 .

[0163] The exemplary method of forming the gate separation region 40 described above may be applied to the method of forming the gate separation regions 240 , 340 , and 440 of various shapes or structures described above.

[0164] Reference again Figure 4A , Figure 4B and Figure 5 Together with Figure 2 and Fig.34 , primary gate line ( Fig.37A and Fig.37B 15) in the example can be replaced by gate line structures 63a and 63b (S60). For example, the primary gate line ( Fig.37A and Fig.37B 15) may include: removing the primary gate line ( Fig.37A and Fig.37B 15) to form a gate trench; forming a gate dielectric covering the inner wall of the gate trench; forming a gate electrode line for filling the gate trench on the gate dielectric; partially etching the gate electrode line and the gate dielectric; and forming a capping line for filling the remaining portion of the gate trench. Thus, a structure such as Figure 4A and Figure 4B The gate line structures 63a and 63b are shown. The gate line structures 63a and 63b may include a first gate line structure 63a and a second gate line structure 63b having end portions 63e1 and 63e2 opposite to each other.

[0165] Then, contact structures 78a and 78b may be formed (S70). For example, contact structures 78a and 78b may be formed on the first source / drain region 24a and the second source / drain region 24b. Contact structures 78a and 78b may be formed of any one or a combination of doped silicon, metal silicide, metal nitride and metal.

[0166] In one embodiment, the gate separation regions 40, 240, 340 and 440 may apply tensile stress to the channel region of the transistor along the longitudinal direction of the gate line structure. For example, the performance of the transistor adjacent to the gate separation regions 40, 240, 340 and 440 may be improved.

[0167] In one embodiment, the above-described gate separation regions 40 , 240 , 340 , and 440 may be formed without defects such as seams, etc. For example, defects may be reduced, and productivity of semiconductor devices may be improved.

[0168] According to an embodiment, a semiconductor device including a gate separation region formed between gate line structures may be provided. The gate separation region may include a buffer structure including a material having a dielectric constant higher than that of silicon oxide and lower than that of silicon nitride. In one embodiment, such a gate separation region may provide tensile stress on a channel region of a transistor along a longitudinal direction of the gate line structure, thereby improving the performance of the transistor. For example, a semiconductor device including a transistor having improved performance may be provided.

[0169] Embodiments may provide a semiconductor device including a gate separation region that separates a gate line structure.

[0170] Embodiments may provide a semiconductor device including a gate separation region, in which performance of a transistor may be improved.

[0171] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and will be interpreted only in a general descriptive sense and not for purposes of limitation. In some cases, as will be appreciated by those of ordinary skill in the art submitting this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in other embodiments, unless expressly stated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: Isolation regions between active regions; an interlayer insulating layer on the isolation region; a gate line structure overlapping the active region, the gate line structure being located on the isolation region and having ends opposite to each other; as well as a gate separation region on the isolation region, the gate separation region being located between the ends of the gate line structure that are opposite to each other and between the interlayer insulating layers, in: The gate separation region includes a gap filling layer and a buffer structure, The buffer structure includes a buffer liner, the buffer liner is located between the gap filling layer and the isolation region, between the ends of the gate line structure opposite to each other and the side surface of the gap filling layer, and between the interlayer insulating layer and the side surface of the gap filling layer. The dielectric constant of the insulating material forming the buffer liner is lower than the dielectric constant of the insulating material forming the gap filling layer.

2. The semiconductor device according to claim 1, wherein The dielectric constant of the insulating material forming the buffer liner is higher than the dielectric constant of silicon oxide.

3. The semiconductor device according to claim 1, wherein: Each of the gate line structures comprises: a gate electrode line, and a gate dielectric covering a bottom surface of the gate electrode line and extending onto a side surface of the gate electrode line, and The gate dielectric includes a portion between the gate separation region and the gate line structure.

4. The semiconductor device according to claim 3, wherein: Each of the gate line structures further includes a capping line on the gate electrode line, and An upper surface of the capping line is coplanar with an upper surface of the gate separation region.

5. The semiconductor device according to claim 4, wherein: An upper end of the gate dielectric is located below the capping line.

6. The semiconductor device according to claim 1, wherein: Each of the active regions comprises: The lower active region, and an upper active region on the lower active region, The isolation area includes: a first isolation region overlapping the lower active region, and a second isolation region surrounding a side surface of the lower active region, The upper active region protrudes from the lower active region and extends through the first isolation region, and An upper surface of the upper active region is located at a height higher than an upper surface of the first isolation region.

7. The semiconductor device according to claim 6, wherein: The upper active area is in a line or strip shape extending in a first direction, The gate line structure is in a linear or strip shape extending in a second direction, and the second direction is perpendicular to the first direction. The gate separation region is located between ends of the gate line structure extending in the second direction, and The gate separation region is located on the second isolation region. 8 . The semiconductor device according to claim 1 , further comprising an extending portion extending from an upper region of the gap-fill layer in a width direction of the gate line structure.

9. The semiconductor device according to claim 1, wherein: The gate separation region extends into the isolation region.

10. The semiconductor device according to claim 1, wherein: The buffer structure further includes a lower buffer layer located between the gap filling layer and the isolation region, and The dielectric constant of the insulating material forming the buffer liner is higher than the dielectric constant of the lower buffer layer.

11. The semiconductor device according to claim 10, wherein: The lower buffer layer is located between the lower surface of the gap filling layer and the buffer liner, and The buffer liner extends from a portion surrounding a side surface of the gap-fill layer to a side surface of the lower buffer layer, and surrounds the side surface of the lower buffer layer.

12. The semiconductor device according to claim 10, wherein: The lower buffer layer is located between the lower surface of the buffer liner and the isolation region.

13. A semiconductor device comprising: a first active region and a second active region, the first active region and the second active region being on a semiconductor substrate and spaced apart from each other; an isolation region on the semiconductor substrate, the isolation region including a region between the first active region and the second active region; a first gate line structure overlapping the first active region and the isolation region; a second gate line structure overlapping the second active region and the isolation region, the second gate line structure having a second end portion, the second end portion facing the first end portion of the first gate line structure on the isolation region; a spacer covering a side surface of the first gate line structure, the spacer extending in a longitudinal direction of the first gate line structure to cover a side surface of the second gate line structure; as well as a first gate separation region located between a first end of the first gate line structure and a second end of the second gate line structure and between the spacers, in: The first gate separation region comprises: a first gap-filling layer, and a first buffer structure, wherein the dielectric constant of the insulating material forming the first buffer structure is lower than the dielectric constant of the insulating material forming the first gap-filling layer; The spacer comprises: a first spacer portion covering side surfaces of the first gate line structure and the second gate line structure; and a second spacer portion covering a side surface of the first gate separation region, and A thickness of each of the second spacer portions is smaller than a thickness of each of the first spacer portions.

14. The semiconductor device according to claim 13, wherein: In a width direction of the first gate line structure and the second gate line structure, a width of each of the first gate line structure and the second gate line structure is narrower than a width of the first gate separation region.

15. The semiconductor device according to claim 13, wherein: The first buffer structure includes a first buffer liner, the first buffer liner is located between the first gap filling layer and the isolation region and surrounds a side surface of the first gap filling layer, The first buffer liner is formed of an insulating material, and a dielectric constant of the insulating material forming the first buffer liner is higher than a dielectric constant of silicon oxide and lower than a dielectric constant of silicon nitride, and is lower than a dielectric constant of the insulating material forming the first gap filling layer.

16. The semiconductor device according to claim 15, further comprising: a third gate line structure having ends opposite to each other on the isolation region; as well as a second gate separation region located on the isolation region and between the third gate line structures; in: The planar size of the second gate separation region is larger than the planar size of the first gate separation region, The second gate separation region comprises: a second gap-filling layer; and a second buffer liner surrounding a side surface of the second gap filling layer and being located between the second gap filling layer and the isolation region, and A thickness of the second buffer liner between the second gap-filling layer and the isolation region is thicker than a thickness of the first buffer liner between the first gap-filling layer and the isolation region.

17. A semiconductor device comprising: a first active region and a second active region spaced apart from each other; an isolation region, including a region between the first active region and the second active region; A first transistor comprising: a first channel region in the first active region; a first source / drain region located on both side surfaces of the first channel region and applying compressive stress or tensile stress to the first channel region; and a first gate line structure extending on the first channel region and above the isolation region; The second transistor comprises: a second channel region in the second active region, a second source / drain region located on both side surfaces of the second channel region and applying compressive stress or tensile stress to the second channel region; and a second gate line structure extending on the second channel region and over the isolation region; and a gate separation region on the isolation region and between ends of the first gate line structure and the second gate line structure, Wherein, the gate separation region includes a buffer structure and a gap filling layer; and The dielectric constant of the insulating material forming the buffer structure is lower than the dielectric constant of the insulating material forming the gap filling layer.

18. The semiconductor device according to claim 17, wherein: The gate separation region applies tensile stress to the first channel region and the second channel region.

19. The semiconductor device according to claim 17, wherein: The buffer structure includes a buffer liner surrounding a side surface of the gap-filling layer and located between the gap-filling layer and the isolation region.

20. The semiconductor device according to claim 17, wherein: The gate separation region comprises: the lower region; and an upper region on the lower region, the width of the lower region being wider than the width of the upper region, The buffer structure is located in a lower region of the gate separation region, and The gap-filling layer is located in an upper region of the gate separation region.

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