Integrated circuit chip testing system and method

Abstract

The present invention provides an integrated circuit chip testing system and method, and relates to the technical field of integrated circuit chip testing. The system includes: a first test device, a second test device, a collection device, a storage device and a computing device, the first test device, the collection device, the storage device and the second test device are electrically connected in sequence, and the computing device is electrically connected to the first test device, the second test device, the collection device and the storage device respectively; the computing device is used to control the first test device, the second test device, the collection device and the storage device, and the collection device collects the operation signal for the preset integrated circuit chip when the first test device is connected to the preset integrated circuit chip, and stores the operation signal to the storage device; the second test device obtains the operation signal from the storage device, and tests the integrated circuit chip to be tested based on the operation signal. The present disclosure can improve the accuracy of testing the integrated circuit chip to be tested.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chip testing, and in particular to an integrated circuit chip testing system and method. Background Art

[0002] An integrated circuit chip is a miniature electronic device or component that uses a certain process to interconnect the transistors, resistors, capacitors, inductors and other components and wiring required in a circuit, and is made on a small piece or several small pieces of semiconductor wafers or dielectric substrates, and then packaged in a tube shell to become a miniature structure with the required circuit function. Due to the complex structure of the integrated circuit chip, it is necessary to test the integrated circuit chip to confirm its operating performance.

[0003] In the prior art, the integrated circuit chip to be tested is tested by connecting the integrated circuit chip to be tested with a test device, inputting a preset input signal to the integrated circuit chip to be tested through the test device, obtaining an output signal of the integrated circuit chip to be tested, and then determining its performance based on the output signal to complete the test.

[0004] However, since the preset input signal is usually obtained by simulating the working environment of the integrated circuit chip under test, the fault coverage is low, which may result in the integrated circuit chip under test passing the test but having more faults when put into use, that is, the test accuracy is low. Summary of the invention

[0005] The object of the present invention is to provide an integrated circuit chip testing system and method to solve the problem of low accuracy in testing the integrated circuit chip to be tested, in view of the above-mentioned deficiencies in the prior art.

[0006] To achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0007] In a first aspect, an embodiment of the present invention provides an integrated circuit chip test system, the integrated circuit chip test system comprising: a first test device, a second test device, a collection device, a storage device and a computing device, the first test device, the collection device, the storage device and the second test device are electrically connected in sequence, and the computing device is electrically connected to the first test device, the second test device, the collection device and the storage device respectively;

[0008] The computing device is used to control the first test device, the second test device, the acquisition device and the storage device respectively according to the control instructions for the first test device, the second test device, the acquisition device and the storage device;

[0009] When the first test device is connected to a preset integrated circuit chip, the acquisition device acquires an operation signal for the preset integrated circuit chip and stores the operation signal in the storage device;

[0010] The second testing device obtains the operation signal from the storage device, and tests the integrated circuit chip to be tested based on the operation signal, and the preset integrated circuit chip is of the same chip type as the integrated circuit chip to be tested.

[0011] Optionally, the operation signal includes an input signal input from the first test device to the preset integrated circuit chip and a first output signal of the preset integrated circuit chip in response to the input signal;

[0012] The second test device is specifically used to input the input signal into the integrated circuit chip under test, obtain a second output signal generated by the integrated circuit chip under test in response to the input signal, and compare the first output signal with the second output signal.

[0013] Optionally, the integrated circuit chip testing system further includes an access device, the access device including a first interface electrically connected to the preset integrated circuit chip, a second interface electrically connected to the first testing device, and a third interface electrically connected to the acquisition device;

[0014] The access device obtains the operation signal through the first interface and the second interface, and sends the operation signal to the acquisition device through the third interface.

[0015] Optionally, the access device further includes a signal amplifier, and the signal amplifier is electrically connected to the third interface;

[0016] The access device amplifies the operation signal through the signal amplifier, and sends the amplified operation signal to the acquisition device through the third interface.

[0017] Optionally, the acquisition device includes a fourth interface, a digital-to-analog converter, a multi-way switch, a timing controller, a synchronization controller, a fifth interface and a sixth interface, the fourth interface, the digital-to-analog converter, the multi-way switch, the timing controller and the sixth interface are electrically connected in sequence, and the synchronization controller is electrically connected to the digital-to-analog converter, the multi-way switch, the timing controller and the fifth interface respectively;

[0018] The acquisition device receives the synchronization control instruction of the computing device through the fifth interface, and performs timing synchronization on the digital-to-analog converter, the multi-way switch, and the timing controller through the synchronization controller. The acquisition device also receives the operation signal through the fourth interface, converts the operation signal from a digital signal to an analog signal through the digital-to-analog converter, transmits the converted operation signal to the timing controller through the multi-way switch, compresses the converted operation signal through the timing controller, and sends the compressed operation signal to the storage device through the sixth interface.

[0019] Optionally, the second test device includes a storage adapter, a plurality of signal processors connected in series, and a controller, the storage adapter includes a seventh interface, an eighth interface, and a ninth interface, the storage adapter is electrically connected to the storage device via the seventh interface, the storage adapter is electrically connected to a first signal processor among the plurality of signal processors connected in series via the eighth interface, the storage adapter is electrically connected to a last signal processor among the plurality of signal processors connected in series via the ninth interface, and the controller is electrically connected to the plurality of signal processors respectively;

[0020] The second test device obtains the operating signal from the storage device through the storage adapter, and the operating signal includes multiple parallel operating sub-signals, converts the multiple parallel operating sub-signals into multiple serial operating sub-signals, controls the multiple signal processors through the controller to pre-process the multiple serial operating sub-signals, and verifies the processed multiple serial operating sub-signals through the storage adapter.

[0021] Optionally, the second test device is specifically used to control the plurality of signal processors through the controller to convert the plurality of serial operating sub-signals from analog signals to digital signals, and verify the converted operating sub-signals through the storage adapter.

[0022] Optionally, the system includes a plurality of the first test devices, and correspondingly, the acquisition device includes a plurality of the fourth interfaces, and each of the four interfaces corresponds to one of the first test devices.

[0023] Optionally, the acquisition device further includes a power supply unit, which is electrically connected to the digital-to-analog converter, the multi-way switch, the timing controller and the synchronization controller respectively.

[0024] Optionally, the storage device includes a disk array.

[0025] In a second aspect, an embodiment of the present invention further provides an integrated circuit chip testing method, the method is applied to an integrated circuit chip testing system, the integrated circuit chip testing system comprising: a first testing device, a second testing device, a collection device, a storage device and a computing device, the first testing device, the collection device, the storage device and the second testing device are electrically connected in sequence, and the computing device is electrically connected to the first testing device, the second testing device, the collection device and the storage device respectively, the computing device is used to control the first testing device, the second testing device, the collection device and the storage device respectively according to control instructions for the first testing device, the second testing device, the collection device and the storage device; the method comprises:

[0026] When the first test device is connected to a preset integrated circuit chip, the collection device collects an operation signal for the preset integrated circuit chip, and stores the operation signal in the storage device;

[0027] The operation signal is obtained from the storage device through the second test device, and the integrated circuit chip to be tested is tested based on the operation signal. The preset integrated circuit chip is of the same chip type as the integrated circuit chip to be tested.

[0028] Optionally, the operation signal includes an input signal input from the first test device to the preset integrated circuit chip and a first output signal of the preset integrated circuit chip in response to the input signal;

[0029] The step of obtaining the operation signal from the storage device through the second test device and testing the integrated circuit chip to be tested based on the operation signal includes:

[0030] The input signal is input to the integrated circuit chip under test through the second test device, a second output signal generated by the integrated circuit chip under test in response to the input signal is obtained, and the first output signal is compared with the second output signal.

[0031] Optionally, the integrated circuit chip testing system further includes an access device, and the access device is electrically connected to the preset integrated circuit chip, the first testing device and the acquisition device respectively; the method further includes:

[0032] Acquiring the operation signal through the access device;

[0033] The collecting, by the collecting device, an operation signal for the preset integrated circuit chip when the first test device is connected to the preset integrated circuit chip, comprises:

[0034] The operation signal sent by the access device is received through the acquisition device.

[0035] Optionally, before testing the integrated circuit chip to be tested based on the operation signal, the method further includes:

[0036] Verifying the operation signal by using the second test device;

[0037] The testing of the integrated circuit chip to be tested based on the operation signal includes:

[0038] The integrated circuit chip to be tested is tested based on the verified operating signal through the second testing device.

[0039] The beneficial effect of the present invention is as follows: in the disclosed embodiment, the integrated circuit test system includes a first test device, a second test device, a collection device, a storage device and a computing device, wherein the first test device, the collection device, the storage device and the second test device are electrically connected in sequence, and the computing device is electrically connected to the first test device, the second test device, the collection device and the storage device respectively. Since the computing device can control the first test device, the second test device, the collection device and the storage device, the collection device can collect the operation signal for the preset integrated circuit chip when the first test device is connected to the preset integrated circuit chip, and the operation signal can illustrate the actual operation status of the preset integrated circuit chip in the actual operation process, therefore, the operation signal is stored in the storage device, and the second test device can obtain the operation signal from the storage device, and based on the operation signal, according to the actual operation status of the preset integrated circuit test chip, the integrated circuit chip to be tested of the same chip type as the preset integrated circuit chip is tested, which can fully cover various faults that may occur in the integrated circuit chip to be tested in actual applications, thereby improving the accuracy of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 A schematic diagram of the structure of an integrated circuit chip testing system provided by an embodiment of the present disclosure;

[0042] Figure 2 A schematic diagram of the structure of an access device provided in an embodiment of the present disclosure;

[0043] Figure 3 A schematic diagram of the structure of another access device provided in an embodiment of the present disclosure;

[0044] Figure 4 A schematic diagram of a process flow of a collection device provided by an embodiment of the present disclosure;

[0045] Figure 5 A schematic diagram of a flow chart of a second testing device provided in an embodiment of the present disclosure;

[0046] Figure 6 A schematic flow chart of an integrated circuit chip testing method provided in an embodiment of the present disclosure.

[0047] Icons: 101-first test equipment; 102-second test equipment; 103-acquisition equipment; 104-storage equipment; 105-computing equipment; 106-access device; 1061-first interface; 1062-second interface; 1063-third interface; 1064-amplifier; 1031-fourth interface; 1032-digital-to-analog converter; 1033-multi-way switch; 1034-timing controller; 1035-synchronous controller; 1036-fifth interface; 1037-sixth interface; 1021-storage adapter; 1022-signal processor; 1023-controller; 10211-seventh interface; 10212-eighth interface; 10213-ninth interface. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0049] Figure 1 A schematic diagram of the structure of an integrated circuit chip testing system provided by the embodiment of the present disclosure is shown in FIG. Figure 1As shown, the integrated circuit chip testing system includes: a first test device 101, a second test device 102, a collection device 103, a storage device 104 and a computing device 105. The first test device 101, the collection device 103, the storage device 104 and the second test device 102 are electrically connected in sequence, and the computing device 105 is electrically connected to the first test device 101, the second test device 102, the collection device 103 and the storage device 104 respectively. The computing device 105 is used to control the first test device 101, the second test device 102, the collection device 103 and the storage device 104. When the first test device 101 is connected to a preset integrated circuit chip, the collection device 103 collects an operation signal for the preset integrated circuit chip and stores the operation signal in the storage device 104. The second test device 102 obtains the operation signal from the storage device 104 and tests the integrated circuit chip to be tested based on the operation signal. The preset integrated circuit chip is of the same chip type as the integrated circuit chip to be tested.

[0050] The first test device 101 or the second test device 102 may include ATE (Automatic Test Equipment). Of course, in practical applications, the first test device 101 or the second test device 102 may also include other types of test equipment. The present disclosure does not specifically limit the device type of the first test device 101 or the second test device 102.

[0051] The first test device 101 and the second test device 102 may be provided with interfaces corresponding to the pins of the integrated circuit chip, so as to be able to access the integrated circuit chip.

[0052] It should be noted that the first test device 101 and the second test device 102 may be pre-configured so that the first test device 101 can collect the operation signal of the preset integrated circuit chip and the second test device 102 can test the integrated circuit chip to be tested.

[0053] The preset integrated circuit chip may be set in advance by relevant technical personnel, for example, the preset integrated circuit chip may include an integrated circuit chip that operates normally, or may include an integrated circuit chip that meets specific standards (such as an integrated circuit chip with at least one specified defect or an integrated circuit chip with specific functions), etc. The integrated circuit chip to be tested is an integrated circuit chip that needs to be tested.

[0054] It should also be noted that the preset integrated circuit chip can be of the same chip type as the integrated circuit chip to be tested, and thus can have the same structure (such as pins) and function as the integrated circuit chip to be tested.

[0055] The acquisition device 103 can detect the information transmission process between the first test device 101 and the preset integrated circuit chip in a wired or wireless manner, thereby obtaining the operation signal of the preset integrated circuit chip when it is running on the first test device 101.

[0056] The storage device 104 may include a disk array, a solid-state drive, or a server deployed with a storage system. Of course, in actual applications, the storage device 104 may also include other types of devices that can be used to store operating signals. The present disclosure does not specifically limit the type of storage device 104.

[0057] The computing device 105 may include a computer, a server, or other devices with computing capabilities. The computing device 105 may be installed with applications or plug-ins related to integrated circuit testing (e.g., upper computer software corresponding to the first test device 101, the second test device 102, the acquisition device 103, and the storage device 104, respectively), so that according to the control instructions for the first test device 101, the second test device 102, the acquisition device 103, and the storage device 104 in these programs or plug-ins, the first test device 101, the second test device 102, the acquisition device 103, and the storage device 104 are controlled respectively, for example, the communication between the first test device 101 and the preset integrated circuit chip is controlled, the acquisition device 103 is controlled to acquire the operation signal and store the operation signal in the storage device 104, the storage space of the storage device 104 is managed, the second test device 102 is controlled to obtain the operation signal from the storage device 104, and the integrated circuit chip to be tested is tested, etc. In addition, the computing device 105 may be provided with input / output devices, such as a display and an operation panel, so as to interact with the user, receive operation instructions related to the integrated circuit test issued by the user, and display relevant information related to the integrated circuit test to the user.

[0058] The operation signal is a signal generated during the operation of the integrated circuit chip on the test equipment, and the operation signal may be a digital signal.

[0059] It should be noted that, since the integrated circuit chip may include multiple pins, the collected operation signal may include multiple operation sub-signals respectively corresponding to the pins.

[0060] Specifically, when performing chip testing through the integrated circuit test system provided by the present disclosure, at least one preset integrated circuit test chip can be determined in advance, and the preset integrated circuit test chip can be connected to the first test device 101, and the operation signal of the preset integrated circuit chip can be collected through the acquisition device 103. The operation signal is generated during the actual operation of the preset integrated circuit chip, and the preset integrated circuit chip is set in advance. Therefore, the operation signal can describe the actual operation status of the preset integrated circuit chip set in advance, including the operation environment and the status information in the operation environment. Therefore, the operation signal can be stored in the storage device 104, so that the operation status of the integrated circuit chip to be tested can be compared with the actual operation status of the preset integrated circuit chip based on the operation signal stored in the storage device 104, so as to determine to test the integrated circuit chip to be tested, wherein, when the operation status of the integrated circuit chip to be tested is the same as the actual operation status of the preset integrated circuit chip, it can be determined that the test is passed, otherwise it is determined that the test is not passed.

[0061] In an embodiment of the present disclosure, an integrated circuit testing system includes a first testing device 101, a second testing device 102, a collection device 103, a storage device 104 and a computing device 105, wherein the first testing device 101, the collection device 103, the storage device 104 and the second testing device 102 are electrically connected in sequence, and the computing device 105 is electrically connected to the first testing device 101, the second testing device 102, the collection device 103 and the storage device 104 respectively. Since the computing device 105 can control the first test device 101, the second test device 102, the acquisition device 103 and the storage device 104, the acquisition device 103 can collect the operation signal for the preset integrated circuit chip when the first test device 101 is connected to the preset integrated circuit chip. The operation signal is sufficient to illustrate the actual operation status of the preset integrated circuit chip during the actual operation process. Therefore, the operation signal is stored in the storage device 104, and the second test device 102 can obtain the operation signal from the storage device 104, and based on the operation signal, according to the actual operation status of the preset integrated circuit test chip, test the integrated circuit chip to be tested that is of the same chip type as the preset integrated circuit chip, which can comprehensively cover various faults that may occur in the integrated circuit chip to be tested in actual applications, thereby improving the accuracy of the test.

[0062] Optionally, the operating signal includes an input signal input by the first test device 101 to a preset integrated circuit chip and a first output signal of the preset integrated circuit chip in response to the input signal. Accordingly, the second test device 102 is specifically used to input the input signal to the integrated circuit chip under test, obtain the second output signal generated by the integrated circuit chip under test in response to the input signal, and compare the first output signal with the second output signal.

[0063] The integrated circuit chip may include a pin for inputting a signal and a pin for outputting a signal, so that the input signal can be obtained from the pin for inputting a signal, and the output signal can be obtained from the pin for outputting a signal. Of course, in practical applications, the input signal and the output signal can also be obtained in other ways according to the structure of the integrated circuit chip.

[0064] It should be noted that the input signal, the first output signal and the second output signal may all be digital signals.

[0065] Since the input signal is the real input signal of the preset integrated circuit chip during the actual operation process, and the first output signal is the real output signal of the preset integrated circuit chip during the actual operation process, for the integrated circuit chip to be tested of the same type as the preset integrated circuit chip, if the second output signal output by the integrated circuit chip to be tested in response to the input signal is the same as the first output signal, it can be determined that the actual operating status of the integrated circuit chip to be tested is consistent with the actual operating status of the preset integrated circuit chip, and the integrated circuit chip to be tested has passed the test; otherwise, it can be determined that the integrated circuit chip to be tested has failed the test.

[0066] In another optional embodiment of the present disclosure, the input signal or the output signal may not be distinguished, so that the operating signal detected for the preset integrated circuit chip is compared with the operating signal detected for the integrated circuit chip to be tested, so as to test the integrated circuit chip to be tested.

[0067] Optionally, see Figure 2 The integrated circuit chip testing system also includes an accessor 106, which includes a first interface 1061 electrically connected to a preset integrated circuit chip, a second interface 1062 electrically connected to the first test device 101, and a third interface 1063 electrically connected to the acquisition device 103. The accessor 106 obtains an operation signal through the first interface 1061 and the second interface 1062, and sends the operation signal to the acquisition device 103 through the third interface 1063.

[0068] The first interface 1061 may correspond to the pin of the preset integrated circuit chip, thereby ensuring that the preset integrated circuit chip can be connected to the device 106. The second interface 1062 may correspond to the pin of the preset integrated circuit chip. The third interface 1063 may correspond to the pin of the preset integrated circuit chip. Therefore, the preset integrated circuit chip can be connected to the first test device 101 through the access device 106, and the acquisition device 103 can detect the operation signal of the preset integrated circuit chip through the third interface 1063 additionally led out by the access device 106 while ensuring the normal communication between the preset integrated circuit chip and the first test device 101.

[0069] It should be noted that the first interface 1061, the second interface 1062 and the third interface 1063 can correspond to the pins of the preset integrated circuit chip. For example, contact pieces corresponding to the preset integrated circuit chip can be provided, including pins, jacks or probes, etc., so as to ensure that information can be collected for the pins of each preset integrated circuit chip, so that the collected operation signal can include multiple operation sub-signals corresponding to one pin respectively.

[0070] Optionally, see Figure 3 The access device 106 further includes a signal amplifier 1064 , which is electrically connected to the third interface 1063 . The access device 106 amplifies the operation signal through the signal amplifier 1064 , and sends the amplified operation signal to the acquisition device 103 through the third interface 1063 .

[0071] Since the operating signal collected through the third interface 1063 may be relatively weak in order not to affect the normal operation of the preset integrated circuit chip, the collected operating signal can be amplified to facilitate subsequent storage of the operating signal and testing of the integrated circuit chip to be tested.

[0072] Optionally, see Figure 4The acquisition device 103 includes a fourth interface 1031, a digital-to-analog converter 1032, a multi-way switch 1033, a timing controller 1034, a synchronization controller 1035, a fifth interface 1036, and a sixth interface 1037. The fourth interface 1031, the digital-to-analog converter 1032, the multi-way switch 1033, and the timing controller 1034 are electrically connected to the sixth interface 1037 in sequence, and the synchronization controller 1035 is electrically connected to the digital-to-analog converter 1032, the multi-way switch 1033, the timing controller 1034, and the fifth interface 1036. The acquisition device 103 receives the synchronization control instruction of the computing device 105 through the fifth interface 1036, and performs timing synchronization on the digital-to-analog converter 1032, the multi-way switch 1033, and the timing controller 1034 through the synchronization controller 1035. The acquisition device 103 also receives an operation signal through the fourth interface 1031, converts the operation signal from a digital signal to an analog signal through the digital-to-analog converter 1032, transmits the converted operation signal to the timing controller 1034 through the multiplexer 1033, compresses the converted operation signal through the timing controller 1034, and sends the compressed operation signal to the storage device 104 through the sixth interface 1037.

[0073] It should be noted that the fourth interface 1031 may correspond to a pin of a preset integrated circuit chip, for example, may be provided with a contact piece corresponding to the preset integrated circuit chip, so as to receive a plurality of parallel operation sub-signals each corresponding to a pin.

[0074] It should also be noted that the multi-way switch 1033 can enable multiple parallel operation sub-signals to be transmitted to the timing controller 1034 in sequence, so that the timing controller 1034 can compress the received operation sub-signals.

[0075] It should also be noted that the sixth interface 1037 may comply with the GTP (Gigabit Transceiver with lowPower) protocol.

[0076] The computing device 105 may generate a synchronization control instruction based on a user operation or in a preset manner, and send the synchronization control instruction to the acquisition device 103 through the fifth interface 1036. When the acquisition device 103 receives the synchronization control instruction, the timing synchronization of each functional component (such as the digital-to-analog converter 1032, the multi-way switch 1033, and the timing controller 1034) in the acquisition device 103 is controlled based on the synchronization control instruction.

[0077] Optionally, the system includes a plurality of first test devices 101 , and correspondingly, the acquisition device 103 includes a plurality of fourth interfaces 1031 , and each fourth interface 1031 corresponds to a first test device 101 .

[0078] The chip types of the preset integrated circuit chips connected to the multiple first testing devices 101 may be different.

[0079] Since it may be necessary to test more than one type of integrated circuit test chips, in order to quickly acquire the operating signals of multiple preset integrated circuit chips, that is, to improve the efficiency of acquiring the operating signals and the testing efficiency, the operating signals can be acquired through multiple fourth interfaces 1031 corresponding to different first test devices 101.

[0080] Optionally, the acquisition device 103 further includes a power supply unit, which is electrically connected to the digital-to-analog converter 1032 , the multi-way switch 1033 , the timing controller 1034 and the synchronization controller 1035 , respectively.

[0081] The power supply unit is used to provide power to the digital-to-analog converter 1032, the multi-way switch 1033, the timing controller 1034 and the synchronization controller 1035, so as to ensure stable and reliable operation of the acquisition device.

[0082] Optionally, see Figure 5 The second test device 102 includes a storage adapter 1021, a plurality of serially connected signal processors 1022 and a controller 1023. The storage adapter 1021 includes a seventh interface 10211, an eighth interface 10212 and a ninth interface 10213. The storage adapter 1021 is electrically connected to the storage device 104 via the seventh interface 10211. The storage adapter 1021 is electrically connected to a first signal processor 1022 in the plurality of serially connected signal processors 1022 via the eighth interface 10212. The storage adapter 1021 is electrically connected to a plurality of serially connected signal processors 1022 via the ninth interface 10213. The last signal processor 1022 in the processor 1022 is electrically connected, and the controller 1023 is electrically connected to the multiple signal processors 1022 respectively. The second test device 102 obtains the operation signal from the storage device 104 through the storage adapter 1021, and the operation signal includes multiple parallel operation sub-signals, and the multiple parallel operation sub-signals are converted into multiple serial operation sub-signals. The controller 1023 controls the multiple signal processors 1022 to pre-process the multiple serial operation sub-signals, and the storage adapter 1021 verifies the processed multiple serial operation sub-signals.

[0083] Since the operation signal stored in the storage device 104 may include multiple parallel operation sub-signals, the multiple parallel operation sub-signals may be converted into multiple serial operation sub-signals through the storage adapter 1021, thereby facilitating subsequent processing of each operation sub-signal.

[0084] Each signal processor 1022 may pre-process the selected operating sub-signal according to a preset signal selection method, thereby ensuring that the multiple signal processors 1022 are able to pre-process each operating sub-signal included in the operating signal.

[0085] The manner of preprocessing the operating sub-signal may be determined in advance, for example, the signal type of the operating signal may be converted or the numerical value of the operating sub-signal may be adjusted.

[0086] It should be noted that the signal processor 1022 may be provided with an output interface, an input interface and a control interface, and may be electrically connected to the storage adapter 1021 or the previous signal processor 1022 via the input interface, and may be electrically connected to the storage adapter 1021 or the next signal processor 1022 via the output interface.

[0087] The controller 1023 is used to control each signal processor 1022, for example, it can control the way each signal processor selects an operating sub-signal, or it can control the way each signal processor pre-processes an operating sub-signal.

[0088] The storage adapter 1021 can verify the operation signal according to a preset verification method, for example, by using a CRC (a Cyclic Redundancy Check) 32 verification utility library, the sending and receiving check bits of each operation sub-signal included in the operation signal can be compared. If they are the same, it is determined that the verification is passed, otherwise it is determined that the verification fails. When the verification passes, the subsequent integrated circuit chip to be tested can be tested based on the operation signal. Of course, if the verification fails, a prompt message can be fed back to the user.

[0089] The storage adapter 1021 and the signal processor 1022 and adjacent signal processors 1022 may communicate based on the GTP protocol.

[0090] Specifically, the second test device 102 may obtain an operation signal from the storage device 104, verify the operation signal, and then test the integrated circuit chip to be tested based on the verified operation signal.

[0091] Optionally, the second test device 102 is specifically configured to control the plurality of signal processors 1022 to convert the plurality of serial operating sub-signals from analog signals to digital signals through the controller 1023 , and to verify the converted operating sub-signals through the storage adapter 1021 .

[0092] As can be seen from the foregoing, the operating signal collected from the preset integrated circuit chip may include a digital signal, and the operating signal stored in the storage device 104 may include an analog signal. Therefore, in order to facilitate the testing of the integrated circuit chip to be tested with an operating signal of the digital signal type, the operating signal obtained from the storage device 104 can be converted into a digital signal.

[0093] Optionally, at least two devices included in the system may be integrated together, for example, the acquisition device 103 may be integrated into the first test device 101 , and the acquisition device 103 may be integrated with the storage device 104 .

[0094] Optionally, the system may include a plurality of first test devices 101 and a plurality of second test devices 102 .

[0095] Figure 6 A flowchart of an integrated circuit chip testing method provided by an embodiment of the present disclosure. The method can be applied to the above-mentioned integrated circuit chip testing system, which includes: a first test device 101, a second test device 102, a collection device 103, a storage device 104 and a computing device 105, wherein the first test device 101, the collection device 103, the storage device 104 and the second test device 102 are electrically connected in sequence, and the computing device 105 is electrically connected to the first test device 101, the second test device 102, the collection device 103 and the storage device 104 respectively, and the computing device 105 is used to control the first test device 101, the second test device 102, the collection device 103 and the storage device 104 respectively according to the control instructions for the first test device 101, the second test device 102, the collection device 103 and the storage device 104. The method may include:

[0096] Step 601 , when the first test device 101 is connected to a preset integrated circuit chip, the collection device 103 collects an operation signal for the preset integrated circuit chip, and stores the operation signal in the storage device 104 .

[0097] Among them, the way in which the acquisition device 103 acquires the operation signal for the preset integrated circuit chip and stores the operation signal in the storage device 104 can be found in the relevant description above and will not be repeated here.

[0098] Step 602: Obtain the operation signal from the storage device 104 through the second test device 102, and test the integrated circuit chip to be tested based on the operation signal. The preset integrated circuit chip is of the same chip type as the integrated circuit chip to be tested.

[0099] The second test device 102 obtains the operation signal from the storage device 104 and tests the integrated circuit chip to be tested based on the operation signal. Please refer to the relevant description above and will not be repeated here.

[0100] In an embodiment of the present disclosure, an integrated circuit testing system includes a first testing device 101, a second testing device 102, a collection device 103, a storage device 104 and a computing device 105, wherein the first testing device 101, the collection device 103, the storage device 104 and the second testing device 102 are electrically connected in sequence, and the computing device 105 is electrically connected to the first testing device 101, the second testing device 102, the collection device 103 and the storage device 104 respectively. Since the computing device 105 can control the first test device 101, the second test device 102, the acquisition device 103 and the storage device 104, the acquisition device 103 can collect the operation signal for the preset integrated circuit chip when the first test device 101 is connected to the preset integrated circuit chip. The operation signal is sufficient to illustrate the actual operation status of the preset integrated circuit chip during the actual operation process. Therefore, the operation signal is stored in the storage device 104, and the second test device 102 can obtain the operation signal from the storage device 104, and based on the operation signal, according to the actual operation status of the preset integrated circuit test chip, test the integrated circuit chip to be tested that is of the same chip type as the preset integrated circuit chip, which can comprehensively cover various faults that may occur in the integrated circuit chip to be tested in actual applications, thereby improving the accuracy of the test.

[0101] Optionally, the operating signal includes an input signal input by the first test device 101 to a preset integrated circuit chip and a first output signal of the preset integrated circuit chip in response to the input signal. Accordingly, the step of obtaining the operating signal from the storage device 104 through the second test device 102 and testing the integrated circuit chip to be tested based on the operating signal may include inputting the input signal to the integrated circuit chip to be tested through the second test device 102, obtaining a second output signal generated by the integrated circuit chip to be tested in response to the input signal, and comparing the first output signal with the second output signal.

[0102] Among them, the input signal is input to the integrated circuit chip under test through the second test device 102, the second output signal generated by the integrated circuit chip under test for the input signal is obtained, and the first output signal is compared with the second output signal. Please refer to the relevant description above and will not be repeated here.

[0103] Optionally, the integrated circuit chip testing system further includes an accessor 106, which is electrically connected to the preset integrated circuit chip, the first test device 101 and the acquisition device 103 respectively. Accordingly, the method further includes: acquiring the operation signal through the accessor, and when the preset integrated circuit chip is accessed to the first test device 101 through the acquisition device 103, the step of collecting the operation signal for the preset integrated circuit chip may include receiving the operation signal sent by the accessor 106 through the acquisition device 103.

[0104] Among them, the manner in which the access device 106 is electrically connected to the preset integrated circuit chip, the first test device 101 and the acquisition device 103, the manner in which the operation signal is obtained through the access device, and the manner in which the acquisition device 103 receives the operation signal sent by the access device 106, can refer to the relevant descriptions above, and will not be repeated here one by one.

[0105] Optionally, before the integrated circuit chip to be tested is tested based on the operating signal, the operating signal can also be verified by the second testing device 102. The step of testing the integrated circuit chip to be tested based on the operating signal can include: testing the integrated circuit chip to be tested based on the verified operating signal by the second testing device 102.

[0106] Among them, the method of verifying the operating signal by the second test device 102 and the method of testing the integrated circuit chip based on the verified operating signal can refer to the relevant description above and will not be repeated here.

Claims

1. An integrated circuit chip testing system, characterized in that: The integrated circuit chip testing system comprises: a first testing device, a second testing device, a collection device, a storage device and a computing device, wherein the first testing device, the collection device, the storage device and the second testing device are electrically connected in sequence, and the computing device is electrically connected to the first testing device, the second testing device, the collection device and the storage device respectively; The computing device is used to control the first test device, the second test device, the acquisition device and the storage device respectively according to the control instructions for the first test device, the second test device, the acquisition device and the storage device; When the first test device is connected to a preset integrated circuit chip, the acquisition device acquires an operation signal for the preset integrated circuit chip and stores the operation signal in the storage device; The second test device obtains the operation signal from the storage device, and tests the integrated circuit chip to be tested based on the operation signal, wherein the preset integrated circuit chip is of the same chip type as the integrated circuit chip to be tested; The integrated circuit chip testing system further includes an access device, the access device including a first interface electrically connected to the preset integrated circuit chip, a second interface electrically connected to the first testing device, and a third interface electrically connected to the acquisition device; The access device obtains the operation signal through the first interface and the second interface, and sends the operation signal to the acquisition device through the third interface; The access device further comprises a signal amplifier, and the signal amplifier is electrically connected to the third interface; The access device amplifies the operation signal through the signal amplifier, and sends the amplified operation signal to the acquisition device through the third interface; The acquisition device includes a fourth interface, a digital-to-analog converter, a multi-way switch, a timing controller, a synchronization controller, a fifth interface and a sixth interface, wherein the fourth interface, the digital-to-analog converter, the multi-way switch, the timing controller and the sixth interface are electrically connected in sequence, and the synchronization controller is electrically connected to the digital-to-analog converter, the multi-way switch, the timing controller and the fifth interface respectively; The acquisition device receives the synchronization control instruction of the computing device through the fifth interface, and performs timing synchronization on the digital-to-analog converter, the multi-way switch, and the timing controller through the synchronization controller. The acquisition device also receives the operation signal through the fourth interface, converts the operation signal from a digital signal to an analog signal through the digital-to-analog converter, transmits the converted operation signal to the timing controller through the multi-way switch, compresses the converted operation signal through the timing controller, and sends the compressed operation signal to the storage device through the sixth interface.

2. The system according to claim 1, characterized in that The operation signal includes an input signal input from the first test device to the preset integrated circuit chip and a first output signal of the preset integrated circuit chip in response to the input signal; The second test device is specifically used to input the input signal into the integrated circuit chip under test, obtain a second output signal generated by the integrated circuit chip under test in response to the input signal, and compare the first output signal with the second output signal.

3. The system according to claim 1, characterized in that The second test device includes a storage adapter, a plurality of signal processors connected in series, and a controller, wherein the storage adapter includes a seventh interface, an eighth interface, and a ninth interface, wherein the storage adapter is electrically connected to the storage device via the seventh interface, wherein the storage adapter is electrically connected to a first signal processor among the plurality of signal processors connected in series via the eighth interface, wherein the storage adapter is electrically connected to a last signal processor among the plurality of signal processors connected in series via the ninth interface, and wherein the controller is electrically connected to the plurality of signal processors respectively; The second test device obtains the operating signal from the storage device through the storage adapter, and the operating signal includes multiple parallel operating sub-signals, converts the multiple parallel operating sub-signals into multiple serial operating sub-signals, controls the multiple signal processors through the controller to pre-process the multiple serial operating sub-signals, and verifies the processed multiple serial operating sub-signals through the storage adapter.

4. A method for testing an integrated circuit chip, characterized in that: The method is applied to an integrated circuit chip test system, which includes: a first test device, a second test device, a collection device, a storage device and a computing device, wherein the first test device, the collection device, the storage device and the second test device are electrically connected in sequence, and the computing device is electrically connected to the first test device, the second test device, the collection device and the storage device respectively, and the computing device is used to control the first test device, the second test device, the collection device and the storage device respectively according to control instructions for the first test device, the second test device, the collection device and the storage device; the integrated circuit chip test system also includes an access device, which includes a first interface electrically connected to a preset integrated circuit chip, a second interface electrically connected to the first test device, and a third interface electrically connected to the first test device. The access device obtains the operation signal through the first interface and the second interface, and sends the operation signal to the acquisition device through the third interface; the access device also includes a signal amplifier, and the signal amplifier is electrically connected to the third interface; the access device amplifies the operation signal through the signal amplifier, and sends the amplified operation signal to the acquisition device through the third interface; the acquisition device includes a fourth interface, a digital-to-analog converter, a multi-way switch, a timing controller, a synchronization controller, a fifth interface and a sixth interface, the fourth interface, the digital-to-analog converter, the multi-way switch, the timing controller and the sixth interface are electrically connected in sequence, and the synchronization controller is electrically connected to the digital-to-analog converter, the multi-way switch, the timing controller and the fifth interface respectively; The method comprises: When the first test device is connected to a preset integrated circuit chip, the collection device collects an operation signal for the preset integrated circuit chip, and stores the operation signal in the storage device; Acquire the operation signal from the storage device through the second test device, and test the integrated circuit chip to be tested based on the operation signal, wherein the preset integrated circuit chip is of the same chip type as the integrated circuit chip to be tested; The collecting, by the collecting device, when the first test device is connected to a preset integrated circuit chip, an operation signal for the preset integrated circuit chip, and storing the operation signal in the storage device, comprises: The acquisition device receives the synchronization control instruction of the computing device through the fifth interface, and performs timing synchronization on the digital-to-analog converter, the multi-way switch, and the timing controller through the synchronization controller. The acquisition device also receives the operation signal through the fourth interface, converts the operation signal from a digital signal to an analog signal through the digital-to-analog converter, transmits the converted operation signal to the timing controller through the multi-way switch, compresses the converted operation signal through the timing controller, and sends the compressed operation signal to the storage device through the sixth interface.

5. The method according to claim 4, characterized in that The operation signal includes an input signal input from the first test device to the preset integrated circuit chip and a first output signal of the preset integrated circuit chip in response to the input signal; The step of obtaining the operation signal from the storage device through the second test device and testing the integrated circuit chip to be tested based on the operation signal includes: The input signal is input to the integrated circuit chip under test through the second test device, a second output signal generated by the integrated circuit chip under test in response to the input signal is obtained, and the first output signal is compared with the second output signal.

6. The method according to claim 4, characterized in that The integrated circuit chip testing system further includes an access device, which is electrically connected to the preset integrated circuit chip, the first testing device and the acquisition device respectively; the method further includes: Acquiring the operation signal through the access device; The collecting, by the collecting device, an operation signal for the preset integrated circuit chip when the first test device is connected to the preset integrated circuit chip, comprises: The operation signal sent by the access device is received through the acquisition device.

7. The method according to claim 4, characterized in that Before testing the integrated circuit chip to be tested based on the operation signal, the method further includes: Verifying the operation signal by using the second test device; The testing of the integrated circuit chip to be tested based on the operation signal includes: The integrated circuit chip to be tested is tested based on the verified operation signal through the second testing device.

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