Semiconductor devices

Abstract

A semiconductor device according to an example embodiment of the present invention includes: a substrate having a first region and a second region horizontally separated from the first region; a first gate line located in the first region, the first gate line including a first lower work function layer and a first upper work function layer arranged on the first lower work function layer; and a second gate line located in the second region and including the second lower work function layer, the width of the second gate line in a first horizontal direction being equal to or narrower than the width of the first gate line in the first direction, wherein the uppermost end of the first upper work function layer and the uppermost end of the second lower work function layer are each located at a higher vertical level than the uppermost end of the first lower work function layer relative to a second direction perpendicular to the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0057093 filed on May 18, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept according to exemplary embodiments relates to a semiconductor device. Background Art

[0004] According to the rapid development of the electronics industry and the needs of users, electronic devices have become more compact and higher performance. Therefore, semiconductor devices used in electronic devices may be required to include transistors that can be continuously scaled down but also provide various operating voltages. Summary of the invention

[0005] An aspect of the inventive concept provides a semiconductor device including transistors having various threshold voltages, and in particular, a p-type transistor having a low threshold voltage.

[0006] According to an example embodiment conceived in the present invention, a semiconductor device includes: a substrate having a first region and a second region horizontally separated from the first region; a first gate line located in the first region, the first gate line including a first lower work function layer and a first upper work function layer arranged on the first lower work function layer; and a second gate line located in the second region and including a second lower work function layer, the width of the second gate line in a first (horizontal) direction being equal to or narrower than the width of the first gate line in the first direction, wherein the uppermost end of the first upper work function layer and the uppermost end of the second lower work function layer are each located at a higher vertical level than the uppermost end of the first lower work function layer relative to a second direction perpendicular to the first direction.

[0007] According to an example embodiment conceived in the present invention, a semiconductor device includes: a substrate having a first region and a second region; a first gate line arranged in the first region and including a first gate insulating layer, a first lower work function layer and a first upper work function layer stacked in sequence; and, a second gate line arranged in the second region and including a second gate insulating layer and a second lower work function layer stacked in sequence, wherein, in the first gate line, the first upper work function layer is arranged to cover the uppermost end of the first lower work function layer, wherein a height of the second gate insulating layer in a direction perpendicular to an upper surface of the substrate is higher than a height of the first gate insulating layer in a direction perpendicular to the upper surface of the substrate, and wherein a height of the second lower work function layer in a direction perpendicular to the upper surface of the substrate is higher than a height of the first lower work function layer in a direction perpendicular to the upper surface of the substrate.

[0008] According to an example embodiment conceived in the present invention, a semiconductor device includes: a substrate having a first region and a second region; a first gate line located in the first region, the first gate line including a first lower work function layer and a first upper work function layer arranged on the first lower work function layer; a second gate line located in the second region and including the second lower work function layer, a width of the second gate line in a first direction being equal to or narrower than a width of the first gate line in the first direction; and a gate cap layer arranged on the second gate line and formed of an insulating material, wherein each of the uppermost end of the first upper work function layer and the uppermost end of the second lower work function layer is at a higher level than the first lower work function layer with respect to a second direction perpendicular to the first direction, and wherein the gate cap layer has a protruding portion filling an internal space of the second lower work function layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The foregoing and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a layout plan view showing a main structure of a semiconductor device including a transistor according to an example embodiment of the inventive concept,

[0011] Figure 2 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept,

[0012] Figures 3 to 9 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept,

[0013] Fig.10 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept,

[0014] Figures 11 to 16 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment of the inventive concept,

[0015] Fig.17 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept, and

[0016] Fig.18 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0017] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0018] Figure 1 is a layout plan view illustrating a main structure of a semiconductor device including a transistor according to an example embodiment of the inventive concept.

[0019] Reference Figure 1 , the semiconductor device 100 may include a first region I, a second region II, a third region III, a fourth region IV, and a fifth region V.

[0020] The first transistor TRA, the second transistor TRB, the third transistor TRC, the fourth transistor TRD, and the fifth transistor TRE may be respectively arranged in the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V. The first transistor TRA, the second transistor TRB, the third transistor TRC, the fourth transistor TRD, and the fifth transistor TRE may be fin field effect transistors FinFETs.

[0021] The first region I may include a plurality of first fin-type active areas FAA and a plurality of first gate lines GLA located on the plurality of first fin-type active areas FAA, the plurality of first fin-type active areas FAA extending parallel to each other in a first direction (X direction), and the plurality of first gate lines GLA extending in a second direction (Y direction) intersecting with the plurality of first fin-type active areas FAA. The first direction (X direction) and the second direction (Y direction) are perpendicular to each other on the same plane, and the first direction (X direction) and the second direction (Y direction) can be described as horizontal directions. The first transistor TRA can be formed respectively on the portions where the plurality of first fin-type active areas FAA and the plurality of first gate lines GLA intersect with each other. The first fin-type active area FAA may have a first fin width FWA in the second direction, and the first gate line GLA may have a first gate width GWA in the first direction.

[0022] The second region II may include a plurality of second fin-type active regions FAB and a plurality of second gate lines GLB located on the plurality of second fin-type active regions FAB, the plurality of second fin-type active regions FAB extending parallel to each other in a first direction (X direction), and the plurality of second gate lines GLB extending in a second direction (Y direction) intersecting with the plurality of second fin-type active regions FAB. The second transistors TRB may be formed respectively on portions where the plurality of second fin-type active regions FAB and the plurality of second gate lines GLB intersect with each other. The second fin-type active region FAB may have a second fin width FWB in the second direction, and the second gate line GLB may have a second gate width GWB in the first direction.

[0023] The third region III may include a plurality of third fin-type active regions FAC and a plurality of third gate lines GLC located on the plurality of third fin-type active regions FAC, the plurality of third fin-type active regions FAC extending parallel to each other in a first direction (X direction), and the plurality of third gate lines GLC extending in a second direction (Y direction) intersecting with the plurality of third fin-type active regions FAC. The third transistors TRC may be formed respectively on portions where the plurality of third fin-type active regions FAC and the plurality of third gate lines GLC intersect with each other. The third fin-type active region FAC may have a third fin width FWC in the second direction, and the third gate line GLC may have a third gate width GWC in the first direction.

[0024] The fourth region IV may include a plurality of fourth fin-type active regions FAD and a plurality of fourth gate lines GLD located on the plurality of fourth fin-type active regions FAD, the plurality of fourth fin-type active regions FAD extending parallel to each other in a first direction (X direction), and the plurality of fourth gate lines GLD extending in a second direction (Y direction) intersecting with the plurality of fourth fin-type active regions FAD. The fourth transistors TRD may be formed respectively on portions where the plurality of fourth fin-type active regions FAD and the plurality of fourth gate lines GLD intersect with each other. The fourth fin-type active region FAD may have a fourth fin width FWD in the second direction, and the fourth gate line GLD may have a fourth gate width GWD in the first direction.

[0025] The fifth region V may include a plurality of fifth fin-type active areas FAE and a plurality of fifth gate lines GLE located on the plurality of fifth fin-type active areas FAE, the plurality of fifth fin-type active areas FAE extending parallel to each other in a first direction (X direction), and the plurality of fifth gate lines GLE extending in a second direction (Y direction) intersecting with the plurality of fifth fin-type active areas FAE. The fifth transistor TRE may be formed respectively on portions where the plurality of fifth fin-type active areas FAE and the plurality of fifth gate lines GLE intersect with each other. The fifth fin-type active area FAE may have a fifth fin width FWE in the second direction, and the fifth gate line GLE may have a fifth gate width GWE in the first direction.

[0026] Each of the first fin width FWA, the second fin width FWB, the third fin width FWC, and the fourth fin width FWD may have a value smaller than the fifth fin width FWE, and each of the first gate width GWA, the second gate width GWB, the third gate width GWC, and the fourth gate width GWD may have a value smaller than the fifth gate width GWE. Each of the first fin width FWA, the second fin width FWB, the third fin width FWC, and the fourth fin width FWD may have the same value as each other, and each of the first gate width GWA, the second gate width GWB, the third gate width GWC, and the fourth gate width GWD may have the same value as each other. A portion of the first gate width GWA, the second gate width GWB, the third gate width GWC, and the fourth gate width GWD may have a lower value than other portions. For example, the fourth gate width GWD may be narrower than each of the first gate width GWA, the second gate width GWB, and the third gate width GWC.

[0027] Each of the first transistor TRA and the second transistor TRB may be a metal oxide semiconductor field effect transistor (MOSFET) of a first conductivity type (e.g., n-type), and each of the third transistor TRC and the fourth transistor TRD may be a MOSFET of a second conductivity type (e.g., p-type), which may be different from the first conductivity type. The fifth transistor TRE may be a p-type MOSFET.

[0028] The operating voltage (threshold voltage) of the first transistor TRA may have a value lower than the operating voltage (threshold voltage) of the second transistor TRB, and the operating voltage (threshold voltage) of the third transistor TRC may have a value higher than the operating voltage (threshold voltage) of the fourth transistor TRD. The operating voltage (threshold voltage) of each of the first transistor TRA, the second transistor TRB, the third transistor TRC, and the fourth transistor TRD may have a value lower than the operating voltage (threshold voltage) of the fifth transistor TRE. The operating voltages (threshold voltages) of the first transistor TRA, the second transistor TRB, the third transistor TRC, the fourth transistor TRD, and the fifth transistor TRE may be compared with each other by the corresponding absolute values ​​of the operating voltages (threshold voltages) of the first transistor TRA, the second transistor TRB, the third transistor TRC, the fourth transistor TRD, and the fifth transistor TRE.

[0029] exist Figure 1In the figure, a plurality of first fin active areas FAA, a plurality of second fin active areas FAB, a plurality of third fin active areas FAC, a plurality of fourth fin active areas FAD and a plurality of fifth fin active areas FAE extending along a first direction (X direction) are exemplarily shown, as well as a plurality of first gate lines GLA, a plurality of second gate lines GLB, a plurality of third gate lines GLC, a plurality of fourth gate lines GLD and a plurality of fifth gate lines GLE extending along a second direction (Y direction). The technical concept of the present invention is not limited to Figure 1 The extension directions of the plurality of first fin type active areas FAA, the plurality of second fin type active areas FAB, the plurality of third fin type active areas FAC, the plurality of fourth fin type active areas FAD and the plurality of fifth fin type active areas FAE and the extension directions of the plurality of first gate lines GLA, the plurality of second gate lines GLB, the plurality of third gate lines GLC, the plurality of fourth gate lines GLD and the plurality of fifth gate lines GLE can be variably selected.

[0030] Figure 2 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Figure 2 shows the corresponding Figure 1 A cross-sectional view related to the positions of the AA' line, the BB' line, the CC' line, the DD' line and the EE' line.

[0031] The semiconductor device 100 may include a first region I, a second region II, a third region III, a fourth region IV, and a fifth region V.

[0032] The first transistor TRA, the second transistor TRB, the third transistor TRC, the fourth transistor TRD, and the fifth transistor TRE may be arranged in the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, respectively.

[0033] The semiconductor device 100 may include a first fin active region FAA, a second fin active region FAB, a third fin active region FAC, a fourth fin active region FAD and a fifth fin active region FAE protruding from the substrate 110 in a first region I, a second region II, a third region III, a fourth region IV and a fifth region V of the substrate 110, respectively.

[0034] The first channel region CHA of the first fin active region FAA and the second channel region CHB of the second fin active region FAB may be regions doped with impurities of the first conductivity type (e.g., carrier impurities). The third channel region CHC of the third fin active region FAC and the fourth channel region CHD of the fourth fin active region FAD may be regions doped with impurities of the second conductivity type (e.g., carrier impurities), the second conductivity type being different from the first conductivity type. The fifth channel region CHE of the fifth fin active region FAE may be a region doped with impurities of the second conductivity type, but is not limited thereto. For example, the first conductivity type may be p-type, and the second conductivity type may be n-type. As used in the present disclosure, carrier impurities refer to impurities to which charge carriers (e.g., holes or electrons) are added relative to an intrinsic semiconductor.

[0035] The first channel region CHA, the second channel region CHB, the third channel region CHC, the fourth channel region CHD, and the fifth channel region CHE may protrude in a fin shape in a direction (Z direction) perpendicular to the main surface (XY plane). Each of the first channel region CHA, the second channel region CHB, the third channel region CHC, and the fourth channel region CHD may be covered with a first interface film 116N, and the fifth channel region CHE may be covered with a second interface film 116W. In the first region I, the second region II, the third region III, and the fourth region IV, respectively, there may be a first gate insulating layer 118N on the first interface film 116N, and the first gate line GLA, the second gate line GLB, the third gate line GLC, and the fourth gate line GLD may cover the first channel region CHA, the second channel region CHB, the third channel region CHC, and the fourth channel region CHD, and may extend in a direction intersecting the first fin type active region FAA, the second fin type active region FAB, the third fin type active region FAC, and the fourth fin type active region FAD. In the fifth region V, there may be a second gate insulating layer 118W on the second interface film 116W, and the fifth gate line GLE may cover the fifth channel region CHE and may extend in a direction intersecting the fifth fin type active region FAE.

[0036] In a direction (X direction) perpendicular to an extending direction (Y direction) of each of the first gate line GLA, the second gate line GLB, the third gate line GLC, and the fourth gate line GLD, each of the first gate line GLA, the second gate line GLB, the third gate line GLC, and the fourth gate line GLD may have a first width ( Figure 4 In the direction (X direction) perpendicular to the extending direction (Y direction) of the fifth gate line GLE, the fifth gate line GLE may have a second width ( Figure 4The first width WGN may be the gate length of each of the first transistor TRA, the second transistor TRB, the third transistor TRC, and the fourth transistor TRD. The second width WGW may be the gate length of the fifth transistor TRE. That is, the second width WGW (the gate length of the fifth transistor TRE) may have a value greater than the first width WGN (the first width WGN may be the gate length of each of the first transistor TRA, the second transistor TRB, the third transistor TRC, and the fourth transistor TRD).

[0037] The first interface film 116N and the second interface film 116W may be formed of a low dielectric material film having a dielectric constant of about 9 or less, such as a silicon oxide film, a silicon oxynitride film, or a combination thereof.

[0038] Terms such as "about" or "approximately" may reflect an amount, size, orientation, or arrangement that varies only in a small relative manner and / or in a manner that does not significantly change the operation, function, or structure of a particular element. For example, a range from "about 0.1 to about 1" may encompass ranges such as 0% to 5% deviations around 0.1 and 0% to 5% deviations around 1, particularly when such deviations maintain the same effect as the listed ranges.

[0039] The first gate insulating layer 118N and the second gate insulating layer 118W may be formed of a silicon oxide film, a high dielectric film, or a combination thereof. The high dielectric film may be formed of a material having a dielectric constant greater than that of the silicon oxide film. The first gate insulating layer 118N and the second gate insulating layer 118W may have a dielectric constant of approximately 10 to 25. According to an exemplary embodiment, the dielectric constant of the first gate insulating layer 118N may be higher than the dielectric constant of the first interface film 116N, and the dielectric constant of the second gate insulating layer 118W may be higher than the dielectric constant of the second interface film 116W. According to an exemplary embodiment, the dielectric constant of the second gate insulating layer 118W may be higher than the dielectric constant of the first interface film 116N, and the dielectric constant of the first gate insulating layer 118N may be higher than the dielectric constant of the second interface film 116W. The first gate insulating layer 118N and the second gate insulating layer 118W may be made of hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, erbium oxide, dysprosium oxide, gadolinium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof, but are not limited thereto.

[0040] The uppermost end of the first gate insulating layer 118N in the fourth region IV may be located at a higher level than the uppermost end of the first gate insulating layer 118N in each of the first region I, the second region II, and the third region III in a direction (Z direction) perpendicular to the upper surface of the substrate 110. The uppermost end of the first gate insulating layer 118N in the fourth region IV and the uppermost end of the second gate insulating layer 118W in the fifth region V may be located at approximately the same level in a direction (Z direction) perpendicular to the upper surface of the substrate 110.

[0041] In a direction (Z direction) perpendicular to the upper surface of the substrate 110, the uppermost end of the first gate insulating layer 118N in each of the first region I, the second region II, the third region III, and the fourth region IV may have a higher level than the uppermost end of each of the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, and the fourth lower work function layer M1D (see, e.g., Figure 2 In the direction (Z direction) perpendicular to the upper surface of the substrate 110, the uppermost end of the second gate insulating layer 118W in the fifth region V may have a higher level than the uppermost end of the fifth lower work function layer M1E (see, for example Figure 2 ).

[0042] The first gate line GLA may include a first lower work function layer M1A, a first upper work function layer M2A, and a first conductive barrier layer BMA. The second gate line GLB may include a second lower work function layer M1B, a second upper work function layer M2B, and a second conductive barrier layer BMB. The third gate line GLC may include a third lower work function layer M1C, a third upper work function layer M2C, and a third conductive barrier layer BMC. The fourth gate line GLD may include a fourth lower work function layer M1D. The fifth gate line GLE may include a fifth lower work function layer M1E, a fifth upper work function layer M2E, a fifth conductive barrier layer BME, and a gap filling metal layer GM.

[0043] The first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may control the work function. The work function of the first gate line GLA, the second gate line GLB, the third gate line GLC, the fourth gate line GLD, and the fifth gate line GLE may be controlled according to the thickness of each of the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E. The first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may be formed of a conductive material having a work function of 4.5 eV or more. The first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may be formed of, for example, a conductive material that does not include aluminum (Al). The first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may be formed of, for example, TiN, TaN, W, WCN, or a combination thereof.

[0044] The first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, and the fourth lower work function layer M1D may be respectively conformally formed on the first gate insulating layer 118N to incompletely fill the first gate space GHA, the second gate space GHB, the third gate space GHC, and the fourth gate space GHD. The fifth lower work function layer M1E may be conformally formed on the second gate insulating layer 118W to incompletely fill the fifth gate space GHE. The first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may have a first thickness to a fifth thickness, respectively. The first thickness of the first lower work function layer M1A in the first direction (X direction) may have a value smaller than the second thickness of the second lower work function layer M1B in the first direction (X direction). The second thickness of the second lower work function layer M1B in the first direction (X direction) may have a value smaller than the third thickness of the third lower work function layer M1C in the first direction (X direction). The third thickness of the third lower work function layer M1C in the first direction (X direction) may have a value smaller than the fourth thickness of the fourth lower work function layer M1D in the first direction (X direction). The fifth thickness of the fifth lower work function layer M1E in the first direction (X direction) may have a value greater than the fourth thickness of the fourth lower work function layer M1D in the first direction (X direction), but is not limited thereto.

[0045] The heights from the lowermost end to the uppermost end of the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may be respectively a first height HA, a second height HB, a third height HC, a fourth height HD, and a fifth height HE. The first height HA, the second height HB, and the third height HC may have approximately the same value. The fourth height HD and the fifth height HE may have approximately the same value. The fourth height HD and the fifth height HE may have a value greater than each of the first height HA, the second height HB, and the third height HC.

[0046] On a plane (XZ plane) perpendicular to the extension direction (Y direction) of the first gate line GLA, the second gate line GLB, the third gate line GLC, the fourth gate line GLD and the fifth gate line GLE, the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D and the fifth lower work function layer M1E may have a U-shaped cross-section.

[0047] The first upper work function layer M2A, the second upper work function layer M2B, and the third upper work function layer M2C may cover the first lower work function layer M1A, the second lower work function layer M1B, and the third lower work function layer M1C, respectively. The fifth upper work function layer M2E may cover the fifth lower work function layer M1E. The first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, and the fifth upper work function layer M2E may control the work function. The first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, and the fifth upper work function layer M2E may be formed of the same material as each other. For example, each of the first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, and the fifth upper work function layer M2E may have the same material composition. The first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, and the fifth upper work function layer M2E may be formed of a conductive material having a lower work function than each of the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E. The first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, and the fifth upper work function layer M2E may be formed of a conductive material having a work function less than 4.5 eV. The first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, and the fifth upper work function layer M2E may be formed of, for example, the following materials: an alloy containing aluminum (Al), a conductive metal carbide containing Al, a conductive metal nitride containing Al, or a combination thereof. In one embodiment, the first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, and the fifth upper work function layer M2E may be formed of TiAl, TiAlC, TiAlN, or a combination thereof.

[0048] The uppermost end of each of the first upper work function layer M2A, the second upper work function layer M2B, and the third upper work function layer M2C may be located at substantially the same level. In the direction perpendicular to the upper surface of the substrate (Z direction), the uppermost end of each of the first upper work function layer M2A, the second upper work function layer M2B, and the third upper work function layer M2C may be located at a higher level than the uppermost end of each of the first lower work function layer M1A, the second lower work function layer M1B, and the third lower work function layer M1C. In the direction perpendicular to the upper surface of the substrate (Z direction), the uppermost end of the fifth upper work function layer M2E may be located at a lower level than the uppermost end of the fifth lower work function layer M1E.

[0049] The first upper work function layer M2A, the second upper work function layer M2B, and the third upper work function layer M2C may fill at least a portion of the U-shaped internal space of each of the first lower work function layer M1A, the second lower work function layer M1B, and the third lower work function layer M1C, and may extend further upward than the uppermost end of each of the first lower work function layer M1A, the second lower work function layer M1B, and the third lower work function layer M1C. In one embodiment, the third upper work function layer M2C may fill the entire U-shaped internal space of the third lower work function layer M1C, and may extend further upward than the uppermost end of the third lower work function layer M1C.

[0050] On a plane (XZ plane) perpendicular to the extension direction (Y direction) of the first, second and third gate lines GLA, GLB and GLC, each of the first, second and third upper work function layers M2A, M2B and M2C may have a U-shaped cross-section.

[0051] The fifth upper work function layer M2E may fill a portion of the U-shaped internal space of the fifth lower work function layer M1E, and in a direction (Z direction) perpendicular to the upper surface of the substrate, the uppermost end of the fifth upper work function layer M2E may be located at a lower level than the uppermost end of the fifth lower work function layer M1E. In a plane (XZ plane) perpendicular to the extension direction (Y direction) of the fifth gate line GLE, the fifth upper work function layer M2E may have a U-shaped cross-section.

[0052] The first conductive barrier layer BMA, the second conductive barrier layer BMB, and the third conductive barrier layer BMC may fill the entire internal space of the first upper work function layer M2A, the second upper work function layer M2B, and the third upper work function layer M2C. In the direction (Z direction) perpendicular to the upper surface of the substrate, the uppermost ends of the first conductive barrier layer BMA, the second conductive barrier layer BMB, and the third conductive barrier layer BMC may be located at a higher level than the uppermost ends of the first upper work function layer M2A, the second upper work function layer M2B, and the third upper work function layer M2C, respectively. The uppermost ends of the first conductive barrier layer BMA, the second conductive barrier layer BMB, and the third conductive barrier layer BMC may be located at approximately the same level as the uppermost end of the fourth lower work function layer M1D.

[0053] In the direction perpendicular to the upper surface of the substrate (Z direction), the lowermost ends of the first conductive barrier layer BMA and the second conductive barrier layer BMB may be located at a lower level than the lowermost end of the third conductive barrier layer BMC. The lowermost end of the first conductive barrier layer BMA may be located at approximately the same level as the lowermost end of the second conductive barrier layer BMB, or the lowermost end of the first conductive barrier layer BMA may be located at a lower level than the lowermost end of the second conductive barrier layer BMB. In the direction perpendicular to the upper surface of the substrate (Z direction), the lowermost ends of the first conductive barrier layer BMA and the second conductive barrier layer BMB may be located at a lower level than the uppermost ends of the first lower work function layer M1A, the second lower work function layer M1B, and the third lower work function layer M1C. In one embodiment, the width WBA of the lower end portion of the first conductive barrier layer BMA in the first direction (X direction) may have a value greater than the width WBB of the lower end portion of the second conductive barrier layer BMB in the first direction (X direction).

[0054] The lowermost end of the third conductive barrier layer BMC may be located at a higher level than the uppermost ends of the first, second, and third lower work function layers M1A, M1B, and M1C in a direction (Z direction) perpendicular to the upper surface of the substrate.

[0055] The fifth conductive barrier layer BME may fill a portion of the U-shaped internal space of the fifth upper work function layer M2E, and in a direction perpendicular to the upper surface of the substrate (Z direction), the uppermost end of the fifth conductive barrier layer BME may be located at a higher level than the uppermost end of the fifth upper work function layer M2E. The uppermost end of the fifth conductive barrier layer BME may be located at approximately the same level as the uppermost end of the fifth lower work function layer M1E. On a plane (XZ plane) perpendicular to the extension direction (Y direction) of the fifth gate line GLE, the fifth conductive barrier layer BME may have a U-shaped cross-section.

[0056] The gap filling metal layer GM may fill the U-shaped internal space of the fifth conductive barrier layer BME. The uppermost end of the gap filling metal layer GM and the uppermost end of the fifth conductive barrier layer BME may be located at approximately the same level. In an embodiment, due to the difference in etching characteristics between the gap filling metal layer GM and the fifth conductive barrier layer BME, the uppermost end of the gap filling metal layer GM may be formed at a higher level than the uppermost end of the fifth conductive barrier layer BME in a direction (Z direction) perpendicular to the upper surface of the substrate.

[0057] The height from the lowest end to the highest end of each of the first gate line GLA, the second gate line GLB, the third gate line GLC, and the fourth gate line GLD may be substantially the same or may have a fourth height HD. The height from the lowest end to the highest end of the fifth gate line GLE may have a fifth height HE substantially equal to the fourth height HD.

[0058] A gate capping layer 134 may be disposed on each of the first gate line GLA, the second gate line GLB, the third gate line GLC, the fourth gate line GLD, and the fifth gate line GLE. In the fourth region IV, the gate capping layer 134 may completely fill the U-shaped inner space of the fourth lower work function layer M1D. In the fourth region IV, the gate capping layer 134 may have a convex portion extending into the inner space of the fourth lower work function layer M1D.

[0059] In each of the first region I, the second region II and the third region III, the gate cover layer 134 may extend along side surfaces corresponding to the first conductive barrier layer BMA, the second conductive barrier layer BMB and the third conductive barrier layer BMC, and may have a protruding portion contacting the uppermost ends of the corresponding first upper work function layer M2A, the second upper work function layer M2B and the third upper work function layer M2C.

[0060] In the fifth region V, the gate capping layer 134 may extend between the fifth lower work function layer M1E and the fifth conductive barrier layer BME, and may have a convex portion contacting the uppermost end of the fifth upper work function layer M2E.

[0061] An operating voltage of a semiconductor device may be determined according to a ratio of a lower work function layer having a relatively high work function and an upper work function layer having a relatively low work function constituting a gate line.

[0062] The semiconductor device 100 conceived according to the present invention may include a fourth transistor TRD, and the fourth transistor TRD is configured so that the fourth height HD (the height of the fourth lower work function layer M1D in the fourth transistor TRD) has a value greater than the first height HA, the second height HB and the third height HC (which are the heights of the first lower work function layer M1A, the second lower work function layer M1B and the third lower work function layer M1C in the first transistor TRA, the second transistor TRB and the third transistor TRC) and the fourth gate line GLD does not include an upper work function layer, and the fourth transistor TRD has an operating voltage lower than the operating voltage of the third transistor TRC.

[0063] In addition, the mask layer ( Figure 6 The ML in the fourth work function layer M1D can be used to form the fourth gate line GLD of the fourth transistor TRD and the fifth gate line GLE of the fifth transistor TRE, so that the height of the fourth lower work function layer M1D in the fourth gate line GLD of the fourth transistor TRD is increased. Therefore, the fourth transistor TRD having a lower operating voltage than the third transistor TRC can be easily implemented without adding a separate photolithography process.

[0064] Figures 3 to 9 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts. Figures 3 to 9 shows the corresponding Figure 1 A cross-sectional view related to the positions of the AA' line, the BB' line, the CC' line, the DD' line and the EE' line.

[0065] Reference Figure 3 , a substrate 110 having a first fin active region FAA, a second fin active region FAB, a third fin active region FAC, a fourth fin active region FAD, and a fifth fin active region FAE may be provided in each of the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, respectively. The first region I and the second region II may be, for example, NMOS transistor regions, and the third region III and the fourth region IV may be, for example, PMOS transistor regions. The fifth region V may be, for example, a PMOS transistor region.

[0066] The substrate 110 may include a semiconductor such as Si or Ge or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. The substrate 110 may include a conductive region such as a well doped with impurities.

[0067] The first fin type active region FAA may protrude from the substrate 110 in the first region I, the second fin type active region FAB may protrude from the substrate 110 in the second region II, the third fin type active region FAC may protrude from the substrate 110 in the third region III, and the fourth fin type active region FAD may protrude from the substrate 110 in the fourth region IV. The fifth fin type active region FAE may protrude from the substrate 110 in the fifth region V.

[0068] According to the channel type of the MOS transistor to be formed, the first fin active area FAA, the second fin active area FAB, the third fin active area FAC, the fourth fin active area FAD and the fifth fin active area FAE may include a p-type impurity diffusion region or an n-type impurity diffusion region, respectively. For example, the first fin active area FAA and the second fin active area FAB may include a p-type impurity diffusion region, and the third fin active area FAC and the fourth fin active area FAD may include an n-type impurity diffusion region. For example, the fifth fin active area FAE may include an n-type impurity diffusion region.

[0069] The first fin active area FAA, the second fin active area FAB, the third fin active area FAC, and the fourth fin active area FAD may have a first level BLN (approximately the same level and the lowest level). The fifth fin active area FAE may have a second level BLW (the lowest level). The first level BLN and the second level BLW may be approximately the same level, but are not limited thereto. The first fin active area FAA, the second fin active area FAB, the third fin active area FAC, and the fourth fin active area FAD may have a first upper surface FTN, which is an upper surface of approximately the same level. The fifth fin active area FAE may have a second upper surface FTW. The first upper surface FTN and the second upper surface FTW may be at substantially the same level, but are not limited thereto.

[0070] In the first region I, the second region II, the third region III, and the fourth region IV, a first dummy gate structure DGSN extending in a direction intersecting the first fin active region FAA, the second fin active region FAB, the third fin active region FAC, and the fourth fin active region FAD may be formed on the first fin active region FAA, the second fin active region FAB, the third fin active region FAC, and the fourth fin active region FAD. In the fifth region V, a second dummy gate structure DGSW extending in a direction intersecting the fifth fin active region FAE may be formed on the fifth fin active region FAE. In a direction (X direction) perpendicular to the extension direction (Y direction) of the first dummy gate structure DGSN and the second dummy gate structure DGSW, the width of the second dummy gate structure DGSW may have a value greater than the width of the first dummy gate structure DGSN. The gate length of the second dummy gate structure DGSW may have a value greater than the gate length of the first dummy gate structure DGSN.

[0071] The first dummy gate structure DGSN may include a first dummy gate insulating layer D114N, a first dummy gate line D116N, and a first dummy gate capping layer D118N, which are sequentially stacked on the first fin type active area FAA, the second fin type active area FAB, the third fin type active area FAC, and the fourth fin type active area FAD. The first dummy gate insulating layer D114N may include silicon oxide. The first dummy gate line D116N may include polysilicon. The first dummy gate capping layer D118N may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0072] The second dummy gate structure DGSW may include a second dummy gate insulating layer D114W, a second dummy gate line D116W, and a second dummy gate capping layer D118W, which are sequentially stacked on the fifth fin type active region FAE. Each of the second dummy gate insulating layer D114W, the second dummy gate line D116W, and the second dummy gate capping layer D118W may be formed of the same material as each of the first dummy gate insulating layer D114N, the first dummy gate line D116N, and the first dummy gate capping layer D118N.

[0073] A first insulating spacer 124N covering both sidewalls of the first dummy gate structure DGSN may be formed in each of the first region I, the second region II, the third region III, and the fourth region IV, and a second insulating spacer 124W covering both sidewalls of the second dummy gate structure DGSW may be formed in the fifth region V. The first insulating spacer 124N and the second insulating spacer 124W may be formed of the same material. For example, the material component of the first insulating spacer 124N may be the same as the material component of the second insulating spacer 124W. The first insulating spacer 124N and the second insulating spacer 124W may include SiN, SiOCN, SiCN, or a combination thereof.

[0074] A first recessed portion RSA, a second recessed portion RSB, a third recessed portion RSC, and a fourth recessed portion RSD may be formed in the first region I, the second region II, the third region III, and the fourth region IV, respectively, by removing a portion of the first fin active region FAA, the second fin active region FAB, the third fin active region FAC, and the fourth fin active region FAD on both sides of the first dummy gate structure DGSN and the first insulating spacer 124N. A fifth recessed portion RSE may be formed in the fifth region V by removing a portion of the fifth fin active region FAE on both sides of the second dummy gate structure DGSW and the second insulating spacer 124W. In one embodiment, the first recessed portion RSA, the second recessed portion RSB, the third recessed portion RSC, and the fourth recessed portion RSD may also extend from both sides of the first insulating spacer 124N to the lower side of the first insulating spacer 124N, and the fifth recessed portion RSE may also extend from both sides of the second insulating spacer 124W to the lower side of the second insulating spacer 124W.

[0075] By performing an epitaxial growth process to form a semiconductor layer in the first fin active region FAA and the second fin active region FAB exposed by the first recessed portion RSA and the second recessed portion RSB on both sides of the first dummy gate structure DGSN, a first source / drain region 130A and a second source / drain region 130B may be formed in the first region I and the second region II. By performing an epitaxial growth process to form a semiconductor layer in the third fin active region FAC and the fourth fin active region FAD exposed by the third recessed portion RSC and the fourth recessed portion RSD on both sides of the first dummy gate structure DGSN, a third source / drain region 130C and a fourth source / drain region 130D may be formed in the third region III and the fourth region IV. By performing an epitaxial growth process to form a semiconductor layer in the fifth fin active region FAE exposed by the fifth recessed portion RSE on both sides of the second dummy gate structure DGSW, a fifth source / drain region 130E may be formed in the fifth region V. The first source / drain region 130A and the second source / drain region 130B may be Si or SiC semiconductor layers doped with n-type impurities, and the third source / drain region 130C and the fourth source / drain region 130D may be SiGe semiconductor layers doped with p-type impurities. For example, the fifth source / drain region 130E may be a SiGe semiconductor layer doped with p-type impurities.

[0076] In the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, an interlayer insulating film 132 covering the first source / drain region 130A, the second source / drain region 130B, the third source / drain region 130C, the fourth source / drain region 130D, and the fifth source / drain region 130E, the first dummy gate structure DGSN and the second dummy gate structure DGSW, and the first insulating spacer 124N and the second insulating spacer 124W may be formed. The upper surface of the interlayer insulating film 132 may be located at the same level as the upper surfaces of the first dummy gate capping layer D118N and the second dummy gate capping layer D118W. The upper surface of the interlayer insulating film 132 may be coplanar with the upper surfaces of the first dummy gate capping layer D118N and the second dummy gate capping layer D118W.

[0077] Reference Figure 4, in the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, the first dummy gate structure DGSN and the second dummy gate structure DGSW exposed by the interlayer insulating film 132 may be removed, thereby forming a first gate space GHA, a second gate space GHB, a third gate space GHC, a fourth gate space GHD, and a fifth gate space GHE in the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, respectively. The first insulating spacer 124N and the second insulating spacer 124W and the first fin type active region FAA, the second fin type active region FAB, the third fin type active region FAC, the fourth fin type active region FAD, and the fifth fin type active region FAE may be exposed through the first gate space GHA, the second gate space GHB, the third gate space GHC, the fourth gate space GHD, and the fifth gate space GHE.

[0078] In the first region I, the second region II, the third region III, and the fourth region IV, a first interface film 116N and a first gate insulating layer 118N may be formed in the first gate space GHA, the second gate space GHB, the third gate space GHC, and the fourth gate space GHD. In the fifth region V, a second interface film 116W and a second gate insulating layer 118W may be formed in the fifth gate space GHE.

[0079] For example, the first interface film 116N and the second interface film 116W may be formed by oxidizing a portion of the first fin active region FAA, a portion of the second fin active region FAB, a portion of the third fin active region FAC, a portion of the fourth fin active region FAD, and a portion of the fifth fin active region FAE exposed in the first gate space GHA, the second gate space GHB, the third gate space GHC, the fourth gate space GHD, and the fifth gate space GHE. The first interface film 116N and the second interface film 116W may be formed on the first fin active region FAA, the second fin active region FAB, the third fin active region FAC, the fourth fin active region FAD, and the fifth fin active region FAE exposed on the lower surfaces of the first gate space GHA, the second gate space GHB, the third gate space GHC, the fourth gate space GHD, and the fifth gate space GHE. The first interface film 116N and the second interface film 116W may be formed of, for example, a silicon oxide film, a silicon oxynitride film, or a combination thereof.

[0080] The first gate insulating layer 118N and the second gate insulating layer 118W may be formed to cover the first interface film 116N, the inner surface of the first gate space GHA, the inner surface of the second gate space GHB, the inner surface of the third gate space GHC, the inner surface of the fourth gate space GHD, the inner surface of the fifth gate space GHE, and the upper surface of the interlayer insulating film 132. The first gate insulating layer 118N and the second gate insulating layer 118W may be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes. In each of the first gate space GHA, the second gate space GHB, the third gate space GHC, and the fourth gate space GHD, the space defined by the first gate insulating layer 118N may have the same value of the first width WGN. In the fifth gate space GHE, the space defined by the second gate insulating layer 118W may have a second width WGW, which has a larger value than the first width WGN.

[0081] In each of the first region I, the second region II, the third region III, and the fourth region IV, a first lower work function layer M1A, a second lower work function layer M1B, a third lower work function layer M1C, and a fourth lower work function layer M1D may be formed on the first gate insulating layer 118N, respectively. In the fifth region V, a fifth lower work function layer M1E may be formed on the second gate insulating layer 118W.

[0082] The first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, and the fourth lower work function layer M1D may be conformally formed on the first gate insulating layer 118N to incompletely fill the first gate space GHA, the second gate space GHB, the third gate space GHC, and the fourth gate space GHD. The fifth lower work function layer M1E may be conformally formed on the second gate insulating layer 118W to incompletely fill the fifth gate space GHE. The first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may have a first thickness WMA, a second thickness WMB, a third thickness WMC, a fourth thickness WMD, and a fifth thickness WME, respectively. The first thickness WMA may have a value smaller than the second thickness WMB. The second thickness WMB may have a value smaller than the third thickness WMC. The third thickness WMC may have a value smaller than the fourth thickness WMD. The fifth thickness WME may have a value greater than the fourth thickness WMD, but is not limited thereto. In one embodiment, the fifth thickness WME may have the same value as the fourth thickness WMD or may have a smaller value than the fourth thickness WMD.

[0083] The first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may be formed of, for example, TiN, TaN, W, WCN, or a combination thereof. The first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may be formed by, for example, ALD, CVD, or PVD processes.

[0084] A dielectric film barrier layer (not shown) may be formed between the first gate insulating layer 118N and the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, and the fourth lower work function layer M1D, and between the second gate insulating layer 118W and the fifth lower work function layer M1E. For example, the dielectric film barrier layer may be formed of at least one metal selected from Ti, Ta, W, Ru, Nb, Mo, and Hf, a metal nitride, a metal carbide, a metal silicon nitride, or a combination thereof.

[0085] Reference Figure 5 , a covering layer may be formed to cover each of the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E located in the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, respectively, and completely fill the first gate space GHA, the second gate space GHB, the third gate space GHC, the fourth gate space GHD, and the fifth gate space GHE (see Figure 4 ). For example, the capping layer may be formed of a carbon-based film. For example, the carbon-based film may be formed of an amorphous carbon layer (ACL) film or a carbon-based spin-on hard mask (C-SOH).

[0086] In each of the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, a portion of the cover layer may be removed to form a first gate space GHA, a second gate space GHB, a third gate space GHC, a fourth gate space GHD, and a fifth gate space GHE covered in the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E (see Figure 4 )’s lower part’s cover layer CLa.

[0087] Reference Figure 6 A cap layer CLa and a mask layer ML completely covering the fourth lower work function layer M1D and the fifth lower work function layer M1E may be formed in the fourth region IV and the fifth region V, respectively. For example, the mask layer ML may be formed of a photoresist. The mask layer ML may not be formed in the first region I, the second region II, and the third region III.

[0088] In the first region I, the second region II, and the third region III, a portion of the first gate insulating layer 118N and a portion of the first lower work function layer M1A, a portion of the second lower work function layer M1B, and a portion of the third lower work function layer M1C are removed. The lower side portions of the first lower work function layer M1A, the second lower work function layer M1B, and the third lower work function layer M1C covered by the cap layer CLa may be retained without being removed. In the direction (Z direction) perpendicular to the upper surface of the substrate, the uppermost end of the first gate insulating layer 118N in each of the first region I, the second region II, and the third region III may have a higher level than the uppermost end of the remaining portions of the first lower work function layer M1A, the second lower work function layer M1B, and the third lower work function layer M1C.

[0089] The fourth and fifth lower work function layers M1D and M1E covered by the mask layer ML in the fourth and fifth regions IV and V, and the first and second gate insulating layers 118N and 118W may remain without being removed.

[0090] Reference Figure 7 , the mask layer can be removed ( Figure 6 ML) and cap layer ( Figure 6 For example, the mask layer ML and the cap layer CLa may be removed together through an ashing process and a stripping process.

[0091] Reference Figure 8 In each of the first region I, the second region II, the third region III, the fourth region IV and the fifth region V, a first upper work function layer M2A and a first conductive barrier layer BMA may be sequentially formed on the first lower work function layer M1A, a second upper work function layer M2B and a second conductive barrier layer BMB may be sequentially formed on the second lower work function layer M1B, a third upper work function layer M2C and a third conductive barrier layer BMC may be sequentially formed on the third lower work function layer M1C, a fourth upper work function layer M2D and a fourth conductive barrier layer BMD may be sequentially formed on the fourth lower work function layer M1D, and a fifth upper work function layer M2E and a fifth conductive barrier layer BME may be sequentially formed on the fifth lower work function layer M1E.

[0092] The first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, the fourth upper work function layer M2D, and the fifth upper work function layer M2E may be formed of a material different from the material used in the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E. For example, the material composition of each of the first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, the fourth upper work function layer M2D, and the fifth upper work function layer M2E may be different from the material composition of a corresponding one of the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E.

[0093] Each of the first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, the fourth upper work function layer M2D and the fifth upper work function layer M2E can be formed by the same material composition. The first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, the fourth upper work function layer M2D and the fifth upper work function layer M2E can be formed by TiAl, TiAlC, TiAlN, or a combination thereof. For example, the first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, the fourth upper work function layer M2D and the fifth upper work function layer M2E can be formed together by ALD, CVD, or PVD processes. The first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, the fourth upper work function layer M2D and the fifth upper work function layer M2E can be respectively formed to have the same thickness in the first region I, the second region II, the third region III, the fourth region IV and the fifth region V.

[0094] In the fourth region IV, the fourth upper work function layer M2D may completely fill the space defined between the fourth lower work function layer M1D in the fourth gate space GHD. In the first region I, the second region II, and the third region III, the first upper work function layer M2A, the second upper work function layer M2B, and the third upper work function layer M2C may respectively fill a portion of the first gate space GHA, a portion of the second gate space GHB, and a portion of the third gate space GHC. In the fifth region V, the fifth upper work function layer M2E may fill a portion of the fifth gate space GHE.

[0095] The first conductive barrier layer BMA, the second conductive barrier layer BMB, the third conductive barrier layer BMC, the fourth conductive barrier layer BMD and the fifth conductive barrier layer BME may be formed of the same material component. The first conductive barrier layer BMA, the second conductive barrier layer BMB, the third conductive barrier layer BMC, the fourth conductive barrier layer BMD and the fifth conductive barrier layer BME may be formed of metal nitrides (e.g., TiN, TaN, or a combination thereof). For example, the first conductive barrier layer BMA, the second conductive barrier layer BMB, the third conductive barrier layer BMC, the fourth conductive barrier layer BMD and the fifth conductive barrier layer BME may be formed together by ALD, CVD, or PVD processes. The first conductive barrier layer BMA, the second conductive barrier layer BMB, the third conductive barrier layer BMC, the fourth conductive barrier layer BMD and the fifth conductive barrier layer BME may be formed to have the same thickness in the first region I, the second region II, the third region III, the fourth region IV and the fifth region V, respectively.

[0096] In the first region I, the second region II, and the third region III, the first conductive barrier layer BMA, the second conductive barrier layer BMB, and the third conductive barrier layer BMC may fill the remaining first gate space GHA, the second gate space GHB, and the third gate space GHC, respectively. In the fifth region V, the fifth conductive barrier layer BME may fill only a portion of the fifth gate space GHE. The first conductive barrier layer BMA, the second conductive barrier layer BMB, and the third conductive barrier layer BMC may extend into the first gate space GHA, the second gate space GHB, and the third gate space GHC, respectively. The lowermost end of the third conductive barrier layer BMC may be located at a higher level than the lowermost ends of the first conductive barrier layer BMA and the second conductive barrier layer BMB. The first conductive barrier layer BMA may extend into the space defined between the first lower work function layer M1A, and the second conductive barrier layer BMB may extend into the space defined between the second lower work function layer M1B. The first conductive barrier layer BMA and the second conductive barrier layer BMB may have a lower side, the width of which is narrower than the upper side of the first gate space GHA and the second gate space GHB.

[0097] In the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, a gap-filling metal layer GM may be formed on the first conductive barrier layer BMA, the second conductive barrier layer BMB, the third conductive barrier layer BMC, the fourth conductive barrier layer BMD, and the fifth conductive barrier layer BME, respectively. For example, the gap-filling metal layer GM may be made of tungsten (W). In the fifth region V, the gap-filling metal layer GM may completely fill the remaining fifth gate space GHE.

[0098] Reference Fig. 9, a first gate line GLA, a second gate line GLB, a third gate line GLC, a fourth gate line GLD and a fifth gate line GLE can be formed. In the first region I, the second region II, the third region III, the fourth region IV and the fifth region V, the following layers formed on the interlayer insulating film 132 can be completely removed by planarization treatment (such as chemical mechanical polishing / planarization (CMP)): the gap filling metal layer GM, the first conductive barrier layer BMA, the second conductive barrier layer BMB, the third conductive barrier layer BMC, the fourth conductive barrier layer BMD and the fifth conductive barrier layer BME, and the first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, the fourth upper work function layer M2D and the fifth upper work function layer M2E. In the first region I, the second region II and the third region III, the gap filling metal layer GM can be completely removed. In the fourth region IV, the fourth conductive barrier layer BMD can be completely removed.

[0099] In addition, a portion of the gap-filling metal layer GM, a portion of the first conductive barrier layer BMA, a portion of the second conductive barrier layer BMB, a portion of the third conductive barrier layer BMC, a portion of the fourth conductive barrier layer BMD, and a portion of the fifth conductive barrier layer BME, and a portion of the first upper work function layer M2A, a portion of the second upper work function layer M2B, a portion of the third upper work function layer M2C, a portion of the fourth upper work function layer M2D, and a portion of the fifth upper work function layer M2E formed in the upper portions of the first gate space GHA, the second gate space GHB, the third gate space GHC, the fourth gate space GHD, and the fifth gate space GHE may be further removed. As a result, in the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, an upper portion of the first insulating spacer 124N and an upper portion of the second insulating spacer 124W may be exposed.

[0100] Subsequently, the fourth upper work function layer M2D in the fourth region IV may be completely removed by an etching process (e.g., a wet etching process). By the wet etching process, a portion of the first upper work function layer M2A, a portion of the second upper work function layer M2B, and a portion of the third upper work function layer M2C in the first region I, the second region II, and the third region III may be removed, and a portion of the fifth upper work function layer M2E in the fifth region V may be removed. Therefore, in a direction perpendicular to the upper surface of the substrate (Z direction), the uppermost ends of the first upper work function layer M2A, the second upper work function layer M2B, and the third upper work function layer M2C may be located at a higher level than the uppermost ends of the first lower work function layer M1A, the second lower work function layer M1B, and the third lower work function layer M1C, respectively. In a direction perpendicular to the upper surface of the substrate (Z direction), the uppermost end of the fifth upper work function layer M2E may be located at a lower level than the uppermost end of the fifth lower work function layer M1E. HF or H 2 SO 4 A wet etching process is performed.

[0101] Refer again Figure 2 , a gate capping layer 134 may be formed on each of the first gate line GLA, the second gate line GLB, the third gate line GLC, the fourth gate line GLD, and the fifth gate line GLE.

[0102] In the fourth region IV, the gate capping layer 134 may fill the space from which the fourth upper work function layer M2D is removed.

[0103] Fig.10 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept. Fig.10 Shows the corresponding Figure 1 A cross-sectional view of the positions of the A-A' line, the B-B' line, the C-C' line, the D-D' line and the E-E' line. Fig.10 In the description of the semiconductor device 100A, the Figure 2 The components of the semiconductor device 100 are the same components.

[0104] The semiconductor device 100A may include a first region I, a second region II, a third region III, a fourth region IV, and a fifth region V. The first transistor TRA, the second transistor TRB, the third transistor TRCa, the fourth transistor TRDa, and the fifth transistor TREa may be arranged in the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, respectively.

[0105] The semiconductor device 100A may include a first fin active region FAA, a second fin active region FAB, a third fin active region FAC, a fourth fin active region FAD and a fifth fin active region FAE protruding from the substrate 110 in a first region I, a second region II, a third region III, a fourth region IV and a fifth region V of the substrate 110, respectively.

[0106] In the first region I, the second region II, the third region III, and the fourth region IV, respectively, there may be a first gate insulating layer 118N on the first interface film 116N, and the first gate line GLA, the second gate line GLB, the third gate line GLCa, and the fourth gate line GLDa may cover the first channel region CHA, the second channel region CHB, the third channel region CHC, and the fourth channel region CHD, respectively, and may extend in a direction intersecting the first fin type active region FAA, the second fin type active region FAB, the third fin type active region FAC, and the fourth fin type active region FAD. In the fifth region V, there may be a second gate insulating layer 118W on the second interface film 116W, and the fifth gate line GLEa may cover the fifth channel region CHE and may extend in a direction intersecting the fifth fin type active region FAE.

[0107] The first gate line GLA may include a first lower work function layer M1A, a first upper work function layer M2A, and a first conductive barrier layer BMA. The second gate line GLB may include a second lower work function layer M1B, a second upper work function layer M2B, and a second conductive barrier layer BMB. The third gate line GLCa may include a third lower work function layer M1C and a first gap filling metal layer GM1. The fourth gate line GLDa may include a fourth lower work function layer M1D and a first gap filling metal layer GM1. The fifth gate line GLEa may include a fifth lower work function layer M1E, a first gap filling metal layer GM1, a fifth intermediate work function layer M1E', a fifth upper work function layer M2E, a fifth conductive barrier layer BME, and a second gap filling metal layer GM2. In one embodiment, the fifth gate line GLEa may not include the fifth intermediate work function layer M1E'.

[0108] The first, second, third, fourth, and fifth lower work function layers M1A, M1B, M1C, M1D, and M1E may be formed of, for example, TiN, TaN, W, WCN, or a combination thereof.

[0109] The height from the lowermost end to the uppermost end of each of the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may be respectively a first height HA, a second height HB, a third height HC, a fourth height HD, and a fifth height HE. The first height HA, the second height HB, and the third height HC may have approximately the same value. The fourth height HD and the fifth height HE may have approximately the same value. The fourth height HD and the fifth height HE may have values ​​greater than the first height HA, the second height HB, and the third height HC.

[0110] On a plane (XZ plane) perpendicular to the extension direction (Y direction) of the first gate line GLA, the second gate line GLB, the third gate line GLCa, the fourth gate line GLDa and the fifth gate line GLEa, the first lower work function layer M1A, the second lower work function layer M1B, the third lower work function layer M1C, the fourth lower work function layer M1D and the fifth lower work function layer M1E may have a U-shaped cross-section.

[0111] The first upper work function layer M2A and the second upper work function layer M2B may cover the first lower work function layer M1A and the second lower work function layer M1B, respectively.

[0112] The first gap-filling metal layer GM1 may cover the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E.

[0113] The first gap-filling metal layer GM1 of the fifth gate line GLEa may conformally cover the fifth lower work function layer M1E, the fifth intermediate work function layer M1E′ may conformally cover the first gap-filling metal layer GM1, and the fifth upper work function layer M2E may conformally cover the fifth intermediate work function layer M1E′.

[0114] The fifth intermediate work function layer M1E' can be made of, for example, TiN, TaN, W, WCN, or a combination thereof. The first upper work function layer M2A, the second upper work function layer M2B, and the fifth upper work function layer M2E can be formed of, for example, the following materials: an alloy containing aluminum (Al), a conductive metal carbide containing Al, a conductive metal nitride containing Al, or a combination thereof. In one embodiment, the first upper work function layer M2A, the second upper work function layer M2B, and the fifth upper work function layer M2E can include TiAl, TiAlC, TiAlN, or a combination thereof.

[0115] In the first region I and the second region II, the uppermost ends of the first conductive barrier layer BMA and the second conductive barrier layer BMB may be located at approximately the same level as the uppermost ends of the first upper work function layer M2A and the second upper work function layer M2B. The uppermost ends of the first conductive barrier layer BMA and the second conductive barrier layer BMB may be located at approximately the same level as the uppermost end of the fourth lower work function layer M1D and the uppermost end of the first gap filling metal layer GM1.

[0116] In the third region III, the first gap filling metal layer GM1 can completely fill the U-shaped internal space of the third lower work function layer M1C, and in the direction perpendicular to the upper surface of the substrate (Z direction), the uppermost end of the first gap filling metal layer GM1 can be located at a higher level than the uppermost end of the third lower work function layer M1C.

[0117] In the fourth region IV, the first gap-filling metal layer GM1 may completely fill the U-shaped inner space of the fourth lower work function layer M1D, and the uppermost end of the first gap-filling metal layer GM1 may be located at approximately the same level as the uppermost end of the fourth lower work function layer M1D.

[0118] In the fifth region V, the first gap-filling metal layer GM1 may fill a portion of the U-shaped internal space of the fifth lower work function layer M1E, and the fifth intermediate work function layer M1E', the fifth upper work function layer M2E and the fifth conductive barrier layer BME may be stacked in sequence in the U-shaped internal space of the first gap-filling metal layer GM1. The second gap-filling metal layer GM2 may completely fill the U-shaped internal space of the fifth conductive barrier layer BME. In the direction (Z direction) perpendicular to the upper surface of the substrate, the uppermost end of the fifth upper work function layer M2E may be located at a lower level than the uppermost end of the fifth lower work function layer M1E.

[0119] A gate capping layer 134 may be disposed on each of the first gate line GLA, the second gate line GLB, the third gate line GLCa, the fourth gate line GLDa, and the fifth gate line GLEa.

[0120] An operating voltage of a semiconductor device may be determined according to a ratio of a lower work function layer having a relatively high work function and an upper work function layer having a relatively low work function constituting a gate line.

[0121] The semiconductor device 100A according to the present invention may include a fourth transistor TRDa, which has an operating voltage lower than that of the third transistor TRCa by being configured so that a fourth height HD (the height of the fourth lower work function layer M1D in the fourth transistor TRDa) has a value greater than the first height HA, the second height HB, and the third height HC (which are the heights of the first lower work function layer M1A, the second lower work function layer M1B, and the third lower work function layer M1C in the first transistor TRA, the second transistor TRB, and the third transistor TRCa) and the fourth gate line GLDa does not include an upper work function layer. In the case of the third transistor TRCa and the fourth transistor TRDa, since they are filled with a gap-filling metal layer formed of tungsten instead of an upper work function layer, they can have a low gate impedance.

[0122] Figures 11 to 16 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts. Figures 11 to 16 shows the corresponding Figure 1 A cross-sectional view related to the positions of the AA' line, the BB' line, the CC' line, the DD' line and the EE' line.

[0123] In reference Figure 3 After the described processing is completed, you can Figures 11 to 16 processing.

[0124] Fig.11 The processing can be compared with the reference Figure 4 and Figure 5 The described process is different in that in the first region I, the second region II, and the third region III, the third lower work function layer M1C may be formed on the first gate insulating layer 118N, and the other parts are the same.

[0125] Reference Fig.12 A cap layer CLa and a mask layer ML covering the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E may be formed in the first region I, the second region II, the fourth region IV, and the fifth region V, respectively. For example, the mask layer ML may be formed of a photoresist. The mask layer ML may not be formed in the third region III.

[0126] In the third region III, a portion of the first gate insulating layer 118N and a portion of the third lower work function layer M1C are removed. A lower side portion of the third lower work function layer M1C covered by the capping layer CLa may remain without being removed.

[0127] Reference Fig.13 , the mask layer can be removed ( Fig.12 ML) and cap layer ( Fig.12For example, the mask layer ML and the cap layer CLa may be removed together through an ashing process and a stripping process.

[0128] In each of the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, a first gap filling metal layer GM1 may be formed on each of the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E. The first gap filling metal layer GM1 may be formed to completely fill the inside of the first gate space GHA, the second gate space GHB, the third gate space GHC, and the fourth gate space GHD, and may be formed to partially fill the inside of the fifth gate space GHE, and may be conformally formed on the fifth lower work function layer M1E. For example, the first gap filling metal layer GM1 may be formed of tungsten (W).

[0129] The first gap-fill metal layer GM1 and the third lower work function layer M1C may be completely removed in the first region I and the second region II by a photolithography process or an etching process. The etching process may include using a 2 O 2 The wet etching process may include a solution of 1% to 5% tantalum. The solution may include dilute sulfuric peroxide (DSP). The etching process may include using an etching gas (such as NF 3 NH 3 The etching process may be a process in which a wet etching process and a dry etching process are mixed.

[0130] Reference Fig.14 , a first lower work function layer M1A and a second lower work function layer M1B may be formed in the first region I and the second region II, respectively. A third intermediate work function layer M1C', a fourth intermediate work function layer M1D', and a fifth intermediate work function layer M1E' may be formed in the third region III, the fourth region IV, and the fifth region V, respectively. In one embodiment, the third intermediate work function layer M1C', the fourth intermediate work function layer M1D', and the fifth intermediate work function layer M1E' formed in each of the third region III, the fourth region IV, and the fifth region V may be removed.

[0131] Each of the first lower work function layer M1A and the second lower work function layer M1B may be conformally formed on the first gate insulating layer 118N.

[0132] The capping layer CLb may be formed to cover lower portions of the first and second lower work function layers M1A and M1B in the first and second regions I and II and to cover a lower portion of the fifth intermediate work function layer M1E′ in the fifth region V.

[0133] Reference Fig.15 In the first region I and the second region II, portions of the first gate insulation layer 118N not covered by the capping layer CLb and portions of the first lower work function layer M1A and the second lower work function layer M1B not covered by the capping layer CLb may be removed.

[0134] Reference Fig.16 , a first upper work function layer M2A and a first conductive barrier layer BMA, a second upper work function layer M2B and a second conductive barrier layer BMB, a third upper work function layer M2C and a third conductive barrier layer BMC, a fourth upper work function layer M2D and a fourth conductive barrier layer BMD, and a fifth upper work function layer M2E and a fifth conductive barrier layer BME can be formed in sequence in the first region I, the second region II, the third region III, the fourth region IV and the fifth region V, respectively.

[0135] In the first region I, the first upper work function layer M2A may be conformally formed between the first lower work function layer M1A in the first gate space GHA, and in the second region II, the second upper work function layer M2B may be conformally formed between the second lower work function layer M1B in the second gate space GHB. In the fifth region V, the fifth upper work function layer M2E may be conformally formed to fill a portion of the fifth gate space GHE. The first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, the fourth upper work function layer M2D, and the fifth upper work function layer M2E may be formed of TiAl, TiAlC, TiAlN, or a combination thereof.

[0136] In each of the first region I and the second region II, the first conductive barrier layer BMA and the second conductive barrier layer BMB may fill the remaining first gate space GHA and the second gate space GHB, respectively. In the fifth region V, the fifth conductive barrier layer BME may be conformally formed to fill a portion of the fifth gate space GHE. The first conductive barrier layer BMA, the second conductive barrier layer BMB, the third conductive barrier layer BMC, the fourth conductive barrier layer BMD, and the fifth conductive barrier layer BME may be formed of metal nitrides (e.g., TiN, TaN, or a combination thereof).

[0137] In the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, a second gap filling metal layer GM2 may be formed on the first conductive barrier layer BMA, the second conductive barrier layer BMB, the third conductive barrier layer BMC, the fourth conductive barrier layer BMD, and the fifth conductive barrier layer BME, respectively. For example, the second gap filling metal layer GM2 may be formed of tungsten (W). In the fifth region V, the second gap filling metal layer GM2 may fill the remaining fifth gate space GHE.

[0138] Refer again Fig.10 In the first region I, the second region II, the third region III, the fourth region IV and the fifth region V, the first gate line GLA, the second gate line GLB, the third gate line GLCa, the fourth gate line GLDa and the fifth gate line GLEa and the gate capping layer 134 may be formed respectively.

[0139] In the first region I, the second region II, the third region III, the fourth region IV and the fifth region V, the first gate line GLA, the second gate line GLB, the third gate line GLCa, the fourth gate line GLDa and the fifth gate line GLEa can be formed by planarization treatment (such as CMP) and by removing the following parts formed on the interlayer insulating film 132: the second gap filling metal layer GM2, the first conductive barrier layer BMA, the second conductive barrier layer BMB, the third conductive barrier layer BMC, the fourth conductive barrier layer BMD and the fifth conductive barrier layer BME, the first upper work function layer M2A, the second upper work function layer M2B, the third upper work function layer M2C, the fourth upper work function layer M2D and the fifth upper work function layer M2E, the third intermediate work function layer M1C', the fourth intermediate work function layer M1D' and the fifth intermediate work function layer M1E', the first gap filling metal layer GM1, and the fourth lower work function layer M1D and the fifth lower work function layer M1E.

[0140] In the first region I, the second region II, the third region III, the fourth region IV and the fifth region V, a portion of the first gate line GLA, a portion of the second gate line GLB, a portion of the third gate line GLCa, a portion of the fourth gate line GLDa and a portion of the fifth gate line GLEa can be removed by additional etching treatment to expose the upper portion of the first insulating spacer 124N and the upper portion of the second insulating spacer 124W.

[0141] A gate capping layer 134 may be formed on the first gate line GLA, the second gate line GLB, the third gate line GLCa, the fourth gate line GLDa, and the fifth gate line GLEa.

[0142] Fig.17 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the inventive concept.

[0143] Fig.17 shows the corresponding Figure 1 A cross-sectional view of the positions of the A-A' line, the B-B' line, the C-C' line, the D-D' line and the E-E' line. Fig.17 In the description of the semiconductor device 100B, the Fig.10 The components of the semiconductor device 100A are the same as the components of the semiconductor device 100A.

[0144] The semiconductor device 100B can be used with Fig.10The semiconductor device 100A is the same as the semiconductor device 100A, except that the fifth gate line GLEb replaces Fig.10 The fifth gate line GLEa.

[0145] and Fig.10 Unlike the fifth gate line GLEa, the fifth gate line GLEb may be formed by the fifth lower work function layer M1E and the first gap filling metal layer GM1. The fifth lower work function layer M1E may be formed of, for example, TiN, TaN, W, WCN, or a combination thereof. For example, the first gap filling metal layer GM1 may be made of tungsten (W).

[0146] Fig.18 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts. Fig.18 shows the corresponding Figure 1 A cross-sectional view related to the positions of the AA' line, the BB' line, the CC' line, the DD' line and the EE' line.

[0147] In reference Figure 3 After the described processing is completed, you can Fig.11 and Fig.12 processing.

[0148] Next, refer to Fig.18 , the mask layer can be removed by ashing and stripping processes ( Fig.12 ML) and cap layer ( Fig.12 Then, in each of the first region I, the second region II, the third region III, the fourth region IV, and the fifth region V, a first gap-filling metal layer GM1 may be formed on the third lower work function layer M1C, the fourth lower work function layer M1D, and the fifth lower work function layer M1E. Fig.13 In a different manner, in the fifth region V, the first gap-filling metal layer GM1 may be formed on the fifth lower work function layer M1E and may be formed to completely fill the fifth gate space GHE.

[0149] Next, the first gap filling metal layer GM1, the fourth lower work function layer M1D, the fifth lower work function layer M1E, the first gate insulating layer 118N and the second gate insulating layer 118W formed on the interlayer insulating film 132 may be removed by a planarization process (such as CMP). In the first region I and the second region II, the first gap filling metal layer GM1 and the third lower work function layer M1C may be completely removed by a photolithography process or an etching process. The etching process may include using a molten metal layer containing H 2 O 2The wet etching process may include a solution of 1% to 5% tantalum. The solution may include dilute sulfuric peroxide (DSP). The etching process may include using an etching gas (such as NF 3 NH 3 The etching process may be a process in which a wet etching process and a dry etching process are mixed.

[0150] Then, you can execute Fig.14 The following subsequent processing is performed to produce Fig.17 Semiconductor device 100B.

[0151] For example, the semiconductor devices 100 , 100A, and 100B may be in the form of semiconductor chips or dies formed from a semiconductor wafer. For example, the substrate 110 may be formed from a wafer such as a silicon wafer.

[0152] The gate line width is reduced due to downsizing, which makes it difficult to reduce the threshold voltage of the p-type transistor. However, according to the present invention, by removing the n-type work function metal from the gate line constituting the p-type transistor, a p-type transistor with a low threshold voltage can be realized.

[0153] According to the inventive concept, a p-type transistor with a low threshold voltage may be realized without using an additional optical process to selectively remove an n-type work function metal in a gate line constituting the p-type transistor.

[0154] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. Unless the context indicates otherwise, these terms are only used to distinguish an element, a component, a region, a layer or a part from another element, another component, another region, another layer or another part, for example, as a naming convention. Therefore, the first element, the first component, the first region, the first layer or the first part discussed in a part of the specification can be referred to as the second element, the second component, the second region, the second layer or the second part in another part of the specification or the claim without departing from the teaching of the present invention. In addition, in some cases, even if "first", "second", etc. are not used to describe the term in the specification, it can still be referred to as "first" or "second" in the claim to distinguish different claimed elements from each other.

[0155] Various advantageous advantages and effects of the present inventive concept are not limited to the above description and can be more easily understood in the course of describing specific embodiments of the present inventive concept.

[0156] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims.

Claims

1. A semiconductor device comprising: a substrate having a first region and a second region horizontally separated from the first region; A first gate line, which is located in the first region, and includes a first lower work function layer and a first upper work function layer arranged on the first lower work function layer; as well as a second gate line, which is located in the second region, includes a second lower work function layer, and no upper work function layer is arranged above the second lower work function layer, the width of the second gate line in the first horizontal direction is equal to or narrower than the width of the first gate line in the first horizontal direction, and the material of the second lower work function layer is the same as that of the first lower work function layer; wherein the uppermost end of the first upper work function layer and the uppermost end of the second lower work function layer are each located at a higher vertical level than the uppermost end of the first lower work function layer relative to a second direction perpendicular to the first horizontal direction, Wherein, the first gate line further includes a first conductive barrier layer located on the first upper work function layer, and Wherein, the uppermost end of the first conductive barrier layer is located at a higher vertical level than the uppermost end of the first upper work function layer.

2. The semiconductor device according to claim 1, wherein The uppermost end of the first upper work function layer is located at a lower vertical level than the uppermost end of the second lower work function layer.

3. The semiconductor device according to claim 1, wherein The uppermost end of the first conductive barrier layer and the uppermost end of the second lower work function layer are located at the same vertical level.

4. The semiconductor device according to claim 1 , further comprising a gate capping layer arranged on the second gate line and formed of an insulating material, in, The second lower work function layer has a U-shape in a cross section on a plane perpendicular to the extending direction of the second gate line, and The gate capping layer has a convex portion extending into an inner space of the U shape of the second lower work function layer.

5. The semiconductor device according to claim 1, wherein The second lower work function layer has a U-shape in a cross section on a plane perpendicular to the extending direction of the second gate line, and The second gate line further includes a gap-filling metal layer filling an inner space of the U-shape of the second lower work function layer.

6. The semiconductor device according to claim 5, wherein: An uppermost end of the gap-fill metal layer is located at a higher vertical level than the uppermost end of the first lower work function layer.

7. The semiconductor device according to claim 1, wherein The first lower work function layer and the second lower work function layer are formed of a material having a larger work function than the first upper work function layer.

8. The semiconductor device according to claim 1, wherein The thickness of the first lower work function layer is thinner than that of the second lower work function layer.

9. The semiconductor device according to claim 1, further comprising: a first fin type active region protruding from the substrate and extending in the first horizontal direction to intersect the first gate line in the first region; as well as a second fin type active region protruding from the substrate and extending in the first horizontal direction to intersect the second gate line in the second region, The first fin type active region is doped with charge carrier impurities of a first conductivity type, and the second fin type active region is doped with charge carrier impurities of a second conductivity type, which is different from the charge carrier impurities of the first conductivity type.

10. The semiconductor device according to claim 9, in, The substrate further has a third region horizontally separated from the first region and the second region, Wherein, the semiconductor device further comprises: a third fin-type active region protruding from the substrate in the third region and doped with charge carrier impurities of the second conductivity type; and a third gate line extending in the first horizontal direction to intersect the third fin type active area, the third gate line having the same width as the first gate line and comprising a third lower work function layer and a third upper work function layer located on the third lower work function layer, and Wherein, the uppermost end of the first upper work function layer and the uppermost end of the third upper work function layer are located at a lower vertical level than the uppermost end of the second lower work function layer.

11. The semiconductor device according to claim 10, wherein The first gate line further includes a first conductive barrier layer located on the first upper work function layer. The third gate line further includes a second conductive barrier layer located on the third upper work function layer, wherein the second conductive barrier layer and the first conductive barrier layer are formed of the same material composition, and An uppermost end of the first conductive barrier layer is located at a higher vertical level than the uppermost end of the first upper work function layer, and An uppermost end of the second conductive barrier layer is located at a higher vertical level than the uppermost end of the third upper work function layer.

12. The semiconductor device according to claim 11, wherein The uppermost end of the first conductive barrier layer and the uppermost end of the second conductive barrier layer are located at the same vertical level, and A lowermost end of the first conductive barrier layer is located at a lower vertical level than a lowermost end of the second conductive barrier layer.

13. The semiconductor device according to claim 11, wherein The uppermost end of the second conductive barrier layer is located at a higher vertical level than the uppermost end of the third upper work function layer.

14. A semiconductor device comprising: a substrate having a first region and a second region horizontally separated from the first region; A first gate line, which is arranged in the first region and includes a first gate insulating layer, a first lower work function layer and a first upper work function layer stacked in sequence; as well as A second gate line, which is arranged in the second region, comprises a second gate insulating layer and a second lower work function layer stacked in sequence, and no upper work function layer is arranged above the second lower work function layer, and a material of the second lower work function layer is the same as that of the first lower work function layer; Wherein, the first upper work function layer is arranged to cover the uppermost end of the first lower work function layer, wherein a height of the second gate insulating layer in a direction perpendicular to an upper surface of the substrate is higher than a height of the first gate insulating layer in the direction perpendicular to the upper surface of the substrate, and The height of the second lower work function layer in the direction perpendicular to the upper surface of the substrate is higher than the height of the first lower work function layer in the direction perpendicular to the upper surface of the substrate.

15. The semiconductor device according to claim 14, wherein: A height of the first upper work function layer in the direction perpendicular to the upper surface of the substrate is lower than a height of the second lower work function layer in the direction perpendicular to the upper surface of the substrate.

16. The semiconductor device according to claim 14, wherein: The first gate line further includes a first conductive barrier layer located on the first upper work function layer, and A height of the first conductive barrier layer in the direction perpendicular to the upper surface of the substrate is higher than a height of the first upper work function layer in the direction perpendicular to the upper surface of the substrate.

17. The semiconductor device according to claim 14, further comprising a gate capping layer disposed on the second gate line and formed of an insulating material, in, The second lower work function layer has a U-shape in a cross section on a plane perpendicular to the extending direction of the second gate line, and The gate capping layer has a convex portion extending into an inner space of the U shape of the second lower work function layer.

18. The semiconductor device according to claim 14, wherein: The cross section of the second lower work function layer on a plane perpendicular to the extending direction of the second gate line has a U shape, The second gate line further includes a gap-filling metal layer filling an inner space of the U-shape of the second lower work function layer, and An uppermost end of the gap-fill metal layer is located at a higher level with respect to the upper surface of the substrate than an uppermost end of the first lower work function layer.

19. A semiconductor device comprising: a substrate having a first region and a second region horizontally separated from the first region; A first gate line, which is located in the first region, and includes a first lower work function layer and a first upper work function layer arranged on the first lower work function layer; a second gate line located in the second region, comprising a second lower work function layer, and no upper work function layer is disposed above the second lower work function layer, the width of the second gate line in the first direction is equal to or narrower than the width of the first gate line in the first direction, and the material of the second lower work function layer is the same as that of the first lower work function layer; and a gate capping layer, which is arranged on the second gate line and is formed of an insulating material, wherein each of the uppermost end of the first upper work function layer and the uppermost end of the second lower work function layer is located at a higher level than the uppermost end of the first lower work function layer with respect to a second direction perpendicular to the first direction, and The gate cap layer has a convex portion filling an inner space of the second lower work function layer.

20. The semiconductor device according to claim 1, in, The substrate further has a fourth region horizontally separated from the first region and the second region, Wherein, the semiconductor device further comprises: a fourth gate line, which is located in the fourth region, and includes a fourth lower work function layer, Wherein, the width of the first gate line in the first horizontal direction is equal to the width of the fourth gate line in the first horizontal direction, and Wherein, the uppermost end of the fourth lower work function layer is located at a higher vertical level than the uppermost end of the first lower work function layer.

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