Semiconductor device and method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a method for manufacturing the same. The method includes forming an active structure, the active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure spanning the active patterns and extending along a first direction; forming a first mask pattern on the active structure; and patterning the active structure to form a groove by using the first mask pattern as an etching mask. Forming the first mask pattern includes forming a plurality of first openings extending along a second direction intersecting the first direction in a first mask layer, and forming a plurality of second openings extending along a third direction intersecting the first direction and the second direction in the first mask layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0056825 filed on May 18, 2018 in the Korean Intellectual Property Office, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of manufacturing a semiconductor device in which a pillar is formed using line patterning and a semiconductor device manufactured using the same. Background Art

[0004] Semiconductor devices are widely used in the electronics industry due to their small size, high functionality, and / or low manufacturing cost. Semiconductor devices may include memory devices for storing data, logic devices for processing data, and hybrid devices for operating various functions simultaneously or synchronously.

[0005] With the advanced development of the electronics industry, semiconductor devices are increasingly required to be highly integrated. Therefore, due to the problem of reduced processing margin in the exposure process for defining fine patterns, it is increasingly difficult to manufacture semiconductor devices. With the development of the electronics industry, semiconductor devices are also increasingly required to operate at high speeds. Various studies have been conducted to meet the requirements of high integration and / or high speed in semiconductor devices. Summary of the invention

[0006] Some embodiments of the inventive concept provide a semiconductor device having a constant minimum distance between any adjacent pillars and a method of manufacturing the same.

[0007] According to some example embodiments of the inventive concept, a method of manufacturing a semiconductor device may include: forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure spanning the active patterns and extending along a first direction; forming a first mask pattern on the active structure; and patterning the active structure to form a trench by using the first mask pattern as an etching mask. The step of forming the first mask pattern may include: forming a plurality of first openings extending along a second direction intersecting the first direction in a first mask layer; and forming a plurality of second openings extending along a third direction intersecting the first direction and the second direction in the first mask layer.

[0008] According to some example embodiments of the inventive concept, a method of manufacturing a semiconductor device may include: forming an active structure including a plurality of active patterns, a device isolation layer between the active patterns, and a gate structure spanning the active patterns and extending along a first direction; forming a first mask pattern on the active structure; and patterning the active structure to form a trench by using the first mask pattern as an etching mask. The step of forming the first mask pattern may include: forming a plurality of first openings extending along a second direction intersecting the first direction in a first mask layer; and forming a plurality of second openings extending along the second direction in the first mask layer.

[0009] According to some example embodiments of the inventive concept, a semiconductor device may include: an active structure including an active pattern and a gate structure, wherein the active pattern includes a first impurity region and a second impurity region, and wherein the gate structure is located between the first impurity region and the second impurity region and extends along a first direction; a trench defining a pillar at an upper portion of the active structure; and a conductive pattern extending along a second direction on the active structure and electrically connected to the first impurity region exposed to the trench, the second direction intersecting the first direction. The pillar may include a first pillar, a second pillar, and a third pillar. The first to third pillars may be spaced apart from each other in a third direction intersecting the first and second directions. The minimum distance between the first and second pillars may be substantially the same as the minimum distance between the second and third pillars. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1A to 14A A plan view illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts is shown.

[0011] Figures 1B to 14B Shown are Figures 1A to 14A A cross-sectional view taken along line AA'.

[0012] Figures 1C to 14C Shown are Figures 1A to 14A A cross-sectional view taken along line BB'.

[0013] Fig.15A and Fig. 15B A plan view illustrating a semiconductor device according to an example embodiment of the inventive concept is shown.

[0014] FIG. 16A to FIG. 21A A plan view illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts is shown.

[0015] FIG. 16B to FIG. 21B Shown are FIG. 16A to FIG. 21A A cross-sectional view taken along line AA'.

[0016] FIG. 16C to FIG. 21C Shown are FIG. 16A to FIG. 21AA cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0017] Figures 1A to 14A A plan view illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts is shown. Figures 1B to 14B Shown are Figures 1A to 14A A cross-sectional view taken along line AA'. Figures 1C to 14C Shown are Figures 1A to 14A A cross-sectional view taken along line BB'.

[0018] Reference Figure 1A , Figure 1B and Figure 1C , a device isolation layer ST may be formed on a substrate 100 including a cell region CR and a dummy region DR adjacent to the cell region CR. For example, a portion of the substrate 100 may be etched, and then the etched portion may be filled with an insulating material to form a device isolation layer ST. The formation of the device isolation layer ST may define an active pattern ACT surrounded by the device isolation layer ST. The device isolation layer ST may include silicon oxide. The substrate 100 may be or may include a semiconductor substrate including silicon, germanium, or silicon germanium. Each active pattern ACT may extend in a third direction D3 parallel to the top surface of the substrate 100. The active patterns ACT may be spaced apart from each other in the third direction D3.

[0019] Reference Figure 2A , Figure 2B and Figure 2C , the gate structure GS may be formed to cross the device isolation layer ST and the active pattern ACT. Each gate structure GS may include a gate dielectric layer GI, a gate electrode GE, and / or a gate capping layer GP.

[0020] For example, the device isolation layer ST and the active pattern ACT may be patterned to form a first trench TR1. The first trench TR1 may extend in a second direction D2 that is parallel to the top surface of the substrate 100 and intersects with a third direction D3. The first trenches TR1 may be spaced apart from each other in the first direction D1 that is parallel to the top surface of the substrate 100 and intersects with the second direction D2 and the third direction D3. The first trench TR1 may cross the active pattern ACT.

[0021] The formation of the first trench TR1 may include forming a hard mask pattern having an opening, and then etching the active pattern ACT and the device isolation layer ST exposed to the opening using the hard mask pattern as an etching mask.

[0022] A gate dielectric layer GI may be conformally formed in each first trench TR1. The gate dielectric layer GI may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric material. For example, the high-k dielectric material may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, silicon zirconium oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0023] A conductive layer filling the first trench TR1 may be formed on the gate dielectric layer GI, which may result in the formation of the gate electrode GE. The conductive layer may include one or more of a conductive metal nitride (eg, titanium nitride or tantalum nitride) and a metal (eg, titanium, tantalum, tungsten, copper or aluminum).

[0024] The gate dielectric layer GI and the gate electrode GE may be recessed, and then a gate capping layer GP may be formed on the recessed gate electrode GE. The gate capping layer GP may have a top surface coplanar with a top surface of the active pattern ACT. The gate capping layer GP may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0025] Impurities may be implanted into the active patterns ACT to form a first impurity region SD1 and a pair of second impurity regions SD2 at an upper portion of each active pattern ACT. The pair of second impurity regions SD2 may be spaced apart from each other in a third direction D3 across the first impurity region SD1. The first impurity region SD1 and the second impurity region SD2 may be doped to have the same conductivity type (e.g., N-type).

[0026] The active pattern ACT, the gate structure GS, and / or the device isolation layer ST may constitute or form an active structure AS. A planarization process may be performed so that the active structure AS has a substantially flat top surface.

[0027] A target layer TL, a first mask layer ML1 , a hard mask layer HM, a first insulating layer IL1 , a second mask layer ML2 , a third mask layer ML3 , and / or a second insulating layer IL2 , which are sequentially formed, may be disposed on the active structure AS.

[0028] The target layer TL may include a plurality of insulating layers. The insulating layer may be a silicon oxide layer, a silicon nitride layer, or a combination thereof or may include these layers. The first mask layer ML1 may include a doped polysilicon layer. The hard mask layer HM may include a spin-on hard mask (SOH) layer. The hard mask layer HM may further include a silicon oxide layer under the SOH layer. The first insulating layer IL1 may include one or more of a silicon nitride layer and a silicon oxynitride layer. The second mask layer ML2 may include a silicon oxide layer. The third mask layer ML3 may include a spin-on hard mask (SOH) layer. The second insulating layer IL2 may include one or more of a silicon nitride layer and a silicon oxynitride layer.

[0029] Reference Figure 3A , Figure 3B and Figure 3C , the third mask layer ML3 and the second insulating layer IL2 may be patterned to form a first opening OP1. The first opening OP1 may extend in a fourth direction D4 that is parallel to the top surface of the substrate 100 and intersects with the second direction D2. For example, the first opening OP1 may extend in a direction that intersects with the gate electrode GE.

[0030] The formation of the first opening OP1 may include forming a first photoresist layer on the second insulating layer IL2 , patterning the first photoresist layer using a first photomask, and patterning the third mask layer ML3 and the second insulating layer IL2 using the patterned first photoresist layer as an etching mask. The remaining first photoresist layer may be removed.

[0031] The first dielectric film IF1 may be conformally formed on the entire surface of the substrate 100. The first dielectric film IF1 may include a silicon oxide layer. The first dielectric film IF1 may be formed by atomic layer deposition (ALD).

[0032] Reference Figure 4A , Figure 4B and Figure 4C , a first filling layer FL1 may be formed on the first dielectric film IF1. The first filling layer FL1 may fill the first opening OP1. The first filling layer FL1 may include a spin-on hard mask (SOH) layer.

[0033] After forming the first filling layer FL1, a first etch-back process may be performed. The first etch-back process may be performed so that the second insulating layer IL2, the portion of the first dielectric film IF1 located on the second insulating layer IL2, and the portion of the first filling layer FL1 located on the second insulating layer IL2 are removed. Both the remaining first dielectric film IF1 and the first filling layer FL1 may selectively fill each of the first openings OP1. Both the remaining first dielectric film IF1 and the first filling layer FL1 may be disposed in the third mask layer ML3. When viewed in a plan view, the third mask layer ML3, the first dielectric film IF1, and the first filling layer FL1 may be exposed on the entire surface of the substrate 100.

[0034] Reference Figure 5A , Figure 5B and Figure 5C, a first etching process may be performed to pattern the second mask layer ML2. The first etching process may include removing the first dielectric film IF1 between the third mask layer ML3 and the first filling layer FL1, and patterning the second mask layer ML2 using the third mask layer ML3 and the first filling layer FL1 as etching masks. A removal process may be performed to remove the third mask layer ML3 and the first filling layer FL1 remaining after the first etching process.

[0035] The first etching process may form second openings OP2 in the second mask layer ML2. The second openings OP2 may extend in the fourth direction D4. The first etching process may cause the second mask layer ML2 to be patterned to have a linear shape extending in the fourth direction D4.

[0036] Reference Fig. 6A , Figure 6B and Figure 6C , a second filling layer FL2 may be formed on the entire surface of the substrate 100. The second filling layer FL2 may fill the second opening OP2. The second filling layer FL2 may include a spin-on hard mask (SOH) layer.

[0037] A third insulating layer IL3, a fourth mask layer ML4 and / or a fourth insulating layer IL4 may be sequentially formed on the second filling layer FL2. The third insulating layer IL3 may include a silicon oxide layer. The fourth mask layer ML4 may include a spin-on hard mask (SOH) layer. The fourth insulating layer IL4 may include one or more of a silicon nitride layer and a silicon oxynitride layer.

[0038] The fourth mask layer ML4 and the fourth insulating layer IL4 may be patterned to form a third opening OP3. The third opening OP3 may extend in a fifth direction D5 that is parallel to the top surface of the substrate 100 and intersects with the second direction D2. For example, the third opening OP3 may extend in a direction that intersects the gate electrode GE and the second opening OP2.

[0039] Forming the third opening OP3 may include forming a second photoresist layer on the fourth insulating layer IL4, patterning the second photoresist layer using a second photomask, and patterning the fourth mask layer ML4 and the fourth insulating layer IL4 using the patterned second photoresist layer as an etching mask. The remaining second photoresist layer may be removed.

[0040] The second dielectric film IF2 may be conformally formed on the entire surface of the substrate 100. The second dielectric film IF2 may include a silicon oxide layer. The second dielectric film IF2 may be formed by atomic layer deposition (ALD).

[0041] Reference Fig. 7A , Figure 7B and Figure 7C, a third filling layer FL3 may be formed on the second dielectric film IF2. The third filling layer FL3 may fill the third opening OP3. The third filling layer FL3 may include a spin-on hard mask (SOH) layer.

[0042] After forming the third filling layer FL3, a second etch-back process may be performed. The second etch-back process may be performed so that the fourth insulating layer IL4 is removed, the portion of the second dielectric film IF2 located on the fourth insulating layer IL4 is removed, and the portion of the third filling layer FL3 located on the fourth insulating layer IL4 is removed. The remaining second dielectric film IF2 and the third filling layer FL3 may both selectively fill each of the third openings OP3. The remaining second dielectric film IF2 and the third filling layer FL3 may both be disposed in the fourth mask layer ML4. When viewed in a plan view, the fourth mask layer ML4, the second dielectric film IF2, and the third filling layer FL3 may be exposed on the entire surface of the substrate 100.

[0043] Reference Fig. 8A , Figure 8B and Figure 8C , a second etching process may be performed to pattern the second mask layer ML2. The second etching process may include removing the second dielectric film IF2 between the fourth mask layer ML4 and the third filling layer FL3, and patterning the third insulating layer IL3, the second filling layer FL2, and the second mask layer ML2 using the fourth mask layer ML4 and the third filling layer FL3 as etching masks. A removal process may be performed to remove the fourth mask layer ML4, the third filling layer FL3, the second dielectric film IF2, the third insulating layer IL3, and / or the second filling layer FL2 remaining after the second etching process.

[0044] The second etching process may form fourth openings OP4 in the second mask layer ML2. The fourth openings OP4 may extend in the fifth direction D5. The fourth openings OP4 may partially overlap with the second openings OP2.

[0045] The second etching process may cause the second mask layer ML2 to be patterned to form first mask patterns MP1. Each of the first mask patterns MP1 may have a diamond shape when viewed in a plan view. Each of the first mask patterns MP1 may be defined by second and fourth openings OP2 and OP4.

[0046] Reference Fig.9A , Fig. 9B and Fig. 9C, a photoresist pattern PR may be formed on the dummy region DR of the substrate 100. For example, the formation of the photoresist pattern PR may include forming a third photoresist layer on the entire surface of the substrate 100 and patterning the third photoresist layer using a third photomask. The photoresist pattern PR may fill a portion OP2P of the second opening OP2 on the dummy region DR of the substrate 100. The photoresist pattern PR may also fill a portion OP4P of the fourth opening OP4 on the dummy region DR of the substrate 100. The photoresist pattern PR may connect the first mask pattern MP1 to each other on the dummy region DR.

[0047] Reference Fig. 10A , Fig. 10B and Fig. 10C , a third etching process may be performed to form the second trench TR2. The third etching process may include patterning the first insulating layer IL1 using the first mask pattern MP1 as an etching mask, patterning the hard mask layer HM using the patterned first insulating layer IL1 as an etching mask, patterning the first mask layer ML1 and the target layer TL using the patterned hard mask layer HM as an etching mask, and patterning the active structure AS using the patterned first mask layer ML1 and the patterned target layer TL as etching masks. A removal process may be performed to remove the photoresist pattern PR, the first mask pattern MP1, the first dielectric film IF1, the first insulating layer IL1, and the hard mask layer HM remaining after the third etching process. Patterning the first insulating layer IL1 using the first mask pattern MP1 as an etching mask may include patterning the first insulating layer IL1 using the second opening OP2 and the fourth opening OP4.

[0048] The patterning of the first mask layer ML1 may form a second mask pattern MP2 on the cell region CR of the substrate 100. Each of the second mask patterns MP2 may have an elliptical shape when viewed in a plan view. Although each of the first mask patterns MP1 has a rhombus shape, the pattern shapes of the plurality of layers may be changed while being sequentially etched during the third etching process. Finally, each of the second mask patterns MP2 may be formed to have an elliptical shape. The second mask patterns MP2 may be spaced apart from each other in the fourth direction D4. The second mask patterns MP2 may also be spaced apart from each other in the fifth direction D5. A single second mask pattern MP2 may vertically overlap two second impurity regions SD2 adjacent to each other in the second direction D2.

[0049] The patterning of the target layer TL may form a target pattern TP on the cell region CR of the substrate 100. The target pattern TP may vertically overlap the second mask pattern MP2. For example, the target pattern TP and the second mask pattern MP2 may have the same planar shape and arrangement.

[0050] The patterning of the active structure AS may form a pillar PL on the cell region CR of the substrate 100, and also form a second trench TR2 between the pillars PL. For example, the second trench TR2 may define the pillar PL of the active structure AS. The active structure AS may have a portion at a level higher than the bottom plate surface of the second trench TR2, and the portion of the active structure AS may be defined as the pillar PL. The second trench TR2 may expose the first impurity region SD1. Each pillar PL may include an upper device isolation layer UST, an upper second impurity region USD2, and / or an upper gate capping layer UGP. The upper device isolation layer UST may be a portion of the device isolation layer ST, which is located at a level higher than the bottom plate surface of the second trench TR2. The upper second impurity region USD2 may be a portion of the second impurity region SD2, which is located at a level higher than the bottom plate surface of the second trench TR2. The upper gate capping layer UGP may be a portion of the gate capping layer GP, which is located at a level higher than the bottom plate surface of the second trench TR2.

[0051] Each of the pillars PL may have an elliptical shape when viewed in a plan view. The pillars PL may be spaced apart from each other in the fourth direction D4. The pillars PL may also be spaced apart from each other in the fifth direction D5.

[0052] The patterning of the first mask layer ML1 may form a first dummy pattern DP1 on the dummy region DR of the substrate 100. The first dummy pattern DP1 may include a portion extending in the first direction D1 and other portions extending in the second direction D2.

[0053] The patterning of the target layer TL may form a second dummy pattern DP2 on the dummy region DR of the substrate 100. The second dummy pattern DP2 may vertically overlap the first dummy pattern DP1. For example, the first dummy pattern DP1 and the second dummy pattern DP2 may have the same planar shape.

[0054] Reference Fig.11A , Fig. 11B and Fig. 11C , a first conductive layer CL1, a second conductive layer CL2, and / or a fifth mask layer ML5 may be sequentially formed on the entire surface of the substrate 100. The first conductive layer CL1 may fill the second trench TR2. The first conductive layer CL1 may contact the first impurity region SD1. The first conductive layer CL1 may include one of a doped semiconductor material (e.g., doped silicon or doped germanium), a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). The conductivity of the first conductive layer CL1 may be greater than the conductivity of the second mask pattern MP2. The second conductive layer CL2 may include a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum). The fifth mask layer ML5 may include a silicon nitride layer or a silicon oxynitride layer.

[0055] Reference Fig. 12A , Fig. 12B and Fig. 12C , the line structures LST may be formed to extend in the first direction D1. The line structures LST may be spaced apart from each other in the second direction D2.

[0056] For example, the fifth mask layer ML5 may be patterned to form a third mask pattern MP3. The third mask pattern MP3 may be patterned using a photolithography process.

[0057] The third mask pattern MP3 may be used as an etching mask to sequentially etch the second conductive layer CL2 and the first conductive layer CL1 to form a bit line BL and a conductive pattern CP, respectively. The third mask pattern MP3, the bit line BL, and the conductive pattern CP may vertically overlap each other. The third mask pattern MP3, the bit line BL, and / or the conductive pattern CP may constitute or form a line structure LST. When viewed in a plan view, the bit line BL may extend while crossing the gate electrode GE.

[0058] The conductive pattern CP may be connected to the first impurity region SD1. For example, the bit line BL may be electrically connected to the first impurity region SD1 through the conductive pattern CP. The second mask pattern MP2 and the target pattern TP covering the second impurity region SD2 may separate the conductive pattern CP from the second impurity region SD2.

[0059] Reference Fig.13A , Fig. 13B and Fig. 13C , the spacer SP may be formed to cover the opposite sidewalls of each line structure LST. The second trench TR2 may be filled with a portion of the spacer SP. The formation of the spacer SP may include conformally forming a spacer layer on the entire surface of the substrate 100 and anisotropically etching the spacer layer. The spacer layer may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0060] Reference Fig.14A , Fig. 14B and Fig. 14C , the third dielectric film IF3 may be formed on the entire surface of the substrate 100. The third dielectric film IF3 may include a silicon oxide layer. A planarization process may be performed to remove an upper portion of the third dielectric film IF3 and an upper portion of the third mask pattern MP3.

[0061] The third dielectric film IF3, the second mask pattern MP2, and the target pattern TP may be patterned, and thus the contact hole CTH may be formed. Alternatively, the contact hole CTH may be formed by patterning the third dielectric film IF3, the first dummy pattern DP1, and the second dummy pattern DP2. Since the third mask pattern MP3 and the spacer SP are used as etching masks during the patterning process, the contact hole CTH may be formed in a self-aligned manner.

[0062] The contact hole CTH may be filled with a conductive material to form a contact CNT. The conductive material may include one or more of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metal (e.g., titanium, tantalum, tungsten, copper, or aluminum). The contact CNT may penetrate the second mask pattern MP2 and the target pattern TP and may be electrically connected to the second impurity region SD2. The spacer SP may separate the contact CNT from the bit line BL.

[0063] A data storage element DS may be formed on each contact CNT. The data storage element DS may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and a variable resistor including a phase change material. For example, the data storage element DS may be a capacitor.

[0064] Return to reference below Fig.14A , Fig. 14B and Fig. 14C Semiconductor devices according to example embodiments of the inventive concepts are described.

[0065] A device isolation layer ST defining active patterns ACT may be disposed on the substrate 100. Each active pattern ACT may extend in the third direction D3. The active patterns ACT may be spaced apart from each other in the third direction D3. The active patterns ACT may be arranged two-dimensionally.

[0066] A device isolation layer ST may be filled between the active patterns ACT.

[0067] Each active pattern ACT may include one first impurity region SD1 and a pair of second impurity regions SD2. The first impurity region SD1 may be placed between the pair of second impurity regions SD2. The first impurity region SD1 and the second impurity region SD2 may have the same conductivity type (eg, N type).

[0068] First trenches TR1 may be defined on the active pattern ACT and the device isolation layer ST. Each first trench TR1 may be defined between the first impurity region SD1 and the second impurity region SD2. The first trench TR1 may extend downward from the top surface of the active pattern ACT toward the bottom surface of the substrate 100.

[0069] The gate electrode GE may be disposed across the active pattern ACT and the device isolation layer ST. The gate electrode GE may be disposed in the first trench TR1. The gate electrodes GE may extend parallel to each other in the second direction D2. The gate electrode GE may have a top surface lower than a top surface of the active pattern ACT (e.g., a top surface of the first impurity region SD1 or the second impurity region SD2).

[0070] A gate dielectric layer GI may be inserted between the gate electrode GE and the active pattern ACT. A gate capping layer GP may be disposed on the gate electrode GE. The gate capping layer GP may cover the top surface of the gate electrode GE. The gate capping layer GP may have a top surface coplanar with the top surface of the active pattern ACT. The gate electrode GE, the gate dielectric layer GI, and the gate capping layer GP may constitute or form a gate structure GS.

[0071] The active pattern ACT, the gate structure GS, and the device isolation layer ST may constitute or form an active structure AS. A second trench TR2 may be defined on the active structure AS. The second trench TR2 may extend downward from the top surface of the active structure AS toward the bottom surface of the substrate 100. The second trench TR2 may define a column PL in the upper portion of the active structure AS. Each column PL may have an island shape vertically protruding from the bottom plate surface of the second trench TR2. Each column PL may include an upper portion of a second impurity region SD2. Each column PL may be disposed on the cell region CR of the substrate 100.

[0072] When viewed in a plan view, any two adjacent pillars PL may be spaced apart by a constant minimum distance. For example, a minimum distance L1 between a first pillar PL1 and a second pillar PL2 adjacent to each other in the fifth direction D5 may be substantially the same as a minimum distance L2 between a second pillar PL2 and a third pillar PL3 adjacent to each other in the fifth direction D5.

[0073] The target pattern TP and the second mask pattern MP2 may be sequentially disposed on the cell region CR of the substrate 100. The target pattern TP may vertically overlap the second mask pattern MP2.

[0074] The second dummy pattern DP2 and the first dummy pattern DP1 may be sequentially disposed on the dummy region DR of the substrate 100. The first dummy pattern DP1 may vertically overlap the second dummy pattern DP2.

[0075] A line structure LST extending in the first direction D1 may be provided on the active structure AS. The line structures LST may be spaced apart from each other in the second direction D2. When viewed in a plan view, the line structures LST may intersect the gate electrode GE. Spacers SP may be disposed on opposite sidewalls of each line structure LST. The second trench TR2 may be filled with a portion of the spacer SP.

[0076] Each of the line structures LST may include a conductive pattern CP, a bit line BL, and a third mask pattern MP3 that are sequentially stacked The bit line BL may be electrically connected to the first impurity region SD1 through the conductive pattern CP.

[0077] A third dielectric film IF3 may be disposed on the active structure AS. Each third dielectric film IF3 may be disposed between spacers SP. A contact CNT may be disposed to be connected to the second impurity region SD2. Each contact CNT may be disposed between the third dielectric films IF3. The spacer SP may separate the contact CNT from the bit line BL. A data storage element DS may be disposed on each contact CNT. For example, the data storage element DS may be a capacitor.

[0078] Fig.15A and Fig. 15B A plan view illustrating a semiconductor device according to an example embodiment of the inventive concept is shown.

[0079] For the sake of brevity, refer to Figures 1A to 14C Components that are substantially the same as those discussed in the present invention are assigned the same reference numerals, and their repeated descriptions are omitted.

[0080] Reference Fig.15A , each of the pillars PL1, PL2, and PL3 may have a rhombus shape when viewed in a plan view. The pillars PL1, PL2, and PL3 may include a first pillar PL1, a second pillar PL2, and a third pillar PL3. The first pillar PL1, the second pillar PL2, and the third pillar PL3 may have the same maximum width in the second direction D2. The first pillar PL1 may have a first width W1 indicating a maximum width in the first direction D1. The second pillar PL2 may have a second width W2 indicating a maximum width in the first direction D1. The third pillar PL3 may have a third width W3 indicating a maximum width in the first direction D1. The second width W2 may be greater than the first width W1. The third width W3 may be greater than the second width W2.

[0081] Reference Fig. 15B , each of the pillars PL1, PL2, and PL3 may have an elliptical shape when viewed in a plan view. The pillars PL1, PL2, and PL3 may include a first pillar PL1, a second pillar PL2, and a third pillar PL3. The first pillar PL1, the second pillar PL2, and the third pillar PL3 may have the same maximum width in the second direction D2. The first pillar PL1 may have a first width W1 indicating a maximum width in the first direction D1. The second pillar PL2 may have a second width W2 indicating a maximum width in the first direction D1. The third pillar PL3 may have a third width W3 indicating a maximum width in the first direction D1. The second width W2 may be greater than the first width W1. The third width W3 may be greater than the second width W2.

[0082] FIG. 16A to FIG. 21A A plan view illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts is shown. FIG. 16B to FIG. 21B Shown are FIG. 16A to FIG. 21A A cross-sectional view taken along line AA'. FIG. 16C to FIG. 21C Shown are FIG. 16A to FIG. 21A A cross-sectional view taken along line BB'.

[0083] For the sake of brevity, refer to Figures 1A to 14C Components that are substantially the same as those discussed in the present invention are assigned the same reference numerals, and their repeated descriptions are omitted.

[0084] Reference Fig.16A , Fig. 16B and Fig. 16C , and reference Figures 1A to 5C The same as those discussed above, the active structure AS, the target layer TL, the first mask layer ML1, the hard mask layer HM, the first insulating layer IL1, the second mask layer ML2, the first dielectric film IF1, and the second opening OP2 may be formed.

[0085] The second filling layer FL2 may be formed on the entire surface of the substrate 100. The second filling layer FL2 may fill the second opening OP2. The second filling layer FL2 may include a spin-on hard mask (SOH) layer.

[0086] A third insulating layer IL3, a fourth mask layer ML4 and a fourth insulating layer IL4 may be sequentially formed on the second filling layer FL2. The third insulating layer IL3 may include a silicon oxide layer. The fourth mask layer ML4 may include a spin-on hard mask (SOH) layer. The fourth insulating layer IL4 may include one or more of a silicon nitride layer and a silicon oxynitride layer.

[0087] The fourth mask layer ML4 and the fourth insulating layer IL4 may be patterned to form a third opening OP3. The third opening OP3 may extend in the second direction D2. For example, the third opening OP3 may extend in a direction parallel to the gate electrode GE.

[0088] Forming the third openings OP3 may include forming a second photoresist layer on the fourth insulating layer IL4 , patterning the second photoresist layer using a second photomask, and patterning the fourth mask layer ML4 and the fourth insulating layer IL4 using the patterned second photoresist layer as an etching mask.

[0089] The second dielectric film IF2 may be conformally formed on the entire surface of the substrate 100. The second dielectric film IF2 may include a silicon oxide layer. The second dielectric film IF2 may be formed by atomic layer deposition (ALD).

[0090] Reference Fig.17A , Fig. 17B and Fig. 17C , a third filling layer FL3 may be formed on the second dielectric film IF2. The third filling layer FL3 may fill the third opening OP3. The third filling layer FL3 may include a spin-on hard mask (SOH) layer.

[0091] After forming the third filling layer FL3, a second etch-back process may be performed. The second etch-back process may be performed so that the fourth insulating layer IL4 is removed, the portion of the second dielectric film IF2 located on the fourth insulating layer IL4 is removed, and the portion of the third filling layer FL3 located on the fourth insulating layer IL4 is removed. The remaining second dielectric film IF2 and the third filling layer FL3 may both selectively fill each third opening OP3. The remaining second dielectric film IF2 and the third filling layer FL3 may both be disposed in the fourth mask layer ML4. When viewed in a plan view, the fourth mask layer ML4, the second dielectric film IF2, and the third filling layer FL3 may be exposed on the entire surface of the substrate 100.

[0092] Reference Fig.18A , Fig.18B and Fig.18C , a second etching process may be performed to pattern the second mask layer ML2. The second etching process may include removing the second dielectric film IF2 between the fourth mask layer ML4 and the third filling layer FL3, and patterning the third insulating layer IL3, the second filling layer FL2, and the second mask layer ML2 using the fourth mask layer ML4 and the third filling layer FL3 as etching masks. A removal process may be performed to remove the fourth mask layer ML4, the third filling layer FL3, the second dielectric film IF2, the third insulating layer IL3, and the second filling layer FL2 remaining after the second etching process.

[0093] The second etching process may form fourth openings OP4 in the second mask layer ML2. The fourth openings OP4 may extend in the second direction D2. The fourth openings OP4 may partially overlap with the second openings OP2.

[0094] The second etching process may cause the second mask layer ML2 to be patterned to form first mask patterns MP1. Each first mask pattern MP1 may have a parallelogram shape when viewed in a plan view. Each first mask pattern MP1 may be defined by second and fourth openings OP2 and OP4.

[0095] Reference Fig.19A , Fig.19B and Fig.19C, a photoresist pattern PR may be formed on the dummy region DR of the substrate 100. For example, the formation of the photoresist pattern PR may include forming a third photoresist layer on the entire surface of the substrate 100 and patterning the third photoresist layer using a third photomask. The photoresist pattern PR may fill a portion OP2P of the second opening OP2 on the dummy region DR of the substrate 100. The photoresist pattern PR may also fill a portion OP4P of the fourth opening OP4 on the dummy region DR of the substrate 100. The photoresist pattern PR may connect the first mask pattern MP1 to each other on the dummy region DR.

[0096] Reference Fig. 20A , Fig. 20B and Fig. 20C , a third etching process may be performed to form a second trench TR2. The third etching process may include patterning the first insulating layer IL1 using the first mask pattern MP1 as an etching mask, patterning the hard mask layer HM using the patterned first insulating layer IL1 as an etching mask, patterning the first mask layer ML1 and the target layer TL using the patterned hard mask layer HM as etching masks, and patterning the active structure AS using the patterned first mask layer ML1 and the patterned target layer TL as etching masks. A removal process may be performed to remove the photoresist pattern PR, the first mask pattern MP1, the first dielectric film IF1, the first insulating layer IL1, and the hard mask layer HM remaining after the third etching process. Patterning the first insulating layer IL1 using the first mask pattern MP1 as an etching mask may include patterning the first insulating layer IL1 using the second opening OP2 and the fourth opening OP4.

[0097] The patterning of the first mask layer ML1 may form a second mask pattern MP2 on the cell region CR of the substrate 100. Each second mask pattern MP2 may include a first sidewall MP21 extending in the second direction D2 and a second sidewall MP22 connecting the first sidewalls MP21 to each other. The second sidewall MP22 may be curved when viewed in a plan view. Although each of the first mask patterns MP1 has a parallelogram shape, the pattern shapes of multiple layers may be changed while sequentially etching during the third etching process. Finally, each second mask pattern MP2 may include a curved second sidewall MP22. The second mask patterns MP2 may be spaced apart from each other in the fourth direction D4. The second mask patterns MP2 may be spaced apart from each other in the second direction D2. A single second mask pattern MP2 may vertically overlap two second impurity regions SD2 adjacent to each other in the second direction D2.

[0098] The patterning of the target layer TL may form a target pattern TP on the cell region CR of the substrate 100. The target pattern TP may vertically overlap the second mask pattern MP2. For example, the target pattern TP and the second mask pattern MP2 may have the same planar shape and arrangement.

[0099] The patterning of the active structure AS may form a pillar PL on the cell region CR of the substrate 100, and also form a second trench TR2 between the pillars PL. For example, the second trench TR2 may define the pillar PL of the active structure AS. The active structure AS may have a portion at a level higher than the bottom plate surface of the second trench TR2, and the portion of the active structure AS may be defined as the pillar PL. The second trench TR2 may expose the first impurity region SD1. Each pillar PL may include an upper device isolation layer UST, an upper second impurity region USD2, and an upper gate capping layer UGP. The upper device isolation layer UST may be a portion of the device isolation layer ST, which is located at a level higher than the bottom plate surface of the second trench TR2. The upper second impurity region USD2 may be a portion of the second impurity region SD2, which is located at a level higher than the bottom plate surface of the second trench TR2. The upper gate capping layer UGP may be a portion of the gate capping layer GP, which is located at a level higher than the bottom plate surface of the second trench TR2.

[0100] When viewed in a plan view, each pillar PL may include a first sidewall PLW1 extending in the second direction D2 and a second sidewall PLW2 connecting the first sidewalls PLW1 to each other. The second sidewall PLW2 may be curved. The pillars PL may be spaced apart from each other in the fourth direction D4. The pillars PL may also be spaced apart from each other in the second direction D2.

[0101] The patterning of the first mask layer ML1 may form a first dummy pattern DP1 on the dummy region DR of the substrate 100. The first dummy pattern DP1 may include a portion extending in the first direction D1 and other portions extending in the second direction D2.

[0102] The patterning of the target layer TL may form a second dummy pattern DP2 on the dummy region DR of the substrate 100. The second dummy pattern DP2 may vertically overlap the first dummy pattern DP1. For example, the first dummy pattern DP1 and the second dummy pattern DP2 may have the same planar shape.

[0103] Reference Fig.21A , Fig. 21B and Fig. 21C , you can do something like FIG. 11A to FIG. 12C, to form a line structure LST extending in the first direction D1. The line structures LST may be spaced apart from each other in the second direction D2. Each line structure LST may include a third mask pattern MP3, a bit line BL, and a conductive pattern CP. The conductivity of the conductive pattern CP may be greater than the conductivity of the second mask pattern MP2. When viewed in a plan view, the bit line BL may extend while crossing the gate electrode GE. The conductive pattern CP may be connected to the first impurity region SD1. For example, the bit line BL may be electrically connected to the first impurity region SD1 through the conductive pattern CP. The second mask pattern MP2 and the target pattern TP covering the second impurity region SD2 may separate the conductive pattern CP from the second impurity region SD2.

[0104] You can do something like Fig.13A , Fig. 13B and Fig. 13C , to form spacers SP covering opposite sidewalls of each line structure LST. The second trench TR2 may be filled with portions of the spacers SP.

[0105] You can do something like Fig.14A , Fig. 14B and Fig. 14C The processes discussed in the above are performed to form a third dielectric film IF3, a contact hole CTH, a contact CNT, and a data storage element DS. The contact CNT may penetrate the second mask pattern MP2 and the target pattern TP and may be electrically connected to the second impurity region SD2. The spacer SP may separate the contact CNT from the bit line BL. The data storage element DS may be formed on each contact CNT.

[0106] According to the inventive concept, the pillars may be formed using line patterning such that a constant minimum distance may be provided between any two adjacent pillars.

[0107] Although the present invention has been described in conjunction with the embodiments of the inventive concept shown in the drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential features of the inventive concept. It is apparent to those skilled in the art that various substitutions, modifications and changes may be made without departing from the scope and spirit of the inventive concept.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: include: forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure spanning the active patterns and extending along a first direction; forming a first mask pattern on the active structure; as well as patterning the active structure to form trenches by using the first mask pattern as an etching mask, The forming of the first mask pattern comprises: forming a first mask layer after forming the gate structure; forming a plurality of first openings extending in a second direction intersecting the first direction in the first mask layer; and A plurality of second openings extending in a third direction intersecting the first direction and the second direction are formed in the first mask layer.

2. The method according to claim 1, wherein each of the plurality of active patterns include: a first impurity region; as well as a plurality of second impurity regions spaced apart from each other across the first impurity region, wherein forming the trench comprises forming a plurality of pillars in an upper portion of the active structure, the pillars being defined by the trench, Each of the pillars includes an upper portion of the second impurity region. The method according to claim 2 , wherein each of the plurality of pillars has an elliptical shape in a plan view. The method according to claim 2 , wherein each of the plurality of pillars has a diamond shape in a plan view.

5. The method according to claim 1, further comprising forming a second mask layer between the active structure and the first mask pattern, Wherein forming the trench includes patterning the second mask layer using the first mask pattern as an etching mask.

6. The method according to claim 1, wherein forming the plurality of first openings include: forming a second mask layer on the first mask layer; patterning the second mask layer to form a third opening extending along the second direction; conformally forming a first dielectric film on the second mask layer; forming a first filling layer filling the third opening; removing the first dielectric film between the first filling layer and the second mask layer; as well as The first mask layer is patterned using the first filling layer and the second mask layer as an etching mask.

7. The method according to claim 6, wherein the plurality of second openings are formed include: forming a second filling layer filling the plurality of first openings; forming a third mask layer on the second filling layer; patterning the third mask layer to form a fourth opening extending along the third direction; conformally forming a second dielectric film on the third mask layer; forming a third filling layer filling the fourth opening; removing the second dielectric film between the third filling layer and the third mask layer; as well as The second mask layer, the second filling layer, and the first mask layer are patterned using the third filling layer and the third mask layer as etching masks.

8. A method for manufacturing a semiconductor device, the method include: forming an active structure, the active structure comprising a plurality of active patterns, a device isolation layer between the active patterns, and a gate structure crossing the active patterns and extending along a first direction; forming a first mask pattern on the active structure; as well as patterning the active structure to form trenches by using the first mask pattern as an etching mask, The forming of the first mask pattern comprises: forming a first mask layer after forming the gate structure; forming a plurality of first openings extending in a second direction intersecting the first direction in the first mask layer; and A plurality of second openings extending along the first direction are formed in the first mask layer.

9. The method according to claim 8, wherein each of the plurality of active patterns include: a first impurity region; as well as a plurality of second impurity regions spaced apart from each other across the first impurity region, Wherein forming the trench includes forming a plurality of pillars in an upper portion of the active structure, the pillars being defined by the trench.

10. The method according to claim 9, further comprising: include: forming a conductive pattern electrically connected to the first impurity region; as well as forming a bit line electrically connected to the conductive pattern, The bit line extends in a third direction intersecting the first direction.

11. The method according to claim 9, further comprising: include: forming a plurality of contacts electrically connected to the second impurity region; as well as A plurality of data storage elements are formed in connection with the plurality of contacts.

12. The method according to claim 10, further comprising forming a second mask layer between the active structure and the first mask pattern, Wherein forming the trench includes patterning the second mask layer using the first mask pattern as an etching mask to form a second mask pattern. The method of claim 12 , wherein the second mask pattern has a parallelogram shape in a plan view. The method according to claim 12 , wherein the conductivity of the conductive pattern is greater than the conductivity of the second mask pattern.

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