A device and method for adjusting duty cycle of a resonance system

Abstract

The present invention discloses a device and method for adjusting the duty cycle of a resonant system, the device comprising a resonant system and a duty cycle adjusting device connected to the resonant system, the resonant system comprising a clock driver, a first capacitor connected to the clock driver, and an inductor connected to the first capacitor, the other end of the inductor being connected to the middle point of the decoupling capacitor and forming a first middle node; the duty cycle adjusting device is used to detect the duty cycle of a clock signal output by the clock driver and / or detect the voltage value of the first middle node, and adjust the duty cycle of the clock signal input to the clock driver according to the duty cycle output by the clock driver and / or the voltage value of the first middle node. The present invention has a simple structure, can accurately adjust the duty cycle of the resonant system, and ensure the integrity of the clock signal waveform to the greatest extent.

Description

Technical Field

[0001] The present invention relates to a duty cycle detection and adjustment technology, and in particular to a duty cycle adjustment device and method for a resonant system. Background Art

[0002] With the development of integrated circuit technology, the scale of chips is getting larger and larger, and the clock mesh is becoming larger and larger, which will bring problems of power consumption and clock skew. The LC resonant clock generates and distributes clock signals through the LC resonant circuit, which can better solve the power consumption, clock skew and jitter problems of large-scale integrated circuit chips (such as processors, GPUs (Graphics Processing Units), FPGAs (Field-Programmable Gate Arrays), and TPUs (Tensorprocessing units)). Among them, the resonant frequency of the LC resonant clock is f = 1 / (2*π*sqrt(LC)). Among them, C is the equivalent parasitic capacitance of the clock mesh, and L is the inductance of the resonant network.

[0003] This application requires an AC virtual ground point established by a decoupling capacitor. In order to ensure the waveform integrity of the clock signal in the LC resonant clock, the theoretical value of the DC voltage of the virtual ground point is usually 1 / 2VDD (VDD is the supply voltage).

[0004] However, due to the existence of parasitic capacitance and resistance, and the unequal upper and lower driving capabilities of the clock driver, the duty cycle of the clock signal in the LC resonant clock (the ratio of the high or low level of the signal in one cycle; in this case, the correct duty cycle is 50%) deviates, and the duty cycle deviation causes the voltage of the virtual ground point to deviate from 1 / 2VDD, and the reverse effect of the voltage deviation of the virtual ground point from 1 / 2VDD will cause the clock signal waveform in the LC resonant clock to be distorted. Figure 1a The voltage deviation of the virtual ground point causes Figure 1b The distorted clock signal waveform.

[0005] In order to solve the problem of clock signal waveform distortion caused by the deviation of the duty cycle and virtual ground voltage, it is necessary to provide a technology for correcting and adjusting the duty cycle of the resonant clock. Summary of the invention

[0006] The purpose of the present invention is to overcome the defects of the prior art and provide a device and method for adjusting the duty cycle of a resonant system which has a simple structure and can effectively ensure the integrity of a clock signal waveform.

[0007] To achieve the above object, the present invention proposes the following technical solution: a duty cycle adjustment device for a resonance system, comprising a resonance system and a duty cycle adjustment device,

[0008] The resonant system comprises a clock driver, a first capacitor and an inductor, wherein one end of the clock driver is connected to the clock signal and the other end is connected to the inductor; the first capacitor is connected between the clock driver and the inductor and is used to charge and discharge at the rising edge and falling edge of the clock signal respectively; the other end of the inductor is connected to the power supply voltage and forms a first intermediate node;

[0009] The duty cycle adjustment device is connected to the resonant system, and is used to detect the duty cycle of the clock signal output by the clock driver and / or detect the voltage of the first intermediate node, and adjust the duty cycle of the clock signal input to the clock driver according to the duty cycle output by the clock driver and / or the voltage value of the first intermediate node.

[0010] Preferably, one end of the first capacitor is connected between the clock driver and the inductor to form a second intermediate node, and the other end is grounded; the first capacitor is the sum of the parasitic capacitance and the load capacitance of the clock grid.

[0011] Preferably, the resonant system also includes a second capacitor and a third capacitor, one end of the second capacitor is connected to the supply voltage, and the other end is connected in series with the third capacitor, and the other end of the third capacitor is grounded; the other end of the inductor is connected between the second capacitor and the third capacitor to form the first intermediate node; the second and third capacitors are decoupling capacitors.

[0012] Preferably, the duty cycle adjustment device includes a connected detection circuit and a duty cycle adjustment circuit, the detection circuit is used to detect the duty cycle of the clock signal output by the clock driver and / or detect the voltage value of the first intermediate node; the duty cycle adjustment circuit is used to adjust the duty cycle of the clock signal input to the clock driver according to the duty cycle of the clock signal output by the clock driver and / or the voltage value of the first intermediate node.

[0013] Preferably, the detection circuit comprises a voltage detection circuit, one end of the voltage detection circuit is connected to the first intermediate node, and the other end is connected to the duty cycle adjustment circuit, for detecting the voltage of the first intermediate node and outputting the voltage value to the duty cycle adjustment circuit.

[0014] Preferably, the detection circuit includes a duty cycle detection circuit, one end of the duty cycle detection circuit is connected to the second intermediate node, and the other end is connected to the duty cycle adjustment circuit, for detecting the duty cycle of the clock signal at the second intermediate node and outputting the duty cycle to the duty cycle adjustment circuit.

[0015] Preferably, the detection circuit includes a voltage detection circuit and a duty cycle detection circuit.

[0016] The voltage detection circuit has one end connected to the first intermediate node and the other end connected to the duty cycle adjustment circuit, and is used to detect the voltage of the first intermediate node and output the voltage value to the duty cycle adjustment circuit;

[0017] The duty cycle detection circuit is connected to the second intermediate node at one end and to the duty cycle adjustment circuit at the other end, and is used to detect the duty cycle of the clock signal at the second intermediate node and output the duty cycle to the duty cycle adjustment circuit.

[0018] Preferably, the duty cycle adjustment circuit comprises an adjustment judgment circuit and a duty cycle correction circuit connected to each other, wherein:

[0019] The adjustment judgment circuit is connected between the detection circuit and the duty cycle correction circuit, and is used to judge whether to adjust the duty cycle of the clock signal input to the clock driver according to the duty cycle output by the detection circuit and / or the voltage value of the first intermediate node, and if so, output the duty cycle correction value to the duty cycle correction circuit;

[0020] The duty cycle correction circuit is connected between the clock signal and the clock driver, and is used to adjust the duty cycle of the clock signal according to the duty cycle correction value.

[0021] Preferably, the voltage detection circuit uses an analog digital converter ADC (Analog Digital Converter).

[0022] Preferably, the duty cycle detection circuit uses a time digital converter (TDC).

[0023] Preferably, the adjustment judgment circuit uses a digital control logic unit or a customized circuit (Customized Circuit) implemented based on a hardware description language.

[0024] Preferably, the resonant system further comprises a controllable switch circuit connected in series between the clock driver and the inductor.

[0025] Preferably, the duty cycle correction value is expressed in binary, wherein the first digit of the binary is a sign bit indicating a high / low level.

[0026] Preferably, the duty cycle adjustment device adjusts the duty cycle of the clock signal, but does not adjust the frequency parameter of the clock signal.

[0027] The present invention also provides another technical solution: a method for adjusting the duty cycle of a resonant system, the resonant system comprising a clock driver, a first capacitor and an inductor, one end of the clock driver being connected to a clock signal and the other end being connected to the inductor; the first capacitor being connected between the clock driver and the inductor and being charged and discharged at the rising edge and falling edge of the clock signal respectively; the other end of the inductor being connected to a power supply voltage and forming a first intermediate node, the method for adjusting the duty cycle comprising:

[0028] S1, detecting a duty cycle of a clock signal output by a clock driver and / or detecting a voltage of the first intermediate node;

[0029] S2, adjusting the duty cycle of the clock signal input to the clock driver according to the duty cycle output by the clock driver and / or the voltage value of the first intermediate node.

[0030] Preferably, in S2, the step of adjusting the duty cycle of the clock signal input to the clock driver according to the duty cycle output by the clock driver comprises:

[0031] S21, detecting a duty cycle of a clock signal output by a clock driver;

[0032] S22, judging whether to adjust the duty cycle of the clock signal input by the clock driver according to the duty cycle, and if so, generating a duty cycle correction value, and entering S23;

[0033] S23, adjusting the duty cycle of the clock signal input by the clock driver according to the duty cycle correction value.

[0034] Preferably, in S2, the step of adjusting the duty cycle of the clock signal input to the clock driver according to the voltage value of the first intermediate node includes:

[0035] S21′, detecting a voltage value of a first intermediate node;

[0036] S22′, judging whether to adjust the duty cycle of the clock signal input by the clock driver according to the voltage, if so, generating a duty cycle correction value, and entering S23′;

[0037] S23', adjusting the duty cycle of the clock signal input by the clock driver according to the duty cycle correction value.

[0038] Preferably, in S2, the step of adjusting the duty cycle of the clock signal input to the clock driver according to the duty cycle output by the detection circuit and the voltage value of the first intermediate node includes:

[0039] S21″, detecting a duty cycle of a clock signal output by a clock driver and a voltage value of a first intermediate node;

[0040] S22″, judging whether to adjust the duty cycle of the clock signal input by the clock driver according to the duty cycle and the voltage value, and if so, generating a duty cycle correction value and entering S23″;

[0041] S23″, adjusting the duty cycle of the clock signal input by the clock driver according to the duty cycle correction value.

[0042] The beneficial effect of the present invention is: by detecting the voltage value of the virtual ground point (i.e., the defined first intermediate node) in the resonant system or the duty cycle of the clock signal output by the clock driver, or by comprehensively considering the two parameters of the voltage and the duty cycle, the duty cycle of the clock signal initially input to the system is accurately adjusted to ensure the integrity of the clock signal waveform to the greatest extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1a It is a schematic diagram of the voltage at the virtual ground point in the existing resonant clock;

[0044] Figure 1b It is a schematic diagram of the clock signal waveform in the existing resonant clock;

[0045] Figure 2a is a schematic structural diagram of a resonance system according to an embodiment of the present invention;

[0046] Figure 2b is a clock distribution grid (Clock Mesh) of an embodiment of the present invention;

[0047] Figure 3 is a schematic structural diagram of a resonance system according to another embodiment of the present invention;

[0048] Figure 4 It is a schematic diagram of the structure of the resonant system in an embodiment of the present invention having parasitic capacitance and resistance;

[0049] Figure 5 is a schematic structural diagram of a duty cycle adjustment device for a resonant system according to embodiment 1 of the present invention;

[0050] Figure 6 is a schematic structural diagram of a duty cycle adjustment device for a resonant system according to embodiment 2 of the present invention;

[0051] Figure 7 is a schematic structural diagram of a duty cycle adjustment device for a resonance system according to a third embodiment of the present invention;

[0052] Figure 8 It is a flow chart of the duty cycle adjustment method of the resonant system of the present invention. DETAILED DESCRIPTION

[0053] The technical solutions of the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention.

[0054] Combined with Figure 2~ Figure 7 As shown, a duty cycle adjustment device for a resonant system disclosed in an embodiment of the present invention includes: a resonant system and a duty cycle adjustment device, wherein the duty cycle adjustment device is connected to the resonant system, and is used to directly or indirectly detect the duty cycle of a clock signal in the resonant system, so as to accurately adjust the duty cycle of the clock signal initially input into the resonant system to ensure the integrity of the clock signal waveform.

[0055] Specifically, in this embodiment, combined with Figure 2a and Figure 2b As shown, the resonant system includes a clock driver, a first capacitor, an inductor, a second capacitor and a third capacitor, wherein one end of the clock driver is connected to the input clock signal (CLK_IN), and the other end is connected in series with one end of the inductor; the first capacitor is connected between the clock driver and the inductor, one end of which is connected to the node between the clock driver and the inductor. For the convenience of description, the node is defined as the second intermediate node Vb, and the other end is grounded; the other end of the inductor is connected between the second capacitor and the third capacitor, also forming a connected intermediate node, and for the convenience of description, the node is defined as the first intermediate node Va; the second capacitor and the third capacitor are connected in series, wherein one end of the second capacitor is connected to the power supply voltage VDD, and the other end is connected in series with the third capacitor; the other end of the third capacitor is grounded. In this embodiment, the first capacitor is the parasitic capacitance (C p ) and load capacitance (C inv ), such as Figure 2b As shown, the inductor is a spiral inductor, and the second and third capacitors are both decoupling capacitors.

[0056] In this embodiment, the first capacitor is discharged at the falling edge (Falling Edge) of the clock signal and is charged at the rising edge (Rising Edge) of the clock signal, and during the discharging process, part of the charge is stored in the inductor, so that during the charging process, part of the charge required to be charged in the capacitor can be obtained from the inductor, that is, the charge in the inductor is charged back into the capacitor, thereby reducing the power consumption of the clock driver and the requirements for the driving capability of the clock driver.

[0057] Furthermore, if Figure 3 As shown, the above resonant system may also include a controllable switch circuit, which is connected in series between the clock driver and the inductor, specifically between the second intermediate node Vb and the inductor, to control the on and off of the resonant system. In this embodiment, the controllable switch circuit uses a transmission gate.

[0058] Of course, the present invention is not only applicable to the resonant system described above, but other resonant systems that can realize the charging and discharging of the first capacitor are also applicable to the present invention.

[0059] The duty cycle adjustment device is used to detect the duty cycle of the clock signal of the second intermediate node Vb and / or detect the voltage value of the above-mentioned first intermediate node Va, and adjust the duty cycle of the clock signal CLK_IN input by the clock driver according to the duty cycle of the clock signal of the second intermediate node Vb and / or the voltage value of the first intermediate node Va.

[0060] The following specifically describes the principle of adjusting the duty cycle of the clock signal CLK_IN by the duty cycle adjusting device of the present invention in detail with three embodiments.

[0061] Example 1

[0062] like Figure 5 As shown, the duty cycle adjustment device disclosed in this embodiment 1 includes a voltage detection circuit, an adjustment judgment circuit and a duty cycle correction circuit, wherein one end of the voltage detection circuit is connected to the first intermediate node Va, and the other end is connected to the adjustment judgment circuit, for detecting the voltage value of the node Va, and outputting the detected voltage value to the adjustment judgment circuit. Theoretically, the voltage value of the node Va should be half of the power supply voltage, that is, VDD / 2, but as described in the background technology, if Figure 4 As shown, since the node Va has different parasitic capacitance and resistance to the power supply voltage and the ground, the voltage value of the node Va will not be VDD / 2. If the power supply voltage is 1V, the theoretical voltage value of the node Va is 0.5V, and the actual voltage value of the node Va is 0.52V, that is, higher than the theoretical node voltage value, the voltage detection circuit will output the detected actual voltage value of the node Va, 0.52V, to the adjustment judgment circuit. In this embodiment, the voltage value detected by the voltage detection circuit at the node Va is an analog quantity, and the analog quantity needs to be converted into a digital quantity, so the voltage detection circuit here uses an analog-to-digital converter ADC, that is, the detected analog voltage value is converted into a digital voltage value for output.

[0063] One end of the adjustment judgment circuit is connected to the voltage detection circuit, and the other end is connected to the duty cycle correction circuit, which is used to receive the digital voltage value transmitted by the voltage detection circuit, and judge whether to adjust the duty cycle of the clock signal CLK_IN according to the digital voltage value. Specifically, the adjustment judgment circuit has a voltage reference value (that is, it is or is close to the theoretical voltage value of the node Va). When the digital quantity corresponding to the voltage value output by the voltage detection circuit is received, the digital quantity is matched with its own set reference value. If it is not equal to the voltage reference value, that is, higher or lower than the voltage reference value, it is judged that the duty cycle of the clock signal CLK_IN needs to be adjusted, and the duty cycle correction value is output to the duty cycle correction circuit accordingly. Specifically, if the actual voltage value of the node Va is higher than the voltage reference value, the low level ratio needs to be increased, that is, the duty cycle is reduced; if the actual voltage value of the node Va is lower than the voltage reference value, the high level ratio needs to be increased, that is, the duty cycle is increased. In this embodiment, the duty cycle correction value can be represented by 4-bit binary, where 0000 represents the initial state, that is, the state where the duty cycle does not need to be adjusted; 0001 represents an increase in the high level by one delay unit time, and the corresponding low level is reduced by one delay unit time; 0010 represents an increase in the high level by two delay unit times, and the corresponding low level is reduced by two delay unit times; 1001 represents an increase in the low level by one delay unit time, and the corresponding high level is reduced by one delay unit time; 1010 represents an increase in the low level by two delay unit times, and the corresponding high level is reduced by one delay unit time. Among them, the first bit of the binary here is the sign bit that identifies the high / low level, that is, 0 represents an increase in the high level, and 1 represents an increase in the low level. Of course, the duty cycle correction value is not limited to the binary representation here, and can also be other bases, and the number of digits here is not limited, and it can be configured according to actual conditions. In this embodiment, the adjustment judgment circuit adopts a digital control logic unit, which can be implemented based on a hardware description language, or a custom circuit can be used to implement the duty cycle adjustment.

[0064] In addition, it should be noted that the execution cycle of the adjustment judgment circuit here is configurable, that is, the voltage detection circuit does not necessarily transmit a voltage value and the adjustment judgment circuit immediately makes a judgment. It can also be that the voltage detection circuit transmits multiple voltage values, and after reaching the execution cycle of the adjustment judgment circuit, the adjustment judgment circuit takes the average or median of these voltage values ​​and compares them with the set reference value.

[0065] The duty cycle correction circuit is connected in series between the clock signal CLK_IN and the clock driver, and is also connected to the adjustment judgment circuit, which is used to receive the duty cycle correction value output by the adjustment judgment circuit, and adjust the duty cycle of the clock signal CLK_IN according to the duty cycle correction value. Specifically, in this embodiment, after receiving the duty cycle correction value, the duty cycle correction circuit determines whether to adjust the low level or high level of the clock signal according to the first digit of the correction value, and then adjusts the corresponding low level or high level of the clock signal according to the specific value of the correction value. Here, the duty cycle correction circuit converts the duty cycle correction value of the digital quantity into the delay time of the high level or low level of the clock signal, so as to achieve the purpose of adjusting the duty cycle of the clock signal CLK_IN. It should be noted that the duty cycle correction circuit here only changes the duty cycle of the clock signal CLK_IN, but does not change the frequency of the clock.

[0066] Example 2

[0067] like Figure 6 As shown, the duty cycle adjustment device disclosed in this embodiment 2 includes a duty cycle detection circuit, an adjustment judgment circuit and a duty cycle correction circuit, wherein one end of the duty cycle detection circuit is connected to the second intermediate node Vb, and the other end is connected to the adjustment judgment circuit, for detecting the duty cycle of the clock signal at the node Vb, and outputting the detected duty cycle to the adjustment judgment circuit. Theoretically, the duty cycle of the clock signal at the node Vb should be 1 / 2, but as described in the background technology, Figure 4 As shown, due to the parasitic capacitance and resistance of the node Vb, the unequal up and down driving capabilities of the clock driver, etc., the duty cycle of the clock signal of the node Vb will deviate. If the duty cycle of the actual clock signal of the node Vb is 0.6, that is, higher than the theoretical duty cycle, the duty cycle detection circuit will output the actual duty cycle value of 0.6 detected at the node Vb to the adjustment judgment circuit. In this embodiment, the duty cycle detection circuit is a square wave signal at the node Vb, so the duty cycle detection circuit here can select a time-to-digital converter TDC, that is, directly output the detected duty cycle value in the form of a digital quantity.

[0068] One end of the adjustment judgment circuit is connected to the duty cycle detection circuit, and the other end is connected to the duty cycle correction circuit, which is used to receive the duty cycle value transmitted by the duty cycle detection circuit, and judge whether to adjust the duty cycle of the clock signal CLK_IN according to the duty cycle value. Specifically, the adjustment judgment circuit has a duty cycle reference value (that is, it is or is close to the theoretical duty cycle value of the node Vb). After receiving the duty cycle value transmitted by the duty cycle detection circuit, the duty cycle value is matched with the duty cycle reference value in itself. If it is not equal to the duty cycle reference value, that is, it is higher or lower than the duty cycle reference value, it is judged that the duty cycle of the clock signal CLK_IN needs to be adjusted, and the duty cycle correction value is output to the duty cycle correction circuit accordingly. Specifically, if the actual duty cycle value of the node Vb is higher than the duty cycle reference value, the duty cycle of the low level needs to be increased; if the actual duty cycle value of the node Vb is lower than the voltage reference value, the duty cycle of the high level needs to be increased. In this embodiment, the duty cycle correction value can be represented by 4-bit binary, where 0000 represents the initial state, that is, the state where the duty cycle does not need to be adjusted; 0001 represents an increase in the high level by one delay unit time, and the corresponding low level is reduced by one delay unit time; 0010 represents an increase in the high level by two delay unit times, and the corresponding low level is reduced by two delay unit times; 1001 represents an increase in the low level by one delay unit time, and the corresponding high level is reduced by one delay unit time; 1010 represents an increase in the low level by two delay unit times, and the corresponding high level is reduced by one delay unit time. Among them, the first bit of the binary here is the sign bit that identifies the high / low level, that is, 0 represents an increase in the high level, and 1 represents an increase in the low level. Of course, the duty cycle correction value is not limited to the binary representation here, and can also be other bases, and the number of digits here is not limited, and it can be configured according to actual conditions. In this embodiment, the adjustment judgment circuit adopts a digital control logic unit, which can be implemented based on a hardware description language, or a custom circuit can be used to implement the duty cycle adjustment. As in the above-mentioned embodiment 1, the duty cycle correction circuit is connected in series between the clock signal CLK_IN and the clock driver, and is also connected to the adjustment judgment circuit, which is used to receive the duty cycle correction value output by the adjustment judgment circuit, and adjust the duty cycle of the clock signal CLK_IN according to the duty cycle correction value. Specifically, in this embodiment, after receiving the duty cycle correction value, the duty cycle correction circuit determines whether to adjust the low level or high level of the clock signal according to the first digit of the correction value, and then adjusts the corresponding low level or high level of the clock signal according to the specific value of the correction value. Here, the duty cycle correction circuit converts the duty cycle correction value of the digital quantity into the delay time of the high level or low level of the clock signal, so as to achieve the purpose of adjusting the duty cycle of the clock signal CLK_IN. It should be noted that the duty cycle correction circuit here only changes the duty cycle of the clock signal CLK_IN, but does not change the frequency of the clock.

[0069] Example 3

[0070] like Figure 7 As shown, the duty cycle adjustment device disclosed in this embodiment 3 includes a voltage detection circuit, a duty cycle detection circuit, an adjustment judgment circuit and a duty cycle correction circuit, wherein one end of the voltage detection circuit is connected to the above-mentioned first intermediate node Va, and the other end is connected to the adjustment judgment circuit, for detecting the voltage value of the node Va, and outputting the detected voltage value to the adjustment judgment circuit; one end of the duty cycle detection circuit is connected to the above-mentioned second intermediate node Vb, and the other end is connected to the adjustment judgment circuit, for detecting the duty cycle of the clock signal at the node Vb, and outputting the detected duty cycle to the adjustment judgment circuit. The voltage detection circuit and the duty cycle detection circuit here are respectively the same in principle and structure as the voltage detection circuit in embodiment 1 and the duty cycle detection circuit in embodiment 2, and can refer to the above description, which will not be repeated here.

[0071] The adjustment judgment circuit is connected to both the duty cycle detection circuit and the voltage detection circuit, and is connected to the duty cycle correction circuit, and is used to receive the duty cycle value transmitted by the duty cycle detection circuit and the voltage value transmitted by the voltage detection circuit, and comprehensively judge whether to adjust the duty cycle of the clock signal CLK_IN based on the duty cycle value and the voltage value. If it is determined that the duty cycle of the clock signal CLK_IN needs to be adjusted, the corresponding duty cycle correction value is output to the duty cycle correction circuit. In this embodiment, the adjustment judgment circuit adopts a digital control logic unit, which can be written and implemented based on a hardware description language, or a custom circuit can be used to implement the duty cycle adjustment. As in the above-mentioned embodiments 1 and 2, the duty cycle correction circuit is connected in series between the clock signal CLK_IN and the clock driver, and is also connected to the adjustment judgment circuit, which is used to receive the duty cycle correction value output by the adjustment judgment circuit, and adjust the duty cycle of the clock signal CLK_IN according to the duty cycle correction value. Specifically, in this embodiment, after receiving the duty cycle correction value, the duty cycle correction circuit determines whether to adjust the low level or high level of the clock signal according to the first digit of the correction value, and then adjusts the corresponding low level or high level of the clock signal according to the specific value of the correction value. Here, the duty cycle correction circuit converts the duty cycle correction value of the digital quantity into the delay time of the high level or low level of the clock signal, so as to achieve the purpose of adjusting the duty cycle of the clock signal CLK_IN. It should be noted that the duty cycle correction circuit here only changes the duty cycle of the clock signal CLK_IN, but does not change the frequency of the clock.

[0072] The embodiment of the present invention discloses a method for adjusting the duty cycle of a resonant system, wherein the resonant system here can refer to the above description, or can be other existing resonant systems, such as Figure 8 As shown, the duty cycle adjustment method includes the following steps:

[0073] S1, detecting the duty cycle of the clock signal of the second intermediate node Vb and / or detecting the voltage value of the first intermediate node Va.

[0074] Specifically, the embodiments of the present invention can simply detect the duty cycle of the clock signal of the second intermediate node Vb, or simply detect the voltage value of the first intermediate node Va, or detect the duty cycle of the clock signal of the second intermediate node Vb and the voltage value of the first intermediate node Va. The specific detection methods can refer to the above description of the voltage detection circuit and the duty cycle detection circuit, which will not be repeated here.

[0075] S2 , adjusting the duty cycle of the clock signal CLK_IN input by the clock driver according to the duty cycle of the clock signal at the second intermediate node Vb and / or the voltage at the first intermediate node Va.

[0076] Specifically, corresponding to step S1, if, what is detected in S1 is the duty cycle of the clock signal of the second intermediate node Vb, then step S2 adjusts the duty cycle of the clock signal CLK_IN input by the clock driver according to the duty cycle of the clock signal of the second intermediate node Vb. For specific detection and adjustment, please refer to the description in the above embodiment 2; similarly, if, what is detected in S1 is the voltage value of the first intermediate node Va, then step S2 adjusts the duty cycle of the clock signal CLK_IN input by the clock driver according to the voltage value of the first intermediate node Va. For specific detection and adjustment, please refer to the description in the above embodiment 1; if, what is detected in S1 is the voltage value of the first intermediate node Va and the duty cycle of the clock signal of the second intermediate node Vb, then step S2 adjusts the duty cycle of the clock signal CLK_IN input by the clock driver according to the voltage value of the first intermediate node Va and the duty cycle of the clock signal of the second intermediate node Vb. For specific detection and adjustment, please refer to the description in the above embodiment 3.

[0077] The present invention detects the voltage value of the virtual ground point in the resonant system or the duty cycle of the clock signal output by the clock driver, or comprehensively considers the two parameters of the voltage value and the duty cycle, to accurately adjust the duty cycle of the clock signal initially input to the system, thereby ensuring the integrity of the clock signal waveform to the greatest extent.

[0078] The technical contents and technical features of the present invention have been disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teachings and disclosures of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the contents disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention and are covered by the claims of this patent application.

Claims

1. A duty cycle adjustment device for a resonant system, characterized in that: Including a resonant system and a duty cycle adjustment device, The resonant system comprises a clock driver, a first capacitor and an inductor, wherein one end of the clock driver is connected to the clock signal and the other end is connected to the inductor; the first capacitor is connected between the clock driver and the inductor and is used to charge and discharge at the rising edge and falling edge of the clock signal respectively, and the other end of the inductor is connected to the power supply voltage and forms a first intermediate node; The resonant system further includes a second capacitor and a third capacitor, one end of the second capacitor is connected to the supply voltage, the other end is connected in series with the third capacitor, the other end of the third capacitor is grounded, and the second and third capacitors are decoupling capacitors; The duty cycle adjustment device is connected to the resonant system, and comprises a detection circuit, an adjustment judgment circuit and a duty cycle correction circuit, wherein the detection circuit is used to detect the duty cycle of the clock signal output by the clock driver and / or detect the voltage of the first intermediate node; The adjustment judgment circuit judges whether to adjust the duty cycle of the clock signal input to the clock driver according to the duty cycle output by the clock driver and / or the voltage value of the first intermediate node, and if so, outputs a duty cycle correction value to the duty cycle correction circuit; The duty cycle correction circuit is connected between the clock signal and the clock driver, and is used to determine whether to adjust the low level or high level of the clock signal according to the first digit of the duty cycle correction value, and then adjust the corresponding low level or high level of the clock signal according to the specific numerical value of the correction value.

2. The duty cycle adjustment device of the resonance system according to claim 1, characterized in that: One end of the first capacitor is connected between the clock driver and the inductor to form a second intermediate node, and the other end is grounded; the first capacitor is the sum of the parasitic capacitance and the load capacitance of the clock grid.

3. The duty cycle adjustment device of the resonance system according to claim 1, characterized in that: The other end of the inductor is connected between the second capacitor and the third capacitor to form the first intermediate node.

4. The duty cycle adjustment device of the resonance system according to claim 2, characterized in that: The detection circuit includes a voltage detection circuit, one end of the voltage detection circuit is connected to the first intermediate node, and the other end is connected to the duty cycle adjustment circuit, and is used to detect the voltage of the first intermediate node and output the voltage value to the duty cycle adjustment circuit.

5. The duty cycle adjustment device of the resonance system according to claim 2, characterized in that: The detection circuit includes a duty cycle detection circuit, one end of the duty cycle detection circuit is connected to the second intermediate node, and the other end is connected to the duty cycle adjustment circuit, which is used to detect the duty cycle of the clock signal at the second intermediate node and output the duty cycle to the duty cycle adjustment circuit.

6. The duty cycle adjustment device of the resonance system according to claim 2, characterized in that: The detection circuit comprises a voltage detection circuit and a duty cycle detection circuit, wherein one end of the voltage detection circuit is connected to the first intermediate node, and the other end is connected to the duty cycle adjustment circuit, and is used to detect the voltage of the first intermediate node and output the voltage value to the duty cycle adjustment circuit; The duty cycle detection circuit is connected to the second intermediate node at one end and to the duty cycle adjustment circuit at the other end, and is used to detect the duty cycle of the clock signal at the second intermediate node and output the duty cycle to the duty cycle adjustment circuit.

7. The duty cycle adjustment device of the resonance system according to claim 2, characterized in that: The adjustment judgment circuit is connected between the detection circuit and the duty cycle correction circuit.

8. A method for adjusting the duty cycle of the duty cycle adjusting device of the resonant system according to claim 1, characterized in that: The method comprises: S1, detecting a duty cycle of a clock signal output by a clock driver and / or detecting a voltage value of the first intermediate node; S2, adjusting the duty cycle of the clock signal input to the clock driver according to the duty cycle output by the clock driver and / or the voltage value of the first intermediate node.

9. The duty cycle adjustment method according to claim 8, characterized in that: In S2, the step of adjusting the duty cycle of the clock signal input to the clock driver according to the duty cycle output by the clock driver includes: S21, detecting a duty cycle of a clock signal output by a clock driver; S22, judging whether to adjust the duty cycle of the clock signal input by the clock driver according to the duty cycle, and if so, generating a duty cycle correction value, and entering S23; S23, adjusting the duty cycle of the clock signal input by the clock driver according to the duty cycle correction value.

10. The duty cycle adjustment method according to claim 8, characterized in that: In S2, the step of adjusting the duty cycle of the clock signal input to the clock driver according to the voltage value of the first intermediate node includes: S21′, detecting a voltage value of a first intermediate node; S22′, judging whether to adjust the duty cycle of the clock signal input by the clock driver according to the voltage value, and if so, generating a duty cycle correction value and entering S23′; S23', adjusting the duty cycle of the clock signal input by the clock driver according to the duty cycle correction value.

11. The duty cycle adjustment method according to claim 8, characterized in that: In S2, the step of adjusting the duty cycle of the clock signal input by the clock driver according to the duty cycle and the voltage value of the first intermediate node includes: S21″, detecting a duty cycle of a clock signal output by a clock driver and a voltage value of a first intermediate node; S22″, judging whether to adjust the duty cycle of the clock signal input by the clock driver according to the duty cycle and the voltage value, and if so, generating a duty cycle correction value and entering S23″; S23″, adjusting the duty cycle of the clock signal input by the clock driver according to the duty cycle correction value.

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