Power semiconductor device and method for forming the same

Abstract

The present application relates to a power semiconductor device and a method for forming the same. The power semiconductor device includes a semiconductor layer having a first conductivity type. A groove is defined in the semiconductor layer, the groove having an opening, a sidewall and a base. A column is arranged below the groove and has a second conductivity type different from the first conductivity type. A metal layer is arranged above the sidewall of the groove, the metal layer contacts the semiconductor layer at the sidewall of the groove to form a Schottky interface of a Schottky diode. A first electrode is arranged above a first side of the semiconductor layer. A second electrode is arranged above a second side of the semiconductor layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to U.S. Non-Provisional Application No. 16 / 009,484, filed on June 15, 2018, which is incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates to a power semiconductor device, in particular to a power device having a super junction structure and a Schottky diode. Background Art

[0004] Power semiconductor devices are used in many different industries. Some of these industries, such as telecommunications, computing, and toll systems, are growing rapidly. These industries will benefit from improved semiconductor device characteristics, including reliability, switching speed, and miniaturization.

[0005] Recent efforts to improve the characteristics of power semiconductor devices include creating a Schottky barrier region separate from the transistor region. A separate Schottky barrier region can reduce leakage current and improve reverse recovery characteristics. However, there is still room for improvement in the structure of power semiconductor devices to achieve lower forward voltages (V F ), faster reverse recovery performance and better reliability of emerging technologies to meet the demand for higher system efficiency. Summary of the invention

[0006] The embodiments of the present application are directed to a power semiconductor device having a superjunction and a Schottky diode, wherein the Schottky diode is integrated into a unit cell of the power device. The device has a lower forward voltage (V F ) and reduced reverse recovery time.

[0007] In one embodiment, the power semiconductor device includes a semiconductor layer having a first conductivity type. A groove is defined in the semiconductor layer, the groove having an opening, a sidewall and a base. A column is disposed below the groove and has a second conductivity type different from the first conductivity type. A metal layer is disposed above the sidewall of the groove, the metal layer contacts the semiconductor layer at the sidewall of the groove to form a Schottky interface of a Schottky diode. A first electrode is disposed above a first side of the semiconductor layer. A second electrode is disposed above a second side of the semiconductor layer.

[0008] In one embodiment of the above device, the power semiconductor device further includes: a gate electrode disposed above the semiconductor layer; a well having a second conductivity type and disposed above and spaced apart from the column; and a gap defining a distance between the well and the column, the gap corresponding to a Schottky interface. A first electrode is disposed near the gate, the gate extends into the trench and is electrically coupled to the metal layer, and a second electrode is disposed below the column. The semiconductor layer provides a vertical current path between the first electrode and the second electrode, and the first conductivity is N-type conductivity and the second conductivity is P-type conductivity.

[0009] In one embodiment of the above device, the power semiconductor device further comprises an enhancement region within the semiconductor layer and between the well and the pillar. The enhancement region has a first conductivity type and a doping concentration greater than a doping concentration of the semiconductor layer.

[0010] In one embodiment of the above device, the trench extends into an upper portion of the pillar such that a base of the trench is disposed within the pillar. The power semiconductor device further includes an ohmic contact region disposed below the base of the trench and within the pillar.

[0011] In one embodiment of the above device, the power semiconductor device further includes: a well having a second conductivity type and disposed above and spaced apart from the pillar; and a gap defining a distance between the well and the pillar, the gap corresponding to a Schottky interface.

[0012] In one embodiment, a power semiconductor device includes a substrate having an upper side and a lower side. A first electrode is disposed above the upper side of the substrate. A second electrode is disposed below the lower side of the substrate. An epitaxial layer is formed above the substrate and between the first electrode and the second electrode, the epitaxial layer having a column and a well, the column and the well defining a gap. A trench is disposed above the column, having a sidewall and a base, the base of the trench being recessed in the column. A metal contact layer is disposed above the base and sidewalls of the trench, the metal contact layer contacting the epitaxial layer at the gap defined by the well and the column, thereby defining a Schottky interface at the gap.

[0013] In one embodiment of the above device, the power semiconductor device further comprises an enhancement region, which is arranged between the well and the pillar and close to the Schottky interface. The power semiconductor device further comprises an ohmic contact region, which is arranged below the trench so that the metal contact layer forms an ohmic contact with the ohmic contact region.

[0014] In one embodiment, a method for forming a power semiconductor device includes: providing an epitaxial layer above a substrate; forming a well at an upper portion of the epitaxial layer; forming a pillar below the well and spaced apart from the well to define a Schottky contact region; etching a trench into the epitaxial layer, the trench having sidewalls and a base, a portion of the sidewall of the trench corresponding to the Schottky contact region; forming a metal contact layer above the sidewalls and base of the trench, the metal contact layer forming a Schottky interface with the epitaxial layer at the Schottky contact region; and forming a gate electrode and a first electrode and a second electrode.

[0015] In one embodiment of the above method, the method further includes forming an insulating layer over the trench, the insulating layer covering the sidewalls and base of the trench; etching the insulating layer to remove a portion of the insulating layer covering the base of the trench, leaving a portion of the insulating layer covering the sidewalls of the trench, thereby exposing a portion of the pillar; and implanting ions into the exposed portion of the pillar to form an ohmic contact region. The metal contact layer forms an ohmic contact with the ohmic contact region, and the portion of the insulating layer remaining on the sidewalls of the trench is used to protect the sidewalls of the trench from scattered ions during the implantation step.

[0016] In one embodiment of the above method, the method further includes forming an enhancement region between the well and the pillar and adjacent to a sidewall of the trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figures 1A to 1C A power semiconductor device having a super junction structure and a Schottky diode according to one embodiment is shown.

[0018] Figure 2 A comparison of conduction losses between a conventional power device and a power device according to an embodiment is shown.

[0019] Figure 3 A comparison of body diode reverse recovery current of a conventional super junction power device and a power device according to one embodiment is shown.

[0020] FIG. 4A to FIG. 4S A method of forming a power semiconductor device according to one embodiment is shown. DETAILED DESCRIPTION

[0021] Embodiments of the present application relate to power semiconductor devices with super junctions and Schottky diodes. The Schottky diode is integrated in the unit cell of the power device so that the Schottky diode does not occupy more area than the unit cell of the power device. The Schottky diode also provides a good current path between the super junction column and the source / emitter of the power device to minimize dynamic switching problems and major failures under high current avalanches. The Schottky diode can also be provided with sufficient shielding, for example, a high doped region adjacent to the Schottky contact region (or Schottky interface) to reduce current leakage under reverse bias. In one embodiment, the power device is configured to have a low epitaxial resistivity and handle a high breakdown voltage, for example, greater than 300 volts, or greater than 500 volts, or greater than 700 volts.

[0022] A detailed description of the embodiments is provided below in conjunction with the accompanying drawings. The scope of the present disclosure is limited only by the claims and encompasses many alternatives, modifications and equivalents. Although the steps of various methods are presented in a given order, the embodiments are not necessarily limited to performing in the listed order. In some embodiments, certain operations may be performed simultaneously in an order different from the described order, or may not be performed at all.

[0023] Many specific details are set forth in the following description. These details are provided to facilitate a thorough understanding of the scope of the present disclosure through specific examples, and embodiments may be practiced according to the claims without some of these specific details. Therefore, the specific embodiments of the present disclosure are illustrative and are not intended to be exclusive or restrictive. For the purpose of clarity, technical materials known in the technical field related to the present disclosure are not described in detail so as not to unnecessarily obscure the present disclosure.

[0024] FIG. 1 shows a power semiconductor device 100 according to one embodiment of the present disclosure. In this embodiment, the power device 100 is a power metal oxide semiconductor field effect transistor (MOSFET) device having a super junction structure (or pillar). In other embodiments, the power device 100 can be other power devices, such as an insulated gate bipolar transistor (IGBT) device. If the power device 100 is an IGBT, then it will have an additional P+ substrate or layer, as will be understood by those skilled in the art.

[0025] The power device 100 includes a semiconductor substrate 102, such as a silicon substrate. An epitaxial layer 104 (or epitaxial layer) is disposed on a first side of the substrate 102, and a first electrode 106 is disposed on or above a second side of the substrate 102. In one embodiment, the epitaxial layer 104 has N-type conductivity. A second electrode 108 is disposed above the epitaxial layer 104. A plurality of gate structures 110 are disposed above the epitaxial layer 104 and close to the second electrode 108. When the gate structures 110 are turned on, the epitaxial layer 104 provides a current path for the first electrode 106 and the second electrode 108. In the present embodiment, the power device 100 is a power MOSFET, and the first electrode 106 and the second electrode 108 are drain electrodes and source electrodes, respectively. In another embodiment, the power device may be an IGBT, and the first electrode 106 and the second electrode 108 may be collector electrodes and emitter electrodes, respectively.

[0026] Each of the gate structures 110 includes a gate electrode 112, a gate oxide 114, and a gate spacer 116. In the epitaxial layer, a plurality of wells 118 are provided between the gate structures 110. The depth of the wells 118 may depend on the characteristics of the power device 100. In one embodiment, the depth of the wells ranges from about 1 micron to about 2 microns, or may be up to 5 microns. In one embodiment, the wells 118 have P conductivity and form a body diode with the epitaxial layer 104. The dopant concentration of the P well 118 is about 1.2×10 16 atoms / cm 3 Up to 8.0×10 17 atoms / cm 3 A plurality of N+ regions 120 are disposed within the P-well 118 and proximate to the gate electrode 112. In one embodiment, the N+ regions 120 are source regions.

[0027] A plurality of pillars 122 (or superjunction structures) are disposed in epitaxial layer 104. Each pillar is spaced apart from P-well 118 to define a gap 123 of 1 to 5 microns or 2 to 3 microns, depending on the embodiment. This vertical gap 123 defines a Schottky diode region, and its size may vary depending on the embodiment. In one embodiment, pillar 122 has P-type conductivity and has a height of about 10 16 atoms / cm 3 In one embodiment, the pillar 122 has a vertical dimension of at least 20 microns or at least 25 microns. In another embodiment, the pillar 122 can have a vertical dimension of about 30 microns to about 60 microns, depending on the implementation. For example, for a 600V to 650V device, in an implementation, the pillar has a vertical dimension of about 45 microns to 50 microns.

[0028] In one embodiment, a plurality of N+ enhancement regions 124 are provided in the gap 123 defined by the P well and the pillar. The N+ enhancement regions 124 are provided to reduce the forward voltage drop of the body diode and reduce the current leakage under reverse bias. In one embodiment, the N+ enhancement regions 124 are provided in an alternating pattern, such as Figure 1B , which shows a top view of the N+ enhancement region 124 and the P well 118. In another embodiment, the gap 123 may only exist where the corresponding N+ enhancement region 124 exists, and not exist in other places, such as Figure 1C In this embodiment, the P-well 118 and the P-column 122 overlap in a region where the N+ enhancement region 124 is not present. In yet another embodiment, the N+ enhancement region 124 is not provided.

[0029] A plurality of trenches 126 extend from the upper surface of epitaxial layer 104 and into upper portions of P pillars 122. Trenches 126 extend through N+ source region 120 and partially into P well 118 such that the base or bottom of the trenches is located in P pillars 122. In one embodiment, trenches 126 extend from about 1 micron to about 8 microns into the P pillars.

[0030] A plurality of ohmic contact regions 128 are provided below the base of the trenches 126. In one embodiment, the ohmic contact regions 128 are formed by providing additional P-type impurities (e.g., boron) to the upper portion of the P-pillars 122. In one embodiment, the ohmic contact regions 128 have a dopant concentration significantly higher than that of the P-pillars 122. For example, the P-pillars have a dopant concentration of about 10 16 atoms / cm 3 The dopant concentration of the ohmic contact region 128 is about 10 19 atoms / cm 3 The dopant concentration of P column 122 is 3 times that of P column 122.

[0031] The Schottky contact layer 130 is disposed above the surface of the trench 126. The Schottky contact layer 130 includes an upper portion 130a, a side portion 130b, and a bottom portion (or base) 130c. The upper portion 130a of the Schottky contact layer 130 extends beyond the trench and abuts the side of the gate structure 110. The side portion 130b of the Schottky contact layer 130 contacts the gap 123 defined by the P well 118 and the P column 122, thereby defining a Schottky contact (Schottky interface). These Schottky contacts define a Schottky diode, in which the anode is connected to (or corresponds to) the source electrode 108, and the cathode is connected to (or corresponds to) the drain electrode 106. The Schottky diode reduces the forward voltage (V F) and reverse recovery time. Since the Schottky contact is formed between the P well 118 and the P column 122, the Schottky diode is integrated into the unit cell of the power device 100. Therefore, the Schottky diode does not occupy more area than the unit cell of the power device 100.

[0032] Additionally, bottom portion 130c of Schottky contact layer 130 forms an ohmic contact with ohmic contact region 128. The ohmic contact creates a good current path between pillar 122 and second electrode 108 (eg, source electrode), which reduces the likelihood of dynamic switching issues and catastrophic failures under high current avalanche conditions.

[0033] The Schottky contact layer 130 forming the Schottky diode may include a metal material such as molybdenum (Mo), platinum (Pt), vanadium (V), titanium (Ti), palladium (Pd), etc. In another embodiment, the Schottky contact layer 130 is a silicide material such as platinum silicide or palladium silicide.

[0034] As described above, the power device 100 having a Schottky diode has certain advantages. Figure 2 shows that the source-drain voltage V SD The waveforms of the current flowing through the two power devices are changed: "SJ MOS" represents a conventional super junction MOSFET device, and "SJ with Schottky diode" represents the power device 100. In experiments, it has been found that the source-drain voltage V of the SJ with Schottky diode (or power device 100) is SD Lower than the source-drain voltage V of conventional superjunction MOSFETs SD , especially at current levels below 15 A. For example, although a conventional superjunction MOSFET has a source-drain voltage V of 0.68 V at 1 A SD , but the source-drain voltage V SD At 1A, it is 0.46V, which is about 30% lower than a conventional superjunction MOSFET. It is believed that the Schottky diode reduces the source-drain voltage V SD , because Schottky diodes have lower forward voltage than PN diodes.

[0035] Similarly, while a conventional superjunction MOSFET has a source-drain voltage V of 0.74V at 5A SD , but the super junction MOSFET with vertical Schottky diode (or power device 100) is 0.66V at 5A, which is about 11% lower than the conventional super junction MOSFET device. The power device 100 has a lower source-drain voltage V than the conventional MOSFET. SD, because the Schottky diode in the power device 100 has a lower forward voltage drop than the PN junction diode in the conventional super junction MOSFET (e.g., 0.2V to 0.5V vs. 0.7V). Therefore, the power device 100 with the Schottky diode has smaller body diode conduction losses than the conventional super junction MOSFET, thereby improving power efficiency in applications including inverters and DC-DC power conversion.

[0036] Figure 3 Waveforms of the body diode reverse recovery current of a PN junction diode in a conventional super junction MOSFET device and a vertical Schottky diode in a super junction MOSFET device (e.g., power device 100) are shown. The reverse recovery current of the vertical Schottky diode is significantly less than the reverse recovery current of the PN junction diode in a conventional super junction MOSFET device. For example, when only the vertical Schottky diode is turned on, the reverse recovery current of the vertical Schottky diode of the power device 100 can be as low as zero when the drain current value is less than 6A. Because the reverse recovery current causes additional losses in the MOSFET switch in a bridge circuit with an inductive load, when the power device 100 with a vertical Schottky diode is used in such a bridge circuit, the conduction loss of the power device 100 will be less than that of a conventional super junction MOSFET switch. In addition, gate-source voltage oscillations in the bridge circuit can be reduced and MOSFET failures can be prevented.

[0037] FIG. 4A to FIG. 4S Aspects of a method of forming a semiconductor power device 200 according to one embodiment of the present disclosure are shown.

[0038] exist Figure 4A , a semiconductor layer 204 is formed over a semiconductor substrate 202. Layer 204 may be formed by an epitaxial growth method. In one embodiment, substrate 202 is silicon, and each epitaxial growth step forms an epitaxial layer having an epitaxial thickness of about 2.5 microns to 3.2 microns. In other embodiments, substrate 202 may be other semiconductor materials, such as a Group IV semiconductor substrate, a Group III-V compound semiconductor substrate, or a Group II-VI oxide semiconductor substrate. For example, a Group IV semiconductor substrate may include a silicon substrate, a germanium substrate, or a silicon germanium substrate.

[0039] Substrate 202 may include an epitaxial layer. In one embodiment, substrate 202 may be an N+ doped layer, where the power device is a MOSFET. In another embodiment, substrate 202 may be a P+ layer, where the power device is an IGBT. N-type impurities ( Figure 4B ) to convert layer 204 to N-type conductivity. Annealing may be performed to promote impurity diffusion. In one embodiment, layer 204 may be formed with N-type impurities so that the implantation step may be skipped.

[0040] A semiconductor layer 206 is formed over layer 204 ( Figure 4C ). N-type impurities are injected into layer 206 to obtain a structure having two N layers. Next, a patterned photoresist 207 ( Figure 4D ) to expose selected portions of layer 206. P-type impurities (or ions) are selectively implanted into the exposed portions of layer 206. These exposed portions of layer 206 will be used to form pillars (see Figure 1A The P-type impurities have a sufficient concentration to convert the exposed portions into a plurality of P regions 208. The photoresist 207 ( Figure 4E Repeat the above steps (for example, 13 to 20 times) to obtain a layer 206' having a plurality of pillars 208' ( Figure 4F ). Layer 206' includes multiple epitaxial layers. In one embodiment, the total depth (or vertical dimension) of pillar 208' from top to base is greater than 20 microns, for example, in the range of about 30 microns to 60 microns. An annealing process can be performed after ion implantation into each epitaxial layer to promote dopant diffusion.

[0041] Next, a semiconductor layer 210 is formed over the entire structure and doped with N impurities ( Figure 4G ). Depending on the embodiment, layer 210 may be a single epitaxial layer or a plurality of epitaxial layers. Layer 210 is formed to have a depth of 2 micrometers to 4 micrometers. Layer 210 has a sufficient depth to form a gap over which a Schottky contact is subsequently formed. Layer 210 is doped with N-type impurities. A patterned photoresist 212 is formed to expose portions of layer 210.

[0042] In one embodiment, additional N-doping is performed to provide a higher N-type concentration at selected portions of layer 210, thereby forming a plurality of N+ enhanced regions 214 ( Figure 4H ). The N+ enhancement region 214 corresponds to the N+ enhancement region 124 in FIG. 1. The doping concentration in the N+ enhancement region 214 may be, for example, about 1.2×10 16 Up to 5×10 17 Among other reasons, the N+ enhancement region 214 is formed to reduce current leakage under reverse bias. In the absence of the N+ enhancement region 214, there is no gap between the P column 208' and the subsequently formed P well ( Figure 1C), the overlap of the P column 208' and the subsequently formed P well can be achieved by additional photomasking and implantation steps, wherein the bridged implant region is formed only in the area outside the N+ enhancement region 214. Alternatively, the bridged implant region can be formed where the N+ enhancement region 214 exists, and the N+ enhancement region 214 is allowed to counter-dope the P column 208' to form the desired gap of the Schottky diode. Depending on the embodiment, the N+ enhancement region 214 may or may not be formed.

[0043] Fig. 4I A top view of the N+ enhancement regions 214 and pillars 208' is shown according to one embodiment. The pattern of the N+ enhancement regions 214 can be described as a checkerboard pattern over the pillars 208'. In other words, each consecutive pillar 208' of the device can have an alternating pattern of N+ enhancement regions 214 and N-body doped regions along its length, with the pattern of the N+ enhancement regions 214 offset relative to each adjacent pillar 208'. The widths of the N+ enhancement regions 214 and the N-body doped regions can be the same or similar, such that the N+ enhancement regions 214 and the N-body doped regions are arranged in an alternating matrix or checkerboard pattern over the pillars 208'. Although Fig. 4I The shape of the N+ enhancement region 214 in FIG. 1 is a rectangle, but the embodiment is not limited to this specific shape. For example, the shape of the N+ enhancement region 214 can be a circle, a hexagon, or other shapes.

[0044] In one embodiment, the N+ enhanced regions 214 disposed above adjacent pillars 208' do not overlap with each other relative to the gate axis direction of the figure or from top to bottom (see Fig. 4I In other embodiments, the N+ enhancement regions 214 of adjacent pillars 208 ′ overlap each other with respect to the gate axis direction. In yet another embodiment, one or more of the N+ enhancement regions 214 may extend over the entire P pillar 210 .

[0045] See also Figure 4J , another layer 216 is formed over the N+ enhancement region 214 by performing one or more epitaxial growth steps using the above steps. Depending on the implementation, the layer 216 has a depth of about 1 micron to 3 microns, or has a sufficient thickness to subsequently form a P well therein. A gate oxide layer 218 is formed over the layer 216. A gate electrode layer 220 is formed over the gate oxide layer 218. In one embodiment, the gate electrode layer is N-doped polysilicon, but may be other conductive materials depending on the implementation.

[0046] The gate electrode layer 220 is etched using photolithography methods known in the art to form a plurality of gate electrodes 220′ ( Figure 4K ).although Figure 4KA complete gate oxide layer 218 is shown in the space between adjacent gate electrodes 220', but some embodiments may include removing the gate oxide material provided between gate electrodes 220'. P-type dopants are injected into layer 216 using gate electrodes 220' as masks to form multiple P wells 222. Annealing may be performed to promote dopant diffusion. P wells 222 are formed to be spaced apart from pillars 208', thereby providing gaps 223. That is, in one embodiment, the bottom of the P well 222 and the top of the pillar 208' define gaps 223 to have a vertical dimension of at least 1 micron. In another embodiment, gap 223 is 2 microns to 4 microns, or 2 microns to 3 microns. The size of the gap defines the Schottky contact (or Schottky cross section) of the Schottky diode, so its size may vary depending on the implementation.

[0047] The gate electrode 220' is used as a mask to selectively implant N-type impurities into the top of the P-well 222 ( Figure 4L ). Alternatively, a photoresist mask may be used to pattern the implant. The N doping is controlled to produce a plurality of N+ regions 224. In one embodiment, the N+ regions are source regions.

[0048] See also Figure 4M , a gate dielectric layer (not shown) is formed above the gate electrode 220' and the N+ source region 224. The gate dielectric layer can be formed by depositing one or more dielectric layers above the upper surface of the device. The dielectric layer may include a nitride layer, an oxide layer, or other dielectric material. In one embodiment, the dielectric layer is a nitride layer. The dielectric layer is selectively etched to remove the portion of the dielectric material disposed between the gate electrodes 220', thereby producing a plurality of gate spacers 226. The gate spacers 226 define a plurality of gate structures 228. The gate structure 228 includes a gate oxide 218', a gate electrode 220', and a gate spacer 226.

[0049] A plurality of trenches 230 are formed above the pillars 208' and extend through the P-well 222 ( Figure 4N ). The trenches are formed using known photolithography and anisotropic etching processes. In one embodiment, the trenches 230 extend 1 micron to 8 microns into the pillars 208'.

[0050] An oxide layer 232 is formed over the trench 230 ( Fig.4O ). The oxide layer 232 may be formed using a deposition process or a thermal oxidation process and may have a thickness of 50 angstroms to 600 angstroms. In one embodiment, the oxide layer 232 is formed entirely over the entire structure, including over the gate structure 228. A nitride layer 234 is formed over the oxide layer 232. In one embodiment, the nitride layer 234 has a thickness of 1000 angstroms to 2500 angstroms.

[0051] Anisotropic etching is performed to expose pillars 208' ( Figure 4P ). The etching removes the horizontally exposed portions of the nitride layer 234 and the oxide layer 232, including the bottom portions of the nitride layer 234 and the oxide layer 232 disposed above the bottom surface of the trench 230. However, the nitride layer 234 and the oxide layer 232 remain on the sidewalls of the trench 230 and the gate structure 228. In some embodiments, a thin portion of the oxide layer 232 may remain at the bottom surface of the trench 230. The remaining nitride layer and oxide layer serve as sidewall spacers 236, which protect the sidewalls of the trench from a subsequent implantation step, which will be described below. In one embodiment, a photoresist mask is formed over the gate structure 228 prior to the anisotropic etching to protect the gate structure.

[0052] An ion implantation step is performed to form an ohmic contact region 238 at the bottom of the trench 230 ( Figure 4Q ), wherein a portion of the pillar 208' is exposed by the anisotropic etching described above. In one embodiment, the ohmic contact region is doped with a P-type dopant to at least 10 19 atoms / cm 3 The ohmic contact region 238 has a much higher conductivity than the body of the pillar 208', which has a conductivity of about 10 16 atoms / cm 3 concentration.

[0053] The sidewall spacers 236 protect the sidewalls of the trench 230 from ions (or dopants) that may be scattered during the implantation step. In one embodiment, a relatively low implantation energy, such as 3keV to 25keV, can be used for the implantation step so that the scattered ions will not have enough energy to penetrate the spacer 236 and be implanted into the sidewalls of the trench 230. In addition, if necessary, a heavier implantation material such as BF2 can be used instead of boron to reduce the expected range of the implantation. Alternatively, the thickness of the spacer 236 can be increased to prevent the scattered ions from penetrating the sidewalls of the trench 230. Alternatively, both the implantation energy and the thickness of the spacer 236 can be adjusted to prevent the scattered ions from penetrating into the sidewalls of the trench 230. If P-type dopants are implanted into the sidewalls of the trench, then these dopants can dilute the N-type conductivity of the sidewalls that will subsequently make Schottky contacts, which will reduce the performance of the Schottky diode.

[0054] After the ion implantation step, the nitride layer 234 and the oxide layer 232 remaining on the gate structure 228 and the trench 230 are removed. Figure 4R). In one embodiment, a wet etching step is used to remove the nitride layer 234 and the oxide layer 232. The wet etching is selected to dissolve the oxide layer 232 below the nitride layer. Thus, the nitride layer is lifted off the structure. In such an embodiment, the gate spacer 226 is formed using the nitride layer to protect the gate structure.

[0055] The Schottky contact layer 240 is formed over the exposed surface of the trench 230 ( Figure 4R ). The Schottky contact layer 240 can be formed by masking and selectively forming a Schottky metal material such as molybdenum (Mo), platinum (Pt), vanadium (V), titanium (Ti), palladium (Pd), etc. In one embodiment, the Schottky contact layer is formed by forming a silicide material such as platinum silicide or palladium silicide. The Schottky contact layer 240 can also be a combination of a metal material and a silicide material. In one embodiment, the Schottky contact layer 240 is conformally formed on the surface of the trench 230. In one embodiment, although not shown, a barrier metal material such as titanium nitride can be formed above the surface of the Schottky material layer. The Schottky contact layer 240 forms a Schottky contact at the gap 223 defined by the P well 222 and the P column 208' to form a Schottky diode. The bottom portion of the Schottky contact layer 240 forms an ohmic contact with the ohmic contact region 238. The ohmic contact helps current flow therethrough.

[0056] The first electrode 242 is formed by depositing a conductive material such as aluminum over the substrate 202. In one embodiment, the first electrode 242 is a drain electrode ( Figure 4S ). A second electrode 244 is formed by depositing a conductive material such as aluminum over the gate structure 228 and into the trench 230. In one embodiment, the second electrode is a source electrode. The resulting device is a power semiconductor device 200, which corresponds to the power device 100 in FIG. 1. Depending on the implementation, the power device 200 may be a power MOSFET, an IGBT, etc.

[0057] A1. Embodiments of the present disclosure include a power semiconductor device, comprising:

[0058] a semiconductor layer having a first conductivity type;

[0059] a trench defined in the semiconductor layer, the trench having an opening, sidewalls, and a base;

[0060] a pillar disposed below the trench and having a second conductivity type different from the first conductivity type;

[0061] a metal layer disposed over the sidewalls of the trench, the metal layer contacting the semiconductor layer at the sidewalls of the trench to form a Schottky interface of the Schottky diode;

[0062] a first electrode disposed over the first side of the semiconductor layer; and

[0063] A second electrode is disposed over the second side of the semiconductor layer.

[0064] A2. The device of A1, wherein the semiconductor layer provides a vertical current path between the first electrode and the second electrode, and the first electrode serves as an anode of the Schottky diode and the second electrode serves as a cathode of the Schottky diode, and

[0065] The semiconductor layer is an epitaxial layer formed on the substrate.

[0066] A3. The device of A2, wherein the substrate comprises an epitaxial layer.

[0067] A4. The device of A3, wherein the power device is a MOSFET, and the first electrode and the second electrode are a source electrode and a drain electrode, respectively, and the pillar is a superjunction pillar having a depth of at least 25 microns.

[0068] A5. The device of A4, wherein the trench extends into an upper portion of the pillar such that a base of the trench is disposed within the pillar.

[0069] A6. Embodiments of the present disclosure include a power semiconductor device, comprising:

[0070] a substrate having an upper side and a lower side;

[0071] a first electrode disposed over an upper side of the substrate;

[0072] a second electrode disposed below a lower side of the substrate;

[0073] an epitaxial layer formed over the substrate and between the first electrode and the second electrode, the epitaxial layer having a pillar and a well, the pillar and the well defining a gap;

[0074] a groove disposed above the post and having sidewalls and a base, the base of the groove being recessed into the post; and

[0075] A metal contact layer is disposed over the base and sidewalls of the trench, the metal contact layer contacts the epitaxial layer at a gap defined by the pillar and the well, thereby defining a Schottky interface at the gap.

[0076] A7. A6 device, further comprising:

[0077] an ohmic contact region, the ohmic contact region being disposed below the trench so that the metal contact layer forms an ohmic contact with the ohmic contact region,

[0078] The Schottky diode is defined by the epitaxial layer and the metal contact layer, and

[0079] The first electrode corresponds to the anode of the Schottky diode, and the second electrode corresponds to the cathode of the Schottky diode.

[0080] A8. The device of A6, wherein the power semiconductor device is a MOSFET.

[0081] A9. The device of A6, wherein the power semiconductor device is an IGBT.

[0082] A10. Embodiments of the present disclosure include a method for forming a power semiconductor device, the method comprising:

[0083] providing an epitaxial layer over a substrate;

[0084] forming a well at an upper portion of the epitaxial layer;

[0085] forming a pillar below and spaced apart from the well to define a Schottky contact region;

[0086] etching a trench into the epitaxial layer, the trench having sidewalls and a base, a portion of the sidewall of the trench corresponding to a Schottky contact region;

[0087] forming a metal contact layer over the sidewalls and base of the trench, the metal contact layer forming a Schottky interface with the epitaxial layer at the Schottky contact region; and

[0088] A gate electrode and first and second electrodes are formed.

[0089] A11. The method of A10 further includes:

[0090] forming an insulating layer above the trench, the insulating layer covering the sidewalls and base of the trench;

[0091] etching the insulating layer to remove a portion of the insulating layer covering a base of the trench while leaving a portion of the insulating layer covering a sidewall of the trench, thereby exposing a portion of the pillar; and

[0092] Ions are implanted into the exposed portion of the pillar to form an ohmic contact region,

[0093] The metal contact layer forms an ohmic contact with the ohmic contact region, and the portion of the insulating layer remaining on the sidewall of the trench is used to protect the sidewall of the trench from scattered ions during the implantation step.

[0094] A12. The method of A11 further includes:

[0095] An enhancement region is formed between the well and the pillar and adjacent to the sidewalls of the trench.

[0096] A13. The method of A12, wherein the power semiconductor device is a MOSFET and the pillar is a superjunction pillar.

[0097] A14. The method of A11, wherein the ions are implanted at an energy level insufficient to penetrate the insulating layer remaining on the sidewalls of the trench.

[0098] Various aspects of the present disclosure have been described together with specific embodiments presented as examples. Various substitutions, modifications and variations may be made to the embodiments described herein without departing from the scope of the claims described below. For example, in another embodiment, the P column may be formed by a method comprising forming alternating epitaxial semiconductor layers and barrier layers, injecting impurities into the barrier layers, and diffusing the impurities from the barrier layers into the epitaxial semiconductor layers, as described in U.S. Application No. 15 / 454,861, which is incorporated by reference. Alternatively, the P column may be formed by a completely different method, such as etching deep trenches, doping P-type dopants in the trenches, and filling the trenches with some material such as single crystal silicon. In addition, the method of doping P-type dopants may include growth of doped epitaxial silicon in deep trenches, angled ion implantation, plasma ion doping, diffusion from a solid source, atomic layer deposition, or some other doping technique. Similarly, although a planar gate structure is used in the previous embodiments, other types of gate structures are also possible. Specifically, a trench gate structure may be used instead of a planar gate structure. Therefore, the embodiments described herein are intended to be illustrative rather than restrictive.

Claims

1. A power semiconductor device, comprising: a semiconductor layer having a first conductivity type; a trench defined in the semiconductor layer, the trench having an opening, sidewalls and a base; a pillar disposed below the trench and having a second conductivity type different from the first conductivity type; a well having the second conductivity type and disposed above the pillar and spaced apart from the pillar; an enhancement region within the semiconductor layer and between the well and the pillar and having the first conductivity type; a metal layer disposed above the sidewalls of the trench, the metal layer contacting the semiconductor layer at a gap to form a Schottky interface of a Schottky diode, the gap defining a distance between the well and the pillar; a first electrode disposed above a first side of the semiconductor layer; and A second electrode is disposed on a second side of the semiconductor layer.

2. The power semiconductor device according to claim 1, further comprising: a gate electrode disposed above the semiconductor layer, wherein the first electrode is disposed near the gate, extends into the trench and is electrically coupled to the metal layer, and the second electrode is disposed below the pillar, and wherein the semiconductor layer provides a vertical current path between the first electrode and the second electrode, and the first conductivity is an N-type conductivity and the second conductivity is a P-type conductivity.

3. The power semiconductor device according to claim 2, The enhancement region has the first conductivity type and a doping concentration greater than a doping concentration of the semiconductor layer.

4. The power semiconductor device of claim 2, wherein the trench extends into an upper portion of the pillar such that the base of the trench is disposed within the pillar, wherein the power semiconductor device further comprises: An ohmic contact region is disposed below the base of the trench and within the pillar.

5. The power semiconductor device according to claim 1, wherein the power semiconductor device further comprises: An ohmic contact region is disposed below the base of the trench and within the pillar, and wherein the ohmic contact region has a second conductivity type and a doping concentration of the ohmic contact region is greater than a doping concentration of the pillar.

6. A power semiconductor device, comprising: a substrate having an upper side and a lower side; a first electrode disposed above the upper side of the substrate; a second electrode disposed below the lower side of the substrate; an epitaxial layer formed over the substrate and between the first electrode and the second electrode, the epitaxial layer having a pillar and a well, the pillar and the well defining a gap; an enhancement region disposed between the well and the pillar; a groove disposed above the column and having sidewalls and a base, the base of the groove being recessed into the column; and a metal contact layer disposed over the base and the sidewalls of the trench, the metal contact layer contacting the epitaxial layer at the gap defined by the pillar and the well, thereby defining a Schottky interface at the gap, The epitaxial layer and the enhanced region have the same conductivity type.

7. The power semiconductor device according to claim 6, further comprising: The enhancement region is close to the Schottky interface; and An ohmic contact region is provided below the trench so that the metal contact layer forms an ohmic contact with the ohmic contact region.

8. A method for forming a power semiconductor device, the method comprising: providing an epitaxial layer over a substrate; forming a well at an upper portion of the epitaxial layer; forming a pillar below the well and spaced apart from the well to define a Schottky contact region; etching a trench into the epitaxial layer, the trench having sidewalls and a base, a portion of the sidewalls of the trench corresponding to the Schottky contact region; forming an enhancement region between the well and the pillar and adjacent to the sidewall of the trench; forming a metal contact layer on the sidewall and the base of the trench, wherein the metal contact layer forms a Schottky interface with the epitaxial layer at the Schottky contact region; as well as forming a gate electrode and a first electrode and a second electrode, The epitaxial layer and the enhanced region have the same conductivity type.

9. The method according to claim 8, further comprising: forming an insulating layer above the trench, the insulating layer covering the sidewalls and the base of the trench; etching the insulating layer to remove a portion of the insulating layer covering the base of the trench and leaving a portion of the insulating layer covering the sidewall of the trench, thereby exposing a portion of the pillar; and implanting ions into the exposed portion of the pillar to form an ohmic contact region, The metal contact layer forms an ohmic contact with the ohmic contact region, and the portion of the insulating layer remaining on the sidewall of the trench is used to protect the sidewall of the trench from scattered ions during the implantation step.

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