Systems and methods for driving a power switch in combination with a regulated DI / DT and / or DV / DT

Abstract

Systems and methods for driving a power switch in combination with a regulated dI / dt and / or dV / dt are disclosed. According to an embodiment, a method of driving a switching transistor includes: driving the switching transistor with a gate drive signal; measuring at least one of a derivative of a load path voltage of the switching transistor and a derivative of a load path current of the switching transistor; measuring a derivative of the gate drive signal; forming an error signal based on a reference signal, the measured derivative of the gate drive signal, and at least one of the measured derivative of the load path voltage of the switching transistor or the measured derivative of the load path current of the switching transistor; and forming the gate drive signal, wherein forming the gate drive signal includes processing the error signal using a dynamic controller.

Description

Technical Field

[0001] The present invention generally relates to systems and methods for driving a power switch in combination with a regulated di / dt and / or dv / dt. Background Art

[0002] Generic driver circuits for power semiconductors such as insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), junction gate field effect transistors (JFETs), and high electron mobility transistors (HEMTs) can be adapted to control the switching slope of the power semiconductor. The switching slope is at least one of: the voltage change over time (dv / dt) that occurs when the voltage on the load path of the power semiconductor rises or falls; and the current change over time (di / dt) that occurs when the current through the load path of the power semiconductor rises or falls. Typically, the slope is not regulated to a specific value or range but only limited, which may be sufficient for many applications. However, limiting the slope may mean, for example, limiting the dv / dt to a maximum voltage change value or limiting the di / dt to a maximum current change value. Limiting the di / dt in the case of a falling current is particularly important because excessive (negative) di / dt with respect to parasitic inductance may generate a voltage that may exceed the maximum voltage rating of the corresponding power semiconductor.

[0003] In cases where the signal for driving the power semiconductor is under closed-loop control, additional problems arise with respect to overshoots that may occur when the drive voltage of the power semiconductor is below the turn-on threshold of the semiconductor. In this operating region, the feedback path including the output of the corresponding semiconductor device is essentially disabled, and at least part of the control loop for regulating the drive voltage of the power semiconductor may operate in an open-loop state. Such open-loop behavior may cause voltage errors and overshoots that are corrected by the loop once the loop is fully closed. Summary of the Invention

[0004] According to an embodiment, a gate drive circuit for controlling a gate-controlled component includes: a dynamic controller configured to receive an input reference signal and control the gate voltage of the gate-controlled component via an output terminal of the gate drive circuit; at least one component feedback circuit for the dynamic controller, the at least one component feedback circuit being configured to provide feedback to the dynamic controller from at least one of: the time derivative of the load path voltage of the gate-controlled component or the time derivative of the load path current of the gate-controlled component; and a gate drive feedback circuit for the dynamic controller, the gate drive feedback circuit being configured to provide feedback from the time derivative of the voltage at the output terminal of the gate drive circuit.

[0005] According to another embodiment, a circuit includes: a gate driver circuit having an output coupled to a gate drive terminal configured to be coupled to a gate of a switching transistor; a dynamic controller having an output coupled to an input of the gate driver circuit; a summing circuit having an output coupled to an input of the dynamic controller and a first input configured to receive a reference signal; at least one feedback circuit coupled between a voltage measurement terminal and a second input of the summing circuit, the at least one feedback circuit configured to provide a signal proportional to at least one of a derivative of a load path voltage of the switching transistor and a derivative of a load path current of the switching transistor to the second input of the summing circuit; and an anti-windup circuit coupled between the output of the gate driver circuit and a third input of the summing circuit, the anti-windup circuit configured to provide a signal proportional to a derivative of an output voltage of the gate driver circuit to the third input of the summing circuit.

[0006] According to a further embodiment, a method of driving a switching transistor includes: driving the switching transistor with a gate drive signal; measuring at least one of a derivative of a load path voltage of the switching transistor and a derivative of a load path current of the switching transistor; measuring a derivative of the gate drive signal; forming an error signal based on the reference signal, the measured derivative of the gate drive signal, and at least one of the measured derivative of the load path voltage of the switching transistor or the measured derivative of the load path current of the switching transistor; and forming the gate drive signal, wherein forming the gate drive signal includes processing the error signal using a dynamic controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To more fully understand the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a schematic diagram illustrating an exemplary driver circuit without an external output boost circuit and having an integrated circuit with analog and digital dv / dt feedback paths;

[0009] Figure 2 is a schematic diagram illustrating an exemplary driver circuit with an external output boost circuit and having an integrated circuit with analog and digital dv / dt feedback paths;

[0010] Figure 3 is a schematic diagram illustrating an exemplary driver circuit without an external output boost circuit and having an integrated circuit with analog and digital dv / dt and di / dt feedback paths;

[0011] Figure 4is a schematic diagram showing an exemplary driver circuit having an external output boost circuit and having an integrated circuit having analog and digital dv / dt and di / dt feedback paths;

[0012] Figure 5 is a schematic diagram showing an exemplary driver circuit having analog and digital feedback paths;

[0013] Figure 6 is a schematic diagram showing an exemplary driver circuit having modified analog and digital feedback paths;

[0014] Figure 7 is a schematic diagram showing an exemplary drive circuit having further modified analog and digital feedback paths;

[0015] Figures 8A to 8E Graphs line charts and waveform charts depicting the performance of an exemplary gate drive system that provides closed-loop slew rate control of the output voltage of a gate driver circuit;

[0016] Figure 9A and Figure 9B is a schematic diagram showing an exemplary gate drive circuit;

[0017] Figures 10A to 10C is a waveform chart showing the performance of an exemplary gate drive circuit;

[0018] Figure 11A and Figure 11B is a schematic diagram showing a feedback circuit that can be used to implement an exemplary gate driver circuit; and

[0019] Figure 12A and Figure 12B is a schematic diagram showing an exemplary gate driver integrated circuit. DETAILED DESCRIPTION

[0020] Figures 1 to 7 Generally describes the regulation of changes in voltage (dv / dt regulation) and changes in current (di / dt regulation) across a power switch as described in German Patent Application DE102016111449.9 filed on June 22, 2016. Reference is made to Figures 8A to 12B for a detailed description of embodiments of the present invention. In embodiments of the present invention, a power switch driver circuit is configured to use a feedback control circuit to regulate the derivative of the load path current (dI c / dt), the derivative of the load path voltage (dV CE / dt), and the derivative of the gate drive voltage (dV out，Driver / dt). In some embodiments, three feedback paths are used to couple dI c / dt, dV CE / dt and dV out，Driver The / dt feedback is provided to a single dynamic controller, such as a proportional integral (PI) controller. By providing d c / dt and dV CE / dt in addition to d Vout，Driver / dt, overshoot of the gate drive voltage can be reduced and / or eliminated. This overshoot can also be referred to as the "snapping" effect. Regarding Figures 8A to 8E 、 Figures 9A to 9B 、 Figures 10A to 10C 、 Figures 11A to 11B and Figures 12A to 12B these embodiments are described.

[0021] In a simple general-purpose driver circuit that primarily limits voltage overshoot during turn-off, the feedback signal acts directly on the control terminals of the semiconductor devices, such as their gates. Since the feedback signal requires a certain amount of current to generate an effective voltage change at the gate when acting against a low gate resistor (less than 1 ohm to a few ohms), this direct feedback structure is not suitable. In other common driver circuits, the feedback current is low because they act on the input of a power amplifier stage that directly drives the gates of the semiconductor devices. The input impedance at the input of the power amplifier stage (where the feedback current must generate a voltage) reaches several orders of magnitude higher than the impedance at the control terminals of the semiconductor devices (such as the gate resistor). Such driver circuits typically use discrete transistors connected as current amplifiers, for example, in an emitter follower type configuration. For high current amplification, two or three amplifier stages may be required, for example, in a Darlington configuration. To evaluate the voltage change dv / dt over time and / or the current change di / dt over time, standard passive discrete components are typically used.

[0022] Figure 1An exemplary driver circuit for driving a controllable semiconductor device 106, such as an insulated gate bipolar transistor (IGBT) or any other suitable semiconductor device, is shown. The emitter of the semiconductor device 106 may be connected to ground 108 via a parasitic inductance 107, and its collector is connected to a load (not shown). The semiconductor device 106 may also be referred to as a gate-controlled component or a switching transistor. The load path of the semiconductor device 106 is the path between its emitter and collector, and may include the parasitic inductance 107. The driver circuit receives an external control signal, such as a control input signal 100, and includes a signal preprocessing stage 101 and a subsequent signal postprocessing stage 102, such as an internal output stage. At least the signal preprocessing stage 101 and the postprocessing stage 102 may be integrated in an integrated circuit device 103. The integrated circuit device 103 may receive the control input signal 100 and at least two feedback signals, the at least two feedback signals from, for example: an analog feedback signal 104, which is from an external analog dv / dt monitoring stage 105; and a digital feedback signal 114, which is from an external analog-to-digital converter 112, the external analog-to-digital converter 112 converting a voltage into a binary word forming the digital feedback signal 114. The analog-to-digital converter 112 is connected upstream of an internal dv / dt monitoring stage 115, which is arranged in the integrated circuit device 103.

[0023] The feedback signal 104 (such as voltage and / or current) may be combined (such as summed) in the integrated circuit device 103 with an internal control signal 111 (such as voltage and / or current), the internal control signal 111 being from an internal preprocessing stage 101 at the input of the postprocessing stage 102. The monitoring stage 105 performs an analog calculation of the voltage change dv / dt over time of the voltage on the load path of the semiconductor device 106 (such as the voltage at the collector of the semiconductor device 106). The monitoring stage 115 performs a digital calculation of the voltage change dv / dt over time of the digital feedback signal 114, the digital feedback signal 114 representing the voltage on the load path of the semiconductor device 106. The monitoring stage 115 controls the preprocessing stage 101, which outputs an analog signal (such as voltage and / or current) depending on the input signal 100 and the digital feedback signal 114.

[0024] Further, the external dv / dt monitoring stage 105 and the internal dv / dt monitoring stage 115 evaluate the voltage change over time of the voltage on the load path of the semiconductor device 106 to be controlled. The voltage evaluation may include at least one of the following: monitoring the voltage change, gating the feedback signal, detecting the rise and fall of the voltage, amplifying or attenuating at least one feedback signal, etc. The output stage 102 provides a control output signal 116 to regulate the voltage change dv / dt at the control path (gate) of the semiconductor device 106, and the control output signal 116 is, for example, a controlled voltage and / or current depending on the control input signal 100 and the feedback signals 104 and 114.

[0025] Optionally, the integrated circuit device 103 may be connected to the gate of the semiconductor device 106 via a resistor 109. Also optionally, the signal preprocessing stage 101 and the postprocessing stage 102 may be connected via a resistor 110. The resistor 109 may have as small a resistance as possible, just sufficient to suppress oscillations in the control path (gate) of the semiconductor device 106 and thus stabilize the entire circuit. The current entering the control path (gate) of the semiconductor device 106 is indirectly controlled by feedback into the output stage which forms part of the signal postprocessing stage 102 of the integrated circuit device 103 in this example. The resistor 110 allows the feedback current (which forms the signal 104) to generate a voltage difference against the voltage provided by the preprocessing stage 101, thus regulating the input of the output stage of the signal postprocessing stage 102 to provide slope control for the semiconductor device 106.

[0026] The signal preprocessing stage 101 may perform at least one of level shifting, electrical isolation, and signal shaping processing. In this example, the signal postprocessing stage 102 is a voltage-to-voltage amplifier that supplies any current required to achieve the output voltage, but alternatively may be a current-to-voltage amplifier, a current-to-current amplifier, or a voltage-to-current amplifier as shown, while the circuitry upstream and downstream of the corresponding amplifier is adapted accordingly. The integrated circuit device 103 may be referenced to ground 108, which is one end of the parasitic inductance 107, for example, the external end of the parasitic inductance 107. As can be seen, the feedback signals 104 and 114 representing the voltage change dv / dt act against the resistor 110.

[0027] Refer to Figure 2 , Figure 1The drive circuit shown in can be modified by using integrated circuit device 200 instead of integrated circuit device 103, where resistor 110 is replaced by a digitally controllable current source 201. As can be seen, the feedback signal 104 (current) acts on the current source 201, which ideally provides an infinite DC resistance. The current source 201 is controlled by a digital dv / dt monitoring stage 208 that digitally evaluates the voltage change over time of the voltage on the load path of semiconductor device 106. The analog monitoring stage 207 performs an analog calculation of the voltage change dv / dt over time of the voltage on the load path of semiconductor device 106. The digital-to-analog converter 112 connected between the analog monitoring stage 207 and the digital dv / dt monitoring stage 208 converts the resulting analog dv / dt signal from the analog monitoring stage 207 into a digital dv / dt signal for the digital dv / dt monitoring stage 208. The current source 201 can be further adjustable to provide a specific current for different semiconductor devices 106.

[0028] Furthermore, an external power amplifier 202 can be inserted between the post-processing stage 102 and the resistor 109. In this example, the power amplifier 202 includes one amplifier stage formed by a complementary transistor pair (e.g., having a pnp bipolar transistor 203 and an npn bipolar transistor 204), which is connected between a negative voltage supply line 205 and a positive voltage supply line 206 in a complementary emitter follower configuration. For example, the post-processing stage 102 can have a current driving capability of up to 1 or 2 amperes, and the current amplifier 202 can increase this capability by a factor of 10 to 50, so that the resistor 109 can be reduced in the circuit shown in Figure 2 The post-processing stage 102 and / or the current amplifier 202 can alternatively have a class A or class A / B amplifier structure to increase the speed at which the transition from positive current to negative current is performed. Alternatively or additionally, the post-processing stage 102 and / or the power amplifier 202 can have more than one amplifier stage to achieve a very low parasitic drive inductance. The internal dv / dt monitoring stage 115 is replaced by the digital monitoring stage 208, which digitally processes the digital input signal and provides a digital output signal.

[0029] By providing access to the input of the internal output stage of an integrated circuit device, the current provided by the feedback stage can be further reduced (to a few tens of mA) due to smaller parasitic capacitances and the integrated circuit can provide increased speed and flexibility. At the same time, it can reduce the number of cascaded external output stages required. The output stage can typically supply a maximum current of 0.5 A to 2 A or, in some cases, up to 6 A. Further, the feedback path needs to feed less current, thus requiring a smaller feedback capacitor (small additional capacitance on the high-voltage switching node), making the overall circuit more efficient in terms of power consumption and size. Amplifying this current through one or more external stages can provide sufficient current to drive very large IGBT devices, power semiconductor modules, etc. Instead of driving the input of the internal power stage through a controllable voltage source and resistor, it can be driven using a controllable current source capable of supplying positive and negative currents. This allows for more linear (if the dv / dt feedback capacitor is linear) and load-independent dv / dt (and / or di / dt) regulation.

[0030] As shown in Figure 3 it is possible to modify the Figure 2 driver circuit shown in

[0031] Figure 3 by using, instead of integrated circuit device 200, integrated circuit device 300, in which current source 201 is omitted and feedback processing and summing stage 301 is connected between preprocessing stage 101 and postprocessing stage 102. Digital dv / dt monitoring stage 207 digitally processes a digital input signal, such as a binary signal representing the voltage on the load path of semiconductor device 106, and provides a digital output signal, such as a binary signal representing the derivative of the voltage on the load path of semiconductor device 106. Further, at least one other external feedback stage, such as external analog di / dt monitoring stage 302 and / or external digital di / dt monitoring stage 303, is connected to the load path of semiconductor device 106 via analog-to-digital converter 304. Feedback processing and summing stage 301 receives signals from dv / dt monitoring stages 105 and 207, signal preprocessing stage 101, and additionally from analog di / dt monitoring stage 302 and digital di / dt monitoring stage 303. Digital di / dt monitoring stage 303 digitally processes a digital input signal, such as a binary signal representing the current through the load path of semiconductor device 106, and provides a digital output signal, such as a binary signal representing the derivative of the current through the load path of semiconductor device 106. The driver circuit shown in Figure 4modified as shown because the power amplifier 400 is inserted between the post - processing stage 102 and the resistor 109. In this example, the power amplifier 400 includes one amplifier stage formed by a complementary transistor pair (e.g., having a pnp bipolar transistor 401 and an npn bipolar transistor 402), and the complementary transistor pair is connected between a negative voltage supply line 403 and a positive voltage supply line 404 in a complementary emitter - follower configuration. Alternatively, the power amplifier 400 may have more than one amplifier stage to achieve a very low parasitic driver inductance and / or may have a class - A or class - A / B amplifier structure in order to increase the speed at which the transition from positive current to negative current is performed. Further, the digital dv / dt monitoring stage 207 is replaced by a digital dv / dt monitoring stage 405, and the digital di / dt monitoring stage 303 is replaced by a digital di / dt monitoring stage 406. The dv / dt monitoring stage 405 and the di / dt monitoring stage 406 digitally process digital input signals and provide digital (binary) output signals.

[0032] Referring Figure 5 , another exemplary driver circuit includes an integrated circuit device 500 having a low - voltage circuit portion and a higher - voltage circuit portion electrically isolated from the low - voltage circuit portion. The low - voltage circuit portion includes an under - voltage lock - out (UVLO) block 501 that receives the (positive) supply voltage VCC of the integrated circuit device 500 1 and a first ground GND 1 , and the integrated circuit device 500 is referenced to this first ground GND 1 . The under - voltage lock - out block 501 is an electronic circuit block that serves to disable and / or turn off the power for the integrated circuit device 500 in the event that the supply voltage VCC 1 drops below the operating value. For example, in the integrated circuit device 500, the under - voltage lock - out block 501 may monitor the supply voltage VCC 1 and turn off the circuit if the supply voltage VCC 1 drops below a specific threshold, thus protecting the integrated circuit device 500 and, possibly, also semiconductor devices and / or loads associated with the integrated circuit device 500. The low - voltage circuit portion of the integrated circuit device 500 may further include a logic block 502 that receives an input (control) signal IN (e.g., for switch control) and an enable signal EN (e.g., for enabling or disabling, e.g., the logic block 502, the integrated circuit device 500, or the entire driver circuit).

[0033] The logic block 502 can also provide a digital input / output interface for exchanging digital data DIO such as specific control data, status data, service data, etc. with other units (not shown). Further, the logic block 502 can be timed using the clock signal provided by the clock signal generator 503 and can be connected to the electrically isolated bidirectional signal coupler 504, which can provide isolation based on inductance (as shown), capacitance, optical, or any other suitable basis. Optionally, an additional signal coupler 505 (e.g., a unidirectional coupler) can couple in terms of signals but is electrically isolated from the low-voltage circuit section and the higher-voltage circuit section.

[0034] In the higher-voltage circuit section, the signal coupler 504 and the signal coupler 505 (if present) are connected to the control block 506, which can be a logic block implemented using a processor, a software block, or a combination of both. The control block 506 receives the clock signal from the clock signal generator 507 and the signal from the under-voltage lockout block 508 for the higher-voltage circuit section. The control block 506 exchanges digital data with the central signal processing block 509, which can provide post-processing, regulation, and adaptation for the load path voltage / current slope. For example, the central signal processing block 509 can be adapted or programmed to implement a digital loop controller that includes at least one of the following: a proportional control mechanism (P); an integral control mechanism (I); a derivative control mechanism (D); or a combination thereof, such as, for example, a PI or PID control mechanism. Further, the control block 506 sends a turn-on / turn-off signal to the central signal processing block 509 and the memory 510, a sampling control signal to the two analog-to-digital conversion blocks 511 and 512, and another turn-on / turn-off signal and slope configuration data to the level shift block 513. The analog-to-digital conversion blocks 511 and 512 send data to the memory 510. The analog-to-digital conversion block 511 receives a voltage sensing signal VSD (e.g., voltage or current) referenced to a second ground GND 2 and the analog-to-digital conversion block 512 receives a current sensing signal IS (e.g., voltage or current) referenced to a second ground GND 2

[0035] The level shift block 513 sends control data to the adaptive driver block 514, which can include two digitally controllable current sources 515 and 516 connected in series between the (negative) supply voltage VEE 2 and the (positive) supply voltage VCC 2 with a node 517 between the two current sources 515 and 516. The supply voltages VEE 2 and VCC 2 ​At least one of them can be monitored by the under-voltage lockout block 508. Each of the current sources 515 and 516 is controlled by the digital data provided by the level-shifting block 513. The driver output stage 518 is connected to the node 517, to the line carrying the voltage sensing signal (such as voltage or current), and to the output of the transconductance amplifier block 519, the non-inverting input of which is connected to the second ground GND 2 and its inverting input is connected to the line receiving the current sensing signal IS (such as the voltage corresponding to the change in the current to be measured on the inductor).

[0036] The external wiring of the integrated circuit device 500 includes two capacitors 520 and 521, which couple the collector line of the semiconductor device 106 to the line carrying the voltage sensing signal VSD and the line carrying the voltage sensing signal VSA respectively. The two capacitors 520 and 521 are used to obtain dv / dt from the voltage on the load path. The second ground GND 2 is established by the node between the emitter of the semiconductor device 106 and one end of the parasitic inductor 107. The current sensing signal IS is picked up at the other end of the parasitic inductor 107. The inductor 107 is used to differentiate the current obtained through the load path di / dt and convert the current into the corresponding voltage to be measured. The gate of the semiconductor device 106 is connected to the output stage 518 via the resistor 522. The supply voltages VEE 2 and VCC 2 can be provided by the bipolar voltage source 523, the ground of which is connected to the second ground GND 2 . Optionally, the power amplifier 524 supplied with the supply voltages VEE 2 and VCC 2 is connected between the output stage 518 and the resistor 522. In the Figure 5 exemplary driver circuit shown, the blocks 501 - 509, 513 can form a preprocessing stage, the blocks 510 - 512, 519 form a feedback processing and superposition stage, and the blocks 515 - 518 form a signal postprocessing stage.

[0037] By adding external feedback capacitors (such as capacitors 520 and 521) and providing a power stage (such as output stage 518) of a buffered current source driver (such as driver block 514), much lower peak currents are required on the current source driver for dv / dt feedback and / or di / dt feedback. In this way, a current source driver can be designed with lower power components, allowing the current source to be more precise and faster in changing its current value. Additionally, the current source driver can be constructed as a current output digital-to-analog converter, which can be digitally programmed to change dv / dt and / or di / dt. Additional external digital period regulation loops can be added to further control dv / dt and / or di / dt, as shown in Figure 5 As shown. The programming of dv / dt and di / dt can be changed independently without changing the dv / dt or di / dt analog feedback network. The digital loop can track changes in the load path voltage and load path current to change the digital-to-analog converter output current at the correct time when a transition occurs between dv / dt and di / dt. Generally, the analog feedback path is faster (fewer delay instances caused by signal processing and / or higher critical frequency) but provides lower precision and flexibility. In contrast, the digital feedback path is slower (more delay instances caused by signal processing and / or lower critical frequency) but provides higher precision and flexibility.

[0038] Figure 5 The driver circuit shown in is an example of how an integrated driver with high voltage level shift and analog and digital dv / dt and di / dt feedback paths can be implemented. The di / dt feedback path (such as corresponding to signal IS) senses the voltage at the emitter inductance (such as parasitic inductance 107), injecting a corresponding (such as proportional) current into the summing node (such as node 517) of the reference current (from the current source pre-driver stage (such as transconductance amplifier block 519) and the dv / dt analog feedback capacitor (such as capacitor 521)) / sinking a corresponding (such as proportional) current from the summing node (such as node 517). The summing node controls the input of a unity gain amplifier (only one internal stage, such as output stage 518, or in combination with an external cascaded stage such as current amplifier 524), and the unity gain amplifier in turn drives the gate voltage of an external semiconductor device (such as semiconductor device 106). The dv / dt digital feedback path can be implemented by means of an analog-to-digital converter (such as analog-to-digital converter block 511), which samples the current flowing through the dv / dt digital feedback capacitor (such as capacitor 520). The di / dt digital feedback path is implemented by means of an analog-to-digital converter (such as analog-to-digital converter block 512), which samples the voltage change representing the current change through the emitter inductance (such as parasitic inductance 107) on the emitter inductance.

[0039] Figure 6 shows the above-described driver circuit in the case of some modified and alternative implementations Figure 5 Two digitally controllable current sources 515 and 516 are connected to each other through a diode series connection 600 of one or more diodes (e.g., four diodes), whereby a node 601 is formed between the current source 515 and one end of the diode series connection 600, and a node 602 is formed between the current source 516 and the other end of the diode series connection 600. Each digitally controllable current source 515, 516 is connected in parallel with a constant current source 603 and 604, respectively. The line carrying the voltage sensing signal VSA is connected to the node 601 and the line carrying the current sensing signal IS is connected to the node 602 through a resistor 605 and a diode 606 (instead of the transconductance amplifier block 519).

[0040] Figure 5 The output stage 518 shown in is replaced by an AB-class amplifier stage, which includes: a metal-oxide-semiconductor field-effect transistor (MOSFET) 607 of n-channel type, whose gate is connected to the node 601 and whose drain is connected to the supply voltage VCC 2 ; and includes a metal-oxide-semiconductor field-effect transistor 608 of p-channel type, whose gate is connected to the node 602 and whose drain is connected to the supply voltage VEE 2 . The sources of the transistors 607 and 608 are connected to each other through another diode series connection circuit 609 having at least one diode (e.g., two diodes). Further, a metal-oxide-semiconductor field-effect transistor 610 of n-channel type is connected to the second ground GND via its gate 2 and is connected to the line carrying the voltage sensing signal VSA via its drain. The source of the transistor 610 is connected to the line carrying the current sensing signal IS through a linearization resistor 611. Further, if required, a resistor 612 can be connected between the line carrying the voltage sensing signal VSD and the second ground GND 2 and a voltage divider including two resistors 613 and 614 connected in series is connected between the second ground GND2 and the line carrying the current sensing signal IS to reduce the voltage swing at the corresponding analog-to-digital converter input.

[0041] The input of the analog-to-digital converter block 512 is now connected to the node between resistors 613 and 614 (instead of directly to the line carrying the current sensing signal IS). Optionally, an external resistor 615 can be connected in parallel to resistor 612. In this example, the current amplifier 524 can be implemented by an n-channel type metal oxide semiconductor field effect transistor (MOSFET) 616 (whose gate is connected to the source of transistor 607 and whose drain is connected to the supply voltage VCC 2 ), and by a p-channel type metal oxide semiconductor field effect transistor 617 (whose gate is connected to the source of transistor 608 and whose drain is connected to the supply voltage VEE 2 ). The sources of transistors 607 and 608 are connected to each other and to resistor 522.

[0042] In Figure 6 the driver circuit, the unity gain buffer stage ( Figure 5 the output stage 518 in Figure 6 ) is replaced by two cascaded class A / B amplifier stages ( Figure 6 transistors 607, 608, 616, 617 and diode series connection 609 in Figure 6 ) and two bias current sources ( Figure 6 constant current sources 603 and 604 in Figure 6 ). The analog dv / dt feedback path remains unchanged. The analog di / dt feedback path is replaced by two separate feedback paths for turning on (transistors 610 and resistor 611) and turning off ( Figure 6 resistor 605 and diode 606 in Figure 6 ).

[0043] In the driver circuit discussed above regarding Figure 6 , resistor 605 and diode 606 can be replaced by an n-channel type metal oxide semiconductor field effect transistor 700, a resistor 701, p-channel type metal oxide semiconductor field effect transistors 702 - 704 and a current source 705. As shown in Figure 7 , transistor 700 can be connected via its gate to the line carrying the current sensing signal IS, and via its source and through a linearizing resistor 701 to a second ground GND 2 , providing voltage-to-current conversion. Transistor 702 is connected via its drain to the supply voltage line VEE 2 , via its gate to the drains of transistors 700 and 704, and via its source to the gates of transistors 703 and 704. The current source 705 is connected between the supply voltage line VCC 2 and the gates of transistors 703 and 704. The sources of transistors 703 and 704 are also connected to the supply voltage line VCC 2。The drain of transistor 703 is connected to node 602. Transistors 702 to 704 connected to current source 705 form a current mirror circuit, which inverts the turn-off di / dt feedback current from transistor 700. The speed of the current mirror with transistors 703 and 704 is increased by adding transistor 702, which acts as a source follower. To increase the current mirror speed in both directions, current source 705 has been added. Further, diode 706 is inserted between the line carrying the voltage sense signal VSA and the drain of transistor 610.

[0044] Figure 7 The driver circuit shown in 2 also allows the ground GND 2 and the supply voltage VEE Figure 6 not to work simultaneously, so that a bipolar power supply can also be used to supply the gate driver. Further, the turn-off di / dt feedback does not directly feed current into the summing node by making the feedback load depend on, for example, the load condition of semiconductor device 106 and / or the resistor of its Miller plateau. For example, if the voltage change dv / dt is directly fed back from the collector of semiconductor device 106 through a capacitor (capacitor 520) to the summing node, then when the gate voltage of semiconductor device 106 is at the Miller plateau, the feedback current through the feedback capacitor (capacitor 520) will depend on the voltage change dv / dt at the collector of semiconductor device 106. However, if the current change di / dt is directly fed back through a resistor (such as

[0045] in Figure 7 the resistor 605 shown in 2When this occurs, the simple diode (diode 706) is set to be reverse-biased. The transistor 610 connected as a source follower via the resistor 611 automatically generates a transition from positive current regulation to negative current regulation. The current summing node (including the gate of the transistor 607) - having dV / dt through the capacitor 521 and di / dt across the inductor 107 - automatically transitions from dV / dt regulation to di / dt regulation. To make the feedback during turn-off independent of the load, the transconductance amplifier can be configured to differentially measure the voltage across the parasitic inductor 107 and then inject a high-side current that is independent of the summing node voltage into the summing node 602. When the semiconductor device 106 turns off, a concept similar to that for the di / dt feedback for the turn-on voltage change can be implemented to generate a current proportional to the voltage across the parasitic inductor 107. However, this current has the wrong polarity. To obtain the correct polarity of the current, a high-side current mirror (transistors 703 and 704) is employed. The transistors 702 and the current source 705 are used to achieve the necessary bandwidth in the current mirror. The methods outlined above can also be implemented using discrete devices, but when implemented in an integrated circuit, control of speed and control of parasitic elements may be more advantageous.

[0046] In the example described above Figures 1 to 7 the analog feedback stage and the digital feedback stage include signal delay times due to their respective signal processing. The signal delay time of the digital feedback stage may be greater than the delay time of the corresponding analog feedback stage. However, the precision of the digital feedback stage may be greater than the precision of the corresponding analog feedback stage. Further, the digital feedback stage or path may include not only digital circuits but also analog and digital (mixed) circuits.

[0047] In some cases, when the gate driver is turned on or off, the driver circuit of the embodiment may be prone to voltage overshoot, as illustrated in Figure 8A the waveform diagram. Figure 8A The trace 801 shown in the waveform diagram of out，driver represents the output voltage V of the gate driver circuit of the embodiment that is used to provide a drive voltage to, for example, the gate of the semiconductor device 106 out，driver . As shown, when the driver is activated, the output voltage V delay,on rises from the minimum voltage of Vss to the maximum voltage Vcc during the first part of the time period t out，driver . Eventually, the driver output voltage V Miller drops to the Miller plateau voltage V out，driver after the control loop of the driver circuit of the embodiment has had a chance to respond. The reason for the initial overshoot of the output voltage V delay,onis disconnected during the initial portion. Since the semiconductor device 106 is disconnected, no dV CE / dt and dI C / dt feedback is provided during this time period, and the driver output voltage V out，driver increases in an essentially unregulated manner until the semiconductor device 106 is turned on and dV CE / dt and dI C / dt feedback loop closes. During the initial delay phase, the feedback signals for both dV CE / dt and dI C / dt are zero while a non-zero reference signal has been applied. The controller struggles to wind up to achieve a non-zero dI C / dt according to the non-zero reference. Due to the winding up, the output of the gate driver may be limited to the driver supply voltage (here labeled Vcc). When the gate voltage reaches its threshold and the current through the switch starts to rise (achieving a positive dI C / dt feedback signal), the output of the driver needs to stabilize from the driver supply to the steady-state value for dI C / dt, which thus takes a longer delay time. During this time period, dI C / dt is unregulated. This voltage overshoot phenomenon is also referred to herein as "winding up" or "winding-up effect".

[0048] In some cases, the controller may wind up or overshoot in such a way that it is difficult or impossible for the controller to stabilize to the driver output voltage V out，driver and / or provide the required dV CE / dt and dI C / dt. In extreme cases, the driver output voltage V out，driver may remain unstable throughout the switching cycle.

[0049] In some conventional systems, the winding-up effect is mitigated by monitoring and controlling the gate current supplied to the gate of the switching device. In such a system, the gate current is monitored by measuring the voltage across a current sense resistor serially coupled to the gate of the switching device. Such a system may require additional pins to support the monitoring of the voltage across the current sense resistor. Additionally, the gate drive current for such a system may need to be recalibrated for different sizes of switching devices.

[0050] In an embodiment of the present invention, the winding-up effect is mitigated and / or eliminated by controlling the slew rate (dV out，Driver / dt) of the driver output voltage during the switching delay phase of turn-on and / or turn-off. The effect of this controlled slew rate control is provided by Figure 8AThe trace 803 in the waveform diagram represents the driver output voltage V when the slew rate of the output driver is under feedback control. out，Driver As can be seen in Figure 8A , the slew rate dV out，driver / dt of the driver output voltage can be controlled in such a way that the driver output voltage V out，driver smoothly approaches the Miller plateau V Miller without overshoot. However, it should be understood that Figure 8A the waveform diagram is a simple illustration of a single scenario. In some embodiments of the present invention, depending on the environment and configuration of the specific system, there may be a slight overshoot. Using the proposed dV out，Driver / dt control, the differences in gate voltage and gate current can be kept small, which reduces the settling time of the gate voltage. Therefore, dI C / dt at turn-on or dV CE / dt at turn-off can reach its steady-state value earlier.

[0051] Advantages of the gate driver system and method of the embodiments include the ability to mitigate the "snapping" effect in a power- and space-efficient manner. In some embodiments, the snapping effect can be mitigated without the need for additional external pins to support monitoring of the current sense resistor and / or without the need to recalibrate the system for different sizes of switching devices.

[0052] During operation, when the gate voltage is stabilized to the Miller plateau voltage V Miller using the slew rate control method of the embodiments, the dI C / dt and dV CE / dt control loops become effective. At this time, the dV out，Driver / dt feedback path of the embodiments can be deactivated to ensure that the amplifier output slew rate (dV out，driver / dt) is no longer restricted and can stabilize quickly. For example, this deactivation can be achieved by electrically disconnecting the feedback path from the controller. Alternatively, for example, in a case where the amplitude of the output of the dI C / dt and dV CE / dt feedback paths exceeds the output of the dV out，Driver / dt feedback path, the dV out，Driver / dt feedback path can remain effective. In some embodiments, the dV out，Driver / dt feedback path can be configured to provide feedback only in a single direction. For example, feedback can be provided for the positive slope of V out，Driver but not for the negative slope of V out，Driver , and vice versa.

[0053] Figure 8B Including the following waveform diagram: which shows the dV used in the embodiment out，Driver / dt slew rate control method's turn-on behavior compared to an exemplary example of a slew rate control method not using the embodiment. For example, trace 801 represents the gate driver output voltage for the exemplary example, while trace 803 illustrates the gate driver output voltage for an embodiment using the dV out，Driver / dt slew rate control method of the embodiment. As can be seen, compared to the exemplary embodiment, for the gate driver using the dV out，Driver / dt slew rate control method, the overshoot ΔV is significantly smaller.

[0054] Trace 805 represents the collector current I of semiconductor device 106 for an exemplary example of a slew rate control method not using the dV out，Driver / dt slew rate control method C , while trace 807 represents the collector current I for an embodiment using the slew rate control method of the embodiment. As can be seen, trace 807 exhibits less ringing compared to trace 805. Therefore, the system using the slew rate control method of the embodiment can be more easily controlled. Trace 809 represents the collector-emitter voltage V of semiconductor device 106 for an exemplary example of a slew rate control method not using the embodiment C , and trace 811 represents the collector current I for an embodiment using the slew rate control method of the embodiment CE . C .

[0055] Figure 8C Including the following waveform diagram: which shows the dV used in the embodiment out，Dirver / dt slew rate control method's turn-off behavior compared to an exemplary example of a slew rate control method not using the embodiment. For the exemplary example of a slew rate control method not using the embodiment, trace 821 represents the gate driver output voltage V out，Driver , trace 831 represents the collector current I C , and trace 841 represents the collector-emitter voltage V of semiconductor device 106 CE . For the embodiment in which dV is permanently enabled out，driver / dt control, trace 823 represents the gate driver output voltage V out，Driver , trace 833 represents the collector current I C , and trace 843 represents the collector-emitter voltage V of semiconductor device 106 CE . For the embodiment in which dV is disabled when not needed after the delay stage out，driverExample of dV / dt control, trace 825 represents the gate driver output voltage V out，Driver , trace 835 represents the collector current I C , and trace 845 represents the collector-emitter voltage V of semiconductor device 106 CE . As can be seen in Figure 8C , compared to the trace 823 representing the case where dV out，driver / dt control is permanently enabled, the trace 825 representing the case where dV out，driver / dt control is deactivated when not needed has a faster settling time after the time period t Delay,off . Thus, in some embodiments, dV out，driver / dt control is deactivated when dV out，driver / dt is positive, and dV out，driver / dt control is activated when dV out，driver / dt is negative. However, in other embodiments, acceptable performance can be achieved when dV out，driver / dt control is activated both when dV out，driver / dt is positive and negative, because the dv / dt of waveforms 823 and 825 have the same value after the Miller plateau.

[0056] In various embodiments, the delay time t out,driver can be directly controlled by controlling the slew rate dV Delay，on / dt of the driver, and the delay time t Delay，on is the time until the threshold of semiconductor device 106 is reached during turn-on:

[0057] (1)

[0058] where V th is the gate threshold voltage of semiconductor device 106, V off is the gate voltage in the off state (such as, for example, the often used values 0V, -8V or -15V), and ΔV is the error voltage described in more detail below.

[0059] During turn-off, the delay time t Delay，off is the time when the gate is discharged from the on-state voltage V on to the Miller plateau voltage V Miller . This gate turn-off time can be controlled by selecting an appropriate slew rate as follows:

[0060] (2)

[0061] The term ΔV in equations (1) and (2) represents the error due to not properly setting dV out，driver / dt is adjusted to the error voltage caused by the voltage difference accumulated during the delay. If the dV out,driver / dt under control is matched in such a way that the gate current during the delay is at the level of the gate current required later for subsequent control (dI C / dt at turn-on and dV CE / dt at turn-off), then it is at a value that will result in a smooth transition to the regulation that becomes effective later (dI C / dt at turn-on and dV CE / dt at turn-off). If dV out，driver / dt results in a final value of the gate voltage different from the Miller plateau voltage V Miller , a non-zero error voltage ΔV will be obtained, which results in a settling time t settle after the delay. Therefore, the subsequent dI C / dt or dV CE / dt regulation loop will require additional time (e.g., t settle ) to establish control. The error voltage ΔV can be expressed as follows:

[0062] (at turn-on) (3)

[0063] (at turn-off) (4)

[0064] where R G is the resistance serially coupled to the gate of the semiconductor device 106, I G，Delay is the value of the current flowing into the gate of the semiconductor device 106 during the switch delay when the control loop of dV out,driver / dt is effective, and I G，dV / dt is the value of the current flowing into the gate of the semiconductor device 106 during the V CE transient when the control loop of dV CE / dt is effective. Figure 8D and Figure 8E illustrate the waveform diagrams as follows: which provide a comparison between the driver output voltage V out,driver where the absolute value of the controlled dV out，driver / dt is too high (trace 851) and the driver output voltage V out，driver with a dV out，driver / dt that produces a zero error voltage ΔV (trace 853). Figure 8D shows the driver output voltage V out，driver at turn-on, and Figure 8E shows the driver output voltage V out，driver at turn-off. In some embodiments, dV out，driver / dt so that the error voltage ΔV approaches zero. However, in some embodiments, small residual errors may result in some practical applications.

[0065] In some embodiments, by adding an additional feedback branch dedicated to regulating dV out,Driver / dt to an existing embodiment driver circuit, in addition to regulating dI C / dt and dV CE / dt of the semiconductor device, the slew rate dV out，Driver / dt of the driver output voltage is also achieved, thereby allowing the use of a single PI controller to regulate dI C / dt, dV CE / dt and dV out，Driver / dt. The basic idea of this additional slew rate control is to prevent driver saturation (voltage saturation or current saturation) by controlling the slew rate (dV out，Driver / dt) of the amplifier output during the on and off switch delay phases. An example of such an embodiment circuit is shown in Figure 9A which illustrates a schematic diagram of a switching system 900.

[0066] As shown, the switching system 900 includes a semiconductor device 106 having a gate node G, and the gate node G is driven by an output amplifier 914 having an output coupled in series with a resistor 918. The amplifier 914 can also be referred to as a buffer circuit. The component feedback circuit provides the time derivatives of the load path voltage and load path current of the semiconductor device 106. In some embodiments, the component feedback circuit includes a first feedback path dedicated to the time derivative of the load path voltage of the semiconductor device 106 and a second feedback path dedicated to the time derivative of the load path current of the semiconductor device 106. The first feedback path configured to provide dV CE / dt feedback includes a differentiator 902 and a gain block 904 coupled between the collector node C of the semiconductor device 106 and a summing circuit 910; and the second feedback path configured to provide dI C / dt feedback includes a differentiator 920 and a gain block 922 coupled between the emitter node E of the semiconductor device 106 and the summing circuit 910. In some embodiments, a limiting circuit 924 is coupled between the gain block 922 and the summing circuit 910, while in other embodiments, the limiting circuit 924 is omitted and the output of the gain block 922 is coupled to the summing circuit 910.

[0067] The circuit further includes a gate drive feedback circuit, which can be implemented as being configured to provide dV out，DriverThe third feedback path of the / dt feedback includes a differentiator 916 and a gain block 906 coupled between the output of the amplifier 914 and the summing circuit 910. This gate drive feedback circuit may also be referred to as an anti-windup circuit. A single PI controller 912 is coupled between the output of the summing block 910 and the input of the output amplifier 914. The output of the summing block may be referred to as the error signal. In an alternative embodiment, the PI controller 912 may be implemented using other dynamic controller structures known in the art (such as P or PID controllers). In various embodiments, the polarities of the feedback signals provided by the various feedback loops and the summing circuit 910 are configured such that each loop provides negative feedback.

[0068] In various embodiments, a reference signal V ref，d / dt and / or I ref，d / dt is introduced at the input of the summing circuit 910 to provide an input reference signal for the control loop. In some embodiments, the signal V ref，d / dt is set to a value proportional to the target slew rate dV out，Driver / dt of the driver output voltage. In some embodiments, the reference signal V ref，d / dt and / or I ref，d / dt is asserted in response to a switch control signal (such as a pulse width modulation (PWM) signal).

[0069] The determination of the overall polarity of each feedback path can be set and determined anywhere within the signal path of each loop. For example, the negative feedback in dV CE / dt can be set by configuring the polarities of the differentiator 902, the gain block 904, and / or the summing circuit 910. It should be understood that although the feedback input to the summing circuit 910 is shown using an inverting input indicated by each corresponding negative sign "-", in an alternative embodiment, each input of the feedback summing block can be configured with the required polarity (positive or negative) to ensure negative feedback and / or stable operation.

[0070] In some embodiments, a switch 908 is coupled between the gain block 906 and the summing circuit 910. In one embodiment, the switch 908 couples the output of the gain block 906 to the summing circuit 910 when the signal EN SR-Ctrl is asserted and provides a zero output (or ground) to the summing circuit 910 when the signal EN SR-Ctrl is not asserted. In such an embodiment, the signal EN Miller is asserted during an initial time period t delay，on when the voltage at the gate node is approaching the Miller plateau V SR-Ctrl and then it is disabled. In other embodiments, the switch 908 may be omitted.

[0071] The summing circuit 910 can be implemented using analog summing circuits known in the art, such as operational amplifier-based adder circuits or current summing nodes. In some embodiments, the summing circuit 910 can be implemented as a node where currents are summed as described below with respect to Figure 11A and Figure 11B described.

[0072] In various embodiments, differentiators 902, 916, and 920 are implemented using differentiator structures known in the art, and gain blocks 904, 906, and 922 are implemented using various circuits known in the art to provide the gain or attenuation as described in the above embodiments. For example, differentiators 902, 916, and 920 can be implemented using capacitors or inductors, and gain blocks 904, 906, and 922 can be implemented using amplifiers or current mirrors. In some embodiments, one or more of the gain blocks 904, 906, and 922 can be omitted if the gain of the corresponding differentiator 902, 916, or 920 provides sufficient gain for the corresponding feedback path. In one embodiment described below, differentiator 916 is implemented using a capacitor, and gain block 906 is implemented using a current mirror.

[0073] Figure 9B FIG. shows a switching system 930 according to an alternative embodiment of the present invention. The switching system 930 is similar to Figure 9A the switching system 900 shown in, except that switch 908 is replaced by a switch 932 including diodes 952 and 954. In an embodiment, each of the diodes 952 and 954 represents a half-wave rectification operation that ensures that the feedback from dV out，Driver / dt is provided to the summing circuit 910 in a single direction (e.g., with a single polarity). For example, when the semiconductor switch 106 is turned on, the control signal EN SR-CTRL can be set to a first state to select diode 954. Thus, diode 954 allows the dV out，Driver / dt feedback in the positive direction to reach the summing circuit 910, but blocks the dV out，Driver / dt feedback in the negative direction. On the other hand, when the semiconductor switch 106 is turned off, the control signal EN SR-CTRL can be set to a second state to select diode 952. Thus, diode 952 allows the dV out，Driver / dt feedback in the negative direction to reach the summing circuit 910, but blocks the dV out,Driver / dt feedback in the positive direction.

[0074] In various embodiments, diodes 952 and 954 may be implemented using solid-state diode devices. Alternatively, other known circuits and systems that rectify signals and / or provide signals in a single polarity may be used. For example, a circuit such as a current source that operates in a single polarity may be used to implement diodes 952 and 954, as discussed further below.

[0075] Figure 10A The waveform diagram shown below depicts various signals within switch system 930 when semiconductor device 106 is turned on. As shown, trace 1002 represents the collector-emitter voltage V of semiconductor device 106 CE ; trace 1004 represents the load current of semiconductor device 106; trace 1006 represents the gate drive voltage V provided to the gate of semiconductor device 106 by amplifier 914 out，drv ; trace 1008 represents the gate current I provided to the gate of semiconductor device 106 by amplifier 914 G ; trace 1010 represents the switch control signal EN of diode 952 or 954 within selection switch 932 SR-Ctrl ; and trace 1012 represents the reference current I introduced into summing circuit 910 as a reference signal ref .

[0076] At time t 0 , when the reference current I ref (1012) transitions from zero to current I ref，on , the process of turning on semiconductor device 106 begins, and the switch control signal EN SR-Ctrl (1010) transitions to low, thereby selecting one of diodes 952 or 954 that allows dV in the positive direction out，Driver / dt feedback to reach summing circuit 910 but blocks dV in the negative direction out，Driver / dt feedback. During phase I between times t 0 and t 1 , the gate drive voltage V out，drv (1006) increases in a controlled manner at a constant slew rate (e.g., constant d Vout，driver / dt), while the gate current I G (1008) charges the gate of semiconductor device 106. The collector-emitter voltage V of semiconductor device 106 CE (1002) remains high and the load current of semiconductor device 106 remains at zero during phase I because the gate drive voltage V out，Driver (1006) has not yet reached the threshold voltage of semiconductor device 106.

[0077] At time t1 , at the start of Phase IIa, the gate drive voltage V out，Driver (1006) reaches the threshold of the semiconductor device, and the semiconductor device starts to turn on. During Phase II between time t 1A and t 1b , the load current I C (1004) of the semiconductor device 106 increases at a controlled rate dI C / dt set by the controller, which in most cases has the effect of reducing the slew rate dV out，drv (1006) of the gate drive voltage V out，driver / dt.

[0078] During the first part of Phase III (between time t 1B and t 2 ), the gate drive voltage V out，driver (1006) slightly overshoots beyond the Miller plateau voltage V Miller , causing a slight overshoot Î C on the load current I rr (1004) of the semiconductor device 106. During the second part of Phase III (between time t 2 and t 2A ), the gate drive voltage V out，Driver (1006) returns to the Miller plateau voltage V Miller , and the collector - emitter voltage V CE of the semiconductor device 106 decreases at a controlled rate dV CE / dt set by the controller. During Phase IV between time t 2A and t 3 , the collector - emitter voltage V CE (1002) of the semiconductor device 106 continues at a controlled rate dV CE / dt until the collector - emitter voltage V CE (1002) reaches zero. After time t 3 , the reference current I ref (1012) transitions back to zero, which effectively turns off the gate current I G (1008).

[0079] Figure 10B The waveform diagram is shown as follows: It shows various signals within the switching system 930 when the semiconductor device 106 is turned off. At time t 5 , when the reference current I ref (1012) transitions from zero to current I ref，off , the process of turning off the semiconductor device 106 starts, and the switch control signal ENSR-Ctrl (1010) transitions to high, thereby selecting one of the following diodes 952 or 954: which allows the dV out，Driver / dt feedback in the negative direction to reach the summing circuit 910, but blocks the dV out，Driver / dt feedback in the positive direction. At time t 5 and t 6 During phase VI between them, the gate drive voltage V out，drv (1006) decreases in a controlled manner at a constant slew rate (e.g., constant dV out，Driver / dt), while the gate current I G (1008) discharges the gate of the semiconductor device 106. During phase VI, the collector-emitter voltage V CE (1002) of the semiconductor device 106 remains low and the load current of the semiconductor device 106 remains at I load , because the gate drive voltage V out，Driver (1006) has not reached the Miller plateau voltage V Miller .

[0080] At time t 6 at the start of phase VIIa, the gate drive voltage V out，driver (1006) reaches the Miller plateau voltage V Miller , and the semiconductor device starts to turn off. At time t 6A and t 7 During phase VII between them, the collector-emitter voltage V CE (1002) of the semiconductor device 106 increases at a controlled rate dV CE / dt set by the controller, while the gate drive voltage V out，driver (1006) remains at the Miller plateau voltage V Miller . At time t 7 and t 7A During phase VIII between them, the gate drive voltage V out，Driver (1006) approaches the threshold voltage V th of the semiconductor device 106, while the load current I C (1004) of the semiconductor device 106 decreases at a controlled rate dI C / dt set by the controller.

[0081] At time t 7A and t 8 During phase IX between them, the gate drive voltage V out，Driver (1006) continues to decrease until the gate drive voltage V out，Driver (1006) at time t 8reaches a minimum at time t 8 , phase X begins and the reference current I ref (1012) transitions back to zero, effectively turning off the gate current I G (1008).

[0082] Figure 10C is a simplified waveform diagram that further illustrates the effect of selecting diodes 952 and 954 within switch 932 based on whether semiconductor device 106 is on or off. As shown, during the on-phase, when the switch control signal EN SR-Ctrl (1010) is low and allows dV out，Driver / dt feedback in the positive direction but blocks dV out，Driver / dt feedback in the negative direction, the gate drive voltage V out，drv (1006) increases in a controlled manner with a fixed slew rate in the positive direction. However, if the gate drive voltage V out，drv (1006) overshoots beyond the Miller plateau voltage V Miller , then as it approaches the Miller plateau voltage V Miller in the negative direction, the gate drive voltage V out，drv (1006) decreases more quickly (e.g., with a higher slope) to the Miller plateau voltage V Miller . This faster stabilization is due to the absence of dV out，Driver / dt in the negative direction.

[0083] Similarly, during the off-phase, when the switch control signal EN SR-Ctrl (1010) is high and allows dV out，Driver / dt feedback in the negative direction but blocks dV out，Driver / dt feedback in the positive direction, the gate drive voltage V out，drv (1006) decreases in a controlled manner with a fixed slew rate in the negative direction. However, if the gate drive voltage V out，drv (1006) undershoots beyond the Miller plateau voltage V Miller , then as it approaches the Miller plateau voltage V Miller in the positive direction, the gate drive voltage V out，drv (1006) increases more quickly (e.g., with a higher slope) to the Miller plateau voltage V Miller .

[0084] Figure 11A Illustrates dV of the illustrated embodiment out，DriverCircuit implementation of the / dt feedback loop. As shown, the output of amplifier 914 is monitored by a feedback circuit that includes capacitor 1102, followed by current mirror 1104, whose output is coupled to the input of amplifier 914 at current summing node 1106. In some embodiments, capacitor 1102 performs the function of differentiator 916, current mirror 1104 performs the function of gain block 906, and current summing node 1106 performs the function of summing circuit 910 shown in Figure 9A and Figure 9B . The current mirror 1104 can be implemented, for example, using current mirror and / or current amplifier circuits known in the art.

[0085] Reference current I ref，on is injected into the regulation loop through an arbitrary constant current source and is controlled by an on / off signal. The current is then converted to a voltage at the summing node at the input of the buffer. A positive reference current results in a positive dV out，driver / dt, and a negative reference current results in a negative dV out，driver / dt.

[0086] As shown in Figure 11A , once the output voltage V out of amplifier 914 changes, a displacement current I fb，SR is generated through capacitor 1102 having capacitance C fb，SR . This current is defined by the following formula

[0087] (5)

[0088] Therefore, the displacement current I fb，SR is proportional to the driver output slew rate dV out，driver / dt and contains information about the driver output slew rate dV out，driver / dt. This current is mirrored by a factor of N and fed back to the input of amplifier 914 to control the slew rate in a closed loop using negative feedback. Thus, the feedback gain of this additional control loop is determined by the capacitance C fb，SR of capacitor 1102 and the ratio N:1 of current mirror 1104. If the output voltage V out，driver drops and thus dV out，driver / dt is negative, the feedback currents I fb，SR and I fb，SRN change their directions and the decreasing slew rate is controlled. Thus, the value of dV out，driver / dt depends on these mentioned loop gain parameters (capacitor, current mirror ratio) and the reference current I ref，on .

[0089] In an alternative embodiment, the slew rate of the output voltage of amplifier 914 can also be directly controlled at the gate of semiconductor device 106 (at the node between gate resistor 918 and the power switch). In a further embodiment, gate resistor 918 can also be removed (set to zero) such that the output of amplifier 914 and the gate of the IGBT are at the same node and its slew rate is controlled.

[0090] Figure 11B Illustrated is the circuit implementation of the dV out，Driver / dt feedback loop according to a further embodiment of the present invention. As shown, the functions of gain block 906 and switch 932 (including the functions of diodes 952 and 954) shown in Figure 9B are implemented using a selectable current source including NMOS transistors MN1, MN2, and MN3 and PMOS transistors MP1, MP2, and MP3. The functions of differentiator 916 shown in Figure 9B are implemented using capacitors 1112 and 1114.

[0091] When control signal EN SR-CTRL is low, the low-side current mirror implemented by NMOS transistors MN1 and MN2 is enabled by turning off NMOS transistor MN3, and the high-side current mirror implemented by PMOS transistors MP1 and MP2 is disabled by coupling the gates of PMOS transistors MP1 and MP2 to Vcc2 by turning on PMOS transistor MP3. During operation, the output of amplifier 914 is coupled to diode-connected NMOS transistor MN1 via capacitor 1114. NMOS transistor MN2, whose gate is coupled to the gate of NMOS transistor MN1, mirrors the current flowing in transistor MN1 to the input of amplifier 914 to provide positive slew rate control. In some embodiments, the width of NMOS transistor MN2 is N times the width of NMOS transistor MN1 to achieve a current gain of N.

[0092] When control signal EN SR-CTRLWhen it is high, the low-side current mirror implemented by NMOS transistors MN1 and MN2 is disabled by turning on NMOS transistor MN3, thereby turning off NMOS transistors MN1 and MN2. The high-side current mirror implemented by PMOS transistors MP1 and MP2 is enabled by turning off PMOS transistor MP3. During operation, the output of amplifier 914 is coupled to diode-connected PMOS transistor MP1 via capacitor 1112. PMOS transistor MP2, whose gate is coupled to the gate of PMOS transistor MP1, mirrors the current flowing in transistor MP1 to the input of amplifier 914 to provide negative slew rate control. In some embodiments, in order to achieve a current gain N, the width of PMOS transistor MN2 is N times the width of PMOS transistor MP1.

[0093] In various embodiments, the current mirror ratio N is selected to provide the desired dV out，Driver / dt feedback level. In some embodiments, the current mirror ratio N can be programmable and / or fine-tunable. In further embodiments, the ratio of the widths of PMOS transistors MP1 and MP2 can be different from the ratio of the widths of NMOS transistors MN1 and MN2. In some embodiments, the amount of dV out，Driver / dt feedback can also be set by selecting the sizes of capacitors 1112 and 1114.

[0094] It should be appreciated that using a current mirror to provide current feedback between the output and input of amplifier 914 provides the ability to provide feedback in a single direction. For example, when an NMOS current mirror is selected, only the positive slew rate of the output voltage of amplifier 914 is mirrored to the input of amplifier 914, while the negative slew rate of the output voltage of amplifier 914 essentially turns off the NMOS current mirror. Similarly, when a PMOS current mirror is selected, only the negative slew rate of the output voltage of amplifier 914 is mirrored to the input of amplifier 914, while the positive slew rate of the output voltage of amplifier 914 essentially turns off the PMOS current mirror. Thus, using a current mirror in the Figure 11B embodiment circuit essentially performs the rectifying function of diodes 952 and 954 shown in the Figure 9B embodiment and affects the system performance described above with respect to Figure 10C . It should be further appreciated that the circuit implementation examples shown in Figure 11A and Figure 11B are just two specific examples among many possible example implementations. In alternative embodiments of the present invention, different transistor types and different current mirror / current amplifier topologies known in the art can be used to implement the dV out，Driver / dt feedback circuit.

[0095] Figure 12AIllustrated is an example driver integrated circuit 1200 coupled to a semiconductor device 106, which implements the example dV out，Driver / dt control technique. Similar to Figure 5 、 Figure 6 and Figure 7 example, the driver integrated circuit 1200 includes a low-voltage circuit section 1201 and a higher-voltage circuit section 1203 that is electrically isolated from the low-voltage circuit section. The low-voltage circuit section 1201 includes an under-voltage lockout (UVLO) block 501 that receives the (positive) supply voltage VCC 1 of the integrated circuit device 500 and a first ground GND 1 to which the integrated circuit device 500 refers, as explained above with respect to Figure 5 . The low-voltage circuit section 1201 also includes a logic block 502, a clock signal generator 503, and an electrically isolated signal coupler 505, as explained above with respect to Figures 5 to 7 . The higher-voltage circuit section 1203 of the driver integrated circuit 1200 includes a control block 506, a clock signal generator 507, and an under-voltage lockout block 508, also as explained above with respect to Figures 5 to 7 . In some embodiments, the integrated circuit 1200 is implemented on a single semiconductor substrate. Alternatively, the low-voltage circuit section 1201 is implemented on a first single semiconductor substrate, and the higher-voltage circuit section 1203 is implemented on a second single semiconductor substrate. In further alternative embodiments, the integrated circuit 1200 may be differently partitioned. For example, all or part of the integrated circuit 1200 may be implemented using discrete circuit elements.

[0096] The higher-voltage circuit section 1203 also includes an amplifier 914 that has an output coupled to the gate of the semiconductor device 106 via a resistor 918 and an input coupled to a dynamic controller 1220. Although the dynamic controller 1220 is depicted as a PI controller, it should be understood that any suitable dynamic controller known in the art may be used. The summing node is implemented as a current summing node at the input to the dynamic controller 1220. Three feedback paths provide feedback from the output of the amplifier 914 or from the semiconductor device 106 back to the input of the amplifier 914. dV CE / dt feedback path includes a capacitor 520 coupled between the collector of the semiconductor device 106 and the input of the dynamic controller 1220; dI C / dt feedback path includes a parasitic inductance 107 and a dI C / dt feedback block 1208 coupled between the emitter of the semiconductor device 106 and the input of the dynamic controller; and the example dV out，DriverThe dV / dt feedback path includes a dV / dt feedback block 1206 coupled between the output of the amplifier 914 and the input of the dynamic controller 1220. A reference current is introduced to the input of the dynamic controller 1220 via a digitally controlled current source 1204, which is configured to generate a current based on a digital word generated by the control block 506 and a level shifted by the level shifter block 1202. As depicted in out，Driver a digitally controlled current source 1204 includes a digital-to-analog converter followed by a controllable current source for generating the reference current I Figure 12A . The level shifter block 1202 is configured to level shift a digital signal obtained from the control block 506 and generate an input for the digitally controlled current source 1204 and a switch / polarity signal EN ref for the embodiment. SR-Ctrl

[0097] In various embodiments, the dI / dt feedback block 1208 monitors the voltage across the parasitic inductor 107 and provides a current proportional to the first derivative of the collector current of the semiconductor device 106. Various circuits and systems disclosed in C can be used to implement the structure of the dI / dt feedback block 1208 for monitoring dI / dt via the parasitic inductor 107. Figures 1 to 7 C C

[0098] The dV / dt feedback block 1206 includes a dV / dt feedback circuit of the embodiment described hereinabove with respect to out,Driver Figure 9A , Figure 9B , Figure 11A and Figure 11B . For example, in some embodiments, the dV / dt feedback block 1206 includes a capacitor serially coupled with a controllable current source (such as a current mirror as depicted in out,Driver ). In embodiments that provide dV / dt in a single direction depending on whether the semiconductor device 106 is turned on or off, the dV / dt feedback block 1206 may include a pair of selectable current mirrors having respective input capacitors serially coupled to the input of each respective current mirror, such as described above with respect to out，Driver Figure 9A . The effective current mirror can be selected according to the control signal EN out，Driver . In some embodiments, the dV / dt feedback block 1206 includes a differentiator serially coupled with a gain block and a switch, as described with respect to out，Driver Figure 11B . In some embodiments, the dV / dt feedback block 1206 includes a differentiator serially coupled with a gain block and a switch, as described with respect to SR-CTRL . The effective current mirror can be selected according to the control signal EN out，Driver . In some embodiments, the dV / dt feedback block 1206 includes a differentiator serially coupled with a gain block and a switch, as described with respect toFigure 9A and Figure 9B as described. The switch can be configured to enable or disable dV out，Driver / dt ( Figure 9A ), or can be configured to select a diode and / or a rectification direction based on a control signal EN SR-CTRL to select a diode and / or a rectification direction based on a control signal EN

[0099] Figure 12B FIG. illustrates an exemplary driver integrated circuit 1200 coupled to a semiconductor device 106 according to a further embodiment of the present invention. Figure 12B The embodiment of Figure 12A is similar to Figure 12B where an external booster stage 1222 is added between the output of the amplifier 914 and the gate of the semiconductor device 106. The external booster stage 1222 can be used in embodiments where the semiconductor device 106 is very large and additional drive is required to operate the device.

[0100] It should be appreciated that Figure 12A and Figure 12B the implementations shown in

[0101] are just two of the many possible exemplary system implementations that can be used to implement an exemplary gate drive system.

[0102] Example 1. A gate drive circuit for controlling a gate-controlled component, comprising: a dynamic controller configured to receive an input reference signal and control a gate voltage of the gate-controlled component via an output terminal of the gate drive circuit; at least one component feedback circuit for the dynamic controller, the at least one component feedback circuit being configured to provide feedback to the dynamic controller from at least one of: a time derivative of a load path voltage of the gate-controlled component or a time derivative of a load path current of the gate-controlled component; and a gate drive feedback circuit for the dynamic controller, the gate drive feedback circuit being configured to provide feedback from a time derivative of a voltage at the output terminal of the gate drive circuit.

[0103] Example 2. The gate drive circuit according to Example 1, further comprising a buffer circuit having an input coupled to an output of the dynamic controller and an output coupled to the output terminal of the gate drive circuit.

[0104] Example 3. The gate drive circuit according to Example 2, wherein the buffer circuit and the dynamic controller are deployed on a single semiconductor substrate.

[0105] Example 4. The gate drive circuit according to any one of Examples 1 to 3, wherein the dynamic controller includes a proportional integral (PI) controller.

[0106] Example 5. The gate drive circuit according to any one of Examples 1 to 4, wherein when the gate drive circuit turns on the gate-controlled component, the gate drive feedback circuit has a first gain of a first polarity; and when the gate drive circuit turns off the gate-controlled component, the gate drive feedback circuit has a second gain of a second polarity, wherein the first polarity and the second polarity are configured to provide negative feedback.

[0107] Example 6. The gate drive circuit according to Example 5, wherein the gate drive feedback circuit is further configured to rectify the feedback of the time derivative of the voltage at the output terminal of the gate drive circuit.

[0108] Example 7. The gate drive circuit according to either Example 5 or Example 6, wherein the gate drive feedback circuit is configured to limit the positive slew rate of the voltage at the output terminal of the gate drive circuit when the gate drive circuit turns on the gate-controlled component; and the gate drive feedback circuit is configured to limit the negative slew rate of the voltage at the output terminal of the gate drive circuit when the gate drive circuit turns off the gate-controlled component.

[0109] Example 8. A circuit, comprising: a gate driver circuit having an output coupled to a gate drive terminal configured to be coupled to the gate of a switching transistor; a dynamic controller having an output coupled to an input of the gate driver circuit; a summing circuit having an output coupled to an input of the dynamic controller and a first input configured to receive a reference signal; at least one feedback circuit coupled between a voltage measurement terminal and a second input of the summing circuit, the at least one feedback circuit being configured to provide a signal proportional to at least one of the derivative of the load path voltage of the switching transistor and the derivative of the load path current of the switching transistor to the second input of the summing circuit; and an anti-aliasing circuit coupled between the output of the gate driver circuit and a third input of the summing circuit, the anti-aliasing circuit being configured to provide a signal proportional to the derivative of the output voltage of the gate driver circuit to the third input of the summing circuit.

[0110] Example 9. The circuit according to Example 8, further comprising a switching transistor.

[0111] Example 10. A circuit according to one of Example 8 or Example 9, wherein the at least one feedback circuit includes: a first feedback circuit configured to provide a first signal proportional to the derivative of the load path voltage to a second input of the summing circuit; and a second feedback circuit configured to provide a second signal proportional to the derivative of the load path current of the switching transistor to a fourth input of the summing circuit.

[0112] Example 11. The circuit according to Example 10, further comprising a limiting circuit coupled between an output of the second feedback circuit and the fourth input of the summing circuit.

[0113] Example 12. A circuit according to one of Example 8 to Example 11, wherein the anti-aliasing circuit is configured to: apply a first gain to a signal proportional to the derivative of the output voltage of the gate driver circuit when the gate driver circuit turns on the switching transistor; and apply a second gain to a signal proportional to the derivative of the output voltage of the gate driver circuit when the gate driver circuit turns off the switching transistor.

[0114] Example 13. The circuit according to Example 12, wherein the anti-aliasing circuit includes: a first current mirror having an output coupled to a third input of the summing circuit; and a first capacitor coupled between the output of the gate driver circuit and the input of the first current mirror.

[0115] Example 14. The circuit according to Example 13, wherein the anti-aliasing circuit further includes: a second current mirror having an output coupled to a third input of the summing circuit; and a second capacitor coupled between the output of the gate driver circuit and the input of the second current mirror.

[0116] Example 15. The circuit according to Example 14, wherein the first current mirror has a mirror ratio different from that of the second current mirror.

[0117] Example 16. A circuit according to one of Example 12 to Example 15, wherein the first gain includes a first polarity and the second gain includes a second polarity opposite to the first polarity, and wherein the first polarity and the second polarity are configured to provide negative feedback.

[0118] Example 17. The circuit according to one of Example 8 to Example 16, further comprising an external booster stage having an input coupled to the gate drive terminal and an output configured to be coupled to the gate of the switching transistor.

[0119] Example 18. A method of driving a switching transistor, comprising: driving a switching transistor with a gate drive signal; measuring at least one of a derivative of a load path voltage of the switching transistor and a derivative of a load path current of the switching transistor; measuring a derivative of the gate drive signal; forming an error signal based on a reference signal, the measured derivative of the gate drive signal, and at least one of the measured derivative of the load path voltage of the switching transistor or the measured derivative of the load path current of the switching transistor; and forming the gate drive signal, wherein forming the gate drive signal includes processing the error signal using a dynamic controller.

[0120] Example 19. The method according to Example 18, wherein forming the gate drive signal further includes: generating a control signal using a dynamic controller; driving an input of a gate drive circuit with the control signal; and generating the gate drive signal using the gate drive circuit.

[0121] Example 20. The method according to one of Example 18 or Example 19, wherein driving the switching transistor with the gate drive signal includes driving a boost stage with the gate drive signal, wherein an output of the boost stage is coupled to a gate of the switching transistor.

[0122] Example 21. The method according to one of Example 18 to Example 20, wherein the dynamic controller is a proportional integral (PI) controller.

[0123] Example 22. The method according to one of Example 18 to Example 21, further comprising: applying a first gain to the measured derivative of the gate drive signal before forming the error signal when turning on the switching transistor; and applying a second gain to the measured derivative of the gate drive signal before forming the error signal when turning off the switching transistor.

[0124] Example 23. The method according to Example 22, further comprising: providing only the measured derivative of the gate drive signal of a first polarity before forming the error signal when turning on the switching transistor; and providing only the measured derivative of the gate drive signal of a second polarity before forming the error signal when turning off the switching transistor, wherein the second polarity is opposite to the first polarity.

[0125] Example 24. The method according to Example 23, wherein the first polarity represents a positive slew rate of the gate drive signal; and the second polarity represents a negative slew rate of the gate drive signal.

[0126] Example 25. The method according to Example 22, wherein the first gain includes a first polarity, and the second gain includes a second polarity opposite to the first polarity.

[0127] Example 26. The method according to any one of Examples 18 to 25 further comprises receiving a switch control signal and generating a reference signal based on the received switch control signal.

[0128] Example 27. The method according to Example 26, wherein the switch control signal comprises a pulse width modulation signal.

[0129] Although the invention has been described with reference to illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to this description. Accordingly, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A circuit for driving a switching transistor, comprising: A gate driver circuit having an output coupled to a gate drive terminal configured to be coupled to the gate of the switching transistor; A dynamic controller having an output coupled to an input of the gate driver circuit; A summing circuit having an output coupled to an input of the dynamic controller and a first input configured to receive a reference signal; At least one feedback circuit coupled between a voltage measurement terminal and a second input of the summing circuit, the at least one feedback circuit being configured to provide a signal proportional to at least one of a derivative of the load path voltage of the switching transistor and a derivative of the load path current of the switching transistor to the second input of the summing circuit; and An anti-aliasing circuit coupled between the output of the gate driver circuit and a third input of the summing circuit, the anti-aliasing circuit being configured to provide a signal proportional to a derivative of the output voltage of the gate driver circuit to the third input of the summing circuit, wherein the anti-aliasing circuit is configured to: Apply a first gain to the signal proportional to the derivative of the output voltage of the gate driver circuit when the gate driver circuit turns on the switching transistor; and Apply a second gain to the signal proportional to the derivative of the output voltage of the gate driver circuit when the gate driver circuit turns off the switching transistor, wherein the anti-aliasing circuit includes: A first current mirror having an output coupled to the third input of the summing circuit; and A first capacitor coupled between the output of the gate driver circuit and the input of the first current mirror.

2. The circuit according to claim 1, further comprising a switching transistor.

3. The circuit according to claim 1, wherein the at least one feedback circuit includes: A first feedback circuit configured to provide a first signal proportional to the derivative of the load path voltage to the second input of the summing circuit; and A second feedback circuit configured to provide a second signal proportional to the derivative of the load path current of the switching transistor to a fourth input of the summing circuit.

4. The circuit according to claim 3, further comprising a limiting circuit coupled between the output of the second feedback circuit and the fourth input of the summing circuit.

5. The circuit according to claim 1, wherein the anti-aliasing circuit further includes: A second current mirror having an output coupled to the third input of the summing circuit; and A second capacitor coupled between the output of the gate driver circuit and the input of the second current mirror.

6. The circuit according to claim 5, wherein the first current mirror has a different mirror ratio from the second current mirror.

7. The circuit according to claim 1, wherein the first gain includes a first polarity and the second gain includes a second polarity opposite to the first polarity, wherein the first polarity and the second polarity are configured to provide negative feedback.

8. The circuit according to claim 1, further comprising an external booster stage having an input coupled to the gate drive terminal and an output configured to be coupled to the gate of the switching transistor.

9. A method of using the circuit according to any one of claims 1 to 8 to drive a switching transistor, the method comprising: Drive a switching transistor using a gate drive signal; Measure at least one of a derivative of a load path voltage of the switching transistor and a derivative of a load path current of the switching transistor; Measure a derivative of the gate drive signal; Form an error signal based on a reference signal, the measured derivative of the gate drive signal, and at least one of the measured derivative of the load path voltage of the switching transistor or the measured derivative of the load path current of the switching transistor; And Form a gate drive signal, wherein forming the gate drive signal includes processing the error signal using a dynamic controller.

10. The method according to claim 9, wherein forming the gate drive signal further includes: Generate a control signal using a dynamic controller; Drive an input of a gate drive circuit using the control signal; And Generate a gate drive signal using the gate drive circuit.

11. The method according to claim 9, wherein driving the switching transistor using the gate drive signal includes driving a booster stage using the gate drive signal, wherein an output of the booster stage is coupled to a gate of the switching transistor.

12. The method according to claim 9, wherein the dynamic controller is a proportional integral (PI) controller.

13. The method according to claim 9, further includes: Apply a first gain to the measured derivative of the gate drive signal before forming the error signal when turning on the switching transistor; And Apply a second gain to the measured derivative of the gate drive signal before forming the error signal when turning off the switching transistor.

14. The method according to claim 13, furtherincludes: Provide only the measured derivative of the gate drive signal of a first polarity before forming the error signal when turning on the switching transistor; And Provide only the measured derivative of the gate drive signal of a second polarity before forming the error signal when turning off the switching transistor, wherein the second polarity is opposite to the first polarity.

15. The method according to claim 14, wherein: The first polarity represents a positive slew rate of the gate drive signal; and The second polarity represents a negative slew rate of the gate drive signal.

16. The method according to claim 13, wherein the first gain includes a first polarity, and the second gain includes a second polarity opposite to the first polarity.

17. The method according to claim 9, further includes receiving a switch control signal and generating a reference signal based on the received switch control signal.

18. The method according to claim 17, wherein the switch control signal includes a pulse width modulation signal. ​

Images