Startup of a boost power converter with switched capacitor network

Abstract

This application discloses start-up of a boost power converter having a switched capacitor network. The boost power converter has stacked nodes, each of the stacked nodes connected to a stacked switch and a pump capacitor to form the switched capacitor network. There are first and second of the stacked nodes. The second stacked node drives a particular stacked switch of a plurality of stacked switches. When all of the stacked switches are off, a first voltage causes the first stacked node to have a first stacked node voltage and causes the second stacked node to have a second stacked node voltage that is less than the first stacked node voltage. During a first state, the second stacked node voltage is insufficient to drive the particular stacked switch. During a second state, the second stacked node voltage is sufficient to drive the particular stacked switch. Transitioning the switched capacitor network from the first state to the second state includes, among other things, causing the second stacked node voltage to become sufficient to drive the particular stacked switch.

Description

Technical Field

[0001] This invention relates to power converters, and more specifically, to the startup of a switched capacitor network in a power converter. Background Technology

[0002] Electronic devices typically require a stable DC power supply to operate correctly. Batteries may not provide this, as their voltage drops as they discharge. Therefore, methods must be found to provide electronic devices with a stable voltage.

[0003] A useful solution is a boost converter, which converts the decreasing voltage of a battery into a stable voltage tuned to the needs of the device. At the heart of many such converters is a capacitor network. In such a network, charge flows from one capacitor to the next in such a way that the voltage at its output is either a multiple or a reciprocal of an integer. The former is used as a boost converter, and the latter as a buck converter. Because their operation is similar to that of a pump, such networks are often called "charge pumps."

[0004] In some cases, diodes are strategically placed between capacitors to prevent charge that has been pumped to a higher voltage from flowing back to the lower voltage from which it originated. This method has the advantage of being passive and therefore requires no control.

[0005] In other cases, active switches are used instead of passive diodes. The use of active switches increases complexity because a controller must now be provided to control when the active switch is turned on and off. However, the resulting charge pump section is more efficient because the inherent voltage drop across the PN junction of the diode is no longer necessary. This can sometimes reduce the number of stages required to perform voltage transformation. This type of capacitor network is often referred to as a "switched capacitor network."

[0006] Switched capacitor networks have switches that interconnect various capacitors in different configurations. The switches themselves are typically implemented using transistors. Accordingly, in order to turn the switch on and off, a sufficient voltage must be applied across the gate and source terminals of the transistor. The natural question that arises is where this voltage should come from. Summary of the Invention

[0007] This invention provides a method for assisting the switched capacitor network during startup, enabling it to achieve self-sustaining operation as quickly as possible and over a wide range of input voltages.

[0008] In one aspect, the invention features a boost power converter with stacked nodes, each of which is connected to a stacked switch and a pump capacitor to form a switched capacitor network. The network has an input terminal receiving a first voltage and an output terminal outputting a second voltage exceeding the first voltage. A controller uses the first voltage to transition the switched capacitor network from operation in a first state to operation in a second state. Among these stacked nodes are a first stacked node and a second stacked node. The second stacked node drives a specific stacked switch among a plurality of stacked switches. When all stacked switches are open, the first voltage causes the first stacked node to have a first stacked node voltage and causes the second stacked node to have a second stacked node voltage less than the first stacked node voltage. During the first state, the second stacked node voltage is insufficient to drive the specific stacked switch. In the second state, the second stacked node voltage becomes sufficient to drive the specific stacked switch. Transitioning the switched capacitor network from the first state to the second state includes, among other aspects, making the second stacked node voltage sufficient to drive the specific stacked switch.

[0009] In another aspect, the present invention includes a boost power converter comprising a controller, stacked switches, and stacked nodes. Each stacked node is connected to one of the stacked switches and to a pump capacitor to form a switched capacitor network having input terminals and output terminals. The input terminals receive a first voltage, while the output terminals output a second voltage exceeding the first voltage. Among these stacked nodes are a first stacked node and a second stacked node. The second stacked node drives one of the stacked switches. The controller uses the first voltage to transition the switched capacitor network from operation in a first state to operation in a second state. In the first state, the first stacked node has a first stacked node voltage and the second stacked node has a second stacked node voltage, which is less than the first stacked node voltage and insufficient to drive the stacked switch that should be driven. In the second state, the second stacked node has generated a voltage sufficient to drive the stacked switch.

[0010] Some implementations include a latching circuit configured to transition to a state whereby the latching circuit prevents a particular stack switch from being driven by a second stack node. This is particularly useful because stack switches are typically implemented as transistors with a body diode. Although less efficient, operation can rely on this body diode until the second stack node has accumulated sufficient voltage to reliably operate the transistor. Therefore, the latching circuit prevents the second stack node from prematurely attempting to operate the stack switch before obtaining the voltage required to do so.

[0011] Other implementations include a latching circuit configured to prevent a specific stack switch from being driven by a second stack node when the voltage of that second stack node falls below a predetermined threshold. This is particularly important because different second stack nodes will reach their desired voltage at different times. For example, a second stack node closer to the circuit input will have a lead in reaching its target voltage compared to a second stack node farther from the circuit input. Consequently, these will tend to reach their target voltage faster. By switching to the use of switches instead of body diodes, the inherent body diode voltage drop can be bypassed more quickly, thus accelerating the rate at which the remaining stack nodes rise toward their target operating voltage. Because of this characteristic, there will be a period during the network's operational startup where some, but not all, stack switches will be operated.

[0012] Another embodiment includes a comparator having a first input, a second input, and an output. The first input is connected to a predetermined threshold voltage, while the second input is connected to a voltage dependent on a second stack node voltage. The comparator output indicates whether the voltage dependent on the second stack node voltage is equal to or greater than the predetermined threshold voltage. This signal selectively prevents the second stack node voltage from being used to operate a specific stack switch.

[0013] These embodiments also include those where first and second resistors are connected across the supply voltage to form a voltage divider. These embodiments also include a comparator having a first input, a second input, and an output, wherein the first input is connected to a node between the first and second resistors, and the second input is connected to a voltage source providing a predetermined threshold voltage. In these embodiments, a signal at the output indicates whether the predetermined threshold voltage is less than the voltage at the node. This signal is used to selectively prevent the voltage of the second stack node from being used to operate a specific stack switch.

[0014] In yet another embodiment, the switched capacitor network includes first and second stacked nodes. A first pump capacitor is connected to the first stacked node, and a second pump capacitor is connected to the second stacked node. A plurality of stacking switches connect the second stacked node to an input terminal. A bypass path extends between the input terminal and the second stacked node. This bypass path bypasses the first stacked node, the plurality of stacking switches, and the first pump capacitor.

[0015] In some implementations, the power converter includes a path that connects an input terminal to a second stack node and bypasses at least one other stack node. This path becomes ineffective when the switched capacitor network begins to transition from a first state to a second state. However, during the first state, this path is used to bias each stack node at least partially to its required operating voltage to give the stack nodes a head start when the switched capacitor network next starts up and transitions from the first state to the second state.

[0016] Another implementation includes multiple bypass paths, each of which extends between one of the stacked nodes and the input terminal. When the switched capacitor network transitions from a first state to a second state, none of the bypass paths can conduct current from the input terminal to each of the stacked nodes.

[0017] Some implementations include a diode along a path connecting a first terminal and a second stacked node. This path bypasses at least one of the stacked nodes. The diode blocks current from the second stacked node to the input terminal during both a first and a second state. During the first state, current flows through this path. The current stops after the transition to the second state.

[0018] Another embodiment includes a switch along a path connecting the first terminal and the first pump capacitor, the path bypassing at least one other pump capacitor in the process. The switch is closed during a first state and open during a second state.

[0019] Other implementations include a path connecting the input terminal to the output terminal. During a first state, current flows along this path between the input and output terminals. This current stops during a second state.

[0020] Other embodiments include those that include a switch connected to the input terminal. In these embodiments, the controller controls the switch to present a voltage with a predetermined switching rate at the input terminal.

[0021] In some implementations, an intermediate capacitor is connected to the input terminal of the charge pump, and an inductor is located between the input port of the power converter and the input terminal of the charge pump. A switch selectively connects and disconnects an LC filter from the input terminal. A controller times the opening and closing of the switch to induce current in the LC filter, thereby transferring charge to the intermediate capacitor. Although the amount of charge is typically insufficient to bring the pump capacitor to the required voltage, it can still be used to assist in this process. It also times the opening of the switch to prevent charge stored in the intermediate capacitor from escaping towards the LC filter.

[0022] In yet another embodiment, a boost converter is connected between the input port of the power converter and the input terminal of the charge pump. A controller controls the boost converter to supply voltage to the input terminal. The voltage supplied to the input terminal exceeds the voltage supplied to the input port.

[0023] In other embodiments, the switched capacitor network includes a phase switch connected to one of the pump capacitors opposite one of the stacked nodes. In these embodiments, the controller operates the phase switch to cause a first voltage breakdown during a first state.

[0024] In yet another embodiment, during the first state, the controller operates the switched capacitor network to cause a first voltage collapse, thereby causing a current directed toward the switched capacitor network so that the voltage at the input terminal exceeds the first voltage.

[0025] Among these embodiments, there is also an embodiment in which the controller operates the switched capacitor network during the first state to control the switching rate of the first voltage. Attached Figure Description

[0026] These and other features of the invention will become apparent from the following detailed description and accompanying drawings, in which:

[0027] Figure 1 A boost power converter including a switched capacitor network is shown;

[0028] Figure 2 It shows Figure 1 Details of the 1:5 boost switched capacitor network of the power converter are shown in the figure.

[0029] Figure 3 It shows Figure 2 A switched capacitor network, in which a transistor switching body diode is shown;

[0030] Figure 4 An implementation of a first bypass switch network is shown, connecting switches and / or diodes from the input to the respective stack nodes and outputs;

[0031] Figure 5 An implementation of a second bypass switch network with some of the switches and / or diodes connected between intermediate stack nodes is shown;

[0032] Figure 6 It shows Figure 3 A switched capacitor network, wherein the switching is implemented by transistors, each transistor being driven by a gate drive block that is de-energized by the respective stacked nodes;

[0033] Figures 7 to 8 An example of a gate drive block and an implementation of a gate driver are shown;

[0034] Figure 9 It shows Figure 6 A switched capacitor network, wherein alternative P-type transistors are implemented for high-side phase switching;

[0035] Figure 10 It shows Figure 6 A switched capacitor network, wherein an alternative bias scheme is used for gate driver control of high-side phase switching;

[0036] Figure 11 It shows Figure 1The diagram shows a two-phase 1:5 boost switched capacitor network for a power converter.

[0037] Figures 12 to 13 An example of a gate drive block with undervoltage lockout and an implementation of undervoltage lockout are shown;

[0038] Figure 14 A boost power converter including a switched capacitor network and insulation elements is shown;

[0039] Figure 15 The thermal insulation element shown includes an inductor. Figure 14 A first example of a power converter;

[0040] Figure 16 The diagram shows thermal insulation elements including inductors, switches, and / or diodes. Figure 14 A second example of a power converter;

[0041] Figure 17 It shows Figure 16 The implementation of the start switch in the thermal insulation element;

[0042] Figure 18 The state transitions for controlling one or more starter switches prior to charge pump operation are shown;

[0043] Figure 19 The insulation element shown includes a regulator. Figure 14 A third example of a power converter; and

[0044] Figures 20 to 22 It shows in Figure 19 An example of a regulator used in a power converter is shown in the image. Detailed Implementation

[0045] Figure 1 A power converter 10 is shown. The power converter 10 receives an input voltage V provided by a voltage source 12. IN The input voltage V IN Transformed into output voltage V OUT And make the output voltage V OUT At output capacitor 14, load 15 is connected across output capacitor 14. Power converter 10 is a boost power converter. Therefore, the output voltage V OUT Exceeding the input voltage V IN The power converter 10 includes a charge pump 20 and a regulator 18.

[0046] The power converter 10 is typically one of many components within a host device or "host". A typical host may have a voltage source, such as a battery. However, the battery voltage may change over time. Additionally, hosts often have different components, each with different voltage requirements. Therefore, it is useful for a typical host to have some means of converting the available voltage to the desired voltage. The power converter 10 is used for this purpose.

[0047] Now refer to Figure 2 The charge pump 20 receives input voltages across first and second charge pump terminals 61, 62 and generates output voltages across third and fourth charge pump terminals 63, 64. The charge pump 20 includes a cascade multiplier 65 and a charge pump controller 66. In the illustrated embodiment, the cascade multiplier 65 is a single-phase symmetrical cascade multiplier.

[0048] The cascade multiplier 65 includes first, second, third, fourth, and fifth stacked switches S1, S2, S3, S4, and S5. Among these stacked switches, the first, third, and fifth stacked switches S1, S3, and S5 define a set of "odd-numbered stacked switches", while the second and fourth stacked switches S2 and S4 define a set of "even-numbered stacked switches".

[0049] The cascaded multiplier 65 also includes first and second low-side phase switches S7 and S8, and first and second high-side phase switches S6 and S9. The first and second low-side phase switches S7 and S8 connect the first and second phase nodes P1 and P2 to the common node V. SS The public node V SS The common node V connected to the second and fourth charge pump terminals 62 and 64 SS The first and second high-side phase switches S6 and S9 connect the first and second phase nodes P1 and P2 to the input node V. X The input node V X Connected to the first charge pump terminal 61. For ease of discussion of the switching sequence, the first high-side phase switch S6 and the second low-side phase switch S8 will sometimes be collectively referred to as the "even-numbered phase switch", while the first low-side phase switch S7 and the second high-side phase switch S9 will sometimes be collectively referred to as the "odd-numbered phase switch".

[0050] The cascade multiplier 65 has four stages. The first stage includes a first stacking switch S1 and a first stacking node V. C1 The first pump capacitor C1; the second stage includes the second stacked switch S2 and the second stacked node V. C2 The second pump capacitor C2; the third stage includes the third stacked switch S3 and the third stacked node V. C3 and the third pump capacitor C3; and the fourth stage including the fourth stacked switch S4, the fourth stacked node V C4 And the fourth pump capacitor C4.

[0051] exist Figure 2 In the embodiment shown, since there are four stages, the maximum voltage conversion ratio is 5. The fifth stacking switch S5 connects the fourth stage to the fifth stacking node V. C5 The fifth stack node V C5 Finally, it is connected to the third charge pump terminal 63. Here, the power converter 10 maintains its output voltage V. OUT .

[0052] The first pump capacitor C1 connects the first phase node P1 to the first stack node V. C1 The third pump capacitor C3 connects the first phase node P1 to the third stack node V. C3 The second pump capacitor C2 connects the second phase node P2 to the second stack node V. C2 ; and the fourth pump capacitor C4 connects the second phase node P2 to the fourth stack node V. C4 .

[0053] In response to receiving one or more input signals at its first and second controller inputs 25, 26, the charge pump controller 66 places control signals on control signal path 60. These control signals cause the first, second, third, fourth, and fifth stacked switches S1, S2, S3, S4, S5, the first and second low-side phase switches S7, S8, and the first and second high-side phase switches S6, S9 to change states according to a specific sequence. Therefore, the charge pump 20 repeatedly transitions between a first and second operating state at a specific frequency.

[0054] For example, during the first operating state, the charge pump controller 66 closes the odd-numbered stacked switches S1, S3, S5, the first low-side phase switch S7, and the second high-side phase switch S9, and opens the even-numbered stacked switches S2, S4, the first high-side phase switch S6, and the second low-side phase switch S8. In contrast, during the second operating state, the charge pump controller 66 opens the odd-numbered stacked switches S1, S3, S5, the first low-side phase switch S7, and the second high-side phase switch S9, and closes the even-numbered stacked switches S2, S4, the first high-side phase switch S6, and the second low-side phase switch S8.

[0055] Figure 3 A cascaded multiplier 65 within the charge pump 20 is shown, wherein the first, second, third, fourth, and fifth stacked switches S1, S3, S5, S4, S5, the first and second high-side phase switches S6, S9, and the first and second low-side phase switches S7, S8 are implemented using MOSFET transistors.

[0056] Each MOSFET transistor has an inherent body diode across its source and drain terminals. The first body diode D1 is associated with the first stacked switch S1, the second body diode D2 is associated with the second stacked switch S2, the third body diode D3 is associated with the third stacked switch S3, the fourth body diode D4 is associated with the fourth stacked switch S4, the fifth body diode D5 is associated with the fifth stacked switch S5, the sixth body diode D6 is associated with the first high-side phase switch S6, the seventh body diode D7 is associated with the first low-side phase switch S7, the eighth body diode D8 is associated with the second low-side phase switch S8, and the ninth body diode D9 is associated with the second high-side phase switch S9.

[0057] A transistor can be used as a switch by using its gate terminal to make the drain-source path conduct or deconduct. As used herein, "turning on" a transistor means forming a conductive path between the source and drain of the transistor. This is equivalent to closing a switch. Expressing "turning off" a transistor means allowing the conductive path to dissipate. This is equivalent to opening a switch.

[0058] Due to the presence and polarity of the first to fifth body diodes D1, D2, D3, D4, and D5, even when all stacked switches S1 to S5 have been turned off, the signal from input node V... X A forward electrical path also exists to the fifth stack node VC5. Therefore, even though all stack switches S1 to S5 have been turned off, a forward electrical path still exists at the input node V. X With the fifth stack node V C5 There will still be a voltage drop between them.

[0059] Stacked Node V C1 To V C5 Each body diode D1 to D5 upstream of the stack node reduces the V of the stack. C1 To V C5 The voltage at the first stack node V. C1 The voltage drop is very small because only the first body diode D1 connects the first stacked node to the input node V. X Separate. However, due to the gradual increase in the number of upstream body diodes, the subsequent stacking node V... C2 To V C5 Gradually, more voltage is lost. According to the input node V... X The magnitude of the voltage at the point, the forward voltage drop across each body diode, and the number of stacked nodes mean that the voltage at the stacked node furthest from the input voltage may be equal to the voltage at the common node V. SS The lowest voltage V at the point SS .

[0060] Some implementations of the charge pump 20 rely on stacked nodes V C1 To V C5The voltage at the location is used to open and close one or more stacked switches S1 to S5 and to open and close one or more phase switches S6 to S9. This arrangement provides an efficient way to operate the charge pump 20. However, operation of such an implementation presupposes that at each stack node V C1 To V C5 There must be sufficient voltage at the location. If even one of the stack nodes has insufficient voltage, the charge pump 20 will not operate correctly and may actually not operate at all.

[0061] Typically, the charge pump 20 will exist in one of three different states: off, steady state, and start-up state.

[0062] During the steady state, charge pump 20 receives input voltage V. IN And convert it into an output voltage V that is a multiple of its input. OUT In this stable state, charge pump 20 should be manufactured first. In the off state, no voltage is applied to the input terminals 61, 62 of the charge pump, or there is no positive differential voltage at the input terminals 61, 62.

[0063] The startup state lies between these two states. During the startup state, a positive voltage difference is presented across the input terminals 61 and 62 of the charge pump. However, at each stack node V... C1 To V C5 There may not be sufficient voltage at the point of origin for the charge pump 20 to perform its function. The methods and apparatus described herein are intended to reduce the length of this start-up state so that the charge pump 20 can quickly reach a steady state, or to prevent the charge pump 20 from getting stuck in the start-up state indefinitely.

[0064] In steady-state operation, the charge pump 20 maintains sufficient charge in its internal capacitors such that those capacitors have the necessary voltage to be applied to the gates of those transistors that must be switched between on and off states. However, the startup state presents a challenge.

[0065] Upon initial startup, these identical internal capacitors may not accumulate enough charge to generate a voltage sufficient to ensure the reliable operation of those identical transistors. Without any switches in operation, the charge in these internal capacitors will never accumulate enough to generate the voltage required to power just those switches that need to accumulate that charge. This presents a "chicken or egg" problem: the source of the voltage required to operate the switches depends on the correct operation of those switches in order to generate the necessary voltage to operate them in the first place. Therefore, charge pump 20 may never reach steady-state operation.

[0066] In the case of boost power converter 10, at each stack node V C1 To VC5 The availability of sufficient voltage at the point of operation is not guaranteed, especially at the start of startup. This is because the input voltage V to the power converter... IN It can be the highest available voltage before operation, and the boost power converter 10 operates by generating a voltage higher than the input voltage V. IN Output voltage V OUT And all other voltages within the charge pump 20, which is necessary for operation.

[0067] To avoid this difficulty, it is useful to provide input node V X Directly connected to each stack node V C1 To V C5 A bypass path is established to precharge the pump capacitor connected to each node. Each such bypass path bypasses one or more individual diodes D1 through D5. Therefore, these bypassed body diodes cannot cumulatively charge the stacked node V. C1 To V C5 It contributes to the voltage drop at that point.

[0068] exist Figure 4 In this configuration, bypass array 28 implements one or more bypass paths 30. Each bypass path 30 bypasses one or more of the stack switches S1 to S4. In doing so, each bypass path 30 provides stack node V C1 To V C4 One of the input nodes V X The direct connection between them. The bypass array 28 also has a direct connection to the input node V. X With stacked node V C5 A bypass path 30 is provided between them for use with Figure 1 The output capacitor 14 in the power converter 10 is pre-charged.

[0069] Bypass path 30 occurs only during the startup state and only at input node V. X The voltage at point V exceeds the input node V X Connected to stack node V C1 To V C5 The voltage at that point is valid.

[0070] Figure 4 Two alternative implementations of the bypass array 28 superimposed on each other are shown. The diode implementation of the bypass array 28 relies on bypass diode 34, while the switch implementation of the bypass array 28 relies on bypass switch 36. The bypass diode 34 is shown in dashed lines to indicate that they can represent alternatives to the bypass switch 36, which is shown in solid lines.

[0071] In the diode implementation, each bypass path 30 includes a bypass diode 34, whose cathode and anode are oriented to allow charge to flow from the input node V.X Flow to the corresponding stack node V C1 V C2 V C3 V C4 V C5 Moreover, it simultaneously blocks current from flowing in the opposite direction from any stack node V. C1 To V C5 Flow to input node V X As long as the stacked nodes V C1 To V C5 Below the input node V X At the voltage point, charge flows to the stacking node V. C1 To V C5 In doing so, the charge bypasses the stacked node V. C1 To V C5 All body diodes D1 through D5 upstream. This will extend along stack node V. C1 To V C5 The voltage drop at the output node is reduced to the voltage drop caused by only one diode. Once the voltage at the stacked node equals or exceeds the voltage at the input node V... X When the voltage at that point is reached, the positive charge flow stops.

[0072] The advantage of the diode implementation lies in its simplicity. The bypass diode 34 automatically disables the bypass path 30 when necessary. No control circuitry is required. Nor is any circuitry needed to sense the voltage, allowing the decision to disable the bypass path 30 to be made. On the other hand, a disadvantage of the first implementation is that the bypass diode 34 will draw its own voltage drop, just like the body diode. Therefore, including the bypass diode 34 in the bypass path 30 leading to the first stack node VC1 offers little benefit.

[0073] In the switch implementation, when charge pump 20 is in the start state, it leads to stack node V. C1 To V C5 The bypass switch 36 remains closed. No switching occurs within the charge pump 20 during this startup state. When the charge pump 20 begins switching in a stable state, the bypass switch 36 opens.

[0074] The bypass switch 36 offers the advantage of reducing the voltage drop inherent in the use of the bypass diode 34. However, this comes at the cost of additional complexity associated with the circuitry required to control each bypass switch 36.

[0075] when Figure 2 When the charge pump 20 operates within the boost power converter 10, the highest operating voltage at each stack node continuously increases the input node V. X The voltage at that point is an integer multiple of the voltage at that location. For example, the voltage at the first stack node V. C1The highest operating voltage at point V is the input node V. X The voltage at the second stack node V is twice that at the second stack node. C2 The highest operating voltage at point V is the input node V. X Three times the voltage at the third stack node V C3 The highest operating voltage at point V is the input node V. X Four times the voltage at that point, and the fourth stack node V C4 The highest operating voltage at point V is the input node V. X Five times the voltage at that point. Because... Figure 2 The voltage conversion ratio of the charge pump 20 shown is 5, therefore the fifth stack node V C5 The voltage at the output node of the charge pump is also the voltage at its input node V. X It is approximately five times the voltage at that location.

[0076] Because the voltage gradually increases as it moves down the stack nodes, the reverse rated voltage of each bypass diode 34 or bypass switch 36 will also have to increase. Therefore, the voltage connected to the (n+1)th stack node V... C(n+1) The bypass diode 34 or bypass switch 36 will be greater than the V connected to the nth stack node. Cn The reverse rated voltage required for the bypass diode 34 or bypass switch 36. Generally, as the reverse rated voltage of a component increases, the chip area required to construct it increases. Additionally, certain other parasitic effects such as capacitance and leakage current will tend to increase.

[0077] exist Figure 4 In the stack, each node V C1 V C2 V C3 V C4 V C5 It has its own bypass path 30. However, this is not required. Different stacked nodes V C1 To V C5 The stack suffers from a continuously large voltage drop caused by the diodes. In view of the above phenomenon, it may be preferable to provide bypass paths 30 only to selected stack nodes, such as those stack nodes that suffer from the largest voltage drop caused by the diodes.

[0078] Figure 5 One such implementation is shown. Figure 5 The implementation shown omits the connection to the first stack node V. C1 The bypass path, because the first stack node V C1 Unable to withstand a sufficiently large voltage drop to reach the first stack node V C1 The additional bypass paths are worthwhile in terms of chip area or complexity.

[0079] and Figure 4 Same, Figure 5 Two alternative implementations superimposed on each other are shown. The first implementation of bypass array 28 relies on bypass diode 34, while the second implementation of bypass array 28 relies on bypass switch 36. Bypass diode 34 is shown in dashed lines to indicate that they can represent alternatives to bypass switch 36, which is shown in solid lines.

[0080] Figure 5 The embodiment shown is characterized by a first bypass path 30 and a second bypass path 31. This leads to the second stack node V. C2 The first bypass path 30 includes a bypass diode 34 and / or a bypass switch 36. The second bypass path 31 branches into a first branch 33 and a second branch 35. The first branch 33 leads to the third stack node V. C3 It also includes two bypass diodes D connected in series. B1 D B2 and / or two bypass switches S connected in series B1 S B2 The second branch 35 is included in the third stack node V. C3 The fifth stack node V, which is also the output of the charge pump, C5 The bypass diode D between B3 and / or bypass switch S B3 .

[0081] Of particular interest is the distribution of diodes along the second bypass path 31.

[0082] It can be seen that the second bypass path 31 uses input node V X With the third stack node V C3 The first and second series bypass diodes D B1 D B2 This is a feature. This will follow from the input node V X To the third stack node V C3 The difference in the forward voltage path at the point decreases from the voltage drop caused by three diodes to the voltage drop caused by two diodes.

[0083] Although the second bypass diode D is omitted B2 This will save chip area and further reduce voltage drop, but then the first bypass diode D B1 It will have to withstand the impact from the third stack node V during steady-state operation. C3 To input node V X The entire reverse voltage.

[0084] To avoid subjecting a single diode to the entire reverse voltage. Figure 5 The embodiment shown uses first and second series bypass diodes D B1D B2 This allows for the splitting of the reverse voltage across the two diodes. This enables the use of bypass diodes with lower reverse voltage ratings.

[0085] In some cases, manufacturing limitations make it difficult to produce diodes with appropriately high reverse voltage ratings. This can be addressed by using first and second series bypass diodes D, each with a relatively small reverse voltage rating. B1 D B2 This is to circumvent such limitations. Therefore, no single diode will have to withstand the entire reverse voltage that occurs during the operation of charge pump 20.

[0086] In some cases, even if the manufacturing process can produce a diode with the desired reverse voltage rating, it is sometimes desirable to place the bypass diodes in series anyway. For example, the combined chip area consumed by two diodes with lower reverse voltage ratings may be less than the chip area consumed by a single diode with the desired reverse voltage rating.

[0087] A similar problem arises in alternative implementations that rely on switches instead of diodes. This is due to the input node V X With the third stack node V C3 The second bypass path 31 between the two provides the first and second series bypass switches S in series. B1 S B2 Solve it in a similar way. By enabling the second bypass switch S B2 With the first bypass switch S B1 In series, the first and second bypass switches S B1 S B2 Instead of dividing the blocking voltage between them, the first bypass switch S... B1 It can withstand the entire blocking voltage. This can save chip area by using two smaller bypass switches, each with a lower reverse rating, instead of one larger switch with at least twice the reverse rating. However, the trade-off is the increased design complexity that arises from having to control two bypass switches instead of one.

[0088] The third series bypass diode D is located along the second branch 35. B3 Let's apply the aforementioned principle again. Fifth stack node V C5 With input node V X The required blocking voltage difference between them will be greater than that of the fifth stack node V. C5 With the third stack node V C3 The blocking voltage difference between them. In the illustrated embodiment, the fifth stack node V C5 With input node V XThe required blocking voltage difference between them will be the input node V X The voltage at that point is four times that of the fifth stack node V. C5 With the third stack node V C3 The required blocking voltage difference between them will only be the input node V X Twice the voltage at the input node V. Accordingly, this can be achieved by... X With the fifth stack node V C5 The first, second and third series bypass diodes D are used between them. B1 D B2 D B3 This reduces the number of voltage drops caused by diodes from 5 to 3, thus consuming less chip area.

[0089] The same principle applies to Figure 5 This is implemented in the second implementation shown. In this second implementation, the third bypass switch S... B3 Located along the second branch at 35. Fifth stack node V. C5 With its input node V X The blocking voltage difference between them will be greater than that of the fifth stack node V. C5 With the third stack node V C3 The blocking voltage difference between them. Accordingly, it can be controlled by the first, second and third bypass switches S. B1 S B2 S B3 The blocking voltage difference is divided to reduce the chip area consumed.

[0090] In principle, it is also possible to have a hybrid implementation where some bypass paths 30 and 31 use bypass diodes 34 while other paths use bypass switches 36. Bypass switches 36 and bypass diodes 34 can also coexist along the same bypass path. This is because bypass switches 36 and bypass diodes 34 essentially serve the same purpose, but achieve that purpose or function in different ways to achieve similar results.

[0091] Figure 6 It shows Figure 2 and Figure 3 The implementation of the cascaded multiplier 65 shown herein is wherein each of the first, second, third, fourth, and fifth stacked switches S1, S2, S3, S4, and S5 is implemented using corresponding first, second, third, fourth, and fifth transistors M1, M2, M3, M4, and M5, and each of the phase switches S6, S7, S8, and S9 is implemented using corresponding sixth, seventh, eighth, and ninth transistors M6, M7, M8, and M9. The fifth transistor M5 is a PMOS transistor, while all other transistors are NMOS transistors.

[0092] The fifth stacked switch S5 can be implemented using an NMOS transistor. However, this requires a higher design complexity than that required for a PMOS transistor. Additionally, extra components will be needed to drive the NMOS transistor. These components are not required when using a PMOS transistor.

[0093] The first, third, fifth, seventh, and ninth transistors M1, M3, M5, M7, and M9 define a group of "odd-numbered transistors," while the second, fourth, sixth, and eighth transistors M2, M4, M6, and M8 define a group of "even-numbered transistors." During the first operating state, only the odd-numbered transistors are turned on. During the second operating state, only the even-numbered transistors are turned on. Therefore, the steady-state operation of the charge pump 20 involves switching back and forth between the first and second operating states.

[0094] Figure 6 Each node shown is accompanied by a pair of numbers in the form of m / n. If in the input node V... X If a voltage of 5 volts is applied at a node, the voltage at that node will be m volts during the first operating state and n volts during the second operating state.

[0095] For example, during the first operating state, the first, second, third, and fourth stack nodes V C1 V C2 V C3 V C4 The voltages at the points are 5V, 15V, 15V, and 25V, respectively, while the voltages at the first and second phase nodes P1 and P2 are 0V and 5V, respectively. In contrast, during the second operating state, the voltages at the first, second, third, and fourth stack nodes V... C1 V C2 V C3 V C4 The voltages at the points are 10V, 10V, 20V, and 20V, respectively, while the voltages at the first and second phase nodes P1 and P2 are 5V and 0V, respectively. Regardless of the operating state, the fifth stack node V... C5 The voltage at each node is 25V. This is by design because the fifth stack node is also the output node of charge pump 20.

[0096] Figure 6 The first to ninth gate drivers G1 to G9 are also shown, each of which is connected to the gate terminal of any transistor intended to be driven. Figure 7 A gate drive block 50 is shown for implementing each of the first to ninth gate drivers G1 to G9.

[0097] Now refer to Figure 7The gate drive block 50 has a gate drive terminal 59 connected to the gate terminals of the transistors M1 to M9 to be driven. As used herein, "driving" a transistor means switching the drain-source channels of the transistor between an on and off state.

[0098] Each gate drive block 50 has a gate drive control terminal 54. The gate drive control terminal 54 receives a signal designed to switch the drain-source channel of the transistor between an on and off state. This signal is as follows: Figure 2 The charge pump controller 66 under discussion places one of the control signals EN1 to EN9 on the control signal path 60. These control signals EN1 to EN9 can... Figure 6 I saw it in the middle.

[0099] Typically, electronic components respond to the difference between two voltages. The higher of the two voltages is usually called the "positive" voltage, and the lower voltage the "negative" voltage. Of course, this doesn't actually mean one voltage is positive and the other negative. This is because the actual value of the voltage depends on an arbitrarily defined reference voltage that is set to zero. Since ultimately only the difference matters, it's useful to set the negative voltage to zero and call it "ground" or "earth." This allows us to discuss only the positive voltage.

[0100] In some embodiments of the charge pump 20, different components with different negative voltages may be presented. In particular, the "ground" at a particular transistor may not correspond to the ground elsewhere in the circuit. To accommodate this, each gate drive block 50 includes a level shifter 51 that converts the voltage difference into another voltage difference more suitable for driving transistors M1 to M9.

[0101] Figure 7 The gate drive block 50 shown includes first and second positive supply terminals 57 and 58, and first and second negative supply terminals 55 and 56. The first positive supply terminal 57 receives a first positive supply voltage V. DDI The first negative supply terminal 55 receives the first negative supply voltage V. SSI These can be found Figure 7 As seen in the context, the second positive supply terminal 58 receives the second positive supply voltage V. DDO The second negative supply terminal 56 receives the second negative supply voltage V. SSO .

[0102] The gate drive block 50 also includes a level shifter 51 and a gate driver 52. The level shifter 51 receives a first positive supply voltage V. DDI First negative supply voltage V SSI Second positive supply voltage V DDO Second negative supply voltage V SSOThe gate driver 52 only receives the second positive supply voltage V. DDO Second negative supply voltage V SSO .

[0103] The four supply voltages define the first supply voltage difference and the second supply voltage difference. The first supply voltage difference is the first positive supply voltage V. DDI With the first negative supply voltage V SSI The difference between them. The second supply voltage difference is the second positive supply voltage V. DDO With the second negative supply voltage V SSO The difference between them.

[0104] Level shifter 51 has level shifter logic inputs connected to gate drive control terminal 54 to receive a first logic signal V. SWI The level shifter 51 also has a level shifter logic output, on which the second logic signal V it generates is placed. LSO .

[0105] Gate driver 52 has gate driver logic input terminals that receive a second logic signal V from level shifter 51. LSO The gate driver 52 also has a gate driver logic output terminal on which the third logic signal V it generates is placed. SWO The third logic signal V SWO It is connected to the gate drive terminal 59 and finally to the gate of the transistor to drive the transistor.

[0106] In response to receiving the first logic signal V SWI The logic within the level shifter 51 is based on the first positive supply voltage V. DDI With the first negative supply voltage V SSI The selection is made between these two options. Then, the level shifter 51 will select the first logic signal V. SWI Converted into the second logic signal V LSO It follows the first logic signal V SWI The logical polarity of the second logical signal V. LSO The second logic signal V is provided to the gate driver logic input terminal. LSO Then the gate driver 52 is made to operate at the second positive supply voltage V DDO With the second negative supply voltage V SSO The choice is made between these two voltages. One of these voltages is used by gate driver 52 as the third logic signal V at gate drive terminal 59. SWO Output voltage.

[0107] Figure 8Details of gate driver 52 are shown. The gate driver has gate driver logic input IN and gate driver logic output OUT. Figure 7 In the context of the gate driver logic input IN receiving the second logic signal V LSO The gate driver logic output OUT carries the third logic signal V. SWO .

[0108] The first, second, third, and fourth inverters couple their gate driver logic inputs IN to their gate driver logic outputs OUT in this order. Each inverter includes a high-side PMOS transistor M. P1 To M P4 and the corresponding low-side NMOS transistor M N1 To M N4 Due to the difference in electron and hole mobility, each PMOS transistor M Pn Typically larger than its corresponding NMOS transistor M Nn .

[0109] The physical dimensions of the four inverters in the gate driver are not exactly the same. Specifically, starting at the gate driver logic input IN, each subsequent inverter is k times larger than the previous one. For example, if k equals 5 and the width of the first inverter is 1 micrometer, then the widths of the second, third, and fourth inverters are 5 micrometers, 25 micrometers, and 125 micrometers, respectively. By gradually reducing the size of the inverters in this way, the small logic gate coupled to the gate driver logic input IN can drive the high-power transistor coupled to the gate driver logic output OUT.

[0110] To reduce the required chip area and improve power efficiency, it is desirable to use low-side NMOS transistors M. N1 To M N4 and high-side PMOS transistor M P1 To M P4 Its rated voltage is equal to or close to the cross voltage. Figure 6 The first to ninth transistors M1 to M9 are shown with rated voltages for their gate and source terminals. Assuming a rated voltage of 5V across the gate and source terminals of transistors M1 to M9, it would also be desirable to use a 5V rated transistor for the low-side NMOS transistor M in gate driver 52. N1 To M N4 and high-side PMOS transistor M P1 To M P4 .

[0111] Typically, the first positive supply voltage V DDI It can be equal to, less than, or greater than the second positive supply voltage V. DDO Similarly, the first negative supply voltage V SSIIt can be equal to, less than, or greater than the second negative supply voltage V. SSO .exist Figure 1 In the example of the boost power converter 10, the second positive supply voltage V DDO Typically greater than the first positive supply voltage V DDI The second negative supply voltage V SSO Typically greater than the first negative supply voltage V SSI .

[0112] However, there are constraints associated with the first and second supply voltage differences. Neither the first nor the second supply voltage difference should exceed the rated voltage of the transistors used in the circuit supplying power between these terminals.

[0113] Reference Figure 6 The first to ninth gate drivers G1 to G9 all receive the same first positive supply voltage V. DDI And the same first negative supply voltage V SSI For clarity, the terminals through which these supplied voltages are received have been omitted.

[0114] Typically, the first to ninth gate drivers G1 to G9 will receive different second negative supply voltages V. SSO This is because of the second negative supply voltage V used for specific gate drivers G1 to G9. SSO This comes from the source terminals of the specific transistors M1 to M9 that it controls. This also means that the different gate drivers G1 to G9 will each receive a different second positive supply voltage V. DDO This is because, in order to use a transistor with a desired rated voltage within the gate driver, a second supply voltage difference—a second positive supply voltage V—is required. DDO With the second negative supply voltage V SSO The difference between them must not exceed the expected rated voltage. Therefore, if the second negative supply voltage V SSO If the voltage changes, then the second positive supply voltage V DDO It must also change.

[0115] To improve power efficiency and reduce the number of required components, it is useful, where possible, to obtain the stacked nodes V from the cascade multiplier 65. C1 To V C5 The second positive supply voltage V of one of the driving transistors DDO To achieve this, it is useful to connect the gate driver to the stack node V. C1 To V C5 To supply its second positive supply voltage V DDO Some paths provide cascaded transistors M C1 M C2 M C3 MC4 M C5 M C9 It has cascaded transistor M C1 M C2 M C3 M C4 M C5 M C9 The path is the stacked node V C1 To V C5 The voltage at the gate and the second negative supply voltage V at each corresponding gate driver SSO The path exceeds the desired transistor rated voltage, which is 5 volts in the illustrated embodiment. To avoid an excessively large supply voltage difference across the driven transistor, cascaded transistors M... C1 To M C5 M C9 The corresponding second positive supply voltage V at the stack node and the corresponding gate driver in the middle. DDO Overvoltage between them, to ensure that the supply voltage difference does not exceed the expected rated voltage.

[0116] The second positive supply voltage V for the seventh and eighth gate drivers G7, G8 DDO It can be determined by the first positive supply voltage V DDI The same voltage or by the input node V X Provided. This selection depends on the first positive supply voltage V. DDI The value or input node V X The voltage that can be obtained at that location.

[0117] When charge pump 20 is operating in a steady state, transistors M1 to M9 that realize stack switches S1 to S5 and phase switches S6 to S9 open and close in a synchronous mode, which pumps each stack node V. C1 To V C5 The voltage at each stack node. This ensures that the voltage at each stack node is maintained. C1 To V C5 There will be enough voltage to power each gate driver G1 to G9 in order to drive the gates of all the transistors in the transistor.

[0118] Before the charge pump 20 begins switching, it applies or has a voltage present at its input node V. X At this time, stacked nodes V C1 To V C5 The body diodes between each adjacent pair in the stack will cannibalize the stacked node voltage. This can be determined by the input node V relative to the magnitude of the forward voltage drop caused by each body diode. X At the voltage at the stack node, the body diode will likely cannibalize enough voltage to cause the stack node voltage V to... C1 To VC5 One or more of them will prove insufficient to power the gate drivers G1 through G9 so that they can drive their respective transistors M1 through M9. In fact, the second supply voltage difference across each of the gate drivers G1 through G9 can even start with a negative voltage, thus preventing any operation or control of the transistor gate in any way.

[0119] Due to their placement, some transistors are less likely to find their operation hindered by these body voltage drops. For example, the second positive supply voltage V of the seventh and eighth transistors M7 and M8. DDO Due to the first positive supply voltage V DDI The same voltage or by the input node V X Provided. Accordingly, the seventh and eighth transistors M7 and M8 will not suffer from the voltage drop caused by the diode.

[0120] The charge pump 20, which has just started operating, relies heavily on phase switches S6 to S9 to pump the stacked node V. C1 To V C5 The voltage at the phase nodes P1 and P2. This is because phase switches S6 to S9 play an important role in controlling the voltage at phase nodes P1 and P2. Each phase node is connected to the bottom terminals of pump capacitors C1 to C4, such as... Figure 2 As shown in the diagram, the first and second high-side phase switches S6 and S9 connect phase nodes P1 and P2 to the input node V. X The low-side phase switches S7 and S8 connect phase nodes P1 and P2 to the common node V. SS The first and second high-side phase switches S6 and S9 are complementary to the low-side phase switches S7 and S8. When one of the two phase nodes P1 and P2 is connected to ground, the pump capacitor connected to that phase node charges. When one of the two phase nodes P1 and P2 is connected to the input node V... X At this time, the pump capacitor connected to the phase node discharges, and at the same time, the voltage on the stacked node connected to the top of these pump capacitors increases.

[0121] Reference Figure 6 In the specific implementation shown, the seventh and eighth transistors M7 and M8 that implement the low-side phase switches S7 and S8 can be controlled immediately at the start of charge pump switching because the seventh and eighth gate drivers G7 and G8 are supplied with a second positive voltage V. DDO Power supply, second positive supply voltage V DDO With the first positive supply voltage V DDI The voltage is the same as or the same as the input node V. X The voltage is the same at each point.

[0122] The above operation assumes that the second positive supply voltage V starts at the beginning of the charge pump switching. DDOThis is sufficient to ensure the correct operation of the seventh and eighth gate drivers G7 and G8. This is unlikely to be the case for the second positive supply voltage provided to the sixth and ninth gate drivers G6 and G9 of the sixth and ninth transistors M6 and M9, which control the high-side phase switches S6 and S9.

[0123] For example, the first stack node V C1 A second positive supply voltage is provided for the sixth gate driver G6, while the second stack node V C2 A second positive supply voltage is provided for the ninth gate driver G9, which has itself and its voltage source, namely the second stack node V. C2 Cascaded transistors M C9 The second positive supply voltage V available for the ninth gate driver G9 is before charge pump 20 operates or when charge pump 20 is turned off. DDO It may be lower than the second positive supply voltage V available for the sixth gate driver G6. DDO This is because of the first stack node V. C1 In comparison, the second stack node V C2 The additional diode at the location causes a voltage drop. This may inhibit the ability of the ninth transistor M9 to be controlled synchronously with respect to the other phase switches M6, M7, and M8. This may delay or even prevent the start-up of the charge pump 20.

[0124] Figure 9 It shows Figure 6 An alternative implementation of the cascaded multiplier 65 is provided, in which the sixth and ninth transistors M6 and M9 that implement the high-side phase switches S6 and S9 are PMOS instead of NMOS. Replacing the NMOS transistors with PMOS transistors alters the second positive supply voltage V at the sixth and ninth gate drivers G6 and G9. DDO Second negative supply voltage V SSO The bias requirements. For both the sixth and ninth gate drivers G6 and G9, the second positive supply voltage is directly connected to the input node V. X This eliminates the need for cascaded transistors connected in series. Furthermore, for both the sixth and ninth gate drivers G6 and G9, the second negative supply voltage is connected to the common node V. SS This means that the second supply voltage difference at the sixth and ninth gate drivers G6 and G9 is no longer affected by the voltage difference along the stack node V. C1 and V C2 The voltage drop caused by the diode is reduced. However, this method consumes more chip area and reduces power efficiency because, for a given size, a PMOS transistor has a larger on-resistance than an NMOS transistor.

[0125] Figure 10 It shows Figure 6An alternative implementation of the cascaded multiplier 65 is provided, in which the sixth and ninth gate drivers G6 and G9 of the NMOS transistors M6 and M9 that control the high-side phase switches S6 and S9 are powered differently. This implementation is similar to... Figure 6 The embodiments shown share certain features. In particular, the second negative supply voltage V SSO The connection to the source terminals of the corresponding sixth and ninth transistors M6 and M9, and the first positive supply voltage V DDI and the first negative supply voltage V SSI Maintain and Figure 6 The same as those shown in the image.

[0126] A difference exists in the second positive supply voltage used for the sixth and ninth gate drivers G6, G9. The second positive supply voltage used for the sixth gate driver G6 is labeled as V. DD_G6 Now from the first bootstrap capacitor C G6 The anode is obtained, and the first bootstrap capacitor C is obtained. G6 By the first bootstrap diode D G6 Based on the same second positive supply voltage V at the seventh and eighth gate drivers G7 and G8 DDO Refresh. Similarly, the second positive supply voltage for the ninth gate driver G9 is labeled V. DD_G9 Now from the second bootstrap capacitor C G9 The anode is obtained, and the second bootstrap capacitor C is obtained. G9 By the second bootstrap diode D G9 Based on the same second positive supply voltage V at the seventh and eighth gate drivers G7 and G8 DDO Refresh. First and second bootstrap diodes D G6 D G9 Alternatively, PMOS transistors can be used in a manner that allows current to flow only to the bootstrap capacitor C. G6 C G9 In this implementation, the PMOS transistor behaves like a diode and cascaded transistors M are no longer required. C9 .

[0127] and Figure 6 The situation is similar in the case of the second positive supply voltage V at the seventh and eighth gate drivers G7 and G8. DDO According to V DDI Or input node V X The voltage level that can be obtained is derived from the first positive supply voltage V. DDI The same voltage or by the input node V X supply.

[0128] Figure 10The advantage of the implementation shown is that it ensures a high second supply voltage difference before the switch in the charge pump begins to switch, particularly the second supply voltage difference at the ninth gate driver G9. This is achieved by matching the second supply voltage difference at the ninth gate driver G9 with the second supply voltage difference at the sixth gate driver G6.

[0129] Implement a bootstrap diode D using a PMOS transistor. G6 D G9 A second supply voltage difference is also added at the sixth and ninth gate drivers G6 and G9. This implementation eliminates the second positive supply voltage V. DDO With the second positive supply voltage (V) for the sixth gate driver G6 DD_G6 ) and the second positive supply voltage (V) for the ninth gate driver G9 DD_G9 The voltage drop caused by the diode between the two is used for switching. This ensures that the low-side phase switches S7 and S8 and the high-side phase switches S6 and S9 can switch correctly from the start of charge pump operation.

[0130] Another solution to match the second supply voltage difference at the ninth gate driver G9 is to use a two-phase symmetrical cascaded multiplier 67 within the charge pump 20, such as Figure 11 As shown in the image.

[0131] exist Figure 11 In the middle, the first phase of the double-phase symmetrical cascaded multiplier 67 includes and Figure 2 The cascaded multiplier 65 has the same stacked switches S1 to S5, phase switches S6 to S9, and stacked node V. C1 To V C4 And pump capacitors C1 to C4. The second phase of the two-phase symmetrical cascaded multiplier 67 replicates the four stages of the first phase, wherein each stage in the second phase includes a pump capacitor C 10 To C 13 One and four corresponding stacked switches S 10 To S 13 One of them. The first stage in the second phase includes stacked switches S. 10 Stacked nodes V C10 and pump capacitor C 10 The second stage in the second phase includes stacked switches S. 11 Stacked nodes V C11 and pump capacitor C 11 The third stage in the second phase includes stacked switches S. 12 Stacked nodes V C12 and pump capacitor C 12 ; and the fourth stage in the second phase includes stacked switches S 13 Stacked nodes V C13 and pump capacitor C 13Stacking switch S 14 Connect the fourth stage in the second phase to the fifth stack node V. C5 Fifth stack node V C5 Connected to the third charge pump terminal 63. The first and second phases of the two-phase symmetrical cascaded multiplier 67 share the same phase switches S6 to S9 and phase nodes P1 and P2.

[0132] In response to receiving the first and / or second controller inputs 25, 26, the charge pump controller 66 places control signals on the control signal path 60. These control signals cause the stacked switches S1, S2, S3, S4, S5, S6 to... 10 S 11 S 12 S 13 S 14 The phase switches S6 to S9 change state according to a specific sequence. Therefore, the charge pump 20 repeatedly switches between the first and second operating states at a specific frequency.

[0133] For example, during the first operating state, the charge pump controller 66 closes the odd-numbered stacked switches S1, S3, S5, and S6. 11 S 13 And disconnect the odd-numbered phase switches S7 and S9 and the even-numbered stacked switches S2, S4, and S9. 10 S 12 S 14 And even-numbered phase switches S6 and S8. In contrast, during the second operating state, the charge pump controller 66 disconnects odd-numbered stacked switches S1, S3, S5, and S6. 11 S 13 And close the odd-numbered phase switches S7 and S9 and the even-numbered stacking switches S2, S4, and S9. 10 S 12 S 14 And even-numbered phase switches S6 and S8. During steady-state operation, the first stack node V... C1 With stacked node V C10 Switching between the same two voltage levels but out of phase. This behavior applies to the second stack node V. C2 and stacked nodes V C11 Third stack node V C3 and stacked nodes V C12 Fourth stack node V C4 and stacked nodes V C13 That's also true.

[0134] Figure 6 The implementation of the first phase in a two-phase symmetrical cascaded multiplier 67 is shown, where transistors implement each stacked switch and phase switch, and gate drives control each transistor. The second phase in the two-phase symmetrical cascaded multiplier 67 is implemented in conjunction with... Figure 6 The same method is used to implement the first phase shown in the diagram, especially in the stacked switch S. 10 To S 14 Regarding the corresponding gate drivers, they share the same transistor phase switches M6 to M9 and gate drivers G6 to G9 as the first phase.

[0135] The dual-phase symmetrical cascaded multiplier 67 matches the second supply voltage difference at the ninth gate driver G9 with the second supply voltage difference at the sixth gate driver G6. This can be achieved by directly connecting the second positive supply voltage of the ninth gate driver G9 to the stack node V. C10 To achieve this, stacked nodes V C10 Conveniently switches in phase with the second phase node P2 while being equal to the input node V X The voltage at point P2 remains higher than the voltage at the second phase node P2. Furthermore, this implementation eliminates the need for cascaded transistor M. C9 And the need for bootstrap diodes and bootstrap capacitors.

[0136] Upon completion of charge pump startup, charge pump 20 moves its stacked node V C1 To V C5 The voltage at the input node V is less than or equal to the voltage at the input node V. X The voltage presented at the point rises to a much higher voltage associated with steady-state operation. Specifically, the average voltage across each pump capacitor C1 through C4 increases to the input node V. X The voltage multiple at that point. For example, the average voltage across the first pump capacitor C1 is roughly equal to the input node V. X The average voltage at point V, and the average voltage across the second pump capacitor C2 are roughly equal to the input node V. X The voltage at point V is twice that of the average voltage across the third pump capacitor C3, which is roughly equal to the input node V. X The voltage at point V is three times that at point V, and the average voltage across the fourth pump capacitor C4 is roughly equal to the input node V. X Four times the voltage at that location.

[0137] The aforementioned method can be used to ensure proper operation of phase switches S6 to S9 at the start of charge pump 20 switching. This is achieved by driving the gates of phase switches S6 to S9 from stack node V. C1 To V C5 The timing of obtaining it is especially important. This is crucial for using, for example... Figure 6 The stacked switches S1 to S5 shown in the diagram, implemented with transistors and gate drivers, are not necessarily like this. This is because at stack node V... C1 To V C5 The body diode of each transistor between adjacent pairs in the stack will cannibalize the stack node voltage. This is determined by the magnitude of the input node voltage V relative to the forward voltage of each body diode.X At the voltage at the stack node, the body diode will likely cannibalize enough voltage to cause the stack node voltage V to... C1 To V C5 One or more of them will prove insufficient to provide enough voltage to the gate drivers G1 to G5 to reliably drive their respective stacked switching transistors M1 to M5. Therefore, the stacked switching transistors M1 to M5 will likely be turned off at the start of charge pump switching and will remain off for several switching cycles thereafter until the second supply voltage difference across the gate drivers G1 to G5 changes from negative to a sufficiently positive level so that the stacked switching transistors M1 to M5 begin to reliably transition between on and off states in response to their respective control signals EN1 to EN5.

[0138] Since the stacked switching transistors M1 to M5 will not function when the charge pump 20 is first started, it is necessary to provide an increased stacking node voltage V. C1 To V C5 Temporary paths are used to replace the stacked switching transistors M1 to M5. The existence of such temporary paths can be achieved by... Figure 3 The cascaded multiplier 65 was obtained in Figure 3 In the cascaded multiplier 65, body diodes D1 through D9 are shown in parallel with each corresponding switch S1 through S9, which is implemented as a transistor. Because of these body diodes D1 through D9, the charge pump 20 can still be started and eventually operated even if all the stacked switches S1 through S5 are off. This is because from the input node V X The transfer of charge from the pump capacitors C1 to C4 to the output of the charge pump can still be carried out through the body diodes D1 to D5.

[0139] Although the use of this temporary path results in poorer efficiency and less accurate output voltage, it is sufficient to increase the stack node Vc. C1 To V C5 The voltage at the point allows the stacked switching transistors M1 to M5 to eventually take over. This is mainly achieved through this temporary path—charge pump 20—of the body diodes D1 to D5 of the stacked switching transistors M1 to M5, while waiting for the stack node V. C1 To V C5 The voltage rises sufficiently to power gate drivers G1 to G5 so that stacked switching transistors M1 to M5 can begin to switch correctly during startup, relying on this temporary path.

[0140] The startup of charge pump 20 involves raising the stack node V. C1 To V C5 The voltage at the location causes them to transition from the first voltage range to the second voltage range. When the stacked node V... C1 To V C5When the voltage at the stacked node is within the first range, they are too low to even turn on any of the stacked switching transistors M1 through M5. Therefore, while they cannot do anything useful, they are at least harmless. In the second range, the voltage at the stacked node V... C1 To V C5 The voltage at the point has risen to a level where they can reliably open and close the stacked switching transistors M1 to M5 as needed.

[0141] However, in order to move from the first range to the second range, stacked nodes V C1 To V C5 The voltage at the point must pass through a third range located in between. Passing through the third range is fraught with danger. These voltages are sometimes just high enough to operate the stacked switching transistors M1 through M5 or to perform so reliably with proper timing or propagation delay.

[0142] There is almost no harm when the propagation delay through gate drive block 50 exceeds the expected delay, causing a closing delay in the stacked switches. However, the delay in opening the switches introduces the possibility of a shoot-through event. In a shoot-through event, two stacked switches that should never close simultaneously will temporarily close at the same time.

[0143] As an example, consider the charge pump 20 transitioning from a first operating state to a second operating state. In the first operating state, stack switches S1, S3, S5 and phase switches S7, S9 are closed when stack switches S2, S4 and phase switches S6, S8 are open. In the second operating state, stack switches S1, S3, S5 and phase switches S7, S9 are open when stack switches S2, S4 and phase switches S6, S8 are closed. Assume that when the second stack node V, which powers the gate driver G1... C2 When the voltage on the transistor is sufficient to operate the stacked switch transistor M1 that implements the stacked switch S1, this transition occurs at startup, but that's all. Therefore, the propagation delay associated with the transition of the transistor between the on and off states is much slower than expected.

[0144] With this just-enough voltage, the transistor will operate. But it will do so slowly. The transistor will be able to change state as needed. However, it may not always do so precisely at this exact moment.

[0145] During the first operating state, stacked node V C1 Coupled to input node V X And the first phase node P1 is coupled to the common node V. SS And stacked nodes V C2 Because the second phase node P2 is coupled to the input node V X Pumped to stack node V C1That's all. During the transition from the first operating state to the second operating state, the second phase node P2 is coupled to the common node V. SS The first phase node P1 is coupled to the input node V. X The goal is to stack nodes V. C1 Pumped to input node V X The above are simultaneously coupled to the stack node V. C2 .

[0146] Despite stacked node V C3 The voltage on the first stack node V is insufficient to power the second gate driver G2 and turn on the stacked switch transistor M2 that implements the stacked switch S2, but the voltage on the second stack node V is insufficient to power the second gate driver G2 and turn on the stacked switch transistor M2. C1 It can still be indirectly coupled to the second stack node V through the body diode D2 of the second stacked switching transistor M2. C2 Simultaneously, the slow propagation delay of the gate driver G1 can keep the first stacked switching transistor M1 on, while the first stacked node V... C1 Coupling to the second stack node V has begun. C2 This makes pass-through events possible.

[0147] Due to this timing error, the first stack node V C1 Simultaneously coupled to the input node V X and stacked nodes V C2 The first phase node P1 is also coupled to the input node V at the start of the second operating state. X This causes the first pump capacitor C1 to discharge immediately. It also prevents the remaining pump capacitors C2 through C4 from continuously charging above the input node V. X The voltage of the charge pump 20 is a multiple of their appropriate voltage. Therefore, the charge pump 20 can remain stuck close to its initial state. Depending on the severity of the timing error, the charge pump 20 may experience a prolonged delay before finally reaching steady-state operation. Alternatively, the charge pump 20 may never reach steady-state operation.

[0148] The scenario described above is not the only consequence of timing errors. Other undesirable results are possible whenever the gate driver misbehaves due to insufficient second supply voltage differential or operates with incorrect timing. Therefore, it is desirable to prevent stacked switch operation until it is truly ready to do so.

[0149] One way to avoid the aforementioned difficulties is to delay or prevent each gate drive block 50 from turning on its corresponding stacked switch transistor until a sufficient second supply voltage difference is detected. Figure 12 An implementation of a gate drive block 50 with circuitry to suppress premature switching is shown. The gate drive block 50 shown is similar to... Figure 7The gate driver block 50 is shown, but an undervoltage lockout 53 and an AND gate 74 are added between the level shifter 51 and the gate driver 52.

[0150] AND gate 74 receives the second logic signal V at the output of level shifter 51. LSO and the fourth logic signal V from undervoltage lockout 53 OK These two serve as inputs. The logic output of the AND gate presents the fifth logic signal V. LSO_OK Its intervention allows the level shifter 51 to cause the gate driver 52 to output the third logic signal V. SWO The only time the value of the fully driven switch is set is when undervoltage lockout 53 is triggered via the fourth logic signal V. OK When permission is granted to do so, the undervoltage lockout 53 will only do so when it deems the switch ready to perform its function. The undervoltage lockout 53 uses... Figure 13 The circuit shown in the diagram is used to do this.

[0151] Now refer to Figure 13 Undervoltage lockout 53 is supplied by the second positive voltage V DDO With the second negative supply voltage V SSO The voltage comparator 49, powered by the voltage difference between the two voltages, is characterized.

[0152] The input of the first comparator is connected to the tap voltage V located between the first and second resistors R1 and R2. DIV The voltage across the first and second resistors R1 and R2 is equal to the difference in the second supply voltage. Therefore, the tap voltage V DIV It is part of the second supply voltage difference. The second comparator input is connected to generate the threshold voltage V. THUV The threshold voltage source V53. Voltage comparator 49 compares the first and second comparator inputs and only compares the tap voltage V. DIV Greater than the threshold voltage V THUV The fourth logic signal V is generated only at this time. OK The fourth logic signal V OK Inform the gate driver block 50 that the switch is now ready to be driven.

[0153] Other possible implementations of the undervoltage lockout 53 include directly connecting the first comparator input to the second positive supply voltage V. DDO Alternatively, a bandgap circuit can be used instead of the threshold voltage source V53 to generate the threshold voltage V. THUV Another implementation of undervoltage lockout 53 relies on a skewed inverter instead of a voltage comparator 49.

[0154] Using the bypass path described above is not the only mechanism for reducing the time spent starting up the power converter 10.

[0155] like Figure 14 As shown, the alternative embodiment is characterized by a power converter 10 that operates as follows: receiving an input voltage V provided by a voltage source 12. IN And convert it into the output voltage V at output capacitor 14. OUT The output capacitor 14 is connected to the load 15. The power converter 10 includes a controller 16, a charge pump 20, and an insulating element 11 connected in series between the voltage source 12 and the charge pump 20.

[0156] Thermal insulation element 11 receives input voltage V IN This generates the intermediate voltage V across the intermediate capacitor 24. X And then the intermediate voltage V X The intermediate voltage V is supplied to charge pump 20. Then, charge pump 20 delivers the intermediate voltage V. X Transformed to a voltage higher than the input voltage V IN Output voltage V OUT The thermal insulation element 11 allows the charge pump 20 to be thermally charged.

[0157] Controller 16 receives a set of input signals and generates a set of output signals. Some of these input signals arrive along input signal path 23. These input signals carry information instructing the operation of the power converter. Controller 16 also receives a clock signal CLK and external signals IO, which may be analog, digital, or a combination of both. Based on the signals received by controller 16, controller 16 generates first, second, third, and fourth control signals 25, 26, 21, and 22, which together control the operation of the thermal insulation element 11 and the charge pump 20.

[0158] Other examples of charge pump 20 include trapezoidal, Dixon, series-parallel, Fibonacci, and multiplier types, all of which can be adiabatic charged and configured as multiphase or single-phase networks. A particularly useful charge pump 20 is an adiabatic-charged version of a full-wave cascaded multiplier. However, a non-adiabatic-charged version can also be used.

[0159] As used herein, "adiabatic" changing the charge on a capacitor means changing at least some of the charge stored in the capacitor by passing it through a non-capacitive element. A positive adiabatic change in the charge on a capacitor is considered adiabatic charging, while a negative adiabatic change in the charge on a capacitor is considered adiabatic discharging. Examples of non-capacitive elements include inductors, magnetic elements, resistors, and combinations thereof.

[0160] In some cases, a capacitor can be adiabatically charged for a portion of the time and non-diabatically charged for the remainder. Such a capacitor is considered adiabatically charged. Similarly, in some cases, a capacitor can be adiabatically discharged for a portion of the time and non-diabatically discharged for the remainder. Such a capacitor is considered adiabatically discharged.

[0161] Non-adiabatic charging includes all charging that is not adiabatic, and non-adiabatic discharging includes all discharging that is not adiabatic.

[0162] As used herein, an adiabatic charging switching network is a switching network having at least one capacitor capable of both adiabatic charging and adiabatic discharging. A non-adiabatic charging switching network is a switching network that is not an adiabatic charging switching network.

[0163] Figure 15 and Figure 16 It shows in Figure 14 A specific implementation of the insulating element 11 in the context of the boost power converter 10 shown.

[0164] exist Figure 15 In this example, the thermal insulation element 11 includes an inductor L. The third and fourth control signals 21 and 22 from the controller 16 are not used. In the off state, when the charge pump 20 neither operates nor switches, the intermediate voltage V across the intermediate capacitor 24... X Equal to the input voltage V provided by voltage source 12 IN .

[0165] exist Figure 16 In the process, the thermal insulation element 11 includes an inductor L and a current-blocking element that blocks current in one direction but allows current to flow in the other direction. The inductor L is connected to the input voltage V. IN With node V PS Between. The current blocking element is connected at node V. PS With the intermediate voltage V received by charge pump 20 X between.

[0166] Some implementations use a current blocking element as a starting diode D. 21 It is oriented to allow current to flow to charge pump 20 but block current flowing out of charge pump 20.

[0167] In other embodiments, the current blocking element is implemented as a starter switch S. 21 It mimics the starting diode D 21 The operation of the switch is such that it closes to allow forward current to flow through the inductor L toward the charge pump 20 and opens to prevent reverse current from flowing out of the charge pump 20. In these embodiments, a third control signal 21 from the controller 16 controls the start switch S.21 .

[0168] Although it is possible Figure 16 Implementing the starting diode D 21 Or start switch S 21 However, starting diode D 21 It offers the advantage of not requiring a separate control circuit. On the other hand, the starter switch S... 21 It will not introduce a starting diode D 21 The same forward voltage drop. In some implementations, the starter switch S 21 and starting diode D 21 They can all exist and be configured to collaborate.

[0169] It has a start switch S 21 Or starting diode D 21 Allowable intermediate voltage V X Equal to or substantially higher than the input voltage V IN Before the charge pump 20 switches on, it has a voltage higher than the input voltage V. IN intermediate voltage V X It will be especially useful.

[0170] With a high intermediate voltage V X One advantage is that such a voltage can be used to start the stack node V. C1 To V C5 This makes each stack node V C1 To V C5 It initiates charge pump operation with a lead at its voltage. Because of this lead, even when crossing stack nodes V... C1 To V C5 When the voltage of the charge pump 20 is consumed by its upstream diodes D1 to D5, sufficient residual voltage will be retained to reduce the delay associated with the start of the correct stacked switch activity when the charge pump 20 starts operating.

[0171] Some implementations pump intermediate voltage V X To further improve the startup of stack node V before charge pump 20 operates. C1 To V C5 This capability can be achieved by increasing the input voltage V when the voltage source 12 first supplies power to the power converter 10. IN The conversion rate or rise time is used for execution.

[0172] exist Figures 15 to 16 In the circuit, inductor L and intermediate capacitor 24 form an LC filter, whose time constant τ is proportional to the square root of the inductance and capacitance. The input voltage V is approximately equal to or less than the time constant τ. IN The switching rate at the point causes a large forward current through the inductor L. This, in turn, causes the intermediate voltage V to...X Surge exceeding input voltage V IN This phenomenon will be referred to as the intermediate capacitor C in this paper. VX "Overcharging".

[0173] exist Figure 15 In this case, as the current induced through inductor L returns to approximately zero, the intermediate voltage V... X Then it will rotate in a sinusoidal pattern around the input voltage V. IN The average voltage fluctuates or oscillates. Eventually, the amplitude of the oscillation will decrease, and the intermediate voltage V... X This will be equal to the input voltage V. IN .

[0174] exist Figure 16 In this configuration, only forward current flow is permitted. This can be achieved using the starting diode D. 21 In cases where it is passively completed, or when the start switch S is activated. 21 This is done actively under certain circumstances. In either case, the result is a response to the input voltage V. IN Similar conversion rate at the intermediate voltage V X Positive voltage rectification is performed at the point.

[0175] Intermediate voltage V X The first half of the sinusoidal oscillation at that point follows Figure 15 intermediate voltage V X The first half of the sinusoidal oscillation occurs at a certain point, but this is due to the starting diode D. 21 The inherent positive voltage drop or across the starting switch S 21 The inherently small voltage drop causes a voltage decrease. The latter half of the sinusoidal oscillation does not follow... Figure 15 The latter half of the sinusoidal oscillation in the image. Instead, it disappears.

[0176] The disappearance of the latter half of the sinusoidal oscillation is caused by the provision of the starting diode D. 21 Or start switch S 21 To block the flow of reverse current.

[0177] By allowing forward current and then blocking reverse current, the starting diode D is activated. 21 Or start switch S 21 Effectively capture the response of input voltage V IN The conversion rate at the intermediate voltage V X The initial voltage overshoot at the point introduces a charge surge. Intermediate capacitor 24 stores this captured charge and uses it to support the stacked node V. C1 To V C5 The voltage on it.

[0178] It should be noted that most hosts using the power converter 10 have an input voltage V IN The power converter 10 has no say in the conversion rate or rise time. Most such hosts will simply supply the input voltage and expect the power converter 10 to perform whatever operation is required for startup and provide a stable output voltage.

[0179] Depending on the nature of the host, the input voltage V IN The power source can be a battery, a USB-powered rail, the DC output of an AC adapter, the output of another power converter, a solar panel, or anywhere else. Typically, the power converter 10 will not be able to control the conversion rate presented to it by the input voltage. Therefore, regardless of the input voltage V... IN Regardless of the associated conversion rate presented to the power converter 10, the power converter 10 should be able to start and operate.

[0180] If the input voltage V IN The conversion rate presented is higher than Figure 16 The time constant τ of the equivalent LC filter shown is much slower, so it is more efficient for starting the stacked nodes V. C1 To V C5 This will be insufficient. This is because the input voltage V IN The slow switching rate at the point allows for an intermediate voltage V X Closely follow the input voltage V IN This minimizes the voltage difference across inductor L, and thus prevents the resulting forward current from being large enough to affect the intermediate voltage V. X Overcharging occurs. Therefore, the intermediate voltage V X The surge voltage V must not exceed the input voltage V. IN And then the oscillation becomes a decaying sine curve, because it will cause the input voltage V to... IN It is presented with a fast conversion rate. Conversely, the intermediate voltage V... X Simply track the slowly rising input voltage V IN However, its amplitude decreased due to the starting diode D. 21 Or start switch S 21 The voltage drop caused by the current.

[0181] Therefore, it is expected that the input voltage V IN The starting intermediate voltage V is provided in a way that is independent of how fast it initially rises. X and stacked nodes V C1 To V C5 The voltage at that point.

[0182] Refer again Figure 16 One solution involves initially disconnecting the starter switch S. 21This blocks all current flow through inductor L. A non-zero input voltage V is detected at the input of the power converter. IN Then, start switch S 21 The circuit closes, introducing an instantaneous voltage difference across inductor L and allowing forward current to flow. This forward current flows from the input terminal of the power converter through inductor L and toward the input of the charge pump. Eventually, the magnitude of the forward current decays to zero and begins to increase in the negative direction. This is the reverse current. Upon detection of the reverse current, or alternatively, after an appropriate interval, the start switch S is activated. 21 Disconnect. Therefore, start switch S is activated. 21 Block reverse current, otherwise this will lower the intermediate voltage V. X At this point, the intermediate voltage V should be activated. X And the stacked node voltage, and charge pump 20 can begin operation in steady-state mode. Upon closing the start switch S 21 The instantaneous voltage difference introduced across the inductor L is similar to that introduced at the input voltage V. IN Apply a fast conversion rate at the location.

[0183] Figure 17 This shows how to implement the start switch S 21 The circuit for starting function.

[0184] Starter switch S 21 Having a first switching terminal V PS Second switch terminal V X Between these terminals is a PMOS transistor M. 21B It has a source-drain path and a series diode D along the source-drain path. 21A .

[0185] The drain and source terminals of the PMOS transistor are connected, so that the body diode of the PMOS transistor uses its cathode at the first switching terminal V. PS The anode of the circuit is connected to the inductor L, and its anode is connected to the series diode D. 21A As long as the body diode of the NMOS transistor has the orientation described above, an NMOS transistor can be used instead of a PMOS transistor M. 21B .

[0186] When the forward and reverse currents flowing through the inductor L are blocked at the start of power converter 10, the gate voltage V is adjusted accordingly. 21B Floating or by adjusting the gate voltage V 21B Connect to the first node V PS Essentially, this makes the PMOS transistor M 21B The gate terminal and source terminal are short-circuited to disconnect the start switch S. 21 .

[0187] A non-zero input voltage V is detected at the input of the power converter. IN Then, start switch S 21 Close to allow forward current flow. Close start switch S. 21 One approach is to set the threshold below the first node V. PS The voltage at the point, and then make the gate voltage V 21B The bias keeps it below that threshold. At the start switch S 21 With this closed state, the source-drain path is conducting. This requires that the PMOS transistor M... 21B The gate-source rated voltage of the series diode D. 21A Ultimately, this blocks the reverse current from flowing through inductor L, while the PMOS transistor M... 21B Keep it on throughout the entire charge pump operation.

[0188] A starter switch S that includes only the switch and excludes the diode. 21 Other implementations are possible, at the cost of using more complex circuitry to control each switch.

[0189] With the input voltage V IN The starting intermediate voltage V is provided in a way that is independent of how fast it initially rises. X and stacked node voltage V C1 V C2 V C3 V C4 V C5 Another solution avoids the use of making Figure 17 The start switch S shown in the figure 21 This reduces design complexity and additional chip area. The solution relies on using the low-side phase switches S7 and S8 within the charge pump 20 as start-up switches before the charge pump switching begins.

[0190] The charge pump 20 is shut down, leaving all switches in their open positions. The start-up sequence of the charge pump 20 begins with closing two of the lower-side phase switches S7 and S8 for a certain duration before switching the odd-numbered stacked switches S1, S3, S5 and the odd-numbered phase switches S7, S9 to the even-numbered stacked switches S2, S4 and the even-numbered phase switches S6, S8 in opposite phases. The initial closing of the lower-side phase switches S7 and S8 during startup causes the pump capacitors C1 to C4 to be charged for the first time. This charge initially comes from the intermediate capacitor 24.

[0191] If the intermediate capacitor 24 is large, it will have a significant amount of charge available to charge the pump capacitors C1 through C4. This means that the voltage across the intermediate capacitor 24 will not change much. Therefore, the intermediate voltage V X It will remain relatively constant.

[0192] On the other hand, if the intermediate capacitor 24 has only a small capacitance relative to the pump capacitors C1 to C4, it will not have enough charge available for the initial charging of the pump capacitors C1 to C4. This means that when the pump capacitors C1 to C4 draw charge from the intermediate capacitor 24, they quickly deplete the charge supply of the intermediate capacitor. Since the voltage across a capacitor depends on how much charge it has, this sudden loss of charge on the intermediate capacitor 24 results in a decrease in the intermediate voltage V. X collapse.

[0193] Intermediate voltage V X The collapse of the circuit produces a sudden voltage difference across inductor L. Since the current through the inductor is the time integral of the voltage across the inductor, the sudden appearance of this voltage difference will cause an increase in the forward current in inductor L, similar to the effect of a current flowing through the inductor. Figure 16 The power converter 10 shown applies an input voltage V with a fast conversion rate. IN The effect.

[0194] The resulting current flows in the positive direction through inductor L and through starting diode D. 21 And toward charge pump 20. Some of this current replenishes the charge supply in intermediate capacitor 24, thereby restoring the intermediate voltage V across intermediate capacitor 24. X Some of this current continues into charge pump 20, where it charges pump capacitors C1 to C4.

[0195] With the intermediate voltage V X As the voltage difference across inductor L is re-established, it will decrease. Therefore, the time integral of the voltage difference will also decrease. Consequently, the forward current induced through inductor L will begin to decrease until it eventually reaches zero.

[0196] The magnitude of the resulting positive current depends on the value of the inductor L and the input voltage V. IN And the relative values ​​of intermediate capacitor 24 and pump capacitors C1 to C4. This amplitude will initially be very high. In fact, the resulting forward current can initially be high enough to temporarily raise the intermediate voltage V. X Even higher than the input voltage V IN This is precisely why the stack node voltage V is increased. C1 V C2 V C3 V C4 V C5 Required.

[0197] Therefore, it is evident that by intentionally making the intermediate capacitor 24 insufficient to supply all the charge required to start the stacked node voltage, a considerable current can be provided from which the pump capacitors C1 to C4 can obtain all the charge they need.

[0198] The use of an improperly sized intermediate capacitor 24 also has a synergistic effect during steady-state operation by enhancing the adiabatic charging and discharging of pump capacitors C1 to C4. This can help improve the electrical efficiency of charge pump 20.

[0199] This starting method is more efficient than adding or making a starter switch S. 21 It is simpler because it utilizes the existing low-side phase switches S7 and S8 within the charge pump 20 without requiring additional devices. Furthermore, the modifications required for the control signals EN7 and EN8 to perform the start-up function before the charge pump operates are relatively straightforward.

[0200] As before Figure 2 and Figure 6 As described, the charge pump controller 66 places control signals EN1 to EN9 on the control signal path 60 to cause the stacked switches S1 to S5 and the phase switches S6 to S9 to change states according to a specific sequence. The charge pump controller 66 does this in response to receiving a first control signal 25 and a second control signal 26 from the controller 16, as... Figure 16 As shown in the diagram. One possible implementation is that the first control signal 25 controls the low-side phase switches S7 and S8 as start switches until the second control signal 26 is activated to enable the charge pump 20 to switch.

[0201] The limitation of the aforementioned methods is that they apply the intermediate voltage V in a highly application-dependent manner. X and stacked node voltage V C1 V C2 V C3 V C4 V C5 This can lead to starting or overcharging. For example, the amount of voltage overcharging depends on the inductance of inductor L, the capacitance of pump capacitors C1 to C4, and the input voltage V. IN And the switching resistor. In some cases, the amount of voltage overcharge can exceed the rated voltage of the transistor used to implement the charge pump switch. At the input voltage V IN This is especially true when the amplitude is high, and coincidentally, the need for starting is also reduced.

[0202] Figure 18 This illustrates a state transition implemented in controller 16 using some or all of the signals received along input signal path 23 when power converter 10 starts from off state 70. Controller 16 implements each state transition by sending first and second control signals 25, 26 to charge pump 20.

[0203] When the power converter 10 is in the off state 70, it can remain in the off state 70 or transition to the first decision state 71 based on other state machine inputs. These other state machine inputs include, for example, whether the power converter 10 has been enabled or disabled and whether any existing faults exist.

[0204] If an input indicating a fault is present or an input indicating that the power converter 10 should remain disabled is present, the controller 16 executes a state transition T70, in which the power converter 10 remains in the off state 70. Conversely, if an enable input is present and no fault is present, the controller 16 transitions from the off state 70 to the first determination state 71 by executing a state transition T71.

[0205] During the first determination state 71, the controller 16 will input voltage V IN The amplitude and the starting threshold voltage V INIT The comparison is performed. In some implementations, it uses a voltage comparator within the controller 16 to do this. If the input voltage V IN Below the starting threshold voltage V INIT Then starting will be necessary.

[0206] Assuming startup is deemed necessary, controller 16 transitions from first determination state 71 to start-up enabled state 72 by executing state transition T72. In start-up enabled state 72, controller 16 sends control signals to cause the execution of the appropriate startup procedure. In some embodiments, this includes closing the start switch S. 21 transistor M 21B In other embodiments, this includes closing the low-side phase switches S7 and S8.

[0207] Finally, after a predetermined time interval or after startup is complete, controller 16 transitions from startup state 72 to operation state 75 by executing state transition T77. In operation state 75, controller 16 operates charge pump 20 according to its steady-state sequence.

[0208] Conversely, if during the first determination state 71, the controller 16 determines the input voltage V IN higher than the starting threshold voltage V INIT Then, controller 16 transitions from the first decision state 71 to the disabled start state 73 by executing state transition T73. In this state, controller 16 disables start-up to avoid interference with the intermediate voltage V. X Perform overcharging and increase the stack node voltage V C1 V C2 V C3 V C4 V C5 Increase it above the rated voltage of its transistor.

[0209] Finally, after a predetermined duration or after the pump capacitors C1 to C4 are fully charged, the controller 16 transitions from the disabled start-up state 73 to the operating state 75 by executing state transition T75. During the operating state, the controller 16 enables the charge pump 20 to operate in its steady state.

[0210] In both the enabled startup state 72 and the disabled startup state 73, pump capacitors C1 to C4 are charged for the first time since exiting the shutdown state 70. The key difference between the enabled startup state 72 and the disabled startup state 73 lies in the charging rate, which determines the intermediate voltage V. X and stacked node voltage V C1 V C2 V C3 V C4 V C5 Is it overcharged or started up to the input voltage V? IN The above describes the process. Enabling startup state 72 causes overcharging or startup by inducing a large forward current through inductor L. By comparison, disabling startup state 73 avoids overcharging by not inducing a large forward current through inductor L.

[0211] One way to disable startup is to reduce the input voltage V. IN The conversion rate. Another way to do this is to bypass those components within the power converter 10 that can behave like a start switch, or alternatively, at least control them so that they do not behave like a start switch. In one example, by closing the start switch S throughout the disabled start state 73. 21 Simultaneously allowing both forward and reverse inductor current flow, it can... Figure 16 The behavior of the insulating element 11 shown in the figure is like Figure 15 The insulating element 11 is shown in the figure.

[0212] As previously mentioned Figure 16 The power converter 10 described herein is used in the presence of a non-zero input voltage V. IN When the low-side phase switches S7 and S8 are closed, the starting diode D is activated. 21 The connection boosts startup and blocks reverse current flow. Therefore, it is necessary to close these switches in a way that would inadvertently boost the startup of stacked nodes.

[0213] Without increasing stack node V C1 To V C4 One way to close the low-side phase switches S7 and S8 during startup is to provide the input voltage V. IN Previously, or even in the absence of input voltage V IN They are closed during this period. This step avoids the starting intermediate voltage V.X .

[0214] However, in the absence of input voltage V IN Closing the low-side phase switches S7 and S8 may not always be possible, especially when the first and second positive supply voltages V DDI V DDO Also from the input voltage V IN When obtained. In addition, the input voltage V to be provided should be known in advance. IN Is it higher or lower than the starting threshold voltage V? INIT It has become necessary, but obtaining it remains unrealistic.

[0215] Another way to disable the starting state 73 is to reduce the switch's ability to act as a starter switch. For example, when a non-zero input voltage V is present... IN When the low-side phase switches S7 and S8 are closed under certain conditions, the closing action can be controlled by limiting the current flowing through switches S7 and S8, thereby also limiting the current induced through inductor L and the charging rate of pump capacitors C1 to C4. This current limiting or current control method for closing the low-side phase switches S7 and S8 can be implemented in several ways.

[0216] exist Figure 6 In the embodiment shown, the seventh and eighth transistors M7 and M8 implement low-side phase switches S7 and S8. The seventh and eighth gate drivers G7 and G8 drive the seventh and eighth transistors M7 and M8 in response to control signals EN7 and EN8, respectively, and the seventh and eighth transistors M7 and M8 experience a voltage from the first positive supply voltage V. DDI and the first negative supply voltage V SSI To the second positive supply voltage V DDO Second negative supply voltage V SSO Voltage conversion. In some implementations, the second positive supply voltage V DDO It can be connected to the first positive supply voltage V DDI Or intermediate voltage V X The same. However, it is also possible to utilize a second positive supply voltage V. DDO The independent source is used to achieve the current limiting closure of the seventh and eighth transistors M7 and M8.

[0217] One approach relies on the effect of gate voltage on the transistor's conductive path. At a sufficiently low gate voltage, the transistor's conductive path becomes smaller and therefore has higher resistance. This, in turn, reduces the current that can pass through. Therefore, an alternative way to control the transistor current is to use a low second positive supply voltage V used to drive the seventh and eighth transistors M7, M8. DDO Start by gradually increasing the voltage to a higher level throughout the entire duration of the disabled startup state 73.

[0218] Another approach relies on having seventh and eighth transistors M7 and M8, which have multiple conductive channels connected in parallel and individually controllable. This is not uncommon for power FETs. In this case, by allowing some, but not all, of these channels to conduct during the disabled startup state 73, the total resistance can be increased, and thus the input current reduced, to avoid startup.

[0219] The relevant method involves connecting the higher-resistance transistors in parallel with the seventh and eighth transistors M7 and M8. These higher-resistance transistors will be turned on during the disabled startup state 73, while the seventh and eighth transistors M7 and M8 remain off. When the disabled startup state 73 ends, the seventh and eighth transistors M7 and M8 will take over, allowing the low-resistance channel to dominate.

[0220] The above method for current limiting closure of low-side phase switches S7 and S8 can also be used for starting switch S. 21 More complex methods for controlling the switching current when closed may involve using a current-sensing amplifier or regulator that monitors the transistor current or inductor current and adjusts the transistor gate voltage accordingly.

[0221] Used to start the intermediate voltage V X and stacked node voltage V C1 V C2 V C3 V C4 V C5 Another method is available when the insulating element 11 is an inductor-based regulator. In this case, the inductor-based regulator itself can be used to start the intermediate voltage V. X and stacked node voltage V C1 V C2 V C3 V C4 V C5 .

[0222] Figure 19 It shows Figure 14 The third example of the power converter 10 shown in the figure includes an insulating element 11 comprising a regulator 18. The regulator 18 receives an input voltage V. IN And then an intermediate voltage V is generated. X And the intermediate voltage V X The intermediate voltage V is supplied to charge pump 20. Then, charge pump 20 delivers the intermediate voltage V. X Transformed to a voltage higher than the input voltage V IN Output voltage V OUT .

[0223] Figure 20A regulator 18 is shown, which receives input voltages across first and second regulator terminals 41, 42 and generates output voltages across third and fourth regulator terminals 43, 44. In addition to the inductor L, regulator 18 includes first, second, third, and fourth regulator switches S. A S B S C S D The switch control circuit 40 is based on... Figure 19 The third and fourth control signals 21 and 22 of the controller 16 are used to control these switches.

[0224] In the illustrated embodiment, regulator 18 can be reconfigured to operate in different modes. A fourth control signal 22 triggers such reconfiguration. However, regulator 18 typically does not need to be reconfigurable.

[0225] When regulator 18 operates in depressurization mode, the third regulator switch S is active throughout each switching cycle. C Keep "on" while the fourth regulator switch S D Keep it "off". First regulator switch S A The duty cycle or on-time of regulator 18 transitions between "on" and "off". This duty cycle depends on the third control signal 21. The second regulator switch S... B It can switch between "on" and "off", making its state similar to that of the first regulator switch S. A The states are complementary. Some implementations of such a regulator 18 omit the fourth regulator switch S. D Furthermore, the third regulator switch S is replaced by a direct connection to the third regulator terminal 43. C .

[0226] When regulator 18 operates in boost mode, the first regulator switch S is active throughout each switching cycle. A Keep "on" while the second regulator switch S B Keep it "Off". Fourth regulator switch S D The regulator 18 switches between "on" and "off" based on the duty cycle or on-time determined by the third control signal 21. C The state changes between "on" and "off", making its state consistent with the fourth regulator switch S. D The states are complementary. Some implementations omit the second regulator switch S. B Furthermore, the first regulator switch S is replaced by a direct connection to the first regulator terminal 41. A This reduces the number of switches to just two.

[0227] When regulator 18 operates in pressure-boosting mode, the first, second, third, and fourth regulator switches S A S B S C S D The switching between "on" and "off" states, in response to the third control signal 21, occurs at the same time during each switching cycle, while some switch at different times. The switch control circuit 40 controls and sequences all regulator switches S in the following manner. A To S D The transition, in this manner, causes the first, second, third, and fourth regulator switches S to be integrated according to the depressurization mode, boost mode, or depressurization-boost mode specified by the fourth control signal 22. A S B S C S D Any necessary dead time required during operation.

[0228] Based on the information indicating the operation of the power converter, controller 16 sends a third control signal 21 to control the first to fourth regulator switches S. A To S D The duty cycle is adjusted, and thus the output voltage across the third and fourth regulator terminals 43, 44 is regulated. Accordingly, the controller 16 uses some or all of the signals received along the input signal path 23, the clock signal CLK, and the external signal IO to define the feedback loop.

[0229] Many other regulator configurations are regulated by having a switch that periodically transitions the inductor between a first and a second state. An example of such a regulator configuration is... Figure 21 The boost converter shown in the figure and Figure 22 The non-inverting voltage reducer-boost converter shown is... Because... Figures 21 to 22 The regulator shown is not reconfigurable, so the fourth control signal 22 is unnecessary. However,

[0230] Figures 21 to 22 The regulators shown are characterized by one or more regulator switches that modulate the inductor L to achieve voltage regulation. In some cases, such as Figures 20 to 22 As shown, inductor L exists alone. In other cases, inductor L is part of a transformer. Figures 21 to 22 The regulator shown is also characterized by the possibility of being replaced by one or more regulator diodes implemented by switches. It should be noted that... Figure 21 The regulator diode D and shown in the figure Figure 22 The regulator diode D shown in the figure C Each can be used as a pair with Figure 16 The starting diode D shown in the figure 21Similar starting diodes. Other suitable regulators, not shown, include voltage-reducing converters, flyback converters, Cook converters, SEPIC converters, resonant converters, multilevel converters, forward converters, and full-bridge converters.

[0231] In U.S. Patent Nos. 8,860,396, 8,743,553, 8,723,491, 8,503,203, 8,693,224, 8,724,353, 8,619,445, 9,203,299, 9,742,266, 9,041,459, U.S. Publication No. 2017 / 0085172, and 9... Suitable regulators and charge pumps are described in detail in U.S. Patent No. 9,882,471, PCT Publication No. WO2017161368, PCT Publication No. WO2017 / 091696, PCT Publication No. WO2017 / 143044, PCT Publication No. WO2017 / 160821, PCT Publication No. WO2017 / 156532, PCT Publication No. WO2017 / 196826, and U.S. Publication No. 2017 / 0244318.

[0232] Figure 20 The regulator 18 shown can be used to start the stack node V using the previously described method. C1 To V C5 One such method involves increasing the input voltage V. IN The conversion rate or rise time and the closing regulator switch S A and S C This also prevents reverse inductor current flow. Another method involves coordinating with both the operation of charge pump 20 and regulator 18 before their respective operation. Figure 16 The start switch S in 21 The third regulator switch S is controlled in a similar manner. C Another alternative is to use the first regulator switch S. A As a start switch, it also keeps the third regulator switch S in place. C The circuit closes and the remaining regulator switches open. The switch control circuit 40 can be used to control a specific regulator switch as a start switch according to a fourth control signal 22, which is part of the reconfiguration at startup.

[0233] For a boost power converter that includes a regulator 18 that drives charge pump 20, startup may include operating regulator 18 before charge pump 20 begins switching, switching charge pump 20 before regulator 18 begins operating, or operating both regulator 18 and charge pump 20 simultaneously.

[0234] Firstly, operating the regulator 18 has the following advantages: it starts the intermediate voltage V within the charge pump 20 in a more controlled and accurate manner than the previously proposed starting method. X and stacked nodes V C1 To V C5 In these cases, regulator 18 starts the intermediate voltage V. X The degree of adjustment depends on its duty cycle. If the regulator 18 can already operate at a fixed minimum duty cycle, the simplest approach is to use only that fixed minimum duty cycle until the feedback loop takes over and sends the appropriate information via the third control signal 21 to update the duty cycle as needed for output voltage regulation.

[0235] However, a fixed minimum duty cycle may not be sufficient to start the intermediate voltage V. X Especially when the input voltage V supplied to the power converter 10 IN When the voltage is low. One solution is to use an adaptive duty cycle, which can be based on the input voltage V detected at the start of the regulator's operation. IN It has been adjusted to be greater than the minimum value. Input voltage V IN The lower the value, the greater the positive adjustment of the adaptive duty cycle, in order to ensure the intermediate voltage V. X Start at or above the minimum level. Conversely, the input voltage V detected at the start of regulator operation. IN The higher the voltage, the smaller the positive adjustment to the adaptive duty cycle, because at the intermediate voltage V... X It requires less startup at stacked nodes.

[0236] Alternatively, regulator 18 may rely on the feedback loop from the very beginning of its operation, and then by using the intermediate voltage V X The voltage is compared to a predetermined voltage threshold to await activation of the charge pump. At the intermediate voltage V... X The charge pump 20 does not participate in the switching until the predetermined voltage threshold is reached. Conversely, once the regulator 18 lowers the intermediate voltage V... X If the voltage is increased to or above a predetermined voltage threshold, the controller 16 provides a second control signal 26 to enable the charge pump 20 to perform a switching operation, such as... Figure 19 As shown.

[0237] The alternative method involves measuring the input voltage V before the regulator 18 or charge pump 20 begins operation. IN And then based on the input voltage V INTo determine whether startup is necessary. If startup is necessary, any of the startup methods described above, involving operating regulator 18 first, can be used. Otherwise, power converter 10 may choose to operate charge pump 20 before operating regulator 18, or it may choose to operate both charge pump 20 and regulator 18 simultaneously for faster startup.

[0238] In some implementations, the tangible and non-transitory computer-readable storage medium includes a database representing one or more components of the power converter 10. Among these implementations, the database includes an implementation of data representing the charge pump 20, which has been optimized to facilitate low-loss operation of the charge pump 20.

[0239] As used herein, computer-readable storage media includes any non-transitory storage medium that is accessible to a computer during use to provide instructions and / or data to a computer. Examples of computer-readable storage media include storage media such as magnetic disks, optical disks, and semiconductor memories. These are non-abstract structures composed of matter with interacting baryons and leptons.

[0240] In a particular implementation, the database representing the system is a database or other data structure that can be read by a program and used directly or indirectly to manufacture hardware including the system. The database is represented in the real world by rearranging certain properties of matter, such as charge and direction of rotation.

[0241] An example of such a database is a behavioral-level description or register-transfer-level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. This description can be read by a synthesis tool, which synthesizes it to produce a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware comprising the system. The netlist can then be positioned and routed to produce a dataset describing the geometry to be applied to a mask. The mask can then be used in various semiconductor manufacturing steps to produce one or more semiconductor circuits corresponding to the system. Alternatively, in other examples, the database itself can be a dataset or a netlist with or without a synthesis library.

[0242] This document has described various features, aspects, and implementations of switched capacitor power converters. As will be understood by those skilled in the art, the described features, aspects, and many implementations are readily combined with each other, as well as varied and modified. Therefore, this disclosure should be considered to cover such combinations, variations, and modifications.

[0243] Furthermore, the terms and expressions used herein are for descriptive purposes and not for limitation. In using such terms and expressions, no equivalents of the shown and described features or portions thereof are intended to be excluded. It should be understood that various modifications may be made within the scope of the claims. Other modifications, variations, and alternatives are also possible. Therefore, the claims are intended to cover all such equivalents.

[0244] The present invention and its preferred embodiments have been described, and the following claims, which are protected by a new patent certificate, are as follows.

Claims

1. A boost power converter, comprising: A cascaded multiplier for converting an input voltage into an output voltage, the cascaded multiplier comprising: Multiple pump capacitors are coupled to multiple stacked switches via corresponding multiple stacked nodes; Input terminals, which are used to receive the input voltage from a voltage source; and An output terminal having the output voltage, wherein the input voltage is less than the output voltage; A bypass path that directly connects the input terminal to one of the corresponding plurality of stack nodes while bypassing at least one other stack node, such that the stack node is charged by the input voltage to the stack node voltage value; A clock used to generate timing signals; and A controller that generates one or more control signals, at least in part based on the timing signal, to control the plurality of stacked switches, thereby facilitating one or more state transitions between a first operating state and a second operating state of the cascaded multiplier, at least in part based on the input voltage. In the first operating state: The first stacking node among the plurality of stacking nodes has a first stacking node voltage, and The second stacking node of the plurality of stacking nodes has a second stacking node voltage, which includes a voltage insufficient to operate the corresponding stacking switch among the plurality of stacking switches, and In the second operating state, the voltage of the second stack node is adjusted to include a voltage sufficient to operate the corresponding stack switch among the plurality of stack switches.

2. The boost power converter according to claim 1, wherein, In the first operating state, the voltage of the second stack node includes a voltage lower than that of the first stack node.

3. The boost power converter according to claim 1, wherein, In the second operating state, the voltage of the second stack node includes a voltage that is higher than that of the first stack node.

4. The boost power converter according to claim 1, wherein, In the second operating state, the voltage of the second stack node is adjusted to include a voltage that is an integer multiple of the input voltage.

5. The boost power converter according to claim 1, wherein, The corresponding stacking switch includes a stacking switch that can be operated via the second stacking node.

6. The boost power converter according to claim 1, wherein, The plurality of pump capacitors includes a second pump capacitor, wherein at least one of the plurality of pump capacitors is coupled to the first stack node, and the second pump capacitor is coupled to the second stack node.

7. The boost power converter according to claim 1, wherein, The corresponding stacking switch interconnects the second stacking node with the input terminal.

8. The boost power converter according to claim 1, wherein, The bypass path stops conducting current at the start of the transition from the first operating state to the second operating state.

9. The boost power converter according to claim 1, wherein, The boost power converter also includes an undervoltage lockout circuit to prevent the corresponding stacking switch from being operated when the voltage of the second stacking node is below a predetermined threshold.

10. The boost power converter according to claim 9, wherein, The undervoltage lockout circuit includes a comparator having a first input port, a second input port, and an output port. The comparator compares a tap voltage provided via the first input port with a predetermined threshold voltage provided via the second input port, and provides a logic signal via the output port when it determines that the tap voltage is greater than the predetermined threshold voltage.

11. The boost power converter according to claim 10, wherein, The logic signal is used at least in part to indicate that the corresponding stack switch is ready to be operated, and the absence of the logic signal is used at least in part to indicate that the corresponding stack switch is not ready to be operated.

12. The boost power converter according to claim 9, wherein, The undervoltage lockout circuit includes a first resistor and a second resistor, which are coupled across the supply voltage to form a voltage divider.

13. The boost power converter according to claim 1, wherein, During the first operating state, current flows between the input terminal and the output terminal, and during the second operating state, the current stops flowing between the input terminal and the output terminal.

14. The boost power converter according to claim 1, wherein, The bypass path is connected to the stack node of at least one output capacitor of the boost power converter.

15. The boost power converter according to claim 1, wherein, The bypass path is configured to conduct current when the voltage at the stack node drops below the input voltage value.

16. The boost power converter according to claim 1, wherein, The bypass path also includes a bypass switch.

17. The boost power converter according to claim 1, wherein, The bypass path includes a diode.

18. The boost power converter of claim 1, further comprising a plurality of phase nodes connected to the plurality of pump capacitors.

19. The boost power converter according to claim 1 further includes a bypass switch and a diode.

20. The boost power converter according to claim 1, wherein, The cascade multiplier is a single-symmetric cascade multiplier.

21. The boost power converter according to claim 20, wherein, The cascaded multiplier also includes multiple phase switches for coupling multiple phase nodes to the input terminal.

22. The boost power converter according to claim 1, wherein, The cascade multiplier includes at least one stage, wherein each of the at least one stage includes at least one of the following: Stacking switches; Stacked nodes; or Pump capacitor.

23. A power converter including an input port for receiving an input voltage and an output port for providing an output voltage, the power converter comprising: The clock that generates the clock signal; A switched capacitor device includes an input terminal for receiving a first voltage and an output terminal for outputting a second voltage, the switched capacitor device including a plurality of pump capacitors coupled to a plurality of stacked switches via corresponding plurality of stacked nodes; A controller that generates one or more control signals, at least in part based on the clock signal, to control the plurality of stacked switches, thereby facilitating one or more state transitions between a first operating state and a second operating state of the switched capacitor device, at least in part based on the first voltage. An intermediate capacitor is coupled between the input terminal of the switched capacitor device and ground. as well as An inductor, coupled between the input port of the power converter and the input of the switched capacitor device, is combined with the intermediate capacitor to form an LC filter. The LC filter is configured to induce a forward current through the inductor of the LC filter, at least in part based on the slew rate at the input voltage being substantially equal to or less than the time constant of the LC filter, to increase the intermediate voltage to a level greater than the input voltage. The positive current facilitates the transfer of charge to the intermediate capacitor, thereby enabling it to be used to charge at least one of the pump capacitors.

24. The power converter according to claim 23, wherein, The one or more control signals facilitate the operation of the switched capacitor device by controlling the slewing rate at the input voltage.

25. The power converter according to claim 23, wherein, The switched capacitor device includes any one of the following: Trapezoid; Dixon; Series and parallel; Fibonacci; or Doubling device.

26. The power converter according to claim 23, wherein, The switched capacitor device is thermally charged.

27. The power converter according to claim 23, wherein, The switched capacitor device is charged in a non-adiabatic manner.

28. The power converter according to claim 23, wherein, In the off state, the intermediate voltage is substantially equal to the input voltage.

29. The power converter according to claim 28, wherein, The forward current causes the intermediate voltage to oscillate sinusoidally around an average voltage that is substantially equal to the input voltage.

30. The power converter according to claim 29, wherein, The intermediate capacitor stores the charge captured from the oscillation of the intermediate voltage.

31. The power converter according to claim 30, wherein, The intermediate capacitor uses the captured charge to support the voltage associated with the plurality of stacked nodes.

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