Envelope Tracking Amplifier Circuit

Abstract

An envelope tracking (ET) amplifier circuit is provided. The ET amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal based on an ET modulation voltage. The ET modulation voltage corresponds to a time-varying voltage envelope, which may not align with the time-varying signal envelope of the RF signal due to inherent time delays in the ET amplifier circuit. Therefore, the amplifier circuit may suffer from degraded linear performance. In this regard, a voltage processing circuit is provided in the ET amplifier circuit, and the voltage processing circuit is configured to operate in a low bandwidth mode and a high bandwidth mode. In the high bandwidth mode, the voltage processing circuit is configured to cause the ET modulation voltage to be modified to help improve the delay tolerance of the ET amplifier circuit. Therefore, the linear degradation of the amplifier circuit can be reduced to a predetermined threshold.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 691,454, filed on June 28, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] The disclosed techniques generally relate to envelope tracking (ET) power management in wireless communication devices. Background Art

[0004] Mobile communication devices are becoming increasingly common in today's society. The popularity of these mobile communication devices is driven in part by the many features now enabled on such devices. Increased processing power in such devices has meant that mobile communication devices have evolved from being mere communication tools to sophisticated mobile multimedia centers, enabling an enhanced user experience.

[0005] The redefined user experience requires higher data rates provided by wireless communication technologies such as Long Term Evolution (LTE). To achieve higher data rates in mobile communication devices, complex power amplifiers (PAs) may be employed to increase the output power (e.g., to maintain sufficient energy per bit) of radio frequency (RF) signals transmitted by the mobile communication devices. However, the increased output power of RF signals may result in increased power consumption and heat dissipation in the mobile communication devices, thereby compromising overall performance and user experience.

[0006] Envelope tracking is a power management technique designed to improve the efficiency level of PAs to help reduce power consumption and heat dissipation in mobile communication devices. As the name implies, envelope tracking employs a system to track the amplitude envelope of the RF signal transmitted by the mobile communication device. The envelope tracking system continuously adjusts the supply voltage applied to the PA to ensure that the PA operates at a higher efficiency for a given instantaneous output power requirement of the RF signal.

[0007] However, envelope tracking systems can only maintain good linearity and high efficiency up to an inherent bandwidth limit. With the advent of fifth generation new radio (5G-NR) technology, RF signals can be modulated at higher bandwidths (e.g., >100 MHz) than the inherent bandwidth limit of envelope tracking systems, thereby reducing the linearity and efficiency of envelope tracking systems. Therefore, it may be desirable to improve the linearity and efficiency of envelope tracking systems to support 5G-NR technology. Summary of the invention

[0008] Various aspects disclosed in a specific embodiment include an envelope tracking (ET) amplifier circuit. The ET amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal based on an ET modulation voltage. The ET modulation voltage corresponds to a time-varying voltage envelope, which may not be aligned with the time-varying signal envelope of the RF signal due to inherent time delays in the ET amplifier circuit. Therefore, the amplifier circuit may suffer from degraded linear performance. In this regard, a voltage processing circuit is provided in the ET amplifier circuit, and the voltage processing circuit is configured to operate in a low bandwidth mode (e.g., a modulation bandwidth ≤ 60 MHz) and a high bandwidth mode (e.g., a modulation bandwidth> 60 MHz). In the high bandwidth mode, the voltage processing circuit is configured to cause the ET modulation voltage to be modified to help improve the delay tolerance of the ET amplifier circuit. Therefore, the linear degradation of the amplifier circuit can be reduced to a predetermined threshold.

[0009] In one aspect, an ET amplifier circuit is provided. The ET amplifier circuit includes an ET voltage circuit, which is configured to generate an ET modulation voltage corresponding to a time-varying voltage envelope. The ET amplifier circuit also includes a signal processing circuit, which is configured to generate an RF signal corresponding to a time-varying signal envelope. The ET amplifier circuit also includes an amplifier circuit configured to amplify the RF signal based on the ET modulation voltage. The ET amplifier circuit also includes a voltage processing circuit configured to operate in a low bandwidth mode and a high bandwidth mode. The voltage processing circuit is further configured to cause the ET voltage circuit to modify the ET modulation voltage in the high bandwidth mode to reduce the linear degradation caused by the time misalignment between the time-varying voltage envelope and the time-varying signal envelope at the amplifier circuit to a predetermined threshold.

[0010] Those skilled in the art will understand the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0012] Figure 1A is a schematic diagram of an exemplary prior art envelope tracking (ET) amplifier circuit that may experience degraded overall linearity performance due to inherent processing and / or propagation delays of prior art ET amplifier circuits;

[0013] Figure 1B is provided in Figure 1AA schematic diagram showing an exemplary illustration of a time misalignment between a time-varying voltage envelope and a time-varying signal envelope that may occur in a conventional ET amplifier circuit;

[0014] Figure 1C is provided how time delays can affect Figure 1A A schematic diagram showing an exemplary illustration of an adjacent channel leakage ratio (ACLR) of an amplifier circuit in a conventional ET amplifier circuit;

[0015] Figure 2 is a schematic diagram of an exemplary ET amplifier circuit configured to reduce linearity degradation by improving the delay margin of the ET amplifier circuit according to an embodiment of the present disclosure;

[0016] Figure 3 is configured according to an embodiment of the present disclosure and may be included in Figure 2 A schematic diagram of an exemplary digital voltage processing circuit in an ET amplifier circuit;

[0017] Figure 4A is a schematic diagram providing an exemplary illustration of generating a plurality of time-varying modified digital voltage amplitudes based on a constant voltage offset;

[0018] Figure 4B is a schematic diagram providing an exemplary illustration of generating a plurality of time-varying modified digital voltage amplitudes based on a plurality of variable voltage offsets;

[0019] Figure 5 is configured according to another embodiment of the present disclosure and may be included in Figure 2 A schematic diagram of an exemplary digital voltage processing circuit in an ET amplifier circuit;

[0020] Figure 6 is configured according to another embodiment of the present disclosure and may be included in Figure 2 a schematic diagram of an exemplary digital voltage processing circuit in an ET amplifier circuit of; and

[0021] Figure 7 is configured according to another embodiment of the present disclosure and may be included in Figure 2 Schematic diagram of an exemplary digital voltage processing circuit in an ET amplifier circuit. DETAILED DESCRIPTION

[0022] The embodiments set forth below represent necessary information to enable those skilled in the art to practice the embodiments, and show the best mode of practicing the embodiments. When reading the following description according to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize the application of these concepts not particularly noted herein. It should be understood that these concepts and applications all fall within the scope of the present disclosure and the appended claims.

[0023] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0024] It should be understood that when an element such as a layer, region or substrate is referred to as "on another element" or "extending onto another element", it may be directly on another element or directly extend to another element, or there may also be an intermediate element. In contrast, when an element is referred to as "directly on another element" or "directly extending onto another element", there is no intermediate element. Similarly, it should be understood that when an element such as a layer, region or substrate is referred to as "above another element" or "extending onto another element", it may be directly above another element or directly extend to another element, or there may also be an intermediate element. In contrast, when an element is referred to as "directly above another element" or "extending directly onto another element", there is no intermediate element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to another element, or there may be an intermediate element. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0025] As shown in the figures, relative terms such as "below" or "above" or "up" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region. It should be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0026] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. It will be further understood that the terms "comprises", "comprising", "includes", and / or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0028] Various aspects disclosed in a specific embodiment include an envelope tracking (ET) amplifier circuit. The ET amplifier circuit includes an amplifier circuit configured to amplify a radio frequency (RF) signal based on an ET modulation voltage. The ET modulation voltage corresponds to a time-varying voltage envelope, which may not be aligned with the time-varying signal envelope of the RF signal due to inherent time delays in the ET amplifier circuit. Therefore, the amplifier circuit may suffer from degraded linear performance. In this regard, a voltage processing circuit is provided in the ET amplifier circuit, and the voltage processing circuit is configured to operate in a low bandwidth mode (e.g., a modulation bandwidth ≤ 60 MHz) and a high bandwidth mode (e.g., a modulation bandwidth> 60 MHz). In the high bandwidth mode, the voltage processing circuit is configured to cause the ET modulation voltage to be modified to help improve the delay tolerance of the ET amplifier circuit. Therefore, the linear degradation of the amplifier circuit can be reduced to a predetermined threshold.

[0029] Before discussing the ET amplifier circuit of the present disclosure, first refer to Figures 1A to 1C A brief overview of existing ET amplifier circuits is provided, which may experience degraded overall linear performance due to inherent time delays associated with existing ET amplifier circuits. Figure 2 A discussion of specific exemplary aspects of the ET amplifier circuits of the present disclosure begins.

[0030] Figure 1A is a schematic diagram of an exemplary prior art ET amplifier circuit 10 that may experience degraded overall linear performance due to inherent processing and / or propagation delays of the prior art ET amplifier circuit 10. The prior art ET amplifier circuit 10 includes a signal processing circuit 12, an ET voltage circuit 14, and an amplifier circuit 16. The signal processing circuit 12 receives a digital signal 18 that includes a plurality of time-varying digital signal amplitudes 20 representing a time-varying digital signal envelope 22. The phrase "time-varying" is used hereinafter to refer to a parameter (e.g., amplitude, voltage, power, etc.) that changes (e.g., increases or decreases) over time.

[0031] The signal processing circuit 12 is configured to convert the digital signal 18 into an RF signal 24 having a time-varying signal envelope 26 formed based on the time-varying digital signal envelope 22. In this regard, the time-varying digital signal envelope 22 defined by the time-varying digital signal amplitude 20 may be considered a digital representation of the time-varying signal envelope 26.

[0032] The digital signal 18 may be modulated to include a digital in-phase signal 28I having a plurality of time-varying in-phase amplitudes I and a digital quadrature signal 28Q having a plurality of time-varying quadrature amplitudes Q. In this regard, the time-varying digital signal amplitude 20 of the digital signal 18 may be represented as

[0033] The prior art ET amplifier circuit 10 includes a mixer 30 that combines the time-varying digital signal amplitude 20 with a digital voltage reference signal 32 to produce a digital target voltage reference signal 34. In this regard, the digital target voltage reference signal 34 is associated with the time-varying digital signal envelope 22, and therefore, the time-varying digital signal amplitude 20.

[0034] The conventional ET amplifier circuit 10 includes a look-up table (LUT) circuit 36 ​​(in Figure 1A 4. The LUT circuit 36 ​​may be a digital signal processing circuit 36 ​​(denoted as "LUT") in the figure, which may store a plurality of predetermined target voltage amplitude values ​​corresponding to the time-varying digital signal amplitude 20. In this regard, the LUT circuit 36 ​​converts the time-varying digital signal amplitude 20 into a plurality of time-varying digital target voltage amplitudes 38 and associates the time-varying digital target voltage amplitudes 38 with the digital target voltage signal 40. As a result of this digital conversion, the time-varying digital target voltage amplitudes 38 may be distorted. For example, the LUT circuit 36 ​​may be non-strictly monotonic. Therefore, the digital target voltage amplitudes in the time-varying digital target voltage amplitudes 38 may become higher or lower than the corresponding digital signal amplitudes in the time-varying digital signal amplitudes 20.

[0035] The prior art ET amplifier circuit 10 includes a voltage digital-to-analog converter (DAC) 42 configured to convert a digital target voltage signal 40 into a target voltage signal 44 having a time-varying target voltage envelope 46 formed based on the time-varying digital target voltage amplitude 38. The DAC 42 is configured to provide the target voltage signal 44 to the ET voltage circuit 14.

[0036] The ET voltage circuit 14 receives a target voltage signal 44 having a time-varying target voltage envelope 46. The time-varying target voltage envelope 46 may represent a time-varying target voltage V for the ET voltage circuit 14. 目标 The ET voltage circuit 14 is configured to generate an ET modulation voltage V CC , which has a time-varying voltage envelope 48 that tracks the time-varying target voltage envelope 46. The ET modulation voltage V CCis based on the time-varying target voltage V 目标 Therefore, the ET modulation voltage V CC Tracking time-varying target voltage V 目标 .

[0037] The amplifier circuit 16 is coupled to the signal processing circuit 12 to receive the RF signal 24 having the time-varying signal envelope 26. The amplifier circuit 16 is also coupled to the ET voltage circuit 14 to receive the ET modulation voltage V corresponding to the time-varying voltage envelope 48. CC The amplifier circuit 16 is configured to modulate the voltage V based on the ET CC The RF signal 24 is amplified. In this regard, in order to maintain linearity and efficiency in the amplifier circuit 16, the ET modulation voltage V CC The time-varying voltage envelope 48 of needs to be closely aligned with the time-varying signal envelope 26 at the amplifier circuit 16 .

[0038] However, the signal processing circuit 12, the LUT circuit 36, the DAC 42, and the ET voltage circuit 14 may each cause processing / propagation delays. In addition, the amplifier circuit 16 may be a multi-stage amplifier including a driver stage 50 and an output stage 52, which also cause corresponding processing / propagation delays. Therefore, the time-varying voltage envelope 48 may not be aligned with the time-varying signal envelope 26 at the amplifier circuit 16.

[0039] In this regard, Figure 1B It is provided Figure 1A Schematic diagram of an exemplary illustration of the time misalignment between the time-varying voltage envelope 48 and the time-varying signal envelope 26. Figure 1B refer to Figure 1A elements and will not be re-described herein.

[0040] If the time-varying signal envelope 26 and the time-varying voltage envelope 48 are perfectly aligned, then the voltage V S The instantaneous amplitude of the RF signal 24 (not shown) at time t x will be substantially equal to the ET modulation voltage V CC However, if Figure 1B As shown, the time-varying signal envelope 26 lags behind the time-varying voltage envelope 48 by a time delay Δt. x At the same time, the amplifier circuit 16 (not shown) receives the lower ET modulation voltage V' CC , instead of ET modulation voltage V CC In this regard, the time-varying voltage envelope 48 at time t x The voltage difference Δv deviates from the time-varying signal envelope 26. As a result, the amplifier circuit 16 may suffer from degraded linearity performance.

[0041] In a non-limiting example, the linear performance of the amplifier circuit 16 can be measured by the adjacent channel leakage ratio (ACLR). ACLR represents the ratio between the in-band power and the out-of-band leakage power. In this regard, a higher ACLR indicates better linear performance of the amplifier circuit 16. Figure 1C It is provided Figure 1B How can the time delay Δt affect Figure 1A FIG. 1 is a schematic diagram of an exemplary illustration of the ACLR of the amplifier circuit 16. Figure 1C refer to Figure 1A and Figure 1B elements and will not be re-described herein.

[0042] Figure 1C A first ACLR curve 54 and a second ACLR curve 56 are included. In a non-limiting example, the first ACLR curve 54 corresponds to an RF signal (e.g., RF signal 24) modulated with a 100 MHz bandwidth, and the second ACLR curve 56 corresponds to an RF signal (e.g., RF signal 24) modulated with a 60 MHz bandwidth. Figure 1C As shown, the first ACLR curve 54 has a steeper slope than the second ACLR curve 56. In this regard, to achieve an ACLR of -32 dB, for example, when the RF signal 24 is modulated with a 100 MHz bandwidth, the conventional ET amplifier circuit 10 is limited to a delay budget of approximately 1.0 nanoseconds (ns). In contrast, when the RF signal 24 is modulated with a 60 MHz bandwidth, for the same ACLR of -32 dB, the conventional ET amplifier circuit 10 will experience a more relaxed delay budget of approximately 1.3 ns.

[0043] It is worth noting that the RF signal 24 may be a long term evolution (LTE) signal, which is typically modulated with a modulation bandwidth of up to 60 MHz, or a fifth generation new radio (5G-NR) signal, which is often modulated with a modulation bandwidth of more than 100 MHz. In this regard, the existing ET amplifier circuit 10 must adhere to a tighter delay budget to achieve a desired ACLR at the amplifier circuit 16 in order to transmit the RF signal 24 in a 5G-NR system.

[0044] Return to reference Figure 1BIn order to mitigate linear degradation and achieve a desired ACLR at the amplifier circuit 16, it is necessary to reduce the time delay Δt between the time-varying voltage envelope 48 and the time-varying signal envelope 26. However, it may be difficult to adequately do so in existing ET amplifier circuits 10 to meet the tighter delay budget required for transmitting 5G-NR signals modulated at higher modulation bandwidths (e.g., >100 MHz). Therefore, it may be desirable to improve the delay tolerance of existing ET amplifier circuits 10 to reduce linear degradation caused by time misalignment between the time-varying voltage envelope 48 and the time-varying signal envelope 26.

[0045] In this regard, Figure 2 is a schematic diagram of an exemplary ET amplifier circuit 58 configured to reduce linearity degradation by improving the delay tolerance of the ET amplifier circuit 58 according to an embodiment of the present disclosure. As discussed in detail below, the ET amplifier circuit 58 can be configured to dynamically reduce Figure 1B The voltage difference Δv in Figure 1B In addition, the ET amplifier circuit 58 can also be configured to reduce the gain sensitivity of the coupled amplifier circuit to the voltage difference Δv, regardless of whether the time delay Δt in the circuit is reduced. Figure 1B ET amplifier circuit 58 is able to reduce the linear degradation to a predefined threshold even without reducing the time delay Δt. Therefore, the ET amplifier circuit 58 becomes more delay tolerant, especially for transmitting 5G-NR signals modulated at bandwidths exceeding 100 MHz.

[0046] The ET amplifier circuit includes an ET voltage circuit 60, which may be functionally equivalent to Figure 1A The ET voltage circuit 14 is configured to generate an ET modulation voltage V based on a target voltage signal 62. CC The target voltage signal 62 corresponds to the time-varying target voltage envelope 64, and the ET modulation voltage V CC corresponds to a time-varying voltage envelope 66 configured to track the time-varying target voltage envelope 64. In this regard, the time-varying voltage envelope 66 may be modified by modifying the time-varying target voltage envelope 64, and thus the ET modulation voltage V CC .

[0047] ET amplifier circuit 58 includes signal processing circuit 68, which may be functionally equivalent to Figure 1AThe signal processing circuit 12 is configured to receive the digital signal 70 and convert the digital signal 70 into an RF signal 72. The signal processing circuit 68 may include a digital pre-distortion (DPD) circuit (not shown) to digitally pre-distort the digital signal 70 before converting the digital signal 70 into the RF signal 72. The digital signal 70 may be modulated to include a digital in-phase signal 74I having a plurality of time-varying in-phase amplitudes I and a digital quadrature signal 74Q having a plurality of time-varying quadrature amplitudes Q. Therefore, the digital signal 70 corresponds to a plurality of time-varying digital signal amplitudes 76. Each time-varying digital signal amplitude 76 may be represented as By converting the digital signal 70 into the RF signal 72 , the RF signal 72 is associated with a time-varying signal envelope 78 formed based on the time-varying digital signal amplitude 76 .

[0048] ET amplifier circuit 58 includes amplifier circuit 80, which may be functionally equivalent to Figure 1A The amplifier circuit 80 is configured to modulate the voltage V based on the ET. CC The RF signal 72 is amplified.

[0049] Similar to Figure 1A In the prior art ET amplifier circuit 10, due to the inherent time delay, the ET amplifier circuit 58 may cause the time-varying voltage envelope 66 to be misaligned with the time-varying signal envelope 78 at the amplifier circuit 80. In a non-limiting example, the amplifier circuit 80 may include a driver stage 82 and an output stage 84. In this regard, the time-varying voltage envelope 66 may be further misaligned with the time-varying signal envelope 78 at the output stage 84. Figure 1B As discussed previously in , the misalignment between the time-varying voltage envelope 66 and the time-varying signal envelope 78 may continually cause a voltage difference Δv at the amplifier circuit 80. As a result, the amplifier circuit 80 may suffer from linearity degradation (e.g., degraded ACLR), particularly when the RF signal 72 is modulated with a high bandwidth exceeding 100 MHz.

[0050] In this regard, the ET amplifier circuit 58 is configured to include a voltage processing circuit 86. The voltage processing circuit 86 can operate in a low bandwidth mode and a high bandwidth mode. In a non-limiting example, the voltage processing circuit 86 operates in the low bandwidth mode when the RF signal 72 is modulated with a bandwidth less than or equal to 60 MHz (≤60 MHz), and operates in the high bandwidth mode when the RF signal 72 is modulated with a bandwidth greater than 60 MHz (>60 MHz).

[0051] In the high bandwidth mode, the voltage processing circuit 86 can be configured to cause the ET voltage circuit 60 to modify the ET modulation voltage V CC To reduce the voltage difference Δv between the time-varying voltage envelope 66 and the time-varying signal envelope 78 (eg Figure 1B ). Thus, the delay margin of the ET amplifier circuit 58 may be improved, thereby helping to reduce the linearity degradation at the amplifier circuit 80 to a predetermined threshold (eg, a predetermined ACLR).

[0052] In contrast, in the low bandwidth mode, the voltage processing circuit 86 may be configured to not cause the ET voltage circuit 60 to modify the ET modulation voltage V CC For example, the ET amplifier circuit 58 may include a control circuit 88, which may be a microprocessor or a digital signal processor (DSP). The control circuit 88 may be configured to control the voltage processing circuit 86 to operate in a high bandwidth mode and a low bandwidth mode via a first control signal 90 and a second control signal 92, respectively. In this regard, the ET amplifier circuit 58 may be flexibly and dynamically switched between the low bandwidth mode and the high bandwidth mode.

[0053] The voltage processing circuit 86 includes a digital voltage processing circuit 94 and a DAC 96. The digital voltage processing circuit 94 is configured to receive the time-varying digital signal amplitude 76 and generate a digital target voltage signal 98. In the low bandwidth mode, the digital voltage processing circuit 94 generates a digital target voltage signal 98 corresponding to a plurality of time-varying digital target voltage amplitudes 100. Subsequently, the DAC 96 converts the digital target voltage signal 98 into the target voltage signal 62. Thus, the time-varying target voltage envelope 64 is formed based on the time-varying digital target voltage amplitude 100 and thus tracks the time-varying digital target voltage amplitude.

[0054] In the high bandwidth mode, the digital voltage processing circuit 94 generates a digital target voltage signal 98 corresponding to a plurality of time-varying modified digital target voltage amplitudes 102. Subsequently, the DAC 96 converts the digital target voltage signal 98 into the target voltage signal 62. Thus, the time-varying target voltage envelope 64 is formed based on the time-varying modified digital target voltage amplitudes 102 and thus tracks the time-varying modified digital target voltage amplitudes. Considering that the time-varying voltage envelope 66 tracks the time-varying target voltage envelope 64, the time-varying modified digital target voltage amplitudes 102 can cause the ET modulation voltage V CC In addition, since the time-varying signal envelope 78 and the time-varying voltage envelope 66 are both formed based on the time-varying digital signal amplitude 76, the ET modulation voltage V CC The voltage difference Δv between the time-varying voltage envelope 66 and the time-varying signal envelope 78 is reduced. Therefore, the delay tolerance of the ET amplifier circuit 58 can be improved, which can lead to an improvement in the linear performance (eg, ACLR) of the amplifier circuit 80 .

[0055] In addition to improving the delay tolerance of the ET amplifier circuit 58, the time delay Δt between the time-varying voltage envelope 66 and the time-varying signal envelope 78 is further reduced. Figure 1BIn this regard, the voltage processing circuit 86 may include a delay adjustment circuit 104 (in Figure 2 The signal processing circuit 68 may also include a delay adjustment circuit 106 for the same purpose. In addition, the voltage processing circuit 86 may include a voltage memory digital predistortion (mDPD) circuit 108. The voltage mDPD circuit 108 may be configured to digitally predistort the digital target voltage signal 98 to help compensate for memory nonlinear distortion in the ET voltage circuit 60.

[0056] The digital voltage processing circuit 94 may be configured based on a number of embodiments discussed next. Figure 3 is configured according to one embodiment of the present disclosure and may be included as a digital voltage processing circuit 94 Figure 2 Schematic diagram of an exemplary digital voltage processing circuit 94A in the ET amplifier circuit 58. Figure 2 and Figure 3 Common elements between the FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described here.

[0057] The digital voltage processing circuit 94A includes a mixer 110 configured to combine the time-varying digital signal amplitude 76 with a digital voltage reference signal 112 to generate a digital target voltage reference signal 114. Therefore, the digital target voltage reference signal 114 corresponds to the time-varying digital signal amplitude 76, which can be represented by the time-varying voltage V 输入 express.

[0058] The digital voltage processing circuit 94A includes a low bandwidth LUT circuit 116 (denoted as “LBW LUT circuit”) and a high bandwidth LUT circuit 118 (denoted as “HBW LUT circuit”). Both the low bandwidth LUT circuit 116 and the high bandwidth LUT circuit 118 are configured to receive a digital target voltage reference signal 114 associated with the time-varying digital signal amplitude 76. The low bandwidth LUT circuit 116 is further configured to generate a digital target voltage signal 98 corresponding to the time-varying digital target voltage amplitude 100. The high bandwidth LUT circuit 118 is further configured to generate a digital target voltage signal 98 corresponding to the time-varying modified digital target voltage amplitude 102.

[0059] The digital voltage processing circuit 94A includes a multiplexer 120 coupled to the low bandwidth LUT circuit 116 and the high bandwidth LUT circuit 118. The control circuit 88 (not shown) can control the multiplexer 120 to output the digital target voltage signal 98 having the time-varying modified digital target voltage amplitude 102 in the high bandwidth mode via the first control signal 90. The control circuit 88 can also control the multiplexer 120 to output the digital target voltage signal 98 having the time-varying digital target voltage amplitude 100 in the low bandwidth mode via the second control signal 92.

[0060] The low bandwidth LUT circuit 116 may include a low bandwidth LUT configured to associate the time-varying digital target voltage amplitude 100 with the time-varying digital signal amplitude 76. Similarly, the high bandwidth LUT circuit 118 may include a high bandwidth LUT configured to associate the time-varying modified digital target voltage amplitude 102 with the time-varying digital signal amplitude 76. As will be described later in Figure 4A and Figure 4B As explained in , the time-varying modified digital target voltage magnitude 102 stored in the high-bandwidth LUT may be determined based on the time-varying digital target voltage magnitude 100 stored in the low-bandwidth LUT.

[0061] Figure 4A is provided based on a constant voltage offset V 偏移 A schematic diagram of an exemplary illustration of generating a time-varying modified digital target voltage magnitude 102 . Figure 4A A first curve 122 is included that represents the correlation between the time-varying digital signal amplitude 76 and the time-varying digital target voltage amplitude 100 . Figure 4A Also included is a second curve 124 representing the correlation between the time-varying digital signal amplitude 76 and the time-varying modified digital target voltage amplitude 102. The second curve 124 is parallel to the first curve 122, which indicates that the constant voltage can be offset by V 偏移 The time-varying modified digital target voltage amplitude 102 is added to the time-varying digital target voltage amplitude 100. It is worth noting that the time-varying digital target voltage amplitude 100 and the time-varying modified digital target voltage amplitude 102 can meet the common digital amplitude upper limit 126, which can be equal to 5.5 volts, for example. Soft clipping can also be applied to the time-varying digital target voltage amplitude 100 and the time-varying modified digital target voltage amplitude 102 in the area near the common digital amplitude upper limit 126 and / or in the area close to zero.

[0062] Figure 4B is provided based on multiple variable voltage offsets V 偏移-1-V偏移-N Schematic diagram of an exemplary illustration of generating a time-varying modified digital target voltage magnitude 102 . Figure 4B A first curve 128 is included that represents the correlation between the time-varying digital signal amplitude 76 and the time-varying digital target voltage amplitude 100 . Figure 4B Also included is a second curve 130 representing the correlation between the time-varying digital signal amplitude 76 and the time-varying modified digital target voltage amplitude 102. Figure 4B As shown, the first curve 128 corresponds to a first slope m 1 (m 1 =tan(θ 1 )), and the second curve 130 corresponds to the second slope m 2 (m 2 =tan(θ 2 )). Considering θ 1 >θ 2 , the first slope m 1 Greater than the second slope m 2 In this regard, the second curve 130 has a slope m relative to the first curve 130. 1 The second decreasing slope m 2 In this regard, the time-varying modified digital target voltage amplitude 102 represented by the second curve 130 may be generated by applying a slope factor to the time-varying digital signal amplitude 75 represented by the first curve 128. In a non-limiting example, the slope factor is less than 1. The first slope m associated with the first curve 128 may be applied by performing a linear fit of the first curve 128. 1 and the first intercept value. The first slope m 1 Multiply by the slope factor to generate the second slope m 2 (m 2 =m 1 × slope factor). Subsequently, a second intercept value associated with the second curve 130 may be determined such that the first curve 128 and the second curve 130 converge at a common digital amplitude upper limit 132. In this regard, the second curve 130 represents a plurality of variable voltage offsets V relative to the first curve 128. 偏移-1 -V 偏移-N Therefore, the variable voltage can be offset by V 偏移-1 -V 偏移-N The time-varying modified digital target voltage amplitude 102 is added to the time-varying digital target voltage amplitude 100. It is worth noting that the time-varying digital target voltage amplitude 100 and the time-varying modified digital target voltage amplitude 102 can meet the common digital amplitude upper limit 132, which can be equal to 5.5 V, for example. Soft clipping can also be applied to the time-varying digital target voltage amplitude 100 and the time-varying modified digital target voltage amplitude 102 in the area near the common digital amplitude upper limit 126 and / or in the area close to zero.

[0063] Figure 5 is configured according to another embodiment of the present disclosure and may be included as a digital voltage processing circuit 94 Figure 2Schematic diagram of an exemplary digital voltage processing circuit 94B in the ET amplifier circuit 58. Figure 3 and Figure 5 Common elements between the FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described here.

[0064] The digital voltage processing circuit 94B includes a gain adjustment circuit 134 that can be activated in the high bandwidth mode via the first control signal 90 and deactivated in the low bandwidth mode via the second control signal 92. When activated, the gain adjustment circuit 134 generates a corresponding voltage offset ΔV for each time-varying digital signal amplitude 76. For the time-varying digital signal amplitude 76, the gain adjustment circuit 134 can generate the voltage offset ΔV as Figure 4A The constant voltage offset V 偏移 or as Figure 4B The variable voltage offset V 偏移-1 -V 偏移-N When deactivated, the voltage adjustment circuit 134 may generate a voltage offset ΔV as a zero voltage offset.

[0065] The digital voltage processing circuit 94B includes a combiner 136. The combiner 136 is configured to combine the corresponding voltage offset ΔV with each time-varying digital target voltage amplitude 100 generated by the low-bandwidth LUT circuit 116. In this regard, in the high-bandwidth mode, the combiner 136 may receive the corresponding voltage offset ΔV as a non-zero voltage offset. Therefore, the combiner 136 outputs the digital target voltage signal 98 with the time-varying modified digital target voltage amplitude 102. In contrast, in the low-bandwidth mode, the combiner 136 may receive the corresponding voltage offset ΔV as a zero voltage offset. Therefore, the combiner 136 outputs the digital target voltage signal 98 with the time-varying digital target voltage amplitude 100.

[0066] Figure 6 is configured according to another embodiment of the present disclosure and may be included as a digital voltage processing circuit 94 Figure 2 Schematic diagram of an exemplary digital voltage processing circuit 94C in the ET amplifier circuit 58. Figure 3 and Figure 6 Common elements between the FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described here.

[0067] The digital voltage processing circuit 94C includes a gain adjustment circuit 138 that can be activated in the high bandwidth mode via the first control signal 90 and deactivated in the low bandwidth mode via the second control signal 92. When activated, the gain adjustment circuit 138 generates a corresponding gain offset ΔG for each time-varying digital signal amplitude 76. When deactivated, the gain adjustment circuit 138 can generate the gain offset ΔG as a zero gain offset.

[0068] The digital voltage processing circuit 94C includes a gain mixer 140. The gain mixer 140 is configured to combine a corresponding gain offset ΔG with each time-varying digital signal amplitude 76. In this regard, in the high bandwidth mode, the gain mixer 140 may receive the corresponding gain offset ΔG as a non-zero gain offset. Therefore, the gain mixer 140 outputs a plurality of time-varying modified digital signal amplitudes 142. In contrast, in the low bandwidth mode, the gain mixer 140 may receive the corresponding gain offset ΔG as a zero gain offset. Therefore, the gain mixer 140 outputs the time-varying digital signal amplitude 76.

[0069] The digital voltage processing circuit 94C includes a LUT circuit 144. In the high bandwidth mode, the LUT circuit 144 generates a digital target voltage signal 98 corresponding to a time-varying modified digital target voltage amplitude 102 formed based on the time-varying modified digital signal amplitude 142. In the low bandwidth mode, the LUT circuit 144 generates a digital target voltage signal 98 corresponding to a time-varying digital target voltage amplitude 100 formed based on the time-varying digital signal amplitude 76.

[0070] Figure 7 is configured according to another embodiment of the present disclosure and may be included as a digital voltage processing circuit 94 Figure 2 Schematic diagram of an exemplary digital voltage processing circuit 94D in the ET amplifier circuit 58. Figure 6 and Figure 7 Common elements between the FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described here.

[0071] In digital voltage processing circuit 94D, gain adjustment circuit 138 is coupled to mixer 110. When activated, gain adjustment circuit 138 generates a corresponding gain offset ΔG for each time-varying digital signal amplitude 76. When deactivated, gain adjustment circuit 138 may generate gain offset ΔG as a zero gain offset.

[0072] The mixer 110 is further configured to combine the corresponding gain offset ΔG with each time-varying digital signal amplitude 76. In this regard, in the high bandwidth mode, the mixer 110 may receive the corresponding gain offset ΔG as a non-zero gain offset. Therefore, the mixer 110 outputs the time-varying modified digital signal amplitude 142. In contrast, in the low bandwidth mode, the mixer 110 may receive the corresponding gain offset ΔG as a zero gain offset. Therefore, the mixer 110 outputs the time-varying digital signal amplitude 76.

[0073] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. An envelope tracking ET amplifier circuit, comprising: an ET voltage circuit configured to generate an ET modulation voltage corresponding to a time-varying voltage envelope; a signal processing circuit configured to generate a radio frequency (RF) signal corresponding to the time-varying signal envelope; an amplifier circuit configured to amplify the RF signal based on the ET modulation voltage; as well as a voltage processing circuit configured to operate in a low bandwidth mode and a high bandwidth mode; The voltage processing circuit is further configured to cause the ET voltage circuit to modify the ET modulation voltage in the high bandwidth mode to compensate for the linear degradation caused by the time misalignment between the time-varying voltage envelope and the time-varying signal envelope at the amplifier circuit to improve the delay tolerance, thereby reducing the linear degradation caused by the time misalignment to a predetermined threshold.

2. The envelope tracking ET amplifier circuit of claim 1, wherein the voltage processing circuit is further configured to not cause the ET voltage circuit to modify the ET modulation voltage in the low bandwidth mode.

3. The envelope tracking (ET) amplifier circuit of claim 1 , wherein the voltage processing circuit is further configured to: operating in the low bandwidth mode when the RF signal is less than or equal to 60 MHz bandwidth; and When the RF signal is modulated to a bandwidth greater than 60 MHz, operation in the high bandwidth mode occurs.

4. The envelope tracking (ET) amplifier circuit of claim 1, wherein the predetermined threshold corresponds to a predetermined adjacent channel leakage ratio (ACLR).

5. The envelope tracking ET amplifier circuit of claim 1, wherein: The voltage processing circuit comprises: A digital voltage processing circuit configured to: generating a digital target voltage signal corresponding to a plurality of time-varying digital target voltage amplitudes in the low bandwidth mode; and generating, in the high bandwidth mode, the digital target voltage signal corresponding to a plurality of time-varying modified digital target voltage amplitudes; A digital-to-analog converter DAC, which is configured to: In the low bandwidth mode, converting the digital target voltage signal into a target voltage signal having a time-varying target voltage envelope formed based on the plurality of time-varying digital target voltage amplitudes; and In the high bandwidth mode, converting the digital target voltage signal into the target voltage signal having the time-varying target voltage envelope formed based on the plurality of time-varying modified digital target voltage amplitudes; and The ET voltage circuit is further configured to generate the ET modulation voltage having the time-varying voltage envelope formed based on the time-varying target voltage envelope.

6. The envelope tracking (ET) amplifier circuit of claim 5, wherein the signal processing circuit is further configured to: receiving a digital signal corresponding to a plurality of time-varying digital signal amplitudes; and The digital signal is converted into the RF signal having the time-varying signal envelope formed based on the plurality of time-varying digital signal amplitudes.

7. The envelope tracking (ET) amplifier circuit of claim 6, wherein the digital voltage processing circuit comprises: a mixer configured to combine the plurality of time-varying digital signal amplitudes with a digital voltage reference signal to generate a digital target voltage reference signal corresponding to the plurality of time-varying digital signal amplitudes; A low bandwidth lookup table LUT circuit configured to: receiving the digital target voltage reference signal; as well as generating the digital target voltage signal having the plurality of time-varying digital target voltage amplitudes based on the plurality of time-varying digital signal amplitudes; as well as A high bandwidth LUT circuit configured to: receiving the digital target voltage reference signal; as well as The digital target voltage signal having the plurality of time-varying modified digital target voltage magnitudes is generated based on the plurality of time-varying digital signal magnitudes.

8. The envelope tracking ET amplifier circuit of claim 7, further comprising a multiplexer configured to: in response to receiving a first control signal, outputting the digital target voltage signal having the plurality of time-varying modified digital target voltage amplitudes; and In response to receiving the second control signal, the digital target voltage signal having the plurality of time-varying digital target voltage amplitudes is output.

9. The envelope tracking ET amplifier circuit of claim 7, wherein the high bandwidth LUT circuit is further configured to generate the plurality of time-varying modified digital target voltage amplitudes by respectively adding a constant voltage offset to the plurality of time-varying digital target voltage amplitudes.

10. The envelope tracking ET amplifier circuit of claim 7, wherein the high bandwidth LUT circuit is further configured to generate the plurality of time-varying modified digital target voltage amplitudes by respectively adding a plurality of variable voltage offsets to the plurality of time-varying digital target voltage amplitudes.

11. The envelope tracking ET amplifier circuit of claim 10, wherein: The plurality of time-varying digital target voltage amplitudes correspond to a first linear curve having a first slope; and The plurality of time-varying modified digital target voltage magnitudes corresponds to a second linear curve having a second slope that is less than the first slope.

12. The envelope tracking (ET) amplifier circuit of claim 11, wherein the first linear curve and the second linear curve converge at a common upper digital amplitude limit.

13. The envelope tracking (ET) amplifier circuit of claim 6, wherein the digital voltage processing circuit comprises: a mixer configured to combine the plurality of time-varying digital signal amplitudes with a digital voltage reference signal to generate a digital target voltage reference signal corresponding to the plurality of time-varying digital signal amplitudes; A low bandwidth lookup table LUT circuit configured to: receiving the digital target voltage reference signal; as well as generating the plurality of time-varying digital target voltage amplitudes based on the plurality of time-varying digital signal amplitudes; and A voltage regulation circuit is configured to: receiving the digital target voltage reference signal; as well as A corresponding voltage offset is generated for each of the plurality of time-varying digital signal amplitudes.

14. The envelope tracking (ET) amplifier circuit of claim 13, further comprising a combiner coupled to the low bandwidth lookup table (LUT) circuit and the voltage adjustment circuit, the combiner configured to: In the high bandwidth mode, combining each of the plurality of time-varying digital target voltage magnitudes with the corresponding voltage offset to output the plurality of time-varying modified digital target voltage magnitudes; and In the low bandwidth mode, the plurality of time-varying digital target voltage amplitudes are output.

15. The envelope tracking ET amplifier circuit of claim 14, wherein: the voltage adjustment circuit being activated in the high bandwidth mode so that the combiner receives the corresponding voltage offset as a non-zero voltage offset; as well as The voltage adjustment circuit is deactivated in the low bandwidth mode such that the combiner receives the corresponding voltage offset as a zero voltage offset.

16. The envelope tracking (ET) amplifier circuit of claim 6, wherein the digital voltage processing circuit comprises: a mixer configured to combine the plurality of time-varying digital signal amplitudes with a digital voltage reference signal to generate a digital target voltage reference signal corresponding to the plurality of time-varying digital signal amplitudes; A gain adjustment circuit is configured to: receiving the digital target voltage reference signal; as well as generating a corresponding gain offset for each of the plurality of time-varying digital signal amplitudes; Gain mixer, which is configured to: receiving the digital target voltage reference signal; combining the corresponding gain offsets with the plurality of time-varying digital signal amplitudes to produce a plurality of time-varying modified digital signal amplitudes in the high bandwidth mode; as well as outputting the plurality of time-varying digital signal amplitudes in the low bandwidth mode; as well as A lookup table LUT circuit configured to: generating the plurality of time-varying modified digital target voltage amplitudes based on the plurality of time-varying modified digital signal amplitudes in the high bandwidth mode; as well as In the low bandwidth mode, the plurality of time-varying digital target voltage amplitudes are generated based on the plurality of time-varying digital signal amplitudes.

17. The envelope tracking ET amplifier circuit of claim 16, wherein: The gain adjustment circuit is activated in the high bandwidth mode so that the gain mixer receives the corresponding gain offset as a non-zero gain offset; as well as The gain adjustment circuit is deactivated in the low bandwidth mode such that the gain mixer receives the corresponding gain offset as a zero gain offset.

18. The envelope tracking (ET) amplifier circuit of claim 6, wherein the digital voltage processing circuit comprises: a mixer configured to combine the plurality of time-varying digital signal amplitudes with a digital voltage reference signal to generate a digital target voltage reference signal corresponding to the plurality of time-varying digital signal amplitudes; a gain adjustment circuit configured to generate a corresponding gain offset for each of the plurality of time-varying digital signal amplitudes; The mixer is further configured to: combining the corresponding gain offsets with the plurality of time-varying digital signal amplitudes to produce a plurality of time-varying modified digital signal amplitudes in the high bandwidth mode; as well as In the low bandwidth mode, outputting the multiple time-varying digital signal amplitudes; as well as A lookup table LUT circuit configured to: generating the plurality of time-varying modified digital target voltage amplitudes based on the plurality of time-varying modified digital signal amplitudes in the high bandwidth mode; as well as In the low bandwidth mode, the plurality of time-varying digital target voltage amplitudes are generated based on the plurality of time-varying digital signal amplitudes.

19. The envelope tracking ET amplifier circuit of claim 5, wherein the voltage processing circuit further comprises a voltage memory digital pre-distortion (mDPD) circuit configured to digitally pre-distort the digital target voltage signal to compensate for memory nonlinear distortion in the ET voltage circuit.

20. The envelope tracking (ET) amplifier circuit of claim 19, wherein the voltage processing circuit further comprises a delay adjustment circuit configured to reduce the time misalignment between the time-varying voltage envelope and the time-varying signal envelope.

21. The envelope tracking (ET) amplifier circuit of claim 19, wherein the signal processing circuit comprises a delay adjustment circuit configured to reduce the time misalignment between the time-varying voltage envelope and the time-varying signal envelope.

22. The envelope tracking ET amplifier circuit of claim 1, further comprising a control circuit configured to control the voltage processing circuit to cause the ET voltage circuit to modify the ET modulation voltage in the high bandwidth mode.

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