Chip packaging method and packaging structure
By using a combined structure of conductive layer, protective layer and plastic sealing layer in wafer packages, warping and alignment accuracy problems in panel-level packages are solved, and chip packaging with stability and durability is achieved, suitable for large panel-level and thin chips.
Patent Information
- Application Number
- CN201910657495.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2019-03-19
- Filing Date
- 2019-07-19
- Publication Date
- 2025-08-05
- Estimated Expiration
- 2039-07-19
AI Technical Summary
There are warping problems and high demands for die alignment accuracy in panel-level packaging, especially in small and thin chip packaging, which increases difficulty, affecting production efficiency and cost.
Using a combined structure of the wafer conductive layer, protective layer and plastic sealing layer, a plastic sealing layer is formed on the active surface of the wafer, and a plastic sealing layer is formed on the back of the die, combined with the dielectric layer, warping and alignment accuracy are controlled, and organic/inorganic composite materials are used to match the thermal expansion coefficient, reducing warping during the packaging process and improving alignment accuracy.
It effectively reduces warpage during the packaging process, reduces the need for bare chip alignment accuracy, improves the stability and durability of the packaging process, and is suitable for large panel-level packaging and large-voltage and thin chip packaging.
Smart Images
Figure CN110729272B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a chip packaging method and a packaging structure. Background Art
[0002] Panel-level packaging is to cut and separate a large number of die from a wafer, arrange and paste the die on a carrier board, and package a large number of die simultaneously in the same process flow. As a technology emerging in recent years, panel-level packaging has received extensive attention. Compared with traditional wafer-level packaging, panel-level packaging has the advantages of high production efficiency, low production cost, and suitability for mass production.
[0003] However, there are many technical barriers in panel packaging, such as the warping problem of the panel; the alignment accuracy problem of the die on the panel, etc.
[0004] Especially in the current trend of miniaturization and light weight of electronic devices, small and thin chips are increasingly favored by the market. However, the packaging process of packaging small and thin chips using large panel packaging technology is even more challenging. Summary of the Invention
[0005] The present disclosure aims to provide a chip packaging method and a chip packaging structure. This packaging method can reduce or eliminate warping during panel packaging, reduce the accuracy requirements for the die on the panel, reduce the difficulty of the panel packaging process, and enable the packaged chip structure to have a durable service life, especially suitable for large panel-level packaging and the packaging of large electrical flux and thin chips.
[0006] The present disclosure provides a chip packaging structure, including: one or more die, the die including a die active surface and a die back surface; a conductive structure, including a wafer conductive layer and a panel-level conductive layer; a protective layer; a molding layer, the molding layer being used to encapsulate the die; a dielectric layer.
[0007] In some embodiments, the wafer conductive layer includes wafer conductive traces and wafer conductive studs; the die active surface includes electrical connection points; at least a part of the wafer conductive traces and at least a part of the electrical connection points are electrically connected; the wafer conductive studs are formed on the pads or connection points of the wafer conductive traces.
[0008] In some other embodiments, at least a part of the wafer conductive traces separately lead out at least a part of the electrical connection points.
[0009] In still some other embodiments, at least a part of the wafer conductive traces interconnect and lead out at least a part of multiple electrical connection points among them.
[0010] In some preferred embodiments, the wafer conductive layer includes wafer conductive studs; the die active surface includes electrical connection points and an insulating layer; at least a portion of the wafer conductive studs and at least a portion of the electrical connection points are electrically connected.
[0011] In some preferred embodiments, the panel-level conductive layer includes conductive traces and / or conductive studs; the panel-level conductive layer is electrically connected to the wafer conductive studs; the panel-level conductive layer is one or more layers.
[0012] In some preferred embodiments, at least a portion of the conductive traces closest to the die active surface are formed on the front surface of the molding layer and extend to the edge of the package.
[0013] In some preferred embodiments, the back surface of the die is exposed from the molding layer.
[0014] In some preferred embodiments, the surface of the dielectric layer has a groove at a position corresponding to the conductive layer.
[0015] In some preferred embodiments, the package structure includes multiple dies, and the multiple dies are electrically connected according to the product design.
[0016] In some embodiments, the Young's modulus of the protective layer is any one of the following numerical ranges or values: 1000 - 20000 MPa, 1000 - 10000 MPa, 4000 - 8000 MPa, 1000 - 7000 MPa, 4000 - 7000 MPa, 5500 MPa.
[0017] In some other embodiments, the material of the protective layer is an organic / inorganic composite material.
[0018] In some further embodiments, the thickness of the protective layer is any one of the following numerical ranges or values: 15 - 50 μm, 20 - 50 μm, 35 μm, 45 μm, 50 μm.
[0019] In some preferred embodiments, the thermal expansion coefficient of the protective layer is any one of the following numerical ranges or values: 3 - 10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.
[0020] In some other preferred embodiments, the thermal expansion coefficient of the molding layer is any one of the following numerical ranges or values: 3 - 10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.
[0021] In some further preferred embodiments, the protective layer and the molding layer have the same or similar thermal expansion coefficients.
[0022] The present disclosure provides a chip packaging method, including: forming a wafer conductive layer on the active surface of a to-be-packaged wafer; forming a protective layer on the wafer conductive layer, the protective layer covering the wafer conductive layer and exposing the surface of the wafer conductive layer; cutting the wafer with the formed wafer conductive layer and protective layer to form bare chips; mounting the bare chips on a carrier, with the active surface of the bare chip facing the front of the carrier and the back of the bare chip facing away from the front of the carrier; forming a plastic encapsulation layer on the back of the bare chips on the carrier; peeling off the carrier; forming a panel-level conductive layer electrically connected to the wafer conductive layer; and forming a dielectric layer.
[0023] In some preferred embodiments, the step of forming the wafer conductive layer includes forming wafer conductive traces and forming wafer conductive studs; at least a part of the formed wafer conductive traces individually lead out at least a part of the electrical connection points or at least a part of the wafer conductive traces interconnect and lead out at least a part of the multiple electrical connection points to each other.
[0024] In some other preferred embodiments, the step of forming the wafer conductive layer includes forming wafer conductive studs; at least a part of the wafer conductive studs are electrically connected to at least a part of the electrical connection points; and at least a part of the wafer conductive studs lead out at least a part of the electrical connection points.
[0025] In some further preferred embodiments, the step of forming the panel-level conductive layer includes forming conductive traces and / or conductive studs; the formed panel-level conductive layer is electrically connected to the wafer conductive studs; and the formed panel-level conductive layer is one layer or multiple layers.
[0026] In some preferred embodiments, it further includes the step of thinning the back of the plastic encapsulation layer to expose the back of the bare chips.
[0027] In some preferred embodiments, it further includes the step of forming grooves at positions corresponding to the panel-level conductive layer on the dielectric layer by metal etching.
[0028] In some preferred embodiments, it further includes the step of performing plasma surface treatment and / or chemical promoter modifier treatment on the surface of the wafer and / or the protective layer.
[0029] In some embodiments, the material of the protective layer is an organic / inorganic composite material and / or the protective layer and the plastic encapsulation layer have the same or similar thermal expansion coefficients.
[0030] In some other embodiments, the Young's modulus of the protective layer is any one of the following numerical ranges or values: 1000 - 20000 MPa, 1000 - 10000 MPa, 4000 - 8000 MPa, 1000 - 7000 MPa, 4000 - 7000 MPa, 5500 MPa, and / or the thickness of the protective layer is any one of the following numerical ranges or values: 15 - 50 μm, 20 - 50 μm, 35 μm, 45 μm, 50 μm.
[0031] In some further embodiments, the thermal expansion coefficient of the protective layer is any one of the following numerical ranges or values: 3 - 10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K, and / or the thermal expansion coefficient of the encapsulation layer is any one of the following numerical ranges or values: 3 - 10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K. Brief Description of the Drawings
[0032] Figures 1 to 13 is a flowchart of a chip packaging method according to an exemplary embodiment of the present disclosure;
[0033] Figure 1 is a schematic diagram of a wafer according to an exemplary embodiment of the present disclosure;
[0034] Figure 2 is a schematic diagram of the wafer after forming the conductive traces of the wafer according to an exemplary embodiment of the present disclosure;
[0035] Figure 3 is a schematic diagram of the wafer after forming the conductive studs of the wafer according to an exemplary embodiment of the present disclosure;
[0036] Figure 4a 、 4b 、4c is a schematic diagram of the wafer after applying the protective layer according to an exemplary embodiment of the present disclosure;
[0037] Figure 5 is a schematic diagram of cutting the wafer to form die according to an exemplary embodiment of the present disclosure;
[0038] Figure 6a is a schematic diagram of mounting the die on the carrier according to an exemplary embodiment of the present disclosure;
[0039] Figure 6b is a schematic diagram of pasting the combined die on the carrier according to an exemplary embodiment of the present disclosure;
[0040] Figure 7 is a schematic diagram of forming an encapsulation layer on the carrier according to an exemplary embodiment of the present disclosure;
[0041] Figure 8a is a schematic diagram of thinning the thickness of the encapsulation layer according to an exemplary embodiment of the present disclosure;
[0042] Figure 8b is a schematic diagram of thinning the encapsulation layer to expose the back side of the bare die according to an exemplary embodiment of the present disclosure;
[0043] Figure 9 is a schematic diagram of peeling off the carrier and the adhesive layer according to an exemplary embodiment of the present disclosure;
[0044] Figure 10 is a schematic diagram of forming conductive traces on the panel assembly according to an exemplary embodiment of the present disclosure;
[0045] Figure 11 is a schematic diagram of forming conductive studs on the panel assembly according to an exemplary embodiment of the present disclosure;
[0046] Figure 12a 、 12b is a schematic diagram of forming a dielectric layer on the panel assembly according to an exemplary embodiment of the present disclosure;
[0047] Figure 13 is a schematic diagram of dividing the panel assembly to form a completed packaged chip according to an exemplary embodiment of the present disclosure;
[0048] Figure 14a 、 14b 、14c, 14d, 14e are schematic diagrams of chip package structures obtained by using the above packaging method according to an exemplary embodiment of the present disclosure;
[0049] Figure 15 is a schematic diagram of the packaged chip in use according to an exemplary embodiment of the present disclosure. Detailed implementation manners
[0050] To make the technical solutions of the present disclosure clearer and the technical effects more distinct, the following provides a detailed and specific description and explanation of the preferred embodiments of the present disclosure with reference to the accompanying drawings. It should not be understood that the following description is the only implementation form of the present disclosure or a limitation to the present disclosure.
[0051] Figures 1 to 13 is the flow of a chip packaging method proposed according to an exemplary embodiment of the present disclosure.
[0052] Such as Figure 1As shown, at least one wafer 100 is provided. The wafer 100 has a wafer active surface 1001 and a wafer back surface 1002. The wafer 100 includes a plurality of dies 113, and the active surface of each die constitutes the wafer active surface 1001. A series of active components and passive components are formed on the active surface of each die in the wafer 100 through a series of processes such as doping, deposition, and etching. The active components include diodes, triodes, etc., and the passive components include voltage transformers, capacitors, resistors, inductors, etc. These active components and passive components are connected by connecting wires to form a functional circuit, thereby realizing various functions of the chip. The wafer active surface 1001 further includes electrical connection points 103 for leading out the functional circuit and an insulating layer 105 for protecting the electrical connection points 103.
[0053] As Figure 2 shown, a wafer conductive trace (wafer trace) 106 is formed on the wafer active surface 1001.
[0054] The wafer conductive trace 106 can be made of materials such as copper, gold, silver, tin, aluminum or their composite materials, or can be made of other suitable conductive materials formed by using PVD, CVD, sputtering, electrolytic electroplating, electroless plating processes, or other suitable metal deposition processes.
[0055] At least a part of the wafer conductive trace 106 can interconnect and lead out multiple of the electrical connection points 103 in at least a part.
[0056] At least a part of the wafer conductive trace 106 can also lead out at least a part of the electrical connection points 103 separately.
[0057] As Figure 3 shown, a wafer conductive stud (wafer stud) 111 is formed on the pad or connection point of the wafer conductive trace 106.
[0058] The shape of the wafer conductive stud 111 can be circular, or other shapes such as oval, square, linear, etc. The wafer conductive stud 111 can be made of one or multiple layers of materials such as copper, gold, silver, tin, aluminum or their composite materials, or can be made of other suitable conductive materials formed by using PVD, CVD, sputtering, electrolytic electroplating, electroless plating processes, or other suitable metal deposition processes.
[0059] Optionally, the wafer conductive stud 111 can also be directly formed at the electrical connection point 103 on the wafer active surface 1001 to lead out the electrical connection point 103.
[0060] The wafer conductive trace 106 and / or the wafer conductive stud 111 is called the wafer conductive layer.
[0061] As Figure 4a , Figure 4b and Figure 4c shown, a protective layer 107 is applied on the wafer conductive layer.
[0062] As Figure 4a shown, the wafer conductive layer includes wafer conductive traces 106 and wafer conductive studs 111. At least a portion of the wafer conductive traces 106 interconnect and lead out multiple ones of the electrical connection points 103 in at least a portion thereof; the protective layer 107 is applied on the wafer conductive traces 106 and the wafer conductive studs 111, covering the wafer conductive traces 106 and the wafer conductive studs 111.
[0063] As Figure 4b shown, the wafer conductive layer includes wafer conductive traces 106 and wafer conductive studs 111. At least a portion of the wafer conductive traces 106 separately lead out at least a portion of the electrical connection points 103; the protective layer 107 is applied on the wafer conductive traces 106 and the wafer conductive studs 111, covering the wafer conductive traces 106 and the wafer conductive studs 111.
[0064] As Figure 4c shown, the wafer conductive layer only includes wafer conductive studs 111, and the wafer conductive studs 111 are formed at the electrical connection points 103. The protective layer is applied on the wafer conductive studs 111, covering the wafer conductive studs 111.
[0065] The protective layer 107 is made of an insulating material, such as optionally BCB (benzocyclobutene), PI (polyimide), PBO (polyphenylene benzoxazole), a polymer matrix dielectric film, an organic polymer film, or other materials having similar insulating and structural properties, and is formed by means such as lamination, coating, printing, etc.
[0066] In one embodiment, the protective layer is applied by lamination.
[0067] In one embodiment, the application of the protective layer 107 is such that the protective layer 107 completely covers the wafer conductive layer. In this case, after the application process of the protective layer 107, there will be a thinning of the thickness of the protective layer 107 to expose the surface of the wafer conductive layer;
[0068] In another embodiment, the applied thickness of the protective layer 107 just exposes the surface of the conductive layer.
[0069] Optionally, before the step of applying the protective layer 107, physical and / or chemical treatment is performed on the active surface 1001 of the wafer formed with the wafer conductive layer and / or the surface of the protective layer 107 applied on the wafer 100, so as to make the bonding between the protective layer 107 and the wafer 100 closer. The treatment method can be, optionally, plasma surface treatment to roughen the surface to increase the bonding area and / or chemical promoter modifier treatment, introducing a promoting modification group between the wafer 100 and the protective layer 107, such as a surface modifier with both affinity for organic and affinity for inorganic groups, to increase the adhesion force between the organic / inorganic interface layers.
[0070] The protective layer 107 can protect the die active surface 1131 during the subsequent encapsulation process.
[0071] The presence of the protective layer 107 can make the bonding between the die 113 and the bonding layer 121 stronger, so that during the encapsulation process, the encapsulation pressure is not likely to cause the die 113 to move in position on the carrier plate 117.
[0072] In a preferred embodiment, the Young's modulus of the protective layer 107 is in the range of 1000 - 20000 MPa, more preferably the Young's modulus of the protective layer 107 is in the range of 1000 - 10000 MPa; further preferably the Young's modulus of the protective layer 107 is 1000 - 7000, 4000 - 7000 or 4000 - 8000 MPa; in the best embodiment, the Young's modulus of the protective layer 107 is 5500 MPa.
[0073] In a preferred embodiment, the thickness of the protective layer 107 is in the range of 15 - 50 μm; more preferably the thickness of the protective layer is in the range of 20 - 50 μm; in a preferred embodiment, the thickness of the protective layer 107 is 35 μm; in another preferred embodiment, the thickness of the protective layer 107 is 45 μm; in yet another preferred embodiment, the thickness of the protective layer 107 is 50 μm.
[0074] When the Young's modulus value range of the protective layer 107 is 1000 - 20000 MPa, on the one hand, the protective layer 107 is soft and has good flexibility and elasticity; on the other hand, the protective layer can provide sufficient supporting force, so that the protective layer 107 has sufficient support for the conductive layer formed on its surface. At the same time, when the thickness of the protective layer 107 is 15 - 50 μm, it ensures that the protective layer 107 can provide sufficient buffering and support.
[0075] Especially in some types of chips, it is necessary to use thin dies for packaging and the conductive layer needs to reach a certain thickness value to form a large electric flux. At this time, the thickness range of the protective layer 107 is selected to be 15-50 μm, and the numerical range of the Young's modulus of the protective layer 107 is 1000-10000 MPa. The soft and flexible protective layer 107 can form a buffer layer between the die 113 and the conductive layer formed on the surface of the protective layer, so that during the use of the chip, the conductive layer on the surface of the protective layer will not overly press the die 113, preventing the pressure of the thick conductive layer from breaking the die 113. At the same time, the protective layer 107 has sufficient material strength, and the protective layer 107 can provide sufficient support for the thick conductive layer.
[0076] When the Young's modulus of the protective layer 107 is 1000-20000 MPa, especially when the Young's modulus of the protective layer 107 is 4000-8000 MPa and the thickness of the protective layer 107 is 20-50 μm, due to the material properties of the protective layer 107, the protective layer 107 can effectively protect the die against the ejector pin pressure of the die transfer equipment during the subsequent die transfer process;
[0077] The die transfer process is the process (reconstruction process) of rearranging and bonding the cut and separated dies 113 onto the carrier 117. The die transfer process requires the use of a die transfer equipment (bonder machine). The die transfer equipment includes ejector pins. The ejector pins are used to lift the dies 113 on the wafer 100, and the lifted dies 113 are picked up by a bonder head and transferred and bonded onto the carrier 117.
[0078] During the process of the ejector pins lifting the dies 113, the dies 113, especially the thin dies 113, are brittle and prone to breaking under the lifting pressure of the ejector pins. The protective layer 100 with material properties can protect the brittle dies 113 and keep the dies 113 intact even under a large lifting pressure in this process.
[0079] In a preferred embodiment, the protective layer 107 is an organic / inorganic composite material layer including filler particles. Further, the filler particles are inorganic oxide particles; further, the filler particles are SiO2 particles; in one embodiment, the filler particles in the protective layer 107 are two or more different kinds of inorganic oxide particles, such as SiO2 mixed with TiO2 particles. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, such as SiO2 mixed with TiO2 particles, are spherical or quasi-spherical. In a preferred embodiment, the filling amount of the filler particles in the protective layer 107, such as inorganic oxide particles, such as SiO2 particles, such as SiO2 mixed with TiO2 particles, is more than 50%.
[0080] Organic materials have the advantages of being easy to operate and apply. The die 113 to be encapsulated is an inorganic material such as silicon. When the protective layer 107 is made of an organic material alone, due to the differences in the material properties between the organic material and the inorganic material, the encapsulation process will be difficult and the encapsulation effect will be affected. Using an organic / inorganic composite material with inorganic particles added to the organic material can modify the material properties of the organic material, making the material have the characteristics of both organic and inorganic materials.
[0081] In a preferred embodiment, when (T < Tg), the thermal expansion coefficient of the protective layer 107 ranges from 3 to 10 ppm / K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 5 ppm / K; in a preferred embodiment; the thermal expansion coefficient of the protective layer 107 is 7 ppm / K; in a preferred embodiment, the thermal expansion coefficient of the protective layer 107 is 10 ppm / K.
[0082] In the subsequent encapsulation process, the die 113 with the protective layer 107 will expand and contract correspondingly during the heating and cooling processes of the encapsulation. When the thermal expansion coefficient of the protective layer 107 is in the range of 3 to 10 ppm / K, the degree of expansion and contraction between the protective layer 107 and the die 113 remains relatively consistent, and the interfacial stress is not easily generated at the connection interface between the protective layer 107 and the die 113, and the bond between the protective layer 107 and the die 113 is not easily damaged, making the structure of the encapsulated chip more stable.
[0083] During the use of the encapsulated chip, it often needs to undergo thermal cycling. The thermal expansion coefficient range of the protective layer 107 is 3 to 10 ppm / K and the die 113 has the same or similar thermal expansion coefficient. During the thermal cycling process, the protective layer 107 and the die 113 maintain a relatively consistent degree of expansion and contraction, avoiding the accumulation of interfacial fatigue at the interface between the protective layer 107 and the die 113, making the encapsulated chip durable and extending the service life of the chip.
[0084] On the other hand, if the coefficient of thermal expansion of the protective layer is too small, an excessive amount of filler particles need to be filled in the composite material of the protective layer 107, which will increase the Young's modulus of the material while further reducing the coefficient of thermal expansion, resulting in reduced flexibility and excessive rigidity of the protective layer material, and poor buffering effect of the protective layer 107. It is optimal to limit the coefficient of thermal expansion of the protective layer to 5-10 ppm / k.
[0085] In a preferred embodiment, the numerical range of the tensile strength of the protective layer 107 is 20-50 MPa; in a preferred embodiment, the tensile strength of the protective layer 107 is 37 MPa.
[0086] Optionally, after the process of applying the protective layer 107 on the active surface 1001 of the wafer, the back surface 1002 of the wafer is polished and thinned to the required thickness.
[0087] Modern electronic devices are miniaturized and lightweight, and chips tend to be thinner. In this step, the wafer 100 sometimes needs to be thinned to a very thin thickness. However, it is difficult to process and transfer thin wafers 100, and the process of polishing and thinning is difficult, and it is often difficult to thin the wafer 100 to the ideal thickness. When the surface of the wafer 100 has a protective layer 107, the protective layer 107 with material properties will support the wafer 100, reducing the difficulty of processing, transferring and thinning the wafer 100.
[0088] First, a wafer conductive layer 170 and a protective layer 107 are formed on the wafer. The electrical connection point 103 is electrically connected to the wafer conductive layer 170. Since the wafer conductive layer 170 is formed at the wafer level, the alignment accuracy between it and the electrical connection point 103 is high. And in the subsequent step of forming the panel-level conductive layer 180, the wafer conductive layer 170 is electrically connected to the panel-level conductive layer 180, and the tolerance of wiring accuracy decreases, and the conductive traces can be closer.
[0089] As Figure 5 shown, the wafer 100 formed with the wafer conductive layer and applied with the protective layer 107 is cut along the scribe line to obtain a plurality of bare chips 113, and the bare chips 113 have a bare chip active surface 1131 and a bare chip back surface 1132.
[0090] Due to the material properties of the protective layer, in the cutting process of the wafer 100, the separated bare chips 113 have no burrs and debris (die chip).
[0091] In one embodiment, before the step of cutting the wafer 100 to separate the die 113, it further includes performing a plasma surface treatment on the side of the wafer 100 with the protective layer 107 applied thereto to increase the surface roughness, so as to increase the adhesion of the die 113 to the carrier plate 117 in the subsequent process and prevent the die movement of the die 113 under the encapsulation pressure.
[0092] It can be understood that, when the process permits, the wafer 100 formed with the wafer conductive layer can be selectively cut into the die 113 to be encapsulated according to the specific actual situation, and then the protective layer 107 is formed on the active die surface 1131 of each die 113 to be encapsulated.
[0093] As Figure 6a shown, a carrier plate 117 is provided. The carrier plate 117 has a carrier plate front surface 1171 and a carrier plate back surface 1172. The divided die 113 are arranged at preset positions on the carrier plate front surface 1171, with the active die surface 1131 facing the carrier plate 117 and the die back surface 1132 facing away from the carrier plate 117.
[0094] The shape of the carrier plate 117 is: circular, triangular, quadrilateral or any other shape. The size of the carrier plate 117 can be a small-sized wafer substrate or various sizes, especially large-sized rectangular carrier plates. The material of the carrier plate 117 can be metal, non-metal, plastic, resin, glass, stainless steel, etc. Preferably, the carrier plate 117 is a large-sized quadrilateral panel made of stainless steel.
[0095] The carrier plate 117 has a carrier plate front surface 113 and a carrier plate back surface 115, and the carrier plate front surface 113 is preferably a flat surface.
[0096] In one embodiment, the die 113 is bonded and fixed to the carrier plate 117 by the bonding layer 121.
[0097] The bonding layer 121 can be formed on the carrier plate front surface 1171 by means of lamination, printing, spraying, coating, etc. In order to facilitate the separation of the carrier plate 117 and the die 113 with the back encapsulation completed in the subsequent process, the bonding layer 121 preferably uses an easily separable material, for example, a thermal separation material is used as the bonding layer 121.
[0098] Preferably, the positions where the die 113 are arranged can be pre-identified on the carrier plate 117. The identification can be formed on the carrier plate 117 by means of laser, mechanical scribing, etc. At the same time, alignment marks are also provided on the die 113 to aim and align with the bonding positions on the carrier plate 117 during pasting.
[0099] Optionally, as Figure 6bAs shown, during the first encapsulation process, multiple die chips 113a and 113b, especially those with different functions, two are shown in the figure, or more than two, can be arranged on the carrier board 117 according to the requirements of the actual product and encapsulated. After encapsulation, it is then cut into multiple packages; thus, one package includes multiple die chips 113a and 113b to form a multi-chip module (MCM), and the positions of multiple die chips 113a and 113b can be freely set according to the needs of the actual product.
[0100] As Figure 7 shown, a molding compound layer 123 is formed.
[0101] The molding compound layer 123 is formed around the die chips 113 to be encapsulated and on the exposed surface of the front side 1171 of the carrier board or the adhesive layer 121. The molding compound layer 123 is used to completely encapsulate the front side 1171 of the carrier board and the die chips 113 to reconstruct a flat structure so that after the carrier board 117 is peeled off, the subsequent encapsulation steps can continue on the reconstructed flat structure.
[0102] The side of the molding compound layer 123 in contact with the front side 1171 of the carrier board or the adhesive layer 121 is defined as the front side 1231 of the molding compound layer. The side of the molding compound layer 123 facing away from the front side 1171 of the carrier board or the adhesive layer 121 is defined as the back side 1232 of the molding compound layer.
[0103] Preferably, the front side 1231 of the molding compound layer and the back side 1232 of the molding compound layer are substantially flat and parallel to the front side 1171 of the carrier board.
[0104] The molding compound layer 123 can be formed by slurry printing, injection molding, thermoforming, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods. The molding compound layer 123 can be made of organic composite materials, resin composite materials, polymer composite materials, polymer composites, such as epoxy resins with fillers, ABF (Ajinomotobuildup film), or other polymers with suitable fillers.
[0105] In one embodiment, the molding compound layer 123 is made of an organic / inorganic composite material and is formed by compression molding.
[0106] Preferably, the coefficient of thermal expansion of the molding compound layer 123 is 3 - 10 ppm / K; in a preferred embodiment, the coefficient of thermal expansion of the molding compound layer 123 is 5 ppm / K; in another preferred embodiment, the coefficient of thermal expansion of the molding compound layer 123 is 7 ppm / K; in yet another preferred embodiment, the coefficient of thermal expansion of the molding compound layer 123 is 10 ppm / K.
[0107] Preferably, the encapsulation layer 123 and the protection layer 107 have the same or similar coefficient of thermal expansion.
[0108] The coefficient of thermal expansion of the encapsulation layer 123 is selected to be 3 - 10 ppm / K and is selected to have the same or similar coefficient of thermal expansion as the protection layer 107. During the heating and cooling processes of the encapsulation process, the degrees of expansion and contraction between the protection layer 107 and the encapsulation layer 123 remain consistent. It is not easy for the two materials to generate interfacial stress. The low coefficient of thermal expansion makes the coefficients of thermal expansion of the encapsulation layer, the protection layer, and the die close to each other, making the interfaces between the encapsulation layer 123, the protection layer 107, and the die 113 tightly bonded, avoiding the separation of the interfacial layer.
[0109] During the use of the packaged chip, it often needs to go through thermal cycling. Since the coefficients of thermal expansion of the protection layer 107, the encapsulation layer 123, and the die 113 are similar, during the thermal cycling process, the interfacial fatigue between the protection layer 107, the encapsulation layer 123, and the die 113 is small, and it is not easy for interface gaps to appear between the protection layer 107, the encapsulation layer 123, and the die 113, increasing the service life of the chip and making the applicable fields of the chip extensive.
[0110] The difference in the coefficients of thermal expansion between the die 113 and the encapsulation layer 123 will also cause the packaged panel assembly to warp. Due to the occurrence of the warping phenomenon, it is difficult to locate the precise position of the die 113 in the panel assembly during the subsequent conductive layer formation process, having a great impact on the conductive layer formation process.
[0111] Especially in the large-panel encapsulation process, due to the large size of the panel, even slight warping of the panel will cause the die at the outer peripheral part far from the center of the panel to have a large-size position change compared to before molding. Therefore, in the large-panel encapsulation process, solving the warping problem becomes one of the keys to the entire process. The warping problem even restricts the enlargement of the panel size and becomes a technical barrier in large-size panel encapsulation.
[0112] Limiting the coefficients of thermal expansion of the protection layer 107 and the encapsulation layer 123 within the range of 3 - 10 ppm / K, and preferably the encapsulation layer 123 and the protection layer 107 having the same or similar coefficient of thermal expansion can effectively avoid the generation of warping of the panel assembly and realize the encapsulation process using a large panel.
[0113] Meanwhile, during the encapsulation process, since the encapsulation pressure will exert pressure on the back of the die 113, this pressure is likely to press the die 113 into the adhesive layer 121, thereby causing the die 113 to sink into the adhesive layer 121 during the formation of the encapsulation layer 123. After the encapsulation layer 123 is formed, the die 113 and the front surface 1231 of the encapsulation layer are not in the same plane, and the surface of the die 113 protrudes beyond the front surface 1231 of the encapsulation layer, forming a stepped structure. During the subsequent formation of the conductive layer, the conductive trace 125 will also correspondingly have a stepped structure, making the packaging structure unstable.
[0114] When there is a protective layer 107 with material properties on the active surface 1131 of the die, it can play a buffering role under the encapsulation pressure, preventing the die 113 from sinking into the adhesive layer 121, thereby avoiding the generation of a stepped structure on the front surface 1231 of the encapsulation layer.
[0115] As Figure 8a shown, the thickness of the encapsulation layer 123 can be reduced by grinding or polishing the back surface 1232 of the encapsulation layer.
[0116] In one embodiment, as Figure 8b shown, the thickness of the encapsulation layer 123 can be reduced to the back surface 1132 of the die 113, thereby exposing the back surface 1132 of the die. The packaged and formed chip structure is as Figure 14b shown.
[0117] As Figure 9 shown, the carrier plate 117 is peeled off, exposing the front surface 1231 of the encapsulation layer, the protective layer 107, and the exposed surface of the wafer conductive layer.
[0118] After the carrier plate 117 is separated, the encapsulation layer 123 structure covering the die 113 is defined as the panel assembly 150.
[0119] Figure 10 And Figure 11 shows an embodiment of the process of forming a patterned panel-level conductive layer on the die 113 in the encapsulation layer 123.
[0120] Figure 10 shows forming a conductive trace 125 on the die 113 in the encapsulation layer 123; at least a part of the conductive trace 125 is formed on the surface of the protective layer 107 on the active surface 1131 of the die, and is electrically connected to at least a part of the wafer stud 111;
[0121] The conductive trace 125 can be one or more layers of materials such as copper, gold, silver, tin, aluminum, etc. or a combination of materials, or can be other suitable conductive materials formed by using PVD, CVD, sputtering, electroplating, electroless plating processes, or other suitable metal deposition processes.
[0122] In one embodiment, the conductive trace 125 extends along the surface of the protective layer 107 and the front surface 1231 of the molding compound layer, and extends to the edge of the chip package when the packaging is completed. The packaged and molded chip structure is as Figure 14d shown. The conductive trace 125 extends to the edge of the package, at which time the conductive trace 125 wraps and connects the interface between the protective layer 107 and the molding compound layer 132, increasing the stability of the packaged chip structure.
[0123] Figure 11 It shows that a conductive stud 127 is formed on the pad or connection point of the conductive trace 125; the shape of the conductive stud 127 can be circular, or other shapes such as oval, square, linear, etc. The conductive stud 127 can be made of one or more layers of materials such as copper, gold, silver, tin, aluminum, or a combination of these materials, or can be made of other suitable conductive materials formed by using PVD, CVD, sputtering, electroplating, electroless plating processes, or other suitable metal deposition processes.
[0124] The panel-level conductive layer is composed of the conductive trace 125 and / or the conductive stud 127, and the panel-level conductive layer can be one layer or multiple layers. The panel-level conductive layer can have the function of fan-out redistribution layer (fan-out RDL).
[0125] As Figure 12a shown, a dielectric layer 129 is formed on the panel-level conductive layer.
[0126] One or more dielectric layers 129 are formed on the surface of the panel-level conductive layer by using lamination, coating, spraying, printing, molding, and other suitable methods.
[0127] The dielectric layer 129 can be BCB (benzocyclobutene), PI (polyimide), PBO (polyphenylene benzoxazole), ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide, aluminum oxide, polymer matrix dielectric film, organic polymer film; it can also be an organic composite material, resin composite material, polymer composite material, polymer composite material, such as an epoxy resin with fillers, ABF, or other polymers with suitable fillers; it can also be other materials with similar insulating and structural properties. In a preferred embodiment, the dielectric layer 129 is ABF. The dielectric layer 129 serves to protect the conductive layer and provide insulation.
[0128] In one embodiment, the thickness of the dielectric layer 129 applied is thicker than the thickness of the panel-level conductive layer, and the panel-level conductive layer is exposed through a grinding process; in another embodiment, the thickness of the dielectric layer 133 applied is the same as the thickness of the panel-level conductive layer, and the panel-level conductive layer is exactly exposed after the dielectric layer 129 is applied.
[0129] In one embodiment, the steps of Figures 10 - 12b are repeated to form a multi-layer panel-level conductive layer on the die active surface 1131 of die 113.
[0130] Return to Figures 10 - 12b the steps of. In one embodiment, the steps for forming the panel-level conductive layer may be:
[0131] Form conductive traces 125 on the die active surface 1131 of die 113;
[0132] Use lamination, coating, spraying, printing, molding and other suitable methods to form one or more dielectric layers 129 on the surface of the conductive traces 125. The height of the dielectric layer 129 is higher than the height of the conductive traces 125, and the conductive traces 125 are completely encapsulated in the dielectric layer 129;
[0133] Form openings at positions corresponding to the pads or connection points of the conductive traces 125 on the dielectric layer 129, and form conductive studs 127 in the openings.
[0134] In another embodiment, no conductive studs 127 are formed in the openings, so that the pads or connection points of the conductive traces 125 of the completed package are exposed from the openings.
[0135] In a preferred embodiment, after the application step of the dielectric layer 129, the outermost panel-level conductive layer thickness is etched and thinned to form a groove 131 on the outer surface of the dielectric layer 129. The packaged chip structure is as Figure 14b , shown in 14c.
[0136] Optionally, as Figure 12b shown, in a single packaging process, multiple dies 113a and 113b, especially multiple dies with different functions, two are shown in the figure, and it can also be more than two, can be packaged into a multi-chip package component. The patterning design of the conductive layers of the multiple dies 113a and 113b is designed according to the electrical connection requirements of the actual product. The packaged chip structure is as Figure 14e shown.
[0137] As Figure 13 shown, the packaged monomers are cut and separated to form the packaged completed chips, and mechanical or laser cutting can be used.
[0138] Figure 14a , Figure 14b , Figure 14c , Figure 14d and Figure 14eIt is a schematic diagram of a chip packaging structure obtained by the packaging method provided in an exemplary embodiment of the present disclosure. As shown in the figure, a chip packaging structure includes: at least one die 113, and the die 113 includes a die active surface 1131 and a die back surface 1132; a conductive structure, including a wafer conductive layer 170 and panel-level conductive layers 125, 127; a protective layer 107; a molding compound layer 123 for encapsulating the die 113; and a dielectric layer 129.
[0139] In some embodiments, the Young's modulus of the protective layer 107 is any one of the following numerical ranges or values: 1000 - 20000 MPa, 1000 - 10000 MPa, 4000 - 8000 MPa, 1000 - 7000 MPa, 4000 - 7000 MPa, 5500 MPa. The protective layer 107 is soft, has good flexibility and elasticity, and provides sufficient support for the panel conductive layer 180 formed on its surface, especially suitable for the packaging of thin dies with large electrical fluxes.
[0140] In some embodiments, the material of the protective layer 107 is an organic / inorganic composite material. Preferably, an organic / inorganic composite material obtained by adding inorganic particles to an organic material can modify the material properties of the organic material, making the material have the characteristics of both organic and inorganic materials.
[0141] In some embodiments, the thickness of the protective layer 107 is any one of the following numerical ranges or values: 15 - 50 μm, 20 - 50 μm, 35 μm, 45 μm, 50 μm. This thickness range ensures that the protective layer 107 can provide sufficient buffering and support.
[0142] In some embodiments, the thermal expansion coefficient of the protective layer 107 is any one of the following numerical ranges or values: 3 - 10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.
[0143] In some embodiments, the thermal expansion coefficient of the molding compound layer 123 is any one of the following numerical ranges or values:
[0144] 3 - 10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.
[0145] In some embodiments, the protective layer 107 and the molding compound layer 123 have the same or similar thermal expansion coefficients. This avoids the accumulation of interfacial fatigue at the interfaces between the protective layer 107, the molding compound layer 123, and the die 113, making the packaged chip durable and extending the chip service life.
[0146] In some embodiments, such as Figure 14a 、 14bAs shown in 14c, the wafer conductive layer 170 includes wafer conductive traces 106 and wafer conductive studs 111; the die active surface 1131 includes electrical connection points 103; at least a portion of the wafer conductive traces 106 and at least a portion of the electrical connection points 103 are electrically connected; the wafer conductive studs 111 are formed on the pads or connection points of the wafer conductive traces 106.
[0147] In some embodiments, as Figure 14c shown, at least a portion of the wafer conductive traces 106 individually lead out at least a portion of the electrical connection points 103.
[0148] In some embodiments, as Figure 14a 、 14b shown, at least a portion of the wafer conductive traces 106 interconnect and lead out multiple ones of at least a portion of the electrical connection points 103 to each other.
[0149] In some embodiments, as Figure 14d shown, the wafer conductive layer 170 includes wafer conductive studs 111; at least a portion of the wafer conductive studs 111 and at least a portion of the electrical connection points 103 are electrically connected.
[0150] In some embodiments, the panel - level conductive layer 180 includes conductive traces 125 and / or conductive studs 127; the panel - level conductive layer 180 and the wafer conductive studs 111 are electrically connected; the panel - level conductive layer is one or more layers.
[0151] In some embodiments, as Figure 14d 、 14e shown, at least a portion of the conductive traces 125 closest to the die active surface 1131 are formed on the front surface 1231 of the encapsulation layer and extend to the edge of the package to increase package stability.
[0152] In some embodiments, as Figure 14b 、 14c shown, the die back surface 1132 is exposed from the encapsulation layer 123 to facilitate chip heat dissipation.
[0153] In some embodiments, as Figure 14b 、 14c shown, the surface of the dielectric layer 129 has grooves at positions corresponding to the conductive layer.
[0154] In some embodiments, as Figure 14e shown, the at least one die 113 is multiple dies 113, and the multiple dies 113 are electrically connected according to product design.
[0155] Figure 15The schematic diagram of the packaged chip in use is shown. During use, the packaged chip is connected to the circuit board or substrate 161 through the solder 160, and then connected to other circuit components.
[0156] When there are grooves 131 on the surface of the dielectric layer 129 of the packaged chip, the connection of the solder 160 can be made stable and not easily movable.
[0157] The above specific embodiments are intended to further elaborate on the technical solutions and technical effects of the present disclosure. However, those skilled in the art will understand that the above specific embodiments are not used to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the inventive concept of the present disclosure shall be included within the protection scope of the present disclosure.
Claims
1. A chip packaging structure, characterized in that: include: at least one die, the die comprising a die active side and a die backside; The active surface of the die includes electrical connection points and an insulating layer; Conductive structures, including wafer-level conductive layers and panel-level conductive layers; The wafer conductive layer includes wafer conductive traces and wafer conductive protrusions, wherein the wafer conductive traces are electrically connected to at least a portion of electrical connection points on the active surface of the die, and the wafer conductive protrusions are electrically connected to the wafer conductive traces; The panel-level conductive layer is electrically connected to the wafer conductive protrusions; a protective layer, the protective layer being located on the wafer conductive traces and the wafer conductive protrusions, and being used to cover the wafer conductive traces and the wafer conductive protrusions, with a side surface of the protective layer being flush with a side surface of the bare chip; The material of the protective layer is an organic / inorganic composite material, and the thermal expansion coefficient of the protective layer is 3 to 10 ppm / K; a plastic encapsulation layer, the plastic encapsulation layer being used to encapsulate the die and the protective layer, wherein a surface of the plastic encapsulation layer close to the protective layer and a surface of the protective layer away from the active surface of the die are coplanar; A dielectric layer is formed on the panel-level conductive layer, and the dielectric layer is used to encapsulate the panel-level conductive layer.
2. The chip packaging structure according to claim 1, wherein: The wafer conductive bumps are formed on pads or connection points of the wafer conductive traces.
3. The chip packaging structure according to claim 2, wherein: At least a portion of the wafer conductive traces individually lead out the electrical connection points.
4. The chip packaging structure according to claim 2, wherein: At least a portion of the wafer conductive traces interconnect and lead out a plurality of the electrical connection points.
5. The chip packaging structure according to claim 1, wherein: The wafer conductive layer includes wafer conductive protrusions; The die active surface includes electrical connection points; At least a portion of the wafer conductive protrusions are electrically connected to the electrical connection points.
6. The chip packaging structure according to any one of claims 2 to 5, characterized in that: The panel-level conductive layer includes conductive traces and / or conductive protrusions; The panel-level conductive layer is one layer or multiple layers.
7. The chip packaging structure according to claim 6, wherein: At least a portion of the conductive trace closest to the active surface of the die is formed on the front side of the plastic layer and extends to the edge of the package body.
8. The chip packaging structure according to any one of claims 2 to 5, characterized in that: The back side of the die is exposed from the molding layer.
9. The chip packaging structure according to any one of claims 2 to 5, characterized in that: The surface of the dielectric layer has a groove at a position corresponding to the conductive layer.
10. The chip packaging structure according to any one of claims 2 to 5, characterized in that: The at least one bare chip is a plurality of bare chips, and the plurality of bare chips are electrically connected according to product design.
11. The chip packaging structure according to any one of claims 2 to 5, characterized in that: The Young's modulus of the protective layer is 1000 to 20000 MPa.
12. The chip packaging structure according to claim 11, wherein: The Young's modulus of the protective layer is 1000-10000 MPa.
13. The chip packaging structure according to claim 12, wherein: The Young's modulus of the protective layer is 4000-8000 MPa.
14. The chip packaging structure according to claim 13, wherein: The Young's modulus of the protective layer is 5500 MPa.
15. The chip packaging structure according to any one of claims 2 to 5, characterized in that: The thickness of the protective layer is 15 to 50 μm.
16. The chip packaging structure according to claim 15, wherein: The thickness of the protective layer is 20 to 50 μm.
17. The chip packaging structure according to claim 16, wherein: The thickness of the protective layer is 35 μm, 45 μm, and 50 μm.
18. The chip packaging structure according to claim 1, wherein: The thermal expansion coefficient of the protective layer is 5 ppm / K, 7 ppm / K, and 10 ppm / K.
19. The chip packaging structure according to claim 18, wherein: The thermal expansion coefficient of the plastic sealing layer is 3 to 10 ppm / K.
20. The chip packaging structure according to claim 19, wherein: The thermal expansion coefficient of the plastic sealing layer is 5ppm / K, 7ppm / K, and 10ppm / K.
21. The chip packaging structure according to any one of claims 2 to 5, characterized in that: The protective layer and the plastic packaging layer have substantially the same thermal expansion coefficient.
22. A chip packaging method, characterized in that: include: forming a wafer conductive layer on the wafer active surface of the wafer to be packaged, including sequentially forming wafer conductive traces and wafer conductive protrusions, wherein the wafer active surface also includes electrical connection points and an insulating layer; forming a protective layer on the wafer conductive layer, wherein the protective layer covers the wafer conductive layer and exposes the surface of the wafer conductive layer; Cutting the wafer conductive layer, the protective layer and the wafer to form a single die having the cut wafer conductive layer and the protective layer; Mounting the single bare chip with the cut wafer conductive layer and the protective layer on a carrier board, with the active surface of the bare chip facing the front surface of the carrier board and the back surface of the bare chip facing away from the front surface of the carrier board; forming a plastic encapsulation layer on the back side of the die on the carrier, wherein the plastic encapsulation layer completely encapsulates the die; and peeling off the carrier; forming a panel-level conductive layer electrically connected to the wafer conductive layer; forming a dielectric layer on the panel-level conductive layer, Optionally, the method further includes thinning the back side of the plastic packaging layer to expose the back side of the die.
23. The chip packaging method according to claim 22, wherein: The wafer conductive traces are formed so that at least a portion of the wafer conductive traces leads out an electrical connection point individually and / or at least a portion of the wafer conductive traces interconnects and leads out a plurality of electrical connection points.
24. The chip packaging method according to claim 23, wherein: The step of forming the wafer conductive layer includes forming wafer conductive protrusions; at least a portion of the wafer conductive protrusions are electrically connected to electrical connection points and the electrical connection points are led out.
25. The chip packaging method according to any one of claims 22 to 24, characterized in that: The step of forming the panel-level conductive layer includes forming conductive traces and / or conductive protrusions; the formed panel-level conductive layer is electrically connected to the wafer conductive protrusions; and the formed panel-level conductive layer is one layer or multiple layers.
26. The chip packaging method according to any one of claims 22 to 24, characterized in that: The method further includes forming grooves at positions corresponding to the panel-level conductive layer on the dielectric layer by metal etching.
27. The chip packaging method according to any one of claims 22 to 24, characterized in that: The method further comprises the step of performing plasma surface treatment and / or chemically accelerated modifier treatment on the wafer and / or the surface of the protective layer located on the wafer.
28. The chip packaging method according to any one of claims 22 to 24, characterized in that: The material of the protective layer is an organic / inorganic composite material and / or the protective layer and the plastic sealing layer have substantially the same thermal expansion coefficient.
29. The chip packaging method according to claim 28, wherein: The Young's modulus of the protective layer is 1000-20000 MPa and / or the thickness of the protective layer is 15-50 μm.
30. The chip packaging method according to claim 29, wherein: The Young's modulus of the protective layer is 1000-10000 MPa and / or the thickness of the protective layer is 20-50 μm.
31. The chip packaging method according to claim 30, wherein: The Young's modulus of the protective layer is 4000-8000 MPa and / or the thickness of the protective layer is 35 μm, 45 μm, or 50 μm.
32. The chip packaging method according to claim 31, wherein: The Young's modulus of the protective layer is 5500 MPa.
33. The chip packaging method according to claim 28, wherein: The thermal expansion coefficient of the protective layer is 3-10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K, and / or the thermal expansion coefficient of the plastic sealing layer is 3-10 ppm / K, 5 ppm / K, 7 ppm / K, 10 ppm / K.
34. The chip packaging method according to claim 33, wherein: The thermal expansion coefficient of the protective layer is 5ppm / K, 7ppm / K, 10ppm / K, and / or the thermal expansion coefficient of the plastic sealing layer is 5ppm / K, 7ppm / K, 10ppm / K.