Semiconductor device and semiconductor package having the same

Abstract

A semiconductor package and a semiconductor device are provided. The semiconductor package includes: a package substrate; a first semiconductor device on an upper surface of the package substrate; a second semiconductor device on an upper surface of the first semiconductor device; a first connection bump attached to a lower surface of the package substrate; a second connection bump disposed between the package substrate and the first semiconductor device and electrically connected to the package substrate and the first semiconductor device; and a third connection bump disposed between the first semiconductor device and the second semiconductor device and electrically connected to the first semiconductor device and the second semiconductor device. The first semiconductor device has an edge and a step at the edge.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0082374 filed on Jul. 16, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to a semiconductor device and a semiconductor package including the semiconductor device, and an article that can be cut (or diced) into semiconductor devices for use in a semiconductor package. The present inventive concept also relates to a cutting method for forming a semiconductor device, and to a method for manufacturing a semiconductor package by cutting a substrate into individual semiconductor devices and then forming a package from at least one semiconductor device. Background Art

[0004] In the process of cutting a semiconductor substrate, the semiconductor substrate is fixed to a tape, and then the semiconductor substrate and the tape are cut. In this case, the tape may be stretched and deformed due to its ductility (tape burr phenomenon) without being cut cleanly, and the cut surface of the semiconductor substrate may be chipped. These problems may lead to contamination of the semiconductor substrate and a reduction in the yield of semiconductor devices manufactured from the semiconductor substrate. Summary of the invention

[0005] According to one aspect of the present invention, a semiconductor package is provided, comprising: a packaging substrate; a first semiconductor device on an upper surface of the packaging substrate; a second semiconductor device on an upper surface of the first semiconductor device; a first connection bump attached to a lower surface of the packaging substrate; a second connection bump disposed between the packaging substrate and the first semiconductor device and electrically connected to the packaging substrate and the first semiconductor device; and a third connection bump disposed between the first semiconductor device and the second semiconductor device and electrically connected to the first semiconductor device and the second semiconductor device, wherein a step in the first semiconductor device is defined at an edge of the first semiconductor device.

[0006] According to another aspect of the inventive concept, there is provided an article for use in manufacturing a semiconductor device, comprising: a semiconductor substrate; and a semiconductor device layer at an upper portion of the semiconductor substrate. The semiconductor device layer comprises a die located on a first region of the semiconductor substrate, and the die are separated by scribe lanes on a second region of the semiconductor substrate. In addition, the semiconductor substrate has a modified region located in a second region thereof and a trench located in a lower portion of the second region.

[0007] According to another aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor substrate having opposite sides; a semiconductor device layer located at one side of the semiconductor substrate and constituting a first surface of the semiconductor device; and an electrical patterning layer on the other side of the semiconductor substrate and constituting a second surface of the semiconductor device, wherein the semiconductor substrate has a step constituting an edge of the semiconductor device, and the semiconductor substrate has a modified region constituting an edge of the semiconductor device.

[0008] According to another aspect of the inventive concept, a semiconductor package is provided, comprising: a stack of vertically spaced components, the components comprising a lower substrate, an upper semiconductor device, and at least one intermediate semiconductor device disposed between the lower substrate and the upper semiconductor device; an underfill material disposed between the components and laterally protruding outward from a combined footprint of the semiconductor devices; and a molding layer encapsulating each of the at least one intermediate semiconductor device and the underfill material on the lower substrate. Each intermediate semiconductor device comprises a semiconductor substrate. The semiconductor substrate has a step constituting an edge of the intermediate semiconductor device and a modified region constituting the edge. The underfill material fills the step. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view of a semiconductor package according to an example of the inventive concept;

[0011] Figure 2A and Figure 2B each is a cross-sectional view of a peripheral portion of a semiconductor device of a semiconductor package according to the inventive concept, each showing an example of a step at an edge of the device;

[0012] Figure 3A is a cross-sectional view of a semiconductor package according to an example of the inventive concept;

[0013] Figure 3B is a cross-sectional view of a semiconductor package according to an example of the inventive concept;

[0014] Figure 4A is a top view of an article including a semiconductor substrate to be cut into semiconductor devices according to an example of the inventive concept;

[0015] Figure 4B is a cross-sectional view of an example article having a groove in a substrate thereof according to an example of the inventive concept;

[0016] Figure 4Cis a cross-sectional view of another example article having a groove in a substrate thereof according to an example of the inventive concept;

[0017] Figure 5 is a cross-sectional view of an article having a through electrode according to an example of the inventive concept;

[0018] Fig. 6A is a cross-sectional view of a semiconductor device according to an example of the inventive concept;

[0019] Figure 6B is a cross-sectional view of a semiconductor device according to another example of the inventive concept;

[0020] Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14A , Fig. 14B , Fig.15 , Fig.16 , Fig.17 and Fig.18 are cross-sectional views of structures during the processes of a method for manufacturing a semiconductor package according to the inventive concept, respectively, wherein: Fig.14A and Fig. 14B Different examples of cutting operations that may be performed in the method are shown. DETAILED DESCRIPTION

[0021] Examples of the inventive concept will be described in detail below with reference to the accompanying drawings.

[0022] Figure 1 is a cross-sectional view of a semiconductor package 100 according to an example of the inventive concept.

[0023] Reference Figure 1 , the semiconductor package 100 may include a package substrate S1. The package substrate S1 may include any one of a wafer, a carrier, a printed circuit board (PCB), and a semiconductor device. In addition, the semiconductor package 100 may further include a first semiconductor device C1 and a second semiconductor device C2 located on the package substrate S1.

[0024] The first semiconductor device C1 and the second semiconductor device C2 may be semiconductor memory devices. The semiconductor memory devices may be volatile memory semiconductor devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices, or non-volatile memory semiconductor devices, such as phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM) or resistive random access memory (RRAM) devices.

[0025] Alternatively, the first semiconductor device C1 and the second semiconductor device C2 may be logic semiconductor devices. For example, the first semiconductor device C1 and the second semiconductor device C2 may be central processing units (CPUs), graphic processing units (GPUs), or application processors (APs).

[0026] The first semiconductor device C1 and the second semiconductor device C2 may be homogeneous semiconductor devices or heterogeneous semiconductor devices. Figure 1 The semiconductor package 100 in which the first semiconductor device C1 and the second semiconductor device C2 are stacked is shown as an example, but the number of semiconductor devices stacked inside the semiconductor package 100 is not limited thereto. For example, 2 to 32 semiconductor devices may be stacked inside the semiconductor package 100.

[0027] Still refer to Figure 1 , the first connection bump 110 may be located below the lower surface of the package substrate S1. The first semiconductor device C1 may be mounted on the upper surface of the package substrate S1, and the second connection bump 120 may be arranged between the package substrate S1 and the first semiconductor device C1, so that the first semiconductor device C1 may be electrically connected to the package substrate S1. The second semiconductor device C2 may be mounted on the upper surface of the first semiconductor device C1 and electrically connected to the first semiconductor device C1 via the third connection bump 130.

[0028] The structure of the first connection bump 110 may be different from the structures of the second connection bump 120 and the third connection bump 130. According to some examples, the second connection bump 120 and the third connection bump 130 have the same structure.

[0029] The package substrate S1 may include a third semiconductor device. The package substrate S1 may include a first semiconductor substrate 141, a first semiconductor device layer 142, a first through electrode 143, and a first connection pad 144. Figure 1As shown, the first semiconductor substrate 141 may include an upper surface 145 and a lower surface 146 arranged at opposite positions, and the first semiconductor device layer 142 may be formed below the lower surface 146 of the first semiconductor substrate 141. The first through electrode 143 extends through the first semiconductor substrate 141. The first connection pad 144 may be formed below the lower surface 146 of the first semiconductor substrate 141 and may be electrically connected to the first through electrode 143.

[0030] In the above description, for convenience, the upper surface 145 refers to the surface of the first semiconductor substrate 141 close to the first semiconductor device C1, and the lower surface 146 refers to the surface of the first semiconductor substrate 141 close to the first connection bump 110. However, in the case where the semiconductor package 100 is turned upside down, the upper surface 145 of the first semiconductor substrate 141 is the bottom surface, and the lower surface 146 thereof is the top surface.

[0031] The first semiconductor substrate 141 of the package substrate S1 may be, for example, a silicon (Si) substrate. Alternatively, the first semiconductor substrate 141 may include a semiconductor element (e.g., germanium (Ge)) or a compound semiconductor (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). Alternatively, the first semiconductor substrate 141 may have a silicon-on-insulator (SOI) structure. For example, the first semiconductor substrate 141 may include a buried oxide (BOX) layer. In addition, the first semiconductor substrate 141 may include a conductive region, such as a doped well or a doped structure. In addition, the first semiconductor substrate 141 may have any of various types of device separation structures, such as a shallow trench isolation (STI) structure.

[0032] The first semiconductor device layer 142 of the package substrate S1 may include various types of individual devices. For example, these individual devices may include microelectronic devices, for example, metal oxide semiconductor field effect transistors (MOSFETs) such as complementary metal insulator semiconductor (CMIS) transistors, image sensors such as system large-scale integration and CMOS imaging sensors (CIS), micro-electromechanical systems (MEMS), active devices, passive devices, etc. These individual devices may be formed inside the first semiconductor device layer 142 and electrically connected to the conductive region of the first semiconductor substrate 141. The first semiconductor device layer 142 may also include conductive wiring or conductive plugs, which are configured to electrically connect at least two of these individual devices or to electrically connect multiple individual devices to the conductive region of the first semiconductor substrate 141. In addition, each of the multiple individual devices may be electrically isolated from other adjacent devices of these individual devices by an insulating film.

[0033] Still refer to Figure 1, the first through electrode 143 may extend from the upper surface 145 of the first semiconductor substrate 141 to the lower surface 146 thereof, and extend into the first semiconductor device layer 142. At least a portion of the first through electrode 143 may be in the shape of a pillar. Figure 1 Although not shown in the drawings, the first through electrode 143 may include a barrier film formed on the surface of the pillar and a buried conductive layer inside the barrier film.

[0034] The first connection pad 144 may be arranged on the first semiconductor device layer 142 and electrically connected to a wiring structure inside the first semiconductor device layer 142. The first connection pad 144 may be electrically connected to the first through electrode 143 through an electrical connection to the wiring structure. The first connection pad 144 may include at least one material selected from the group consisting of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au).

[0035] The first upper connection pads 147 electrically connected to the first through electrodes 143 may be formed on the upper surface 145 of the first semiconductor substrate 141. The first upper connection pads 147 may include at least one material selected from the group consisting of Al, Cu, Ni, W, Pt, and Au.

[0036] The first connection bump 110 may be arranged below the first connection pad 144. The first connection bump 110 may be arranged below the lowermost surface of the semiconductor package 100, and may be a chip substrate connection bump for mounting the semiconductor package 100 on an external substrate or an interposer. The first connection bump 110 may receive at least one of a control signal, a power signal, and a ground signal for operations of the first semiconductor device C1, the second semiconductor device C2, and the third semiconductor device from the outside, or transmit data stored in the first semiconductor device C1, the second semiconductor device C2, and the third semiconductor device to the outside.

[0037] The first semiconductor device C1 may be mounted on an upper surface of the package substrate S1 , and the second connection bumps 120 may be interposed between the package substrate S1 and the first semiconductor device C1 , so that the first semiconductor device C1 is electrically connected to the package substrate S1 .

[0038] The first semiconductor device C1 may include a second semiconductor substrate 151, a second semiconductor device layer 152, a second through electrode 153, and a second connection pad 154. Figure 1Although not shown in the figure, the upper surface 155 of the first semiconductor device C1 may include an electrically patterned layer for electrically connecting to another semiconductor device. The electrically patterned layer may be electrically connected to the second semiconductor device layer 152 of the second semiconductor substrate 151 via the second through electrode 153, and electrically connected to the second semiconductor device C2 via the second upper connection pad 157 formed on the upper surface 155 of the first semiconductor device C1.

[0039] The first semiconductor device C1 may have technical features similar to those of the third semiconductor device included in the package substrate S1 , and thus, a detailed description of the first semiconductor device C1 is omitted.

[0040] The second connection bump 120 may be interposed between the second connection pad 154 and the first upper connection pad 147 and may electrically connect the first semiconductor device C1 to the package substrate S1. Figure 1 Although not shown in FIG. 1 , the second connection bump 120 may include a pillar structure and a solder layer.

[0041] The second semiconductor device C2 may be mounted on an upper surface of the first semiconductor device C1. The third connection bump 130 may be interposed between the first semiconductor device C1 and the second semiconductor device C2 so that the second semiconductor device C2 is electrically connected to the first semiconductor device C1.

[0042] The second semiconductor device C2 may include a third semiconductor substrate 161, a third semiconductor device layer 162, and a third connection pad 164. The second semiconductor device C2 may have similar technical features to those of the third semiconductor device included in the package substrate S1, and thus a detailed description of the second semiconductor device C2 is omitted.

[0043] The third connection bump 130 may be disposed between the third connection pad 164 and the second upper connection pad 157 and may electrically connect the second semiconductor device C2 to the first semiconductor device C1. The third connection bump 130 may include a pillar structure and a solder layer. The third connection bump 130 may be an inter-chip connection bump disposed between semiconductor devices.

[0044] The connection film 170 may be disposed between the upper surface of the package substrate S1 and the lower surface of the first semiconductor device C1, and surround the side surface of the second connection bump 120. In addition, the connection film 170 may be disposed between the upper surface of the first semiconductor device C1 and the lower surface of the second semiconductor device C2, and surround the side surface of the third connection bump 130. According to an example of the inventive concept, the connection film 170 protrudes laterally by a certain amount outside the occupied areas of the first semiconductor device C1 and the second semiconductor device C2. Figure 1As shown, the protruding portion of the connection film 170 placed between the upper surface of the package substrate S1 and the lower surface of the first semiconductor device C1 and the protruding portion of the connection film 170 placed between the upper surface of the first semiconductor device C1 and the lower surface of the second semiconductor device C2 can be connected to each other, that is, integrated with each other. However, the concept of the present invention is not limited to this, and the connection films 170 can be separated from each other, that is, the protruding portions of the films 170 are not directly connected to each other. Whether the connection films 170 remain separated from each other or are integrated, they can be referred to as bottom filling materials.

[0045] Despite Figure 1 Although not shown, according to an example, the protruding portion of the connection film 170 may be located on the same plane as the side surface of the semiconductor package 100. Therefore, when the outside of the semiconductor package 100 is viewed, the connection film 170 may be seen from the side of the semiconductor package 100.

[0046] Still refer to Figure 1 , the molding member 180 (or "molding layer") may encapsulate various components on the package substrate S1 by surrounding the upper surface of the package substrate S1 and the side surfaces of the first semiconductor device C1 and the second semiconductor device C2. In more detail, the molding member 180 may surround the side surfaces of the connection film 170 and the side surfaces of the first semiconductor device C1 and the second semiconductor device C2. Figure 1 As shown, the width (dimension in the horizontal direction) of the package substrate S1 may be greater than the width of the first semiconductor device C1 and the second semiconductor device C2 in the horizontal direction, and the molding member 180 may contact the edge of the upper surface of the package substrate S1. In addition, the molding member 180 may be formed on the upper surface of the second semiconductor device C2. However, in Figure 1 In another example not shown in FIG. 1 , the molding member 180 may not extend over the upper surface of the second semiconductor device C2 but may expose the upper surface of the second semiconductor device C2 to the outside of the semiconductor package 100 .

[0047] The molding member 180 may include an underfill material such as an insulating polymer or epoxy resin. According to an example of the inventive concept, the molding member 180 is formed of an epoxy molding compound. The molding member 180 may cover the side surface of the connection film 170. In addition, since the molding member 180 is not formed below the lower surface of the package substrate S1, the first connection bump 110 may be exposed to the outside.

[0048] The first semiconductor device C1 may include a step at an edge D thereof. Here, according to its ordinary meaning, the term "edge" refers to the outer limit of an object; therefore, in this case, the edge D refers to the outer peripheral side surface of the first semiconductor device C1. As will be described below, the step formed at the edge D of the first semiconductor device C1 may be a residual portion of a trench formed at the back side of a semiconductor substrate on which a plurality of first semiconductor devices C1 are formed.

[0049] In addition, a modified region A may be formed in (the substrate of) the first semiconductor device C1 along a portion of the edge D. Here, the term "modified region" refers to a region of material that is modified to have different properties from the surrounding material. For example, due to the modified region A formed within the edge D of the first semiconductor device C1, the density of the first semiconductor device C1 at the edge D may be less than the density at the center portion of the first semiconductor device C1. Figure 2A and Figure 2B The modified region A within the edge D of the first semiconductor device C1 is described in more detail.

[0050] Figure 2A and Figure 2B is a cross-sectional view of an example of an edge D (ie, edges D1 and D2 ) of the first semiconductor device C1 of the semiconductor package 100 according to the inventive concept.

[0051] Reference Figure 2A and Figure 2B , the modified region A formed in the edges D1 and D2 of the first semiconductor device C1 can be formed using an invisible laser device. The invisible laser device can use a lens to focus laser light of a wavelength that can pass through the semiconductor substrate on a point within the semiconductor substrate. As a result, very high nonlinear multiphoton absorption occurs near the light convergence point. Due to the nonlinear multiphoton absorption, the crystals in the semiconductor substrate can absorb the energy of the light concentrated inside the semiconductor substrate, thereby forming the modified region A through the thermal melting phenomenon.

[0052] In the photolithography process of patterning the conductive layer on the semiconductor substrate including the first semiconductor device C1, the modified region A formed in the edges D1 and D2 of the first semiconductor device C1 can be used as an alignment key, which will be described in more detail below. In addition, the modified region A is formed as an alignment key in the scribe lane of the semiconductor substrate, and the groove to be formed in the scribe lane of the semiconductor substrate can be formed deeper than when the modified region A is not formed. The greater the depth of the groove, the greater the height h of the step at the edges D1 and D2 of the first semiconductor device C1 can be.

[0053] exist Figure 2AIn the example shown, the step at the edge D1 of the first semiconductor device C1 is concave, that is, defined by a surface that curves inward. When the individual first semiconductor devices C1 are separated by cutting a semiconductor substrate including the first semiconductor devices C1 and having an arched groove formed below the scribe line, the edge D1 of the first semiconductor device C1 may have a shape as shown in FIG. Figure 2A Concave step shown.

[0054] exist Figure 2B In the example shown, the step at the edge D2 of the first semiconductor device C1 may be defined by a flat surface. When the individual first semiconductor devices C1 are separated by cutting a semiconductor substrate including the first semiconductor devices C1 and having a quadrilateral groove formed at the lower portion of the scribe line, the edge D2 of the first semiconductor device C1 may have a flat surface. Figure 2B Straight steps shown.

[0055] However, the shape of the step at the edge D of the first semiconductor device C1 is not limited to Figure 2A and Figure 2B Those shown.

[0056] Reference Figure 2A and Figure 2B , the height h of the step at the edges D1 and D2 of the first semiconductor device C1 may be about 30% to about 80% of the thickness g of the first semiconductor device C1. Preferably, the height h of the step at the edges D1 and D2 of the first semiconductor device C1 is about 50% to about 70% of the thickness g of the first semiconductor device C1. In some examples of the present inventive concept, the thickness g of the first semiconductor device C1 is about 50 μm, and the height h of the step is about 25 μm to about 35 μm. Here, the term "height of the step" refers to the thickness of the portion of the first semiconductor device C1 in which the recess defined by the step is formed, and the thickness refers to the maximum thickness of the first semiconductor device C1 (i.e., the thickness at the region excluding the step), as shown in the figure.

[0057] In addition, still refer to Figure 2A and Figure 2B , the area of ​​the upper surface 155 of the first semiconductor device C1 is different from the area of ​​the lower surface 156 of the first semiconductor device C1. According to an example of the inventive concept, the area of ​​the upper surface 155 of the first semiconductor device C1 is smaller than the area of ​​the lower surface 156 of the first semiconductor device C1. The horizontal distance b measured from the top of the upper surface 155 to the bottom of the lower surface 156 may be about 30 μm to about 100 μm. In an example of the inventive concept, the horizontal distance b is about 50 μm to about 60 μm.

[0058] Figure 3A and Figure 3B2 is a cross-sectional view of semiconductor packages 300 a and 300 b according to other examples of the inventive concept.

[0059] Reference Figure 3A , the semiconductor package 300 a has a quad-stack structure, in which the first to fourth semiconductor devices C1 ′ to C4 ′ are stacked on a package substrate S1 ′.

[0060] Reference Figure 3B , the semiconductor package 300b has an eight-stack structure in which the first to eighth semiconductor devices C1" to C8" are stacked on a package substrate S1". However, the semiconductor package according to the inventive concept is not limited to semiconductor packages of four-stack and eight-stack structures, and may include other numbers of stacked semiconductor devices.

[0061] Reference Figure 3A and Figure 3B , a semiconductor device (e.g., Figure 3A The first to third semiconductor devices C1′ to C3′ and Figure 3B The first to seventh semiconductor devices C1" to C7") in the embodiment may each form a step in the edge D thereof. In addition, the semiconductor devices C1' to C3' and the semiconductor devices C1" to C7" may each have a modified region A formed in the edge D thereof. The step at the edge D and the modified region A may have the same Figure 2A and Figure 2B The technical features described are similar to the technical features, so their detailed description is omitted.

[0062] In addition, Figure 3A and Figure 3B In the example of FIG. 1 , semiconductor devices (eg, Figure 3A The package substrate S1′ and the fourth semiconductor device C4′ in Figure 3B The package substrate S1″ and the eighth semiconductor device C8″ in the embodiment have no steps and modified areas at their edges.

[0063] The semiconductor devices (eg, Figure 3A The fourth semiconductor device C4′ and Figure 3B The eighth semiconductor device C8") in the embodiment does not require an electrical patterning process on the rear surface corresponding to the semiconductor device layer. Therefore, the groove and the modified region are not formed on the rear surface of the semiconductor substrate on which the semiconductor device is formed. Therefore, Figure 3A The fourth semiconductor device C4′ and Figure 3BThe eighth semiconductor device C8″ in FIG. 4 may not have a step at an edge thereof and may not have a modified region inside the edge.

[0064] Figure 3A and Figure 3B The components of the semiconductor devices of the semiconductor packages 300a and 300b shown may have the same Figure 1 The technical features of the components of the described semiconductor device are similar to the technical features, and therefore, a detailed description thereof is omitted.

[0065] Figure 4A is a top view of a semiconductor substrate W according to an example of the inventive concept.

[0066] In more detail, Figure 4A 4 is a top view of a semiconductor substrate W including a plurality of semiconductor devices to be stacked inside a semiconductor package. The semiconductor substrate W may include any one of a wafer, a carrier substrate, and a PCB. The semiconductor substrate W may include a plurality of semiconductor devices in the form of bare chips composed of a semiconductor device layer 401 at its upper surface, and each bare chip composed of the semiconductor device layer 401 may include reference Figure 1 The bare chips composed of the semiconductor device layer 401 may be separated from each other by a certain distance through the scribe lane 402. There is no semiconductor device in the scribe lane 402. The semiconductor substrate W may be cut into a plurality of bare chips along virtual cutting lines L defined in the scribe lane 402.

[0067] Figure 4B and Figure 4C is a cross-sectional view of an example of a semiconductor substrate W according to the present inventive concept. In more detail, Figure 4B and Figure 4C is a cross-sectional view of a semiconductor substrate W including a plurality of semiconductor devices to be stacked inside a semiconductor package.

[0068] Reference Figure 4B and Figure 4C , the semiconductor substrate W may include a first region 430 and a second region 440 .

[0069] The first region 430 of the semiconductor substrate W may include the semiconductor device layer 401 described above on the upper surface 431 and include an electrical patterning layer 433 below the lower surface 432. The semiconductor device layer 401 formed on the upper surface 431 is similar to the reference Figure 1The semiconductor device layers described are substantially the same. The electrically patterned layer 433 formed below the lower surface 432 can be electrically connected to the semiconductor device layer 401 formed on the upper surface 431. In addition, the electrically patterned layer 433 can include a connection pad, and the connection pad can be electrically connected to the semiconductor device layer of another semiconductor device. The electrically patterned layer 433 below the lower surface 432 of the first region 430 can be produced by a photolithography process as described below.

[0070] The second region 440 of the semiconductor substrate W may include the scribe lane 402 at an upper portion thereof and include the modified region A in the upper portion. In addition, the second region 440 may include the trench T1 or the trench T2 in a lower portion thereof.

[0071] The scribe lanes 402 may prevent electrical shorts from occurring between semiconductor devices of the die of the semiconductor substrate W. Furthermore, as described above, virtual scribe lines L along which the semiconductor substrate W is to be diced into a plurality of semiconductor devices are located in the scribe lanes 402 and are thus defined by the scribe lanes 402 .

[0072] In addition, the modified region A within the second region 440 of the semiconductor substrate W can be formed by using an invisible laser device that focuses laser light at a position within the second region 440 of the semiconductor substrate W. The detailed description of forming the modified region A is substantially the same as that of the reference Figure 2A and Figure 2B The content described is the same.

[0073] The formed modified region A may be used as an alignment mark in a photolithography process of forming the electrical patterned layer 433 below the lower surface 432 of the first region 430 of the semiconductor substrate W. In more detail, the invisible laser device may amorphize the crystal structure within the second region 440 of the semiconductor substrate W, and the density of the amorphous modified region A generated by the invisible laser device may be less than the density of the crystal region within the semiconductor substrate W. Therefore, the modified region A may be highly visible and thus easily aligned with a photomask in a photolithography process of forming the electrical patterned layer 433 below the lower surface 432 of the first region 430.

[0074] In addition, the trench formed in the lower portion of the second region 440 of the semiconductor substrate W may have various shapes. Figure 4B , the trench T1 may have an arched shape, that is, may have an arched profile. When the semiconductor substrate W including the arched trench T1 is cut into individual semiconductor devices (the above-mentioned bare chips), the individual semiconductor devices may have a concave surface defining a curved step in their edges. Figure 4C, the trench T2 may have a quadrilateral (cross-sectional) shape. When the semiconductor substrate W including the quadrilateral trench T2 is cut into individual semiconductor devices, the individual semiconductor devices may have a flat surface defining a straight step in their edges. However, the present inventive concept is not limited to Figure 4B or Figure 4C The arched groove or quadrilateral groove shown.

[0075] Figure 4B and Figure 4C The trenches T1 and T2 shown may be formed by various methods. For example, the trenches may be mechanically formed in the lower portion of the semiconductor substrate W by using a cutting device, or may be chemically formed in the lower portion of the semiconductor substrate W by a chemical reaction (etching process).

[0076] The height h of the trench T1 or the trench T2 formed in the lower portion of the semiconductor substrate W may be about 30% to about 80% of the thickness of the semiconductor substrate W. Preferably, the height h of the trench T1 or the trench T2 may be about 50% to about 70% of the thickness of the semiconductor substrate W. According to an example of the inventive concept, the thickness of the semiconductor substrate W is about 50 μm, and the height h of the trench T1 or the trench T2 is about 25 μm to about 35 μm.

[0077] When the alignment mark is formed of a separate material protruding on the scribe line (as can be conventionally formed by a photolithography process), no groove is formed in the lower portion of the semiconductor substrate, thereby preventing the alignment mark from being damaged by the groove forming process. Or even when such a groove is formed, the height of the groove is again limited to prevent the alignment mark from being damaged. In contrast, according to the present concept, the amorphous modified region A in the second region 440 of the semiconductor substrate W is used as an alignment mark, and therefore, the height h of the trench T1 or the trench T2 formed in the lower portion of the semiconductor substrate W can be relatively large.

[0078] Since the trench T1 or the trench T2 may have a relatively large height h in the lower portion of the scribe lane 402 of the semiconductor substrate W, it is not necessary to cut the dicing tape in the process of cutting the semiconductor substrate W into individual semiconductor devices as will be described below. Therefore, the existing problem that the tape is stretched due to the ductility of the tape and is not cut cleanly can be avoided.

[0079] As described above, the semiconductor substrate W includes the modified region A adjacent to the scribe line 402 as an alignment mark, so the trench T1 or the trench T2 can be formed relatively deep. Therefore, the depth to which the semiconductor substrate W must be cut is minimized. Therefore, the possibility of chipping the cut surface of the semiconductor device by the cutting process is reduced.

[0080] In addition, a step at the edge of the semiconductor device formed by the trench T1 or the trench T2 of the semiconductor substrate W may cause Figure 1 The connection film 170 shown flows at the bottom so that the connection film 170 is accommodated in the edge. Therefore, in the operation of manufacturing the semiconductor package, the formation of a fillet bridge is prevented, which would occur if the connection film 170 contacts the connection film of the adjacent semiconductor package. Therefore, the warping phenomenon of the semiconductor package due to such a fillet bridge can be prevented. In addition, the distance separating the semiconductor devices formed on the semiconductor substrate W can be minimized, thereby improving the yield of the semiconductor package.

[0081] Figure 5 5 is a cross-sectional view of a semiconductor substrate W having a through electrode 501 according to an example of the inventive concept.

[0082] Reference Figure 5 The through electrode 501 may electrically connect the semiconductor device layer 401 formed on the upper surface 431 of the first region 430 of the semiconductor substrate W and the electrical patterned layer 433 formed below the lower surface 432 of the first region 430. The through electrode 501 may include a conductive pillar. Figure 5 Although not shown in the drawings, the conductive pillar may include a barrier film formed on a surface of the pillar and a buried conductive layer inside the barrier film.

[0083] Fig. 6A and Figure 6B is a cross-sectional view of a semiconductor device C according to the inventive concept.

[0084] Reference Fig. 6A and Figure 6B , the semiconductor device C may include a semiconductor substrate 601, a semiconductor device layer 602, an electrical patterning layer 604, and a through electrode 603. In more detail, the semiconductor device C may include a first surface 610 and a second surface 620 opposite to the first surface 610. The first surface 610 of the semiconductor device C may include the semiconductor device layer 602. The semiconductor device layer 602 may have Figure 1 The technical features of the first semiconductor device layer 142 are similar to those of the first semiconductor device layer 142, and therefore, a detailed description of the semiconductor device layer 602 is omitted.

[0085] In addition, the second surface 620 of the semiconductor device C may include an electrically patterned layer 604. The electrically patterned layer 604 formed on the second surface 620 of the semiconductor device C may be electrically connected to the semiconductor device layer 602 formed below the first surface 610 of the semiconductor device C. In addition, the electrically patterned layer 604 may include a connection pad electrically connected to the electrically patterned layer 604, and the connection pad may be electrically connected to the semiconductor device layer of another semiconductor device.

[0086] The through electrode 603 of the semiconductor device C may electrically connect the semiconductor device layer 602 formed below the first surface 610 and the electrical patterned layer 604 formed on the second surface 620. The through electrode 603 may include a conductive column. Fig. 6A and Figure 6B Although not shown in the figure, the through electrode 603 may include a barrier film formed on the surface of the pillar and a buried conductive layer inside the barrier film.

[0087] The semiconductor device C may have a step at the edge D. The edge D may have a Fig. 6A The concave step shown or Figure 6B However, the step in the edge D of the semiconductor device C according to the inventive concept is not limited to such a shape.

[0088] The height h of the step at the edge D of the semiconductor device C may be about 30% to about 80% of the thickness g of the semiconductor device C. Preferably, the height h of the step at the edge D of the semiconductor device C is about 50% to about 70% of the thickness g of the semiconductor device C. According to an example of the inventive concept, the thickness g of the semiconductor device C is about 50 μm, and the height h of the step is about 25 μm to about 35 μm.

[0089] In addition, the area of ​​the first surface 610 of the semiconductor device C is different from the area of ​​the second surface 620 thereof. In particular, the area of ​​the first surface 610 of the semiconductor device C is greater than the area of ​​the second surface 620. The horizontal distance b measured from the top of the second surface 620 to the bottom of the first surface 610 may be about 30 μm to about 100 μm. Preferably, the horizontal distance b is about 50 μm to about 60 μm.

[0090] In addition, still refer to Fig. 6A and Figure 6B , the semiconductor device C may further include a modified region A within the edge D. The modified region A may be exposed to the outside at one side of the semiconductor device C. Methods for forming the modified region A and improvements provided by the modified region A and reference Figure 4B and Figure 4C The description is basically the same.

[0091] As above Figure 4B and Figure 4C As described, the modified region A can be formed as an alignment mark so that the trench depth of the semiconductor device C is relatively large. Therefore, in the cutting process, the cutting depth gh of the semiconductor device C is minimized, thereby reducing the possibility of chipping at the cutting surface of the semiconductor device C.

[0092] Furthermore, due to the grooves of the semiconductor device C, a dicing tape is not required in the semiconductor substrate dicing process, and thus contamination of the semiconductor device C caused by the tape can be reduced.

[0093] Reference Fig. 6A and Figure 6B , the step at the edge D of the semiconductor device C may cause underflow of the connection film located on the second surface 620 of the semiconductor device C. Therefore, in the operation of manufacturing the semiconductor package, the formation of a rounded bridge is prevented, which would occur if the connection film contacts the connection film of the adjacent semiconductor package. Therefore, the warping phenomenon of the semiconductor package due to such a rounded bridge can be prevented. In addition, the distance separating the semiconductor devices formed on the semiconductor substrate W can be minimized, thereby increasing the yield of the semiconductor package.

[0094] Figures 7 to 18 A method of manufacturing a semiconductor package according to the inventive concept is illustrated.

[0095] Reference Figure 7 , first, a semiconductor device is formed at an upper portion of a semiconductor substrate W1 , and a through electrode is formed in the semiconductor substrate W1 .

[0096] The semiconductor substrate W1 may include a plurality of semiconductor devices C separated by scribe lines 701. The semiconductor device C may include a first semiconductor device layer 702 and a first through electrode 703. The first through electrode 703 may extend from a first upper surface 710 of the semiconductor substrate W1 into the semiconductor substrate W1. At least a portion of the first through electrode 703 may have a column form. The first through electrode 703 may include a barrier film formed on the portion in the column form and a buried conductive layer inside the barrier film. In addition, although Figure 7 Not shown in the figure, a through-hole insulating film may be interposed between the semiconductor substrate W1 and the first through-electrode 703 .

[0097] Reference Figure 8 Next, the first connection pad 802 is formed to be electrically connected to the first through electrode 703 of the semiconductor substrate W1. After the first connection pad 802 is formed, the first connection bump 803 may be formed to be electrically connected to the first through electrode 703 through the first connection pad 802. Figure 8 Although not shown in the figure, the first connection bump 803 may include a pillar structure and a solder layer. In order to form the first connection bump 803, a mask pattern having an opening through which a portion of the first connection pad 802 is exposed may be formed on the first semiconductor device layer 702. Subsequently, the pillar structure and the solder layer may be sequentially formed on the portion of the first connection pad 802 exposed by the mask pattern. The pillar structure and the solder layer may be formed by performing an electroplating process.

[0098] Reference Fig. 9 Next, a carrier substrate 910 may be attached to the semiconductor substrate W1. The carrier substrate 910 may include a support substrate 912 and an adhesive material layer 911. The semiconductor substrate W1 may be attached to the carrier substrate 910 so that the first connection bumps 803 face the carrier substrate 910. Therefore, the first connection bumps 803 may be encapsulated by the adhesive material layer 911.

[0099] In addition, a portion of the lower surface 720 of the semiconductor substrate W1 may be removed to expose the first through electrode 703 to the outside. A chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof may be used to expose the first through electrode 703 to the outside.

[0100] Reference Fig.10 , a protective layer 1001 covering the lower surface 720 of the semiconductor substrate W1 may be formed. The protective layer 1001 may be formed, for example, by a spin coating process or a spray coating process. The protective layer 1001 may be made of, for example, an insulating polymer. An insulating polymer film covering the lower surface 720 of the semiconductor substrate W1 and the first through electrode 703 exposed to the outside may be formed to form the protective layer 1001, and then a portion of the insulating polymer film may be removed by an etch-back process to expose the first through electrode 703 to the outside.

[0101] Reference Fig.10 , after the protective layer 1001 has been formed, the first upper connection pad 1002 electrically connected to the first through electrode 703 exposed to the outside through the protective layer 1001 may be formed.

[0102] Fig.11 It is shown that a modified region is formed within a semiconductor substrate W2 including a semiconductor device.

[0103] Reference Fig.11 The semiconductor substrate W2 including the semiconductor device may include a plurality of first regions 1110 and a plurality of second regions 1120. The first region 1110 may include a second semiconductor device layer 1111 on an upper surface thereof, and further, a second through electrode 1112 electrically connected to the second semiconductor device layer 1111 may be formed inside the first region 1110.

[0104] Furthermore, the semiconductor substrate W2 may include a scribe lane 1121 on an upper portion of the second region 1120 .

[0105] The modified region A may be formed in the second region 1120 of the semiconductor substrate W2 by an invisible laser device. In more detail, the invisible laser device may use a lens to focus laser light of a wavelength that can pass through the semiconductor substrate W2 on a point in the second region 1120 of the semiconductor substrate W2. As a result, very high nonlinear multiphoton absorption may occur near the focal point. Due to the nonlinear multiphoton absorption, the crystals in the second region 1120 of the semiconductor substrate W2 may absorb the energy of the light focused inside the semiconductor substrate W2, thereby causing a thermal melting phenomenon, thereby forming a modified region A such as Fig.11 The amorphous modified region A is shown.

[0106] The amorphous modified region A formed in the second region 1120 of the semiconductor substrate W2 may be used as an alignment mark for aligning with a photomask in a photolithography process of forming an electrical patterning layer below the lower surface of the first region 1110 of the semiconductor substrate W2 .

[0107] Fig.12 It is shown that a trench T is formed in a lower portion of the semiconductor substrate W2.

[0108] The trench T may be formed by various methods. For example, the trench T may be mechanically formed in the lower portion of the semiconductor substrate W2 by using a cutting device, or may be chemically formed in the lower portion of the semiconductor substrate W2 by a chemical reaction.

[0109] As reference Fig.11 As described, the modified region A formed in the second region 1120 of the semiconductor substrate W2 is used as an alignment mark, and therefore, there is no need to worry about the alignment mark being damaged in the process of forming the trench T. In addition, according to the present inventive concept, the trench T formed in the lower portion of the second region 1120 of the semiconductor substrate W2 may have a relatively large depth h. In particular, the depth h of the trench T may be about 50% to about 70% of the thickness of the semiconductor substrate W2. According to an example of the present inventive concept, the thickness of the semiconductor substrate W2 is about 50 μm, and the depth h of the trench T is about 25 μm to about 35 μm.

[0110] Since the trench T is formed in the lower portion of the second region 1120 of the semiconductor substrate W2, as shown in FIG. Fig.14A As described, no dicing tape is required in the process of cutting the semiconductor substrate W2 into individual semiconductor devices. Therefore, the existing problem that the dicing tape is stretched due to its ductility and is not cut cleanly can be avoided. In addition, the possibility of chipping of the cut surface of the individual semiconductor devices can be reduced.

[0111] Fig.13 A process of forming an electrically patterned layer 1320 at the lower surface of the semiconductor substrate W2 is shown.

[0112] An electrically patterned layer 1320 may be formed on a surface 1310 corresponding to the second semiconductor device layer 1111 in the first region 1110 of the semiconductor substrate W2 by a photolithography process. For the photolithography process of forming the electrically patterned layer 1320, a photomask 1301 and a focusing lens 1303 may be used. The photomask 1301 may include an alignment mark 1302. The alignment mark 1302 of the photomask 1301 may be aligned with the amorphous modified region A formed in the second region 1120 of the semiconductor substrate W2. Once the alignment is completed, the surface 1310 corresponding to the second semiconductor device layer 1111 in the first region 1110 of the semiconductor substrate W2 may be uniformly coated with a sensitizing (photosensitive) solution. Then, light is selectively emitted on the surface of the sensitizing solution layer by the photomask 1301, and the sensitizing solution is developed to selectively remove the exposed portion or the non-exposed portion of the layer, whereby a patterned layer of the sensitizing solution may be formed on the surface 1310 corresponding to the second semiconductor device layer 1111. The electrical patterned layer 1320 may be finally formed through a process of filling the patterned layer with a conductive material including metal.

[0113] Fig.14A and Fig. 14B A corresponding example of dicing the semiconductor substrate W2 into individual semiconductor devices or “dies” is shown.

[0114] Reference Fig.14A The semiconductor substrate cutting device 1410 can cut the second region 1120 of the semiconductor substrate W2 along the virtual cutting line L in the scribing lane 1121 of the second region 1120 of the semiconductor substrate W2 to separate the semiconductor substrate W2 into individual semiconductor devices. The semiconductor substrate cutting device 1410 can, for example, use a cutting blade or an invisible laser for cutting. However, the inventive concept is not limited to the use of any particular semiconductor substrate cutting device.

[0115] Still refer to Fig.14A , a dicing tape 1401 may be attached to a surface 1310 (i.e., a surface having an electrically patterned layer 1320) corresponding to the second semiconductor device layer 1111 of the semiconductor substrate W2. The dicing tape 1401 may prevent the semiconductor devices cut from the semiconductor substrate W2 from scattering during the cutting process. When the dicing tape 1401 is attached to the semiconductor substrate W2, an air gap may be formed between the dicing tape 1401 and the semiconductor substrate W2 through the trench T in the second region 1120.

[0116] In the case where a semiconductor substrate without a trench T is cut into individual semiconductor devices, the cutting tape may be stretched and plastically deformed by the substrate cutting device. As a result, the cut surface of the semiconductor substrate may be broken. These fragments may contaminate the semiconductor substrate and reduce the yield of semiconductor devices produced from the semiconductor substrate.

[0117] However, in the process of cutting the semiconductor substrate W2 according to the inventive concept, due to the groove T formed in the lower portion of the second region 1120 of the semiconductor substrate W2, the semiconductor substrate cutting device 1410 can cut the semiconductor substrate W2 into individual semiconductor devices without cutting the dicing tape 1401. Therefore, the above-mentioned phenomenon that the dicing tape is stretched and deformed without being cleanly cut, thereby causing the cut semiconductor devices to be contaminated, can be prevented.

[0118] In addition, as described above, the modified area A formed by the invisible laser device in the second area 1120 of the semiconductor substrate W2 is used as an alignment mark, and therefore, the height h of the trench T may be about 50% to about 70% of the thickness of the semiconductor substrate W2. Therefore, the semiconductor substrate cutting device 1410 does not have to cut the thickness of the semiconductor substrate W2 corresponding to the height h of the trench T. Therefore, the cutting depth i to be cut by the semiconductor substrate cutting device 1410 in the second area 1120 of the semiconductor substrate W2 is relatively small. Therefore, the chipping of the semiconductor substrate W2 at its surface where the cut individual semiconductor devices are located can be minimized or prevented.

[0119] Reference Fig. 14B In this example, a dicing tape 1401 is attached to the surface of the second semiconductor device layer 1111 forming the semiconductor substrate W2. The semiconductor substrate W2 may include a first layer X and a second layer Y, the thickness of the first layer X includes the trench T, and the second layer Y does not include the trench T. Fig. 14B As shown, the first layer X may include an electrical patterned layer 1320 , and the second layer Y may include a second semiconductor device layer 1111 .

[0120] The first layer X and the second layer Y of the semiconductor substrate W2 may include materials different from each other. In addition, the first layer X may be weaker than the second layer Y. For example, the material of the first layer X may be a silicon-based material, and the material of the second layer Y may be an epoxy-based material.

[0121] The first layer X in the second region 1120 of the semiconductor substrate W2 has a groove T. Therefore, the semiconductor substrate cutting device 1410 can start cutting the semiconductor substrate W2 from the second layer Y in the second region 1120 without cutting the first layer X in the second region 1120. Therefore, the selection range of the cutting blade of the semiconductor substrate cutting device 1410 can be wide, and the cutting process can be performed quickly. In addition, the semiconductor substrate cutting device 1410 only has to cut through the thickness of the second layer Y in the second region 1120 of the semiconductor substrate W2. Therefore, the chipping phenomenon at the surface of the cut individual semiconductor devices can be minimized or prevented.

[0122] Fig.15An operation of stacking semiconductor devices on the semiconductor substrate W1 and electrically connecting the semiconductor devices to the semiconductor substrate W1 is shown.

[0123] Reference Fig.15 , a second connection pad 1501 and a second connection bump 1502 electrically connected to the second semiconductor device layer 1111 may be formed on the second semiconductor device layer 1111 of each semiconductor device in the plurality of semiconductor devices C1 ′ to be stacked.

[0124] A connection film 1503 may be formed on the first upper connection pad 1002 of the semiconductor substrate W1. The connection film 1503 may be an insulating polymer, and more specifically, the connection film 1503 may be a non-conductive film (NCF).

[0125] The second connection bump 1502 of each semiconductor device in the plurality of semiconductor devices C1′ to be stacked may be arranged to correspond to the first upper connection pad 1002 of the semiconductor substrate W1. The plurality of semiconductor devices C1′ may be stacked on the semiconductor substrate W1 such that the second connection bump 1502 of each semiconductor device in the plurality of semiconductor devices C1′ contacts the first upper connection pad 1002 of the semiconductor substrate W1 to electrically connect the first through electrode 703 to the second through electrode 1112.

[0126] Once the plurality of semiconductor devices C1 ′ have been stacked on the connection film 1503 on the semiconductor substrate W1 , a reflow process or a thermal compression process may be performed. As a result of this process, the second connection bumps 1502 may contact and be electrically connected to the first upper connection pads 1002 .

[0127] Reference Fig.16 , you can refer to it repeatedly Fig.15 The stacking process described above. Therefore, the semiconductor devices C1′, C2′, C3′, and C4′ can be stacked on the semiconductor substrate W1. The connection film 1503 can be located between the stacked semiconductor devices C1′, C2′, C3′, and C4′, and the semiconductor devices C1′, C2′, C3′, and C4′ can be electrically connected through the above process.

[0128] exist Fig.16 In the stacking process shown, the connection film 1503 can be squeezed out of the occupied areas of the stacked semiconductor devices C1′, C2′, C3′ and C4′ by the pressure applied by the stacked semiconductor devices C1′, C2′, C3′ and C4′. In the example shown, the connection film 1503 does not reach the virtual cutting line L. Therefore, in this example, the connection film 1503 cannot be seen from the side of the cut semiconductor package by naked eyes.

[0129] In another example, the connection film 1503 extruded outside the occupied area of ​​the stacked semiconductor devices C1′, C2′, C3′, and C4′ contacts another extruded connection film to form a rounded bridge. The rounded bridge formed by the connection film 1503 can be seen by naked eyes from the side of the cut semiconductor package. The shape and thickness of the connection film 1503 seen from the side surface of the cut semiconductor package can allow inspection of whether the semiconductor devices C1′, C2′, C3′, and C4′ in the semiconductor package are stacked with appropriate intervals therebetween.

[0130] However, if such a rounded bridge of the connection film is formed to a certain thickness, the semiconductor package may be warped in the process of manufacturing the semiconductor package. According to an example of the inventive concept, since the semiconductor devices C1′, C2′, C3′, and C4′ have steps at their edges, underflow of the connection film 1503 may be caused. Therefore, the thickness to which the rounded bridge may be formed due to the connection film 1503 in the semiconductor package may be limited. Therefore, the warping of the semiconductor package may be suppressed.

[0131] although Fig.16 A structure in which four semiconductor devices C1′, C2′, C3′, and C4′ are stacked on each other on the semiconductor substrate W1 is illustratively shown, but the number of semiconductor devices stacked on the semiconductor substrate W1 may vary. In addition, the semiconductor devices C1′, C2′, C3′, and C4′ may be homogeneous semiconductor devices including the same individual elements or heterogeneous semiconductor devices including different individual elements.

[0132] Reference Fig.17 Next, an encapsulation material 1701 covering the semiconductor devices C1′, C2′, C3′, and C4′ stacked on the semiconductor substrate W1 may be formed. The encapsulation material 1701 may be formed to cover the side surfaces of the stacked semiconductor devices C1′, C2′, C3′, and C4′, and to cover the upper surface of the top stacked semiconductor device C4′. In addition, the encapsulation material 1701 may cover the side surfaces of the connection film 1503. According to one example, the encapsulation material 1701 includes an epoxy molding compound (EMC).

[0133] Reference Fig.18 , the scribe line 701 along the semiconductor substrate W1 will be Fig.17 Shown and referenced in Fig.17 The described structure is cut into individual semiconductor packages. The process of cutting the semiconductor package may be performed by a cutting device using a cutting blade or an invisible laser.

[0134] Finally, while the inventive concept has been particularly shown and described with reference to examples thereof, it will be understood that various changes in form and details may be made to these examples without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package, the semiconductor package include: Package substrate; A first semiconductor device is located on the upper surface of the packaging substrate; a second semiconductor device, located on an upper surface of the first semiconductor device; a first connection bump attached to a lower surface of the package substrate; a second connection bump disposed between the package substrate and the first semiconductor device and electrically connected to the package substrate and the first semiconductor device; as well as a third connection bump disposed between the first semiconductor device and the second semiconductor device and electrically connected to the first semiconductor device and the second semiconductor device, wherein a step in the first semiconductor device is defined at an edge of the first semiconductor device, wherein the edge of the first semiconductor device has a modified region, and The density of the modified region of the first semiconductor device is less than the density of the central region of the first semiconductor device.

2. The semiconductor package according to claim 1, in, The package substrate includes a third semiconductor device having a semiconductor substrate and a first through-electrode extending through the semiconductor substrate and electrically connected to the first semiconductor device, and The first semiconductor device includes a second semiconductor substrate and a second through-electrode extending through the second semiconductor substrate and electrically connected to the second semiconductor device.

3. The semiconductor package according to claim 2, in, A height of the step at the edge of the first semiconductor device is 30% to 80% of a maximum thickness of the first semiconductor device.

4. The semiconductor package according to claim 3, in, The edge of the first semiconductor device has a concave curved surface defining the step.

5. The semiconductor package according to claim 3 further comprises a connection film wrapping the first connection bump between the upper surface of the third semiconductor device and the lower surface of the first semiconductor device, and a connection film wrapping the second connection bump between the upper surface of the first semiconductor device and the lower surface of the second semiconductor device.

6. The semiconductor package according to claim 5, in, At least one of the connection films protrudes beyond a combined footprint of the first semiconductor device and the second semiconductor device.

7. The semiconductor package according to claim 6, in, At least one side surface of the connection film forms a portion of a side surface of the semiconductor package.

8. A semiconductor package, the semiconductor package include: a stack of a plurality of vertically spaced components, the plurality of components comprising a lower substrate, an upper semiconductor device, and at least one intermediate semiconductor device disposed between the lower substrate and the upper semiconductor device; an underfill material disposed between the plurality of components and protruding laterally outward from a combined footprint of the upper semiconductor device and at least one intermediate semiconductor device; as well as a molding layer encapsulating each of the at least one intermediate semiconductor device and the underfill material on the lower substrate, wherein each of the at least one intermediate semiconductor devices comprises a semiconductor substrate, The semiconductor substrate has a step constituting an edge of the intermediate semiconductor device and a modified region constituting the edge, The bottom filling material is filled in the step, and The modified region of the semiconductor substrate has a density that is different from a density of material of the semiconductor substrate adjacent to the modified region.

9. The semiconductor package according to claim 8, in, The semiconductor substrate has opposing surfaces, and the intermediate semiconductor device further comprises: a semiconductor device layer located at one surface of the semiconductor substrate and constituting a first surface of the intermediate semiconductor device; an electrically patterned layer located on another surface of the semiconductor substrate and constituting a second surface of the intermediate semiconductor device; and A through electrode vertically extends through the semiconductor substrate and connects the electrical patterning layer and the semiconductor device layer.

10. The semiconductor package according to claim 9, in, The area of ​​the footprint of the first surface of the intermediate semiconductor device is greater than the area of ​​the footprint of the second surface of the intermediate semiconductor device.

11. The semiconductor package according to claim 9, in, The step of the intermediate semiconductor device has a height of 30% to 80% of a thickness of the intermediate semiconductor device measured between the first surface and the second surface of the intermediate semiconductor device.

12. A semiconductor device, the semiconductor device include: a semiconductor substrate having opposing surfaces; A semiconductor device layer, located at one surface of the semiconductor substrate and constituting a first surface of the semiconductor device; as well as an electrically patterned layer, located on the other surface of the semiconductor substrate and constituting the second surface of the semiconductor device, The semiconductor substrate has a step constituting an edge of the semiconductor device. The semiconductor substrate has a modified region constituting the edge of the semiconductor device, and The density of the modified region of the semiconductor substrate is lower than that of the central region of the semiconductor substrate.

13. The semiconductor device according to claim 12, in, The step is defined by a concave curved surface of the semiconductor substrate.

14. The semiconductor device according to claim 12, in, The height of the step is 30% to 80% of the maximum thickness of the semiconductor device.

15. The semiconductor device according to claim 14, further comprising a through electrode, in, The through-electrode electrically connects the semiconductor device layer to the electrical patterning layer.

16. The semiconductor device according to claim 15, in, An area of ​​an occupied region of the first surface of the semiconductor device is larger than an area of ​​an occupied region of the second surface.

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