Integrated circuit device and method for manufacturing the same

Abstract

An integrated circuit device and a method for manufacturing the same are provided. The integrated circuit device comprises: a substrate; a bonding pad located on the substrate; and a through-via structure passing through the substrate and connected to the bonding pad. The through-via structure comprises a conductive plug, a first conductive barrier layer covering the sidewall and lower surface of the conductive plug, and a second conductive barrier layer covering the sidewall of the first conductive barrier layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0084274 filed on Jul. 19, 2018, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present disclosure relate to an integrated circuit device and a method for manufacturing the same, and more particularly, to an integrated circuit device including a through silicon via (TSV) structure and a method for manufacturing the same. Background Art

[0004] With the development of three-dimensional packages in which a plurality of semiconductor chips are mounted in a single package, a reliable connection structure may be required to form a vertical electrical connection using a through silicon via (TSV) structure extending through a substrate or a die. Summary of the invention

[0005] According to an exemplary embodiment of the present invention, an integrated circuit device may include: a substrate; a landing pad located on the substrate; and a through-via structure passing through the substrate. The through-via structure may be connected to the landing pad. The through-via structure includes a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.

[0006] According to an exemplary embodiment of the present invention, an integrated circuit device may include: a substrate; an interlayer insulating layer located on the substrate; a bonding pad located on the interlayer insulating layer; and a through-via structure. The interlayer insulating layer and the substrate may define a through-via that penetrates the substrate and the interlayer insulating layer. The through-via structure may be located in the through-via and may be connected to the bonding pad. The through-via structure may include a conductive plug, a first conductive barrier layer on a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer on a sidewall of the first conductive barrier layer.

[0007] According to an exemplary embodiment of the present inventive concept, an integrated circuit device may include: a substrate; a bonding pad located on the substrate; and a through-via structure passing through the substrate and connected to the bonding pad. The through-via structure may include a conductive plug, a first conductive barrier layer on a sidewall and a lower surface of the conductive plug, a second conductive barrier layer on a sidewall of the first conductive barrier layer, and a via insulating layer on a sidewall of the second conductive barrier layer and spaced apart from the bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a top view illustrating an integrated circuit device according to an exemplary embodiment.

[0009] Figure 2 It is shown Figure 1 A cross-sectional view of a portion of the main cell region MCR and a portion of the through via region TVR.

[0010] Figure 3 yes Figure 2 A magnified view of a portion of the CX2.

[0011] Figure 4 is a cross-sectional view illustrating an integrated circuit device according to an exemplary embodiment.

[0012] Figure 5 is a cross-sectional view illustrating an integrated circuit device according to an exemplary embodiment.

[0013] Figure 6 is a cross-sectional view illustrating an integrated circuit device according to an exemplary embodiment.

[0014] Figure 7 is a cross-sectional view illustrating an integrated circuit device according to an exemplary embodiment.

[0015] Figure 8 , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15 and Fig.16 are cross-sectional views illustrating operations in a method of fabricating an integrated circuit device according to example embodiments.

[0016] Fig.17 is a cross-sectional view illustrating a main configuration of a semiconductor package according to an exemplary embodiment. DETAILED DESCRIPTION

[0017] Various exemplary embodiments will now be described more fully with reference to the accompanying drawings in which some exemplary embodiments are shown. The inventive concept may, however, be embodied in many alternate forms and should not be construed as limited to only the exemplary embodiments set forth herein.

[0018] Figure 1 is a top view showing an integrated circuit device 100 according to an exemplary embodiment. Figure 2 It is shown Figure 1A cross-sectional view of a portion of the main cell region MCR and a portion of the through via region TVR. Figure 3 yes Figure 2 A magnified view of a portion of the CX2.

[0019] Reference Figures 1 to 3 , the integrated circuit device 100 may include a substrate 110 having a plurality of main cell regions MCR and through via regions TVR.

[0020] As an example, a plurality of memory cells may be disposed in each of a plurality of main cell regions MCR. A first peripheral circuit region PR1 may be disposed on one side of each main cell region MCR, and a second peripheral circuit region PR2 may be disposed on the other side of each main cell region MCR. For example, a row decoder may be disposed in the first peripheral circuit region PR1 to be connected to the memory cells disposed in each main cell region MCR, and a column decoder may be disposed in the second peripheral circuit region PR2 to be connected to the memory cells disposed in each main cell region MCR. In some embodiments, other driving devices such as control logic circuits, sense amplifiers, and / or page buffers for driving memory cells may be disposed in the first peripheral circuit region PR1 and the second peripheral circuit region PR2.

[0021] A plurality of through via structures 150 may be disposed in the through via region TVR and pass through the substrate 110. A signal may be received from or transmitted to an external terminal through the through via structure 150.

[0022] In some embodiments, you can modify Figure 1 1 and 2. For example, the main cell region MCR may be disposed in a central region of the substrate 110, and the first and second peripheral regions PR1 and PR2 and the through via region TVR may be disposed to surround the main cell region MCR in a top view.

[0023] The substrate 110 may have a first surface 110F1 and a second surface 110F2 opposite to each other. The substrate 110 may include a semiconductor substrate including silicon, germanium, silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 110 may have a silicon-on-insulator (SOI) structure. For example, the substrate 110 may include a buried oxide (BOX) layer. In some embodiments, the substrate 110 may include various isolation structures such as a shallow trench isolation (STI) structure.

[0024] The interlayer insulating layer 120 may be disposed on the first surface 110F1 of the substrate 110. The interlayer insulating layer 120 may cover a plurality of semiconductor devices 122 and a wiring structure 124. The plurality of semiconductor devices 122 may include a memory device (such as a DRAM, a PRAM, a flash memory, or a RERAM), a metal oxide semiconductor field effect transistor, a system large-scale integrated circuit (LSI), an image sensor (such as a CMOS image sensor (CIS)), a micro-electromechanical system (MEMS), an active device, and / or a passive device. The semiconductor device 122 may be electrically connected to the wiring structure 124. A structure including the interlayer insulating layer 120 and the semiconductor devices 122 and the wiring structure 124 covered by the interlayer insulating layer 120 may be referred to as a front-end-of-line (FEOL) structure.

[0025] The intermetallic insulating layer 130 may be disposed on the interlayer insulating layer 120. The intermetallic insulating layer 130 may cover a multilayer wiring structure 132 disposed on the interlayer insulating layer 120. The multilayer wiring structure 132 may include a plurality of wiring layers 132W and a plurality of wiring paths 132P. In some embodiments, the intermetallic insulating layer 130 may have a stacked structure of a plurality of insulating layers, and each of the plurality of insulating layers may cover a portion of the plurality of wiring layers 132W and a portion of the plurality of wiring paths 132P. A structure including the intermetallic insulating layer 130 and the multilayer wiring structure 132 covered by the intermetallic insulating layer 130 may be referred to as a back-end-of-line (BEOL) structure.

[0026] The bonding pad 134 may be disposed on the interlayer insulating layer 120. At least a portion of the bonding pad 134 may be covered by the metal interlayer insulating layer 130. The bonding pad 134 may be a portion of the multilayer wiring structure 132 disposed in the through via region TVR.

[0027] Reference Figure 3, the bonding pad 134 may include a bonding pad metal layer 134W and a bonding pad barrier layer 134B. The bonding pad barrier layer 134B may cover the upper surface 134WU and the sidewall of the bonding pad metal layer 134W. Here, among the relative surfaces of the bonding pad barrier layer 134B extending in the horizontal direction (e.g., the X direction and the Y direction), the surface of the bonding pad barrier layer 134B closer to the interlayer insulating layer 120 or the substrate 110 may refer to the upper surface 134BU of the bonding pad barrier layer 134B. In addition, the surface of the bonding pad metal layer 134W extending in the horizontal direction (for example, the X direction and the Y direction) and facing the interlayer insulating layer 120 (or facing the substrate 110) may refer to the upper surface 134WU of the bonding pad metal layer 134W, and the other surface of the bonding pad metal layer 134W opposite to the upper surface 134WU of the bonding pad metal layer 134W may refer to the lower surface of the bonding pad metal layer 134W.

[0028] In some embodiments, the bonding pad metal layer 134W may include Ni, Cu, Al, Au, W, or a combination thereof, but is not limited thereto. The bonding pad barrier layer 134B may include at least one of W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB, but is not limited thereto.

[0029] The first pad 142 may be disposed on the intermetallic insulating layer 130. A passivation layer 144 including an opening 144H exposing at least a portion of an upper surface of the first pad 142 may be disposed on the intermetallic insulating layer 130. The first pad 142 may include Al, Ni, Cu, or a combination thereof. The passivation layer 144 may include polyimide and / or silicon nitride.

[0030] The bump structure 146 may be disposed on the first pad 142. The bump structure 146 may include a pillar 146P and a solder layer 146S sequentially stacked on the first pad 142. For example, the pillar 146P may include Cu, Ni, or an alloy thereof, and the solder layer 146S may include Sn, Ag, Pb, Au, Cu, B, or an alloy thereof.

[0031] Reference Figure 2 , the first pad 142 and the bump structure 146 may be disposed in the through via region TVR. In some embodiments, the first pad 142 and the bump structure 146 may optionally be further disposed in the main cell region MCR.

[0032] The through-via structure 150 may pass through the substrate 110 and the interlayer insulating layer 120 to connect to the bonding pad 134. For example, when the substrate 110 is a silicon substrate, the through-via structure 150 may be a through-silicon via (TSV) structure. The through-via structure 150 may include a conductive plug 152, a first conductive barrier layer 154, a second conductive barrier layer 156, and a via insulating layer 158.

[0033] The through via structure 150 may be disposed in a through via hole 150H passing through the substrate 110 and the interlayer insulating layer 120. The through via hole 150H may extend from the second surface 110F2 of the substrate 110 to the first surface 110F1 of the substrate 110, and penetrate the interlayer insulating layer 120. A via insulating layer 158, a second conductive barrier layer 156, a first conductive barrier layer 154, and a conductive plug 152 may be sequentially disposed on an inner sidewall of the through via hole 150H.

[0034] The conductive plug 152 may extend through the substrate 110 and the interlayer insulating layer 120. A lower surface 152L of the conductive plug 152 may be located at a lower plane than a lower surface of the interlayer insulating layer 120 (e.g., the lower surface 152L of the conductive plug 152 may be farther from the first surface 110F1 of the substrate 110 than the lower surface of the interlayer insulating layer 120).

[0035] In some embodiments, the conductive plug 152 may include Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRE, CuW, W, or a W alloy, but is not limited thereto. For example, the conductive plug 152 may include at least one of Al, Au, Be, Bi, Co, Cu, Hf, In, Mn, Mo, Ni, Pb, Pd, Pt, Rh, Re, Ru, Ta, Te, Ti, W, Zn, and Zr, and include a stack of one or more layers.

[0036] The first conductive barrier layer 154 may cover the sidewalls and the lower surface 152L of the conductive plug 152. In some embodiments, the first conductive barrier layer 154 may include at least one of W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB. The thickness t11 of the first conductive barrier layer 154 may be about 500 to 1000 mm.

[0037] The second conductive barrier layer 156 may cover the sidewalls of the first conductive barrier layer 154. The second conductive barrier layer 156 may not cover the lower surface and lower sidewalls of the first conductive barrier layer 154. The lower surface and lower sidewalls of the first conductive barrier layer 154 may contact the bonding pad metal layer 134W. In some embodiments, the second conductive barrier layer 156 may include at least one of W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB. The second conductive barrier layer 156 may include the same material as the first conductive barrier layer 154, but is not limited thereto. The thickness t12 of the second conductive barrier layer 156 may be about 500 to 1000 mm.

[0038] The via insulating layer 158 may cover the sidewalls of the second conductive barrier layer 156. The via insulating layer 158 may serve as an insulating spacer to limit and / or prevent the conductive materials (e.g., the conductive plug 152 and the first and second conductive barrier layers 154 and 156) included in the through via structure 150 from directly contacting the substrate 110.

[0039] The via insulating layer 158 may include oxide, nitride, carbon, polymer, or a combination thereof. The via insulating layer 158 may be formed by, for example, a chemical vapor deposition (CVD) process. The via insulating layer 158 may have a thickness of about 500 to 1000 Å. For example, the via insulating layer 158 may include silicon oxide. In some embodiments, the via insulating layer 158 may include a material different from that of the interlayer insulating layer 120 .

[0040] The second pad 162 may be disposed on the second surface 110F2 of the substrate 110 to be connected to the through via structure 150. The second pad 162 may include Al, Ni, Cu, or a combination thereof.

[0041] Reference Figure 3 , the via insulating layer 158 or the second conductive barrier layer 156 may not contact the bonding pad metal layer 134W (or may be spaced apart from the bonding pad metal layer 134W), but the first conductive barrier layer 154 may contact the bonding pad metal layer 134W.

[0042] The lower surface of the first conductive barrier layer 154 may be positioned at a first vertical distance VD1 from the first surface 110F1 of the substrate 110 along the vertical direction (e.g., the Z direction). The lower surface of the second conductive barrier layer 156 may be positioned at a second vertical distance VD2 from the first surface 110F1 of the substrate 110 along the vertical direction (e.g., the Z direction) that is smaller than the first vertical distance VD1.

[0043] The step portion 150HS may be formed at the bottom of the through via hole 150H. For example, the step portion 150HS may be defined by a portion of the interlayer insulating layer 120, by the lowermost surface of the via insulating layer 158 and the sidewall of the second conductive barrier layer 156 adjacent to the lowermost surface of the via insulating layer 158, or by the lowermost surface of the second conductive barrier layer 156 and the sidewall of the first conductive barrier layer 154 adjacent to the lowermost surface of the second conductive barrier layer 156. This may be a structure obtained by a plurality of etching processes of downwardly expanding the through via hole 150H to sequentially form the via insulating layer 158, the second conductive barrier layer 156, and the first conductive barrier layer 154.

[0044] In some embodiments, in order to form the through-via structure 150, after first forming the bonding pad 134 and the metal interlayer insulating layer 130 on the first surface 110F1 of the substrate 110, a process of forming the through-via structure 150 may be performed (e.g., a via last method may be performed). For example, after a plurality of semiconductor devices 122, a wiring structure 124, and an interlayer insulating layer 120 are formed on the first surface 110F1 of the substrate 110, the bonding pad 134, the multi-layer wiring structure 132, and the metal interlayer insulating layer 130 may be formed on the interlayer insulating layer 120, and then a through-via 150H penetrating the substrate 110 and a portion of the interlayer insulating layer 120 (e.g., extending from the second surface 110F2 of the substrate 110 into the interlayer insulating layer 120) may be formed. A via insulating layer 158 may be formed on the inner surface of the through-hole 150H, and then a portion of the via insulating layer 158 located on the bottom of the through-hole 150H and the interlayer insulating layer 120 may be etched to expose the upper surface 134BU of the bonding pad barrier layer 134B, so that the bottom of the through-hole 150H may be expanded in the depth direction of the through-hole 150H. Thereafter, a second conductive barrier layer 156 may be formed on the inner surface of the through-hole 150H having the via insulating layer 158, and then a portion of the second conductive barrier layer 156 located on the bottom of the through-hole 150H and the bonding pad barrier layer 134B may be etched to expose the upper surface 134WU of the bonding pad metal layer 134W, so that the bottom of the through-hole 150H may be further expanded in the depth direction of the through-hole 150H. Next, a first conductive barrier layer 154 may be formed on the inner surface of the through-hole 150H having the via insulating layer 158 and the second conductive barrier layer 156.

[0045] In the through-via structure according to the comparative example, the second conductive barrier layer 156 may be omitted, and the outer sidewall of the first conductive barrier layer 154 may be covered by the via insulating layer 158 and the interlayer insulating layer 120. In this case, when etching the bonding pad metal layer 134W located on the bottom of the through-via 150H, the metal etched from the bonding pad metal layer 134W may remain in the through-via 150H without being removed, so that the metal may be easily re-deposited on the inner sidewall of the through-via 150H (e.g., on the interlayer insulating layer 120 and / or the via insulating layer 158). Therefore, the interlayer insulating layer 120 and / or the via insulating layer 158 may be contaminated by the metal, resulting in that the insulating properties of the interlayer insulating layer 120 and / or the via insulating layer 158 may not be sufficiently ensured.

[0046] However, in the through-via structure 150 according to the exemplary embodiment, the second conductive barrier layer 156 may be formed in the inner surface of the through-via 150H to conformally cover the via insulating layer 158 and the interlayer insulating layer 120, and then an etching process for exposing the upper surface 134WU of the bonding pad metal layer 134W may be performed at the bottom of the through-via 150H. When etching the bonding pad metal layer 134W located at the bottom of the through-via 150H, the second conductive barrier layer 156 may be used as a protective layer covering the surface of the via insulating layer 158 and the surface of the interlayer insulating layer 120. Therefore, the metal etched from the bonding pad metal layer 134W may no longer be deposited on the interlayer insulating layer 120 and / or the through-via insulating layer 158, so that the interlayer insulating layer 120 and / or the through-via insulating layer 158 may be limited and / or prevented from being contaminated by metal. Therefore, the reliability of the integrated circuit device 100 may be improved.

[0047] Figure 4 is a cross-sectional view showing an integrated circuit device 100A according to an exemplary embodiment, and corresponds to Figure 2 A magnified view of a portion of the CX2.

[0048] Reference Figure 4 , the through via 150HA may have an enlarged portion 150EA at a boundary region between the substrate 110 and the interlayer insulating layer 120. The enlarged portion 150EA may be defined as a space between a circular sidewall of the substrate 110 and a circular sidewall of the interlayer insulating layer 120. The width of the enlarged portion 150EA of the through via 150HA may be greater than the width of the bottom surface of the through via 150HA.

[0049] The through-via structure 150A may be disposed in the through-via 150HA. Specifically, the through-via insulating layer 158A may be conformally disposed to correspond to the sidewall profile of the enlarged portion 150EA located on the inner surface of the through-via 150HA, and the second conductive barrier layer 156A and the first conductive barrier layer 154A may be sequentially conformally disposed to correspond to the sidewall profile of the enlarged portion 150EA located on the inner surface of the through-via 150HA having the through-via insulating layer 158A. The conductive plug 152A may include a protruding portion 152AP corresponding to the sidewall profile of the enlarged portion 150EA.

[0050] In some embodiments, during the process of forming the through-hole 150HA, a portion of the substrate 110 and a portion of the interlayer insulating layer 120 exposed on the inner surface of the through-hole 150HA at the boundary area between the substrate 110 and the interlayer insulating layer 120 can be etched at a relatively high etching rate to form an enlarged portion 150EA.

[0051] In some embodiments, the sidewalls of the substrate 110 and the interlayer insulating layer 120 in the expanded portion 150EA are not limited to rounded surfaces. For example, the sidewalls of the substrate 110 and the interlayer insulating layer 120 in the expanded portion 150EA may have inclined surfaces inclined at a desired (and / or optionally predetermined) angle.

[0052] Figure 5 is a cross-sectional view showing an integrated circuit device 100B according to an exemplary embodiment, and corresponds to Figure 2 A magnified view of a portion of the CX2.

[0053] Reference Figure 5 , the through via 150HB may have an enlarged portion 150EB at a boundary region between the substrate 110 and the interlayer insulating layer 120. The enlarged portion 150EB may be defined as a space extending in a horizontal direction (e.g., X direction or Y direction) between a circular sidewall of the substrate 110 and an upper surface of the interlayer insulating layer 120. The width of the enlarged portion 150EB of the through via 150HB may be greater than the width of the bottom surface of the through via 150HB.

[0054] The through-via structure 150B may be disposed in the through-via 150HB. Specifically, the through-via insulating layer 158B may be conformally disposed to correspond to the sidewall profile of the enlarged portion 150EB on the inner surface of the through-via 150HB, and the second conductive barrier layer 156B and the first conductive barrier layer 154B may be sequentially conformally disposed to correspond to the sidewall profile of the enlarged portion 150EB on the inner surface of the through-via 150HB having the through-via insulating layer 158B. The conductive plug 152B may include a protruding portion 152BP corresponding to the sidewall profile of the enlarged portion 150EB.

[0055] In some embodiments, the through via 150HB may include a sidewall having a desired (and / or optionally predetermined) slope and a bottom having a rounded profile. For example, the upper width W11 of the conductive plug 152B (the width of a portion of the conductive plug 152B located in the same plane as a portion of the substrate 110 away from the first surface 110F1 of the substrate 110) is greater than the lower width W12 (for example, the width of another portion of the conductive plug 152B located in the same plane as the lower surface of the interlayer insulating layer 120).

[0056] In some embodiments, during the formation of the through via 150HB, the etching rate of the substrate 110 may be different from the etching rate of the interlayer insulating layer 120. Therefore, while the interlayer insulating layer 120 may be etched at the bottom of the through via 150HB, the first surface 110F1 of the substrate 110 in contact with the interlayer insulating layer 120 may be etched at a relatively high etching rate, thereby forming the expansion portion 150EB having an asymmetric shape.

[0057] Figure 6 is a cross-sectional view showing an integrated circuit device 100C according to an exemplary embodiment, and corresponds to Figure 2 A magnified view of a portion of the CX2.

[0058] Reference Figure 6 The through-via structure 150C may include a conductive plug 152, a first conductive barrier layer 154C, a second conductive barrier layer 156C, and a via insulating layer 158. The thickness t12C of the second conductive barrier layer 156C may be less than the thickness t11C of the first conductive barrier layer 154C. For example, the thickness t11C of the first conductive barrier layer 154C may be about 500 to 1000 mm. The thickness t12C of the second conductive barrier layer 156C may be about 500 to 1000 mm.

[0059] As an example, the second conductive barrier layer 156C may be formed on the inner surface of the through-hole 150H to conformally cover the via insulating layer 158 and the interlayer insulating layer 120, and then an etching process may be performed on the bottom of the through-hole 150H to expose the upper surface 134WU of the bonding pad metal layer 134W. When etching the bonding pad metal layer 134W at the bottom of the through-hole 150H, the metal etched from the bonding pad metal layer 134W may no longer be deposited on the interlayer insulating layer 120 and / or the through-hole insulating layer 158. Therefore, the interlayer insulating layer 120 and / or the through-hole insulating layer 158 may be restricted and / or prevented from being contaminated by metal. In addition, since the thickness t12C of the second conductive barrier layer 156C is relatively small, the volume of the conductive plug 152 filling the through-hole 150H may be relatively increased, so that the resistance of the conductive plug 152 may be reduced. Therefore, the reliability of the integrated circuit device 100C may be improved.

[0060] Figure 7 is a cross-sectional view showing an integrated circuit device 100D according to an exemplary embodiment, and corresponds to Figure 2 A magnified view of a portion of the CX2.

[0061] Reference Figure 7 , the through-via structure 150D may further include a metal island 159 between the first conductive barrier layer 154 and the second conductive barrier layer 156. The metal island 159 may include particles formed of a metal, or may be a material layer formed by agglomerating particles formed of a metal. In some embodiments, the metal islands 159 may be arranged spaced apart from each other to form a discontinuous layer. In some embodiments, the metal island 159 may be a continuous material layer extending continuously in a vertical direction (e.g., a Z direction) between the first conductive barrier layer 154 and the second conductive barrier layer 156.

[0062] In some embodiments, the metal islands 159 may include the same metal as the bonding pad metal layer 134W. For example, the metal islands 159 may include Ni, Cu, Al, Au, W, or a combination thereof, but are not limited thereto.

[0063] As an example, the second conductive barrier layer 156 may be formed on the inner surface of the through-hole 150H to conformally cover the via insulating layer 158 and the interlayer insulating layer 120, and then an etching process may be performed on the bottom of the through-hole 150H to expose the upper surface 134WU of the bonding pad metal layer 134W. When etching the bonding pad metal layer 134W at the bottom of the through-hole 150H, the second conductive barrier layer 156 may be used as a protective layer covering the surface of the interlayer insulating layer 120 and the surface of the through-hole insulating layer 158, and the metal etched from the bonding pad metal layer 134W may be re-deposited on or adhered to the second conductive barrier layer 156 to form a metal island 159. Thereafter, the first conductive barrier layer 154 may be formed on the second conductive barrier layer 156 to cover the metal island 159.

[0064] According to an exemplary embodiment, in the process of etching the bonding pad metal layer 134W located at the bottom of the through via 150H, even if the metal etched from the bonding pad metal layer 134W is redeposited on the inner surface of the through via 150H, the second conductive barrier layer 156 may be used as a protective layer covering the surface of the interlayer insulating layer 120 and the surface of the via insulating layer 158. The metal islands 159 may be redeposited on the second conductive barrier layer 156 instead of the interlayer insulating layer 120 and the via insulating layer 158. Therefore, metal contamination of the interlayer insulating layer 120 and / or the via insulating layer 158 may be limited and / or prevented, so that the reliability of the integrated circuit device 100D may be improved.

[0065] Figure 8 , Fig. 9 , Fig.10 , Fig.11A , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15 and Fig.16 100D are cross-sectional views illustrating operations in a method of fabricating an integrated circuit device 100D according to example embodiments. Figure 8 , Fig. 9 , Fig.10 , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15 and Fig.16 It is shown Figure 1 A cross-sectional view of a portion of the main cell region MCR and a portion of the through via region TVR. Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B They are Fig.11A , Fig. 12A , Fig.13A and Fig.14A A magnified view of a portion of the CX2.

[0066] Reference Figure 8 , a plurality of semiconductor devices 122 and a wiring structure 124 may be formed on the first surface 110F1 of the substrate 110 . An interlayer insulating layer 120 may be formed on the substrate 110 to cover the plurality of semiconductor devices 122 and the wiring structure 124 .

[0067] The bonding pad 134 and the multilayer wiring structure 132 may be formed on the interlayer insulating layer 120 , and then the metal interlayer insulating layer 130 may be formed on the interlayer insulating layer 120 to cover the bonding pad 134 and the multilayer wiring structure 132 .

[0068] In some embodiments, the process of forming the bonding pad 134 and the multilayer wiring structure 132 may include a single damascene process or a dual damascene process. For example, the intermetallic insulating layer 130 may be formed on the interlayer insulating layer 120, and then the intermetallic insulating layer 130 may be patterned to form a wiring hole in the main cell region MCR and a bonding pad hole in the through-path region TVR. Thereafter, the bonding pad 134 may be formed in the bonding pad hole, and the wiring layer 132W may be formed in the wiring hole. For example, the formation of the bonding pad 134 may include: sequentially forming a first layer for forming a bonding pad barrier layer 134B and a second layer for forming a bonding pad metal layer 134W, and planarizing the first layer and the second layer until the intermetallic insulating layer 130 is exposed to leave the bonding pad barrier layer 134B and the bonding pad metal layer 134W in the bonding pad hole.

[0069] In some embodiments, the bonding pad barrier layer 134B may be formed of W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB, and may be formed by a CVD process or a physical vapor deposition (PVD) process. The bonding pad metal layer 134W may be formed of Ni, Cu, Al, W, or a combination thereof, and may be formed by an electroplating process. For example, the formation of the bonding pad metal layer 134W may include forming a seed layer including copper (Cu) on the bonding pad barrier layer 134B, and forming a Cu layer from the seed layer by an electroplating process.

[0070] Thereafter, a process similar to the process of forming the bonding pad 134 may be repeatedly performed on the bonding pad 134 and the wiring layer 132W to form the multilayer wiring structure 132 including the wiring path 132P and the wiring layer 132W.

[0071] A conductive layer may be formed on the intermetallic insulating layer 130, and then the conductive layer may be patterned to form the first pad 142. The first pad 142 may be formed of Al, Ni, Cu, or a combination thereof.

[0072] A passivation layer 144 exposing a portion of the first pad 142 may be formed on the intermetallic insulating layer 130. The passivation layer 144 may be formed of polyimide and / or silicon nitride.

[0073] The bump structure 146 may be formed on the first pad 142 exposed by the passivation layer 144 to be electrically connected to the first pad 142. The bump structure 146 may include a column 146P and a solder layer 146S. The column 146P may be formed of Cu, Ni, or an alloy thereof, and may be formed by an electroplating process. The solder layer 146S may be formed of Sn, Ag, Pb, Au, Cu, B, or a combination thereof, and may be formed by sequentially performing an electroplating process and a reflow process.

[0074] Reference Fig. 9 , the support substrate 172 may be bonded to the bump structure 146 and the passivation layer 144. The support substrate 172 may be bonded to the bump structure 146 and the passivation layer 144 through the adhesive layer 174. A grinding process may be performed on the second surface 110F2 of the substrate 110 to remove a portion of the substrate 110 of a desired (and / or optionally predetermined) thickness from the second surface 110F2 of the substrate 110.

[0075] A mask pattern may be formed on the second surface 110F2 of the substrate 110 , and then the substrate 110 may be etched using the mask pattern as an etching mask to form the through vias 150H. The through vias 150H may penetrate the substrate 110 and may extend into the interlayer insulating layer 120 .

[0076] In some embodiments, the through via 150H may be formed by an anisotropic etching process or a laser drilling process. Since the through via 150H does not completely penetrate the interlayer insulating layer 120 , the upper surface of the bonding pad 134 is not exposed by the through via 150H and may be covered by the interlayer insulating layer 120 .

[0077] The through hole 150H may be formed to have various widths, depths, or shapes. Fig. 9 As shown, the through via 150H may be formed to have a sidewall perpendicular to the first surface 110F1 of the substrate 110. In some embodiments, when forming Figure 5In the process of forming the through-hole 150HB as shown, the sidewall of the through-hole 150HB may be formed to have a desired (and / or optionally predetermined) slope, so that the upper width of the through-hole 150HB may be greater than the lower width of the through-hole 150HB. Figure 5 An integrated circuit device 100B is described.

[0078] In addition, in the formation Figure 5 In the process of forming the through hole 150HB shown in FIG. 1 , when the etching conditions of the substrate 110 and the etching conditions of the interlayer insulating layer 120 are controlled differently, a portion of the substrate 110 located at the boundary region between the substrate 110 and the interlayer insulating layer 120 may be etched at a relatively high etching rate to form the expanded portion 150EB. In this case, the reference Figure 5 An integrated circuit device 100B is described.

[0079] In some embodiments, in forming Figure 4 In the process of forming the through-hole 150HA shown in FIG. 1 , a portion of the substrate 110 and a portion of the interlayer insulating layer 120 at the boundary region between the substrate 110 and the interlayer insulating layer 120 and exposed on the inner surface of the through-hole 150HA may be etched at a relatively high etching rate to form the enlarged portion 150EA. In this case, the reference Figure 4 An integrated circuit device 100A is described.

[0080] After forming the through via hole 150H, the mask pattern may be removed.

[0081] Reference Fig.10 The via insulating layer 158 may be formed on the second surface 110F2 of the substrate 110 to cover the inner surface of the through-hole 150H. The via insulating layer 158 may be formed of oxide, nitride, carbide, polymer, or a combination thereof. The via insulating layer 158 may be formed by, for example, a CVD process. The via insulating layer 158 may have a thickness of about 500 to 1000 mm. For example, the via insulating layer 158 may be formed of a silicon oxide layer formed by a CVD process below atmospheric pressure.

[0082] Reference Fig.11A and Fig. 11B , the via insulating layer 158 and the interlayer insulating layer 120 at the bottom of the through via 150H may be etched to expand the through via 150H downward. At this time, the bonding pad barrier layer 134B may be used as an etching stop layer, so that the upper surface 134WU of the bonding pad metal layer 134W covered by the bonding pad barrier layer 134B is not exposed by the through via 150H.

[0083] Reference Fig. 12A and Fig. 12B , the second conductive barrier layer 156 may be formed on the inner surface of the through-hole 150H having the via insulating layer 158. The second conductive barrier layer 156 may be formed of WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB, and may be formed by a PVD process, an electroplating process, or an electroless plating process. The second conductive barrier layer 156 may have a thickness of about 500 to 1000 mm. The thickness (see e.g. Figure 3 t12).

[0084] The second conductive barrier layer 156 may be conformally formed to cover the entire surface of the via insulating layer 158 and the interlayer insulating layer 120 exposed on the inner surface of the through via 150H. The second conductive barrier layer 156 may be conformally formed on the interlayer insulating layer 120 and the pad barrier layer 134B at the bottom of the through via 150H.

[0085] Reference Fig.13A and Fig. 13B , the second conductive barrier layer 156 and the bonding pad barrier layer 134B located at the bottom of the through-hole 150H may be etched to expose the upper surface 134WU of the bonding pad metal layer 134W, thereby further expanding the through-hole 150H downward. At this time, the bonding pad metal layer 134W may be over-etched so that a portion of the upper portion of the bonding pad metal layer 134W may be recessed. Therefore, the upper surface 134WU of the portion of the bonding pad metal layer 134W exposed at the bottom of the through-hole 150H may be located at a plane lower than the upper surface 134WU of another portion of the bonding pad metal layer 134W that is not exposed by the through-hole 150H.

[0086] In the etching process for enlarging the through-hole 150H, the etching particles of the bonding pad metal layer 134W may not be completely removed and may be redeposited on the inner surface of the through-hole 150H. By the redeposition of the etching particles, a metal island 159 may be formed on the sidewall of the second conductive barrier layer 156. For example, when the bonding pad metal layer 134W includes Cu, the metal island 159 may include particles containing Cu, or may be a material layer formed by the aggregation of particles including Cu. In some embodiments, the metal islands 159 may be arranged at intervals from each other to form a discontinuous layer. In some embodiments, the metal island 159 may be a continuous material layer that extends continuously in a vertical direction (e.g., Z direction).

[0087] In the method of forming the through via structure according to the comparative example, the second conductive barrier layer 156 may be omitted, and the bonding pad metal layer 134W may be etched in a state where the via insulating layer 158 and the interlayer insulating layer 120 are exposed on the inner surface of the through via hole 150H. In this case, metal particles etched away in the etching process may be redeposited on the sidewall of the through via hole 150H (e.g., on the interlayer insulating layer 120 and / or the via insulating layer 158). Therefore, the interlayer insulating layer 120 and / or the via insulating layer 158 may be contaminated with metal, resulting in that the insulating properties of the interlayer insulating layer 120 and / or the via insulating layer 158 may not be sufficiently ensured.

[0088] However, according to an exemplary embodiment, in the etching process of the bonding pad metal layer 134W, the second conductive barrier layer 156 may cover the surface of the via insulating layer 158 and the surface of the interlayer insulating layer 120, so the via insulating layer 158 and the interlayer insulating layer 120 are not exposed on the inner surface of the through via hole 150H. Therefore, the metal particles removed in the etching process are not deposited on the interlayer insulating layer 120 and / or the via insulating layer 158, so that the interlayer insulating layer 120 and / or the via insulating layer 158 can be restricted and / or prevented from being contaminated by metal.

[0089] Reference Fig.14A and Fig. 14B , a first conductive barrier layer 154 may be formed on the inner surface of the through-hole 150H having the via insulating layer 158 and the second conductive barrier layer 156. The first conductive barrier layer 154 may be formed of W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB, and may be formed by a PVD process, an electroplating process, or an electroless plating process. The first conductive barrier layer 154 may have a thickness of about 500 to 1000 mm. The thickness (see e.g. Figure 3 t11).

[0090] The first conductive barrier layer 154 may be formed to cover the second conductive barrier layer 156 and the metal islands 159. Thus, the metal islands 159 may be disposed between the first conductive barrier layer 154 and the second conductive barrier layer 156.

[0091] Reference Fig.15, the conductive plug 152 may be formed on the first conductive barrier layer 154 to fill the through-hole 150H. The conductive plug 152 may be formed of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W or W alloy, and may be formed by an electroplating process. For example, in order to form the conductive plug 152, a metal seed layer may be formed on the surface of the first conductive barrier layer 154, and then a metal layer may be formed from the metal seed layer by an electroplating process, so that the conductive plug 152 may be formed on the first conductive barrier layer 154 to fill the through-hole 150H. The metal seed layer may be formed of Cu, Cu alloy, Co, Ni, Ru, Co / Cu or Ru / Cu, and may be formed by a PVD process. The electroplating process may be performed at a temperature of about 10 to 65°C. For example, the electroplating process may be performed at room temperature. In some embodiments, the resulting structure including the conductive plug 152 may be annealed at a temperature of about 150 to 450°C.

[0092] Reference Fig.16 , the resulting structure including the conductive plug 152 may be polished by a chemical mechanical polishing (CMP) process to expose the second surface 110F2 of the substrate 110, so that the conductive plug 152, the first conductive barrier layer 154, the second conductive barrier layer 156, and the via insulating layer 158 may remain only in the through via hole 150H. Therefore, a through via structure 150D may be formed in the through via hole 150H.

[0093] Refer again Figure 2 , a conductive layer may be formed on the second surface 110F2 of the substrate 110, and then the conductive layer may be patterned to form a second pad 162. The second pad 162 may be electrically connected to the through via structure 150D.

[0094] According to the above-described method of manufacturing the integrated circuit device 100D, after the via insulating layer 158 and the second conductive barrier layer 156 are first formed on the inner surface of the through-hole 150H, an etching process for exposing the upper surface 134WU of the bonding pad metal layer 134W located at the bottom of the through-hole 150H may be performed. Therefore, even if the metal particles etched from the bonding pad metal layer 134W during the etching process are redeposited on the sidewall of the through-hole 150H, the metal island 159 including the metal particles may be disposed between the first conductive barrier layer 154 and the second conductive barrier layer 156. Therefore, the metal particles may be restricted and / or prevented from contacting the via insulating layer 158. When the second conductive barrier layer 156 is omitted, the possibility of the via insulating layer 158 being contaminated by the metal particles generated during the etching process of forming the through-hole 150H may be reduced. Therefore, the reliability of the integrated circuit device 100D may be improved.

[0095] Fig.17 is a cross-sectional view illustrating a main configuration of a semiconductor package 200 according to an exemplary embodiment.

[0096] Reference Fig.17 The semiconductor package 200 may include a plurality of semiconductor chips 220 sequentially stacked on a package substrate 210. The control chip 230 may be disposed on the plurality of semiconductor chips 220 to be connected to the plurality of semiconductor chips 220. The stacked structure of the plurality of semiconductor chips 220 and the control chip 230 may be sealed on the package substrate 210 with a sealant 240 (e.g., a thermosetting resin). Fig.17 As shown, six semiconductor chips 220 are stacked vertically, but the number and stacking direction of the semiconductor chips 220 are not limited thereto. For example, more than six or less than six semiconductor chips 220 may be stacked. In some embodiments, a plurality of semiconductor chips 220 may be arranged in a horizontal direction. In some embodiments, a plurality of semiconductor chips 220 may be arranged in a horizontal direction and in a vertical direction. In some embodiments, the control chip 230 may be omitted.

[0097] The package substrate 210 may include a flexible printed circuit board, a rigid printed circuit board, or a combination thereof. The package substrate 210 may include a substrate internal wiring 212 and a connection terminal 214. The connection terminal 214 may be formed on a first surface of the package substrate 210. The solder ball 216 may be formed on a second surface of the package substrate 210. The connection terminal 214 may be electrically connected to the solder ball 216 through the substrate internal wiring 212. In some embodiments, the solder ball 216 may be replaced with a conductive bump or a lead grid array (LGA).

[0098] The plurality of semiconductor chips 220 and the control chip 230 may include through silicon via (TSV) units 222 and 232. The TSV units 222 and 232 may be electrically connected to the connection terminals 214 of the package substrate 210 through connection portions 250 such as bumps. In some embodiments, the TSV unit 232 in the control chip 230 may be omitted.

[0099] At least one of the semiconductor chip 220 and the control chip 230 may include a reference Figures 1 to 7 At least one of the integrated circuit devices 100, 100A, 100B, 100C, and 100D described. The TSV cells 222 and 232 may include reference Figures 1 to 7 At least one of the through-passage structures 150, 150A, 150B, 150C, and 150D described. The connecting portion 250 may include reference Figure 2 The first pad 142 and the reference Figure 2 The second pad 162 connected to the TSV units 222 and 232 through the first pad 142 is depicted.

[0100] Each of the plurality of semiconductor chips 220 may include a system LSI, a flash memory, a DRAM, an SRAM, an EEPROM, a PRAM, an MRAM, or a ReRAM. The control chip 230 may include a logic circuit such as a serializer / deserializer circuit.

[0101] While certain inventive concepts have been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising: substrate; a bonding pad on the substrate; as well as a through via structure passing through the substrate and connected to the bonding pad, The through-via structure includes a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, a second conductive barrier layer covering a sidewall of the first conductive barrier layer, and a via insulating layer covering a sidewall of the second conductive barrier layer and spaced apart from the bonding pad, and The second conductive barrier layer contacts the bonding pad.

2. The integrated circuit device according to claim 1, wherein: The bonding pad further comprises a bonding pad metal layer and a bonding pad barrier layer, The bonding pad metal layer is located on the substrate, The bonding pad barrier layer is located on the upper surface and sidewalls of the bonding pad metal layer, A lower surface of the first conductive barrier layer contacts the bonding pad metal layer, and A lower surface of the second conductive barrier layer contacts the bonding pad barrier layer.

3. The integrated circuit device according to claim 2, wherein: The second conductive barrier layer is spaced apart from the bonding pad metal layer.

4. The integrated circuit device according to claim 2, wherein: The lower surface of the first conductive barrier layer is located at a first distance from the first surface of the substrate, The lower surface of the second conductive barrier layer is located at a second distance from the first surface of the substrate, and The first distance is greater than the second distance.

5. The integrated circuit device according to claim 2, wherein: The through via structure further includes a metal island located between the first conductive barrier layer and the second conductive barrier layer, and The metal islands include the same metal as the bond pad metal layer.

6. The integrated circuit device according to claim 5, wherein: The via insulating layer is spaced apart from the metal island.

7. The integrated circuit device according to claim 1, further comprising: an interlayer insulating layer located on the substrate; as well as a metal interlayer insulating layer located on the interlayer insulating layer and covering the bonding pad, wherein: A portion of the side wall of the through via structure is covered by the interlayer insulating layer, and A lower surface of the through via structure contacts the bonding pad.

8. The integrated circuit device according to claim 7, wherein: The substrate and the interlayer insulating layer define a through via that penetrates the substrate and the interlayer insulating layer, The through-passage structure is located in the through-hole, and The interlayer insulating layer defines a step portion at a bottom of the through via.

9. The integrated circuit device according to claim 8, wherein: The via insulating layer, the second conductive barrier layer, the first conductive barrier layer, and the conductive plug are sequentially stacked on a sidewall of the through via.

10. The integrated circuit device according to claim 9, wherein: The stepped portion of the through via is defined by a lower surface of the via insulating layer and a sidewall of the second conductive barrier layer.

11. The integrated circuit device according to claim 8, wherein: The through via includes an enlarged portion at a boundary region between the substrate and the interlayer insulating layer.

12. The integrated circuit device of claim 1, further comprising: an interlayer insulating layer located on the substrate, the interlayer insulating layer and the substrate defining a through-hole penetrating the substrate and the interlayer insulating layer, wherein: The bonding pad is located on the interlayer insulating layer, and The through-via structure is located in the through-through hole.

13. The integrated circuit device according to claim 12, wherein: The lower surface of the first conductive barrier layer is located at a first distance from the first surface of the substrate, The lower surface of the second conductive barrier layer is located at a second distance from the first surface of the substrate, and The first distance is greater than the second distance.

14. The integrated circuit device according to claim 12, wherein: The through via structure further includes a metal island located between the first conductive barrier layer and the second conductive barrier layer, and The metal islands include the same metal as the bonding pads.

15. The integrated circuit device according to claim 14, wherein: The via insulating layer is spaced apart from the metal island.

16. An integrated circuit device comprising: substrate; an interlayer insulating layer located on the substrate, the interlayer insulating layer and the substrate defining a through-hole penetrating the substrate and the interlayer insulating layer, a bonding pad located on the interlayer insulating layer; as well as a through via structure located in the through via and connected to the bonding pad, The through via structure includes a conductive plug, a first conductive barrier layer on a sidewall and a lower surface of the conductive plug, a second conductive barrier layer on a sidewall of the first conductive barrier layer, and a via insulating layer on a sidewall of the second conductive barrier layer and spaced apart from the bonding pad, and The second conductive barrier layer contacts the bonding pad.

17. The integrated circuit device according to claim 16, wherein: The bonding pad includes a bonding pad metal layer and a bonding pad barrier layer, The bond pad metal layer is located on the substrate; and The bonding pad barrier layer is located on the upper surface and sidewalls of the bonding pad metal layer.

18. The integrated circuit device according to claim 17, wherein: A lower surface of the first conductive barrier layer contacts the bonding pad metal layer, and A lower surface of the second conductive barrier layer contacts the bonding pad barrier layer.

19. The integrated circuit device of claim 16, further comprising: a metal interlayer insulating layer located on the interlayer insulating layer and covering the bonding pad, wherein: The interlayer insulating layer defines a step portion at a bottom of the through via.

20. A method of manufacturing an integrated circuit device, the method comprising: forming a bonding pad on the first surface of the substrate, the bonding pad comprising a bonding pad metal layer and a bonding pad barrier layer; forming a through via in the substrate, the through via passing through the substrate from the second surface of the substrate to the first surface of the substrate, and the through via exposing the bonding pad barrier layer; forming a second conductive barrier layer at least on a sidewall of the through via to contact the bonding pad; enlarging the through via to expose the bonding pad metal layer; as well as A first conductive barrier layer is formed at least on the sidewalls of the through via.

21. The method according to claim 20, further comprising: A conductive plug is formed on the first conductive barrier layer, wherein: The conductive plug fills the through via.

22. The method according to claim 20, wherein: Forming the bonding pad includes: forming an interlayer insulating layer on the first surface of the substrate; forming a metal interlayer insulating layer on the interlayer insulating layer; forming a bonding pad hole in the intermetallic insulating layer; and The bonding pad is formed in the bonding pad hole.

23. The method according to claim 22, wherein: The forming of the through via further comprises: forming the through via to penetrate the interlayer insulating layer, and During the enlargement of the through via hole, the interlayer insulating layer is not exposed on the sidewall of the through via hole.

24. The method of claim 22, further comprising: Before forming the second conductive barrier layer, a via insulating layer is formed on the sidewall of the through via.

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