Semiconductor device and electronic control device

Abstract

The present disclosure relates to a semiconductor device and an electronic control device. A semiconductor device and an electronic control device capable of cutting off a reverse current from a load to a power supply are provided. A power transistor QN1 is provided between a positive power supply terminal Pi2(+) and a load driving terminal Po2(+), and has a source and a back gate coupled to the positive power supply terminal Pi2(+). A power transistor QN2 is provided in series with the power transistor QN1, and a source and a back gate of the power transistor QN2 are coupled to the load driving terminal Po2(+). A booster CP1a charges the gate of the power transistor QN1. When the potential of the negative power supply terminal Pi2(−) is higher than the potential of the positive power supply terminal Pi2(+), a gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2018-136573, filed on July 20, 2018 (including the specification, drawings, and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices and electronic control devices, and for example, relates to a technique for cutting off reverse current from a load to a power supply. Background Art

[0004] In Japanese Unexamined Patent Application Publication No. 2007-82374 (hereinafter "Patent Document 1"), a power supply reverse connection protection circuit is disclosed, which sequentially includes an n-channel FET [1] and an n-channel FET [2] on the positive electrode side in a power supply path from the positive electrode terminal of a battery to a power supply target. The drains of FET [1] and FET [2] are commonly connected, and the gate voltages of FET [1] and FET [2] are generated by a charge pump circuit, and a working power supply is provided to the charge pump circuit from the drain side.

[0005] In Japanese Unexamined Patent Application Publication No. 2003-37933 (hereinafter "Patent Document 2"), a protection device is disclosed, which includes a p-channel FET, and the drain of the p-channel FET is on the power supply terminal side in a power supply path from the power supply terminal on the positive electrode side to the power supply input terminal of an electronic device. The gate of the p-channel FET is connected to the power supply terminal on the negative electrode side via a resistor, and is also connected to the source via a capacitor. Summary of the Invention

[0006] For example, in an electronic control device (electronic control unit) for a vehicle or the like, a relay composed of two series-connected transistors can be provided to control the excitation between a power supply and a load. One of the two series-connected transistors is required to disconnect the reverse conduction from the load to the power supply. On the other hand, it is desirable that the two series-connected transistors are n-channel type transistors as shown in Patent Document 1 to reduce the size and loss of the relay. However, in the configuration shown in Patent Document 1, there is a concern that the excitation in the opposite direction cannot be cut off.

[0007] In view of the above circumstances, the embodiments described below are made, and other problems and novel features will be clear from the description and drawings of this specification.

[0008] A semiconductor device according to an embodiment includes a positive power terminal and a negative power terminal coupled to a power supply, and a load driving terminal coupled to a load to control excitation between the power supply and the load in response to a control input. The semiconductor device includes an n-channel first power transistor and a second power transistor, a first boost circuit, and a first gate discharge circuit. The first power transistor is provided between the positive power terminal and the load driving terminal, and has a source and a back gate coupled to the positive power terminal side and a drain coupled to the load driving terminal side. The second power transistor is provided in series with the first power transistor between the positive power terminal and the load driving terminal, and the source and the back gate are coupled to the load driving terminal side, and the drain is coupled to the positive power terminal side. The first boost circuit charges the gate of the first power transistor. When the potential of the negative power terminal is higher than the potential of the positive power terminal, the first gate discharge circuit discharges the gate charge of the first power transistor to the source.

[0009] According to the above embodiment, the supply of reverse current from the load to the power supply can be cut off. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram showing a configuration example of a vehicle to which an electronic control device according to a first embodiment of the present invention is applied;

[0011] Figure 2 is a schematic diagram showing an exemplary configuration of a main part of the electronic control device;

[0012] Figure 3 is a block diagram showing a schematic configuration example of a semiconductor device (relay device) according to the first embodiment;

[0013] Figure 4 is showing Figure 3 a circuit diagram showing a detailed configuration example of a main part in the semiconductor device (relay device) in;

[0014] Figure 5 is showing Figure 4 a cross-sectional view showing a configuration example of each transistor in the boosting circuit in;

[0015] Figure 6 is showing Figure 3 a schematic diagram showing an outline of the semiconductor device (relay device) in;

[0016] Figure 7 is a block diagram showing a schematic configuration example of a semiconductor device (relay device) according to the second embodiment;

[0017] Figure 8 is showing Figure 7 a circuit diagram showing a schematic structure of a negative potential detection circuit in the semiconductor device (relay device) in;

[0018] Figure 9 is a circuit diagram showing Figure 7 a detailed configuration example of the main part in a semiconductor device (relay device) in

[0019] Figure 10 is a circuit diagram showing a configuration example when Figure 9 the circuit in

[0020] Figure 11 is a comparison Figure 7 between the relay device in Figure 10 and a relay device according to

[0021] Figure 12 is a waveform diagram showing an example of a prerequisite problem in a semiconductor device (relay device) according to the third embodiment;

[0022] Figure 13 is a block diagram showing a schematic configuration example of a semiconductor device (relay device) according to the third embodiment;

[0023] Figure 14 is a circuit diagram showing Figure 13 a detailed configuration example of the main part in a semiconductor device (relay device) in

[0024] Figure 15 is a circuit diagram showing Figure 13 a detailed configuration example of a delay circuit in

[0025] Figure 16 is a circuit diagram showing Figure 14 an example of the operation of the circuit in

[0026] Figure 17 is a schematic diagram showing different configurations of a relay device as a first comparative example of the present invention ((a), (b), and (c)). DETAILED DESCRIPTION

[0027] In the following embodiments, for convenience, the description will be divided into multiple parts or embodiments. However, unless otherwise specified, these parts and embodiments are not independent of each other, and one part and embodiment are related to some or all of the modified examples, details, supplementary descriptions, etc. of another part and embodiment. In the following embodiments, the number of elements, etc. (including the number of elements, numerical values, quantities, ranges, etc.) is not limited to a specific number, but can be greater than or less than a specific number, except in cases where the number is specifically stated or is clearly limited to a specific number in principle.

[0028] In addition, in the following embodiments, needless to say, constituent elements (including element steps, etc.) are not necessarily essential, unless they are specifically specified and unless they are considered to be clearly essential in principle. Similarly, in the following embodiments, when it comes to the shape, positional relationship, etc. of components, etc., it is assumed that the shape, etc. is substantially close to or similar to the shape, etc., except in cases where they are specifically described and in cases where they are considered to be obvious in principle. The same applies to the above numerical values and ranges.

[0029] In addition, although a MOSFET (Metal Oxide Semiconductor Field Effect Transistor (referred to as a MOS transistor) is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) in the embodiment, a non-oxide film is not excluded as the gate insulating film. In this embodiment, a p-channel MOSFET is referred to as a pMOS transistor, and an n-channel MOSFET is referred to as an nMOS transistor.

[0030] In all the drawings used to explain the embodiments, the same components are denoted by the same reference numerals in principle, and repeated descriptions thereof are omitted.

[0031] First Embodiment

[0032] Figure 1 is a schematic diagram showing an exemplary configuration of a vehicle to which an electronic control device according to this first embodiment is applied. Figure 1 The vehicle (e.g., a motor vehicle) VCL shown includes a battery BAT, a fuse box FSU, an electronic control device (specifically, a relay box) ECU, a body control module BCM, and a plurality of loads LD[1],..., LD[k],..., LD[n]. The fuse box FSU is used to transmit the power of the battery BAT to the electronic control device ECU and protect them from high current.

[0033] The loads LD[1] to LD[n] are various electrical components for an automobile and correspond to, for example, a DC motor, a lamp, a heater, various inductive loads, various capacitive loads, etc. The body control module BCM controls various loads, here LD[k],..., LD[n]. The electronic control device (relay box) ECU includes a plurality of relays (switches), and supplies the power of the battery BAT transmitted through the fuse box FSU to various loads (here LD[1],...) and the body control module BCM through the relays. That is, the electronic control device ECU controls the excitation between the battery BAT and the loads.

[0034] Here, it is desired that the electronic control unit ECU has low losses with respect to supplying the power of the battery BAT to various loads. In addition, it is desirable that the electronic control unit ECU is compact. Since miniaturization alleviates the restrictions on the mounting position of the relay box, for example, the routing efficiency of the wiring harness can be improved. The routing efficiency of the wiring harness contributes to reducing the weight, cost, losses, etc. of the vehicle.

[0035] Figure 2 is a schematic diagram showing Figure 1 an exemplary configuration of the main part of the electronic control unit in Figure 2 The electronic control unit ECU shown includes a microcontroller MCU, a relay device RLY, a power regulator VREG, and an external resistor Re mounted on a printed circuit board. The electronic control unit ECU supplies the high-potential side battery power (also referred to as the battery power potential) VB from the battery BAT via the positive electrode side battery terminal Pi1(+). The electronic control unit ECU supplies the low-potential side battery power (also referred to as the ground power potential) GND from the battery BAT via the negative electrode side battery terminal Pi1(-). When the ground power potential GND is 0V, the battery power potential VB is typically 12V or the like.

[0036] The power regulator VREG generates a power supply (e.g., 5V) for the microcontroller MCU from the battery power VB. As is well known, the microcontroller MCU includes a memory for storing various programs and data, a processor for executing the programs stored in the memory, various analog peripheral circuits, and various digital peripheral circuits. The device RLY controls the excitation between the battery BAT and the load LD in response to a control input signal IN from the MCU. Specifically, the relay device RLY controls the excitation from the battery BAT to the load LD to conduct when the control input signal IN is asserted and to disconnect when the control input signal IN is negated.

[0037] In addition, the relay device RLY includes a diagnostic circuit for performing self-diagnosis. The relay device RLY outputs a result notification signal PF, which is the result of the diagnosis of the diagnostic circuit, to the microcontroller MCU. In this embodiment, when the diagnosis result is abnormal, the relay device RLY notifies the microcontroller MCU of the abnormality by controlling the potential level of the result notification signal PF to a predetermined level via the external resistor Re. The microcontroller MCU identifies the abnormality by converting the potential level of the result notification signal PF into a digital signal by an analog-to-digital conversion circuit.

[0038] The load LD is coupled to the positive load driving terminal Po1(+) and the negative load driving terminal Po1(-) of the electronic control unit ECU. The output potential VO from the relay device RLY is applied to the load driving terminal Po1(+), and the ground power potential GND is applied to the load driving terminal Po1(-) and the battery terminal Pi1(-). The electronic control unit ECU is not actually limited to one relay device RLY, but includes a plurality of relay devices RLY.

[0039] Figure 17 (a), 17(b), and 17(c) are schematic diagrams showing different configuration examples of the relay device as a first comparative example. In Figure 2 it, for example, when the load LD is a DC motor or the like, if the battery BAT is erroneously reversely connected, reverse rotation (i.e., a failure) occurs due to the reverse excitation. Therefore, it is necessary for the relay device RLY to cut off such reverse excitation.

[0040] Figure 17 The relay device RLY'a shown in (a) includes a mechanical switch (mechanical relay) MSW for exciting the load LD. Since the mechanical switch MSW is mechanically opened when it is OFF, the reverse current supply can be cut off when the battery BAT is reversely connected. However, when using the mechanical switch MSW, it is difficult to miniaturize the mechanical switch MSW, so the installation position of the relay device RLY'a may be restricted. In addition, since the mechanical switch MSW has a contact life, the installation position of the relay device RLY'a may be restricted due to the need for maintenance.

[0041] Figure 17 The relay device RLY'b shown in (b) includes a diode Dr and an n-channel power transistor (e.g., MOSFET) QN2 coupled in series, and the series circuit excites the load LD. The back gate and source of the power transistor QN2 are coupled to the load LD, and the on / off of the power transistor QN2 is controlled by a driver DV receiving a control input signal IN. The power transistor QN2 includes a parasitic diode Dn2 between the source (back gate) and the drain, and the parasitic diode QN2 has a cathode on the drain side (anode on the source side). Therefore, for example, when the battery BAT is reversely connected, even if the battery BAT is in the cut-off state, the power transistor QN2 is reversely excited through the parasitic diode Dn2.

[0042] Therefore, a diode Dr with the power transistor QN2 as the cathode is provided. When the battery BAT is reversely connected, the diode Dr can cut off the reverse current unless it breaks down. As described above, by using the semiconductor element Dr and the semiconductor element QN2, the size of the relay device RLY'b can be reduced compared with the case of using the mechanical switch MSW. However, when using the diode Dr, when a forward current (i.e., the current from the battery BAT to the load LD) is provided, a loss accompanied by a forward voltage occurs, so there is still a problem from the viewpoint of reducing losses.

[0043] In Figure 17 the relay device RLY'c shown in (c), a p-channel power transistor (e.g., MOSFET) QP1 is provided instead of Figure 17 the diode Dr shown in (c). The power transistor QP1 has a parasitic diode Dp1, the source of the parasitic diode Dp1 is coupled to the power transistor QN2 side and the cathode of the parasitic diode Dp1 is the power transistor QN2 side. When the gate of the power transistor QP1 is coupled to the negative battery terminal Pi1(-) and the battery BAT is connected in sequence, the power transistor QP1 is turned on. On the other hand, when the battery BAT is reversely connected, the power transistor QP1 is turned off, and the parasitic diode Dp1 of the power transistor BAT is also reversely biased, thus cutting off the reverse current source.

[0044] As described above, by using the p-channel power transistor QP1 instead of the diode Dr, the problem of the forward voltage as described in Figure 17 (b) can be solved. However, when using the p-channel type, the on-resistance in the same area increases compared with the case of using the n-channel type. As a result, it is disadvantageous in terms of miniaturization or low loss compared with the case of using the n-channel type. When using the p-channel type, since the gate-source voltage of the power transistor QP1 is determined by the battery power supply potential VB, when the battery power supply potential VB is low, the on-resistance of the power transistor QP1 may increase.

[0045] Figure 3 is a block diagram showing a schematic configuration of a semiconductor device (relay device) according to the first embodiment. Figure 3 The semiconductor device (relay device) RLYa shown is an intelligent power device (IPD) composed of a single semiconductor package and is applied to Figure 2 the relay device RLY shown. The relay device RLYa includes a positive power supply terminal Pi2(+) and a negative power supply terminal Pi2(-) coupled to the power supply, a positive load drive terminal Po2(+) coupled to the load LD, and a control input terminal Pi3 input with a control input signal IN. The other end of the load LD is coupled to the negative load drive terminal Po2(-).

[0046] The positive power supply terminal Pi2(+) is coupled to a power supply (power supply potential) [1a] VD1a, and the negative power supply terminal Pi2(-) is coupled to a power supply (power supply potential) [3] VD3. The negative-side load drive terminal Po2(-) is coupled to a power supply (power supply potential) [2] VD2. As Figure 2 shown, when the battery BAT is coupled to the positive power supply terminal Pi2(+) and the negative power supply terminal Pi2(-), the power supply potential [1a] VD1a becomes the battery power supply potential VB, and the power supply potential [3] VD3 becomes the ground power supply potential GND. The power supply potential [2] VD2 is also the ground power supply potential GND. The power supply [3] VD3 serves as a ground power supply for control, and the power supply [2] VD2 serves as a ground power supply for power supply.

[0047] The relay device RLYa includes an input buffer IBF, a level shifter LS, a control circuit CTLa, boost circuits CP1a and CP2, a reverse current prevention circuit RCF, gate discharge circuits DCG1a and DCG2, and power transistors QN1 and QN2. When the reverse current prevention circuit RCF is "VD1a > VD3" (i.e., the battery BAT is forward-connected), the circuit RCF conducts the power supply [la] VD1a and the power supply [1b] VD1b, and when the circuit RCF is "VD1a < VD3" (i.e., the battery BAT is reverse-connected), the reverse current prevention circuit RCF cuts off the power supply [1a] VD1a and the power supply [1b] VD1b. The power supply (power supply potential) [1b] VD1b is a high-potential internal power supply (internal power supply potential).

[0048] The power transistors QN1 and QN2 are, for example, n-channel MOSFETs. The power transistor QN1 is provided between the positive power supply terminal Pi2(+) and the positive load drive terminal Po2(+), and its source and back gate are coupled to the positive power supply terminal Pi2(+) side and its drain is coupled to the load drive terminal Po2(+) side. The power transistor QN2 is provided in series with the power transistor QN1 between the positive power supply terminal Pi2(+) and the positive load drive terminal Po2(+), and has a source and back gate (+) coupled to the load drive terminal Po2(+) side, and a drain coupled to the positive power supply terminal Pi2(+) side. The output potential VO corresponding to the on / off states of the power transistors QN1 and QN2 is applied to the positive load drive terminal Po2(+).

[0049] The input buffer IBF receives a control input signal IN from the control input terminal Pi3 and outputs the control input signal IN to the control circuit CTLa via the level shifter LS. The level shifter LS converts the control input signal IN that varies by a predetermined amplitude when the ground power supply potential GND is set to "L" level into a signal that varies by a predetermined amplitude when the power supply potential [1b]VD1b is set to "H" level. The control circuit CTLa operates with the power supply (power supply potential) [4]VD4 as a reference, and the control circuit operates using the power supply [1b]VD1b. The power supply [4]VD4 is an internal ground power supply IGND and is generated, for example, by reducing the power supply [1b]VD1b by a predetermined potential. For example, when the power supply potential [1b]VD1b is 12V, the power supply potential [4]VD4 is 6V, etc. The power supply [4]VD4 is a variable power supply and is short-circuited to the power supply [1b]VD1b during standby to save power.

[0050] In response to the control input signal IN, the control circuit CTLa outputs an enable signal S_EN1 to the boost circuit CP1a and outputs an enable signal S_EN2 to the boost circuit CP2. Specifically, for example, when the control input signal IN is made valid, the control circuit CTLa makes both the enable signals S_EN1 and S_EN2 valid, and when the control input signal IN is made invalid, the control circuit CTLa invalidates both the enable signals S_EN1 and S_EN2.

[0051] The boost circuits CP1a and CP2 operate with the power supply (power supply potential) [5]VD5 as a reference and use the power supply [1b]VD1b for operation. The power supply [5]VD5 is an internal ground power supply IGND, and its generation and control method are the same as those of the power supply [4]VD4. The boost circuit CP1a generates a boosted potential (specifically, a power supply potential higher than the power supply potential [1a]VD1a) in response to the validity of the enable signal S_EN1 to turn on the power transistor QN1, and charges the gate of the power transistor QN1 with the boosted potential. Similarly, the boost circuit CP2 generates a boosted potential in response to the validity of the enable signal S_EN2 to turn on the power transistor QN2, and charges the gate of the power transistor QN2 with the boosted potential.

[0052] When the potential of the negative power supply terminal Pi2(-) is higher than the potential of the positive power supply terminal Pi2(+) (i.e., when the battery BAT is reversely connected), the gate discharge circuit DCG1a discharges the gate charge of the power transistor QN1 to the source). On the other hand, different from the gate discharge circuit DCG1a, the gate discharge circuit DCG2 discharges the gate charge of the power transistor QN2 to the source in response to the invalidity of the enable signal S_EN2.

[0053] Figure 4 is shown Figure 3Circuit diagram of a detailed configuration example of the main part in a semiconductor device (relay device), showing the main part of the relay device (first embodiment). Figure 5 shows Figure 4 Cross-sectional view of an example of the structure of a transistor in a booster. Figure 4 shows around Figure 3 The detailed configuration of the anti-backflow circuit RCF, boost circuit CP1a, and gate discharge circuit DCG1a in. The anti-backflow circuit RCF includes an anti-backflow diode Dc and a pMOS transistor MP1 coupled in parallel between the power supply [1a] VD1a and the power supply [1b] VD1b.

[0054] Here, when the battery BAT is reversely connected, current can flow backward from the power supply [3] VD3 to the power supply [1b] VD1b via the forward-biased ESD protection diode De1, and current can flow backward from the power supply [1b] VD1b to the power supply [1a] VD1a. Therefore, the anti-backflow diode Dc prevents current from flowing back from the power supply [1b] VD1b to the power supply [1a] VD1a. However, in the anti-backflow diode Dc, a forward voltage drop occurs when the battery BAT is forward connected. Therefore, the gates of the pMOS transistors MP1 are coupled to the power supply [3] VD3 so that they conduct when the battery BAT is connected in sequence, and the power supply potential [1b] VD1b and the power supply potential [1a] VD1a are controlled to have the same potential. When the battery BAT is reversely connected, the pMOS transistor MP1 is cut off, and the parasitic diode Dp3 of the battery BAT is also reversely biased.

[0055] For example, in a vehicle-mounted system of a 12V system as Figure 1 shown, since the rated value of the reverse voltage is usually -16V, the breakdown voltage of the reverse current prevention diode Dc can be 16V or higher and is designed to be, for example, 20V or the like. If only the reverse voltage is considered, the breakdown voltage of the pMOS transistor MP1 can be greater than or equal to the breakdown voltage of the diode Dc to prevent backflow, but considering the dump surge when the battery BAT is forward connected, etc., it is desirable that the diode Dc be designed to be greater than or equal to 50V.

[0056] The boost circuit (charge pump circuit) CP1a includes a pMOS transistor MP2 and a resistor R2 serially coupled between the power supply [1b] VD1b and the load driving terminal Po2(+), and nMOS transistors MN1 to MN3 and capacitors C1 to C3 that serve as the main body of the boost circuit. The clock signal CK (inverted clock signal CKB) from an oscillation circuit (not shown) is applied to one end of each of the capacitors C1 to C3. The gate discharge circuit DCG1a includes a resistor R1 for discharging the gate charge of the power transistor QN1 to the source, and a protection diode D2 for protecting the gate of the power transistor QN1.

[0057] In such a configuration, first, it is assumed that the battery BAT is connected forward and the control input signal IN is made valid. In this case, in response to the validity of the control input signal IN, the enable signal S_EN1 is also made valid. The pMOS transistor MP2 conducts in response to the valid level of the enable signal S_EN1 and supplies the power supply potential [1b] VD1b to the back gates of the nMOS transistors MN1 to MN3.

[0058] Each of the nMOS transistors MN1 to MN3 is formed on an n-type semiconductor substrate SUB, as Figure 5 shown. A p-type well PW is formed on the main surface of the semiconductor substrate SUB. In the p-type well PW, an n-type source diffusion layer DFs and a drain diffusion layer DFd that serve as a source (S) and a drain (D), and a p-type feed diffusion layer DFb that serves as a back gate (BG) are formed. A gate electrode GE that serves as a gate (G) is provided above the source diffusion layer DFs and the drain diffusion layer DFd, with a gate insulating film interposed therebetween.

[0059] In such a configuration, there is an npn-type parasitic bipolar transistor BT, and the npn-type parasitic bipolar transistor BT uses the source diffusion layer DFs and the drain diffusion layer DFd as an emitter, the p-type well PW as a base, and the semiconductor substrate SUB as a collector. The power supply potential [1b] VD1b is supplied to the semiconductor substrate SUB at a specific position (not shown). As described above, when the power supply potential [1b] VD1b is supplied to the back gate BG via the pMOS transistor MP2, the parasitic bipolar transistor BT conducts.

[0060] When the parasitic bipolar transistor BT conducts, the parasitic bipolar transistor BT performs a charging operation on the Figure 4 capacitors C1 to C3 by causing a charging current to flow through the source diffusion layer DFs and the drain diffusion layer DFd, and additionally, performs an initial charge on the gate of the power transistor QN1. In this case, Figure 4The booster CP1a applies the clock signal CK (inverted clock signal CKB) to one end of each of the capacitors C1 to C3 to sequentially pump the capacitors C1 to C3, thereby generating a predetermined boosted potential.

[0061] On the other hand, in parallel with the gate charging current flowing to the gate of the power transistor QN1 by the charge pumping operation of the booster circuit CP1a, the resistor R1 in the gate discharge circuit DCG1a allows the gate discharge current to flow. Here, the resistor R1 is set to a high resistance value such that the above-mentioned gate discharge current is sufficiently smaller than the gate charging current. As a result, the boosted potential is applied to the gate of the power transistor QN1, and the power transistor QN1 is turned on.

[0062] Next, it is assumed that the control input signal IN is invalid when the battery BAT is connected forward. In this case, in response to the invalidation of the control input signal IN, the enable signal S_EN1 is also invalidated. In response to the negative gate level of the enable signal S_EN1, the pMOS transistor MP2 is turned off. As a result, the back-gate potential of the nMOS transistors MN1 to MN3 in the booster circuit CP1a is controlled to be the same potential as the output potential VO via the resistor R2.

[0063] As a result, the parasitic bipolar transistors BT of the nMOS transistors MN1 to MN3 are turned off, and the application of the clock signal CK stops with the invalidation of the control signal IN. As a result, the booster circuit CP1a is deactivated. As a result, the charge on the gate of the power transistor QN1 is discharged to the source through the resistor R1 in the gate discharge circuit DCG1a, and the gate potential approaches the power supply potential [1a]VD1a over time. During this discharge period, the power transistor QN1 is turned on. However, since even when the power transistor QN1 is turned on, Figure 3 the gate discharge circuit DCG2 of also quickly controls the power transistor QN2 to be turned off in response to the invalidation of the enable signal S_EN2, so the forward current supply from the power supply circuit [1a]VD1a to the load LD is cut off.

[0064] Next, it is assumed that the battery BAT is connected in reverse. In this case, the power supply potential [3]VD3 is the battery power supply potential VB, the power supply potential [1a]VD1a is the ground power supply potential GND, and the power supply potential [1b]VD1b is "VB - VF" (VF is the forward voltage of the ESD protection diode De1). The control circuit CTLa does not operate with this potential relationship, and the control circuit outputs the battery power supply potential VB as the enable signal S_EN1. As a result, the pMOS transistor MP2 is turned off, and the back-gate potential of the nMOS transistors MN1 to MN3 becomes the same potential as the load drive terminal Po2(+) (for example, approximately the battery power supply potential VB).

[0065] On the other hand, when the battery BAT is reversely connected, the power transistor QN1 is cut off by the resistor R1 in the gate discharge circuit DCG1a. In the booster CP1a, although the pumping operation is not performed because no clock signal is generated due to the reverse connection, the parasitic bipolar transistor BT is turned on in response to the potential from the load driving terminal Po2(+) (e.g., the battery power supply potential VB), and the capacitors C1 to C3 are charged. However, the charging current at this time (in other words, the gate charging current of the power transistor QN1) can be adjusted by the resistor R2.

[0066] Therefore, if the resistance of the resistor R2 is designed to be high enough so that the gate discharge current of the resistor R1 is sufficiently greater than the gate charging current determined by the resistor R2 and the hfe of the parasitic bipolar transistor BT, the power transistor QN1 remains in the cut-off state. For example, for hfe = 100, the resistance value of the resistor R2 can be designed to be 1000 times the resistance value of the resistor R1, etc. As another method, a diode for preventing the reverse current from the load driving terminal Po2(+) to the booster circuit CP1a can be provided in series with the resistor R2 separately.

[0067] Figure 6 is a schematic diagram showing Figure 3 the external configuration of the semiconductor device (relay device). As Figure 6 shown, Figure 3 the semiconductor device (relay device) RLYa consists of a semiconductor chip or a semiconductor package. On the other hand, for example, the relay device RLY' d shown in Patent Document 1 as the second comparative example has a configuration in which a plurality of components (two power transistor components (QN1, QN2) and two booster circuit components (CP'1, CP'2)) are mounted on the wiring board BD1.

[0068] As described above, when using Figure 3 the semiconductor device (relay device) RLYa, the size of the device can be reduced compared to the relay device RLY' d of the second comparative example. As a result, the restrictions on the position for mounting the relay device are relaxed, and the wiring route of the harness in the vehicle as Figure 1 shown can be simplified. This simplification of the harness helps to reduce the weight, cost, power consumption, etc. of the vehicle.

[0069] In the first embodiment, when the control input signal IN is valid when the battery BAT is connected in the forward direction, the boost circuit CP1a is valid both in the charging operation and the pumping operation, and the power transistor QN1 is turned on by "the gate charging current of the boost circuit CP1a" > "the gate discharging current of the gate discharging circuit DCG1a". When the battery BAT is connected in the forward direction and the control input signal IN is a negative input signal, the boost circuit CP1a is invalid, and after a predetermined period of time, the power transistor QN1 is turned off due to the gate discharging current of the gate discharging circuit DCG1a. On the other hand, when the battery BAT is connected in the reverse direction, the boost circuit CP1a is activated in a weak charge operation, and the power transistor QN1 is turned off by "the gate charging current of the boost circuit CP1a" < "the gate discharging current of the gate discharging circuit DCG1a".

[0070] By providing the gate discharging circuit DCG1a between the gate and the source of the power transistor QN1 in this way, the reverse current supply from the load LD to the power supply can be cut off. In addition, by assuming the use of n-channel type two-stage configured power transistors QN1 and QN2, low loss or miniaturization of the relay device RLYa can be achieved. In addition, by implementing the relay device RLYa with one semiconductor package (IPD), further miniaturization of the device can be achieved. Here, although the resistor R1 is provided in the gate discharging circuit DCG1a, an nMOS transistor can be provided instead of the resistor R1. Then, the gate of the nMOS transistor is coupled to the power supply [3]VD3.

[0071] Second embodiment

[0072] As Figure 1 and 2 shown, the relay device RLY for an automobile (for example, the power supply shown as [1a]VD1a in Figure 3 ) is usually coupled to the battery power supply VB. In this case, various external surges can be applied to the power supply [1a]VD1a. Here, when a positive polarity surge represented by a dump surge caused by an alternator occurs, it is difficult to apply excessive power to Figure 3 the power transistor QN1 shown. This is because, even when the power transistor QN1 is turned off, the parasitic diode Dn1 is excited. On the other hand, when a negative polarity surge caused by a field coil or an inductive load occurs, the power transistor QN1 may consume excessive power due to breakdown when the field coil or the inductive load is disconnected, resulting in breakdown.

[0073] Figure 7 is a block diagram showing a schematic configuration of a semiconductor device (relay device) according to the second embodiment. Figure 7 The semiconductor device (relay device) RLYb shown is the same asFigure 3 The configuration shown differs in the following five points. As a first difference, a power transistor QN1(L) is provided instead of Figure 3 the power transistor QN1 shown. The breakdown voltage of the power transistor QN1(L) is lower than that of the power transistor QN1 and the power transistor QN2. As a specific example, the breakdown voltage of the power transistor QN2 (and the power transistor QN1) is 40V etc., while the breakdown voltage of the power transistor QN1(L) is 20V etc.

[0074] As a second difference, the gate discharge circuit DCG1b includes a short-circuit transistor MN16 instead of Figure 4 the resistor R1 in Figure 9 as shown in detail in Figure 4 As a third difference, the boost circuit CP1b is constituted by the boost circuit main body (MN1 to MN3, C1 to C3) shown in Figure 3 As a fourth difference, a negative potential detection circuit VNDET is provided instead of the anti-backflow circuit RCF shown in Figure 3 The negative potential detection circuit VNDET controls the short-circuit transistor in the gate discharge circuit DCG1b through the negative potential detection signal [1]S_DET 1, and controls the boost circuit CP1b through the negative potential detection signal [1]S_DET 2. Therefore, as a fifth difference, the control circuit CTLb does not output

[0075] In a vehicle-mounted system of a 12V system as shown in Figure 1 and 2 usually, considering incorrect connections etc. at the start of a jump, the DC rating of the positive polarity needs to be 28V. On the other hand, the DC rating of the negative polarity (which is not assumed to be a situation such as the start of a jump) is usually -16V. Focusing on this rated potential difference between the positive and negative polarities, the power transistor QN1(L) can be implemented with a low breakdown voltage configuration. As a specific structural example, for example, Japanese Unexamined Patent Application Publication No. 2016-207716 etc. can be cited. By using such a configuration, compared with the configuration of Figure 3 the on-resistance of the power transistor QN1(L) can be reduced, and the loss or miniaturization of the device can be further reduced.

[0076] However, when a negative surge such as -60 V to -120 V is applied to the power supply [1a] VD1a, the loss caused by the breakdown of the power transistor QN1(L) increases by an amount corresponding to the low withstand voltage. Therefore, for example, when using the method disclosed in Patent Document 2, the power transistor can be controlled to conduct when a negative surge is applied, so that such loss can be reduced and the power transistor can be protected. However, in the method of Patent Document 2, since a large capacitor is required according to, for example, the duration of the negative surge, it may be difficult to construct a relay device in one semiconductor chip or one semiconductor package. Therefore, in Figure 7 a negative potential detection circuit VNDET and the like are provided.

[0077] Figure 8 is a circuit diagram showing Figure 7 a schematic configuration example of the negative potential detection circuit in the semiconductor device (relay device) of, in which the main part (second embodiment) of the relay device is described in detail. Figure 9 is a circuit diagram showing Figure 7 the detailed configuration of the main part of the semiconductor device (relay device) of. For example, in Figure 7 when the battery BAT is reversely connected and when a negative surge is applied to the power supply [1a] VD1a, the negative potential reference power supply [3] VD3 is applied to the power supply [1a] VD1a. However, it is desirable that the power transistor QN1(L) be cut off when the battery BAT is reversely connected and conduct when a negative surge is applied to the battery BAT. Therefore, a negative potential detection circuit VNDET is provided to distinguish the reverse connection of the battery BAT and the application of the negative surge, and to turn on / off the power transistor QN1(L) according to the result of distinguishing the reverse connection of the battery BAT and the application of the negative surge.

[0078] In addition to Figure 4 the pMOS transistor MP1 and the reverse current prevention diode Dc in the reverse current prevention circuit RCF shown in, Figure 8 the negative potential detection circuit VNDET shown in also includes a resistor R11 and a negative potential discrimination circuit JDG. The resistor R11 and the anti-backflow diode (Zener diode) Dc are provided in series between the power supply [1a] VD1a (in other words, the positive power supply terminal Pi2(+)) and the power supply [1b] VD1b. Here, when the battery BAT is reversely connected or when a negative surge is applied to the battery BAT, the power supply [1b] VD1b is coupled to the power supply [3] VD3 (in other words, the negative power supply terminal Pi2(-)) via the forward-biased ESD protection diode De1. Therefore, the resistor R11 and the anti-backflow diode Dc are basically provided in series between the positive power supply terminal Pi2(+) and the negative power supply terminal Pi2(-).

[0079] The breakdown voltage of the reverse current prevention diode Dc is 16 V or higher, and is set to, for example, 20 V or the like. When the battery BAT is reversely connected (for example, when -12 V or the like is applied to the power supply [1a]VD1a), the anti-backflow diode Dc is not damaged, and thus no predetermined potential difference occurs between both ends of the resistor R11. On the other hand, when a negative surge exceeding the breakdown voltage of the anti-backflow diode Dc (for example, a negative surge on the negative side of -20 V) is applied to the power supply [1a]VD1a, the anti-backflow diode Dc breaks down, thereby generating a predetermined potential difference between both ends of the resistor R11. The negative potential determination circuit JDG determines whether the battery BAT is reversely connected or when a negative surge is applied based on whether there is a predetermined potential difference in the resistor R11 (that is, whether there is a breakdown of the reverse current prevention diode Dc).

[0080] As will be described in reference Figure 9 in detail, when the battery BAT is reversely connected, the negative potential determination circuit JDG controls the gate discharge circuit DCG1b to be turned on via the negative potential detection signal [1]S_DET1, and deactivates the boost circuit CP1b via the negative potential detection signal [2]S_DET2. As a result, the power transistor QN1(L) is turned off to cut off the reverse conduction. On the other hand, when a negative surge is applied, the negative potential determination circuit JDG controls the gate discharge circuit DCG1b to be turned off via the negative potential detection signal [1]S_DET1, and causes the boost circuit CP1b to output a predetermined potential that is more positive than the power supply potential [1a]VD1a via the negative potential detection signal [2]S_DET2. As a result, the power transistor QN1(L) is turned on, and power loss due to the negative surge can be reduced.

[0081] On the other hand, when the battery BAT is connected in sequence, the power supplies [1a]VD1a and [1b]VD1b have substantially the same potential via the pMOS transistor MP1. In this case, the negative potential determination circuit JDG controls the gate discharge circuit DCG1b to be turned off via the negative potential detection signal [1]S_DET1, and activates the boost circuit CP1b via the negative potential detection signal [2]S_DET2, thereby controlling the power transistor QN1(L) to be turned on.

[0082] As described above, the negative potential detection circuit VNDET determines whether the negative potential applied to the power supply [1a] VD1a (positive power supply terminal Pi2(+)) is on the positive side or the negative side relative to the power supply [3] VD3 (negative power supply terminal Pi2(-)) serving as a reference, and whether it is higher than a predetermined negative threshold potential (i.e., -20V or the like based on the breakdown voltage of the reverse current prevention diode Dc). Then, the negative potential detection circuit VNDET controls the gate discharge circuit DCG1b to conduct in the case of the positive side (e.g., -12V or the like associated with the reverse connection of the battery BAT), and controls the gate discharge circuit DCG1b to disconnect in the case of the negative side (e.g., -100V or the like associated with a negative surge).

[0083] Figure 9 illustrates Figure 7 and 8 Examples of the configurations around the negative potential detection circuit VNDET, around the boost circuit CP1b, and around the gate discharge circuit DCG1b shown. The gate discharge circuit DCG1b includes a protection diode D2 and an nMOS transistor (short-circuit transistor) MN16 coupled in parallel between the power supply [1a] VD1a and the gate of the power transistor QN1(L). The booster CP1b includes the same nMOS transistors MN1 to MN3 and capacitors C1 to C3 as in Figure 4 therein.

[0084] The negative potential detection circuit VNDETa (VNDET) includes a negative potential determination circuit JDGa. The negative potential discrimination circuit JDGa includes nMOS transistors MN11 to MN15, resistors R12 to R15, a pMOS transistor MP11, a diode D11, and a capacitor C11. The negative potential detection signal [1] S_DET1 from the negative potential determination circuit JDGa is applied to the gate of the nMOS transistor (short-circuit transistor) MN16 in the gate discharge circuit DCG1b.

[0085] The negative potential detection signal [2] S_DET2 from the negative potential determination circuit JDGa is applied to the back gates of the nMOS transistors MN1 to MN3 in the boost circuit CP1b. A diode (Zener diode) D11 is coupled between the power supply [1a] VD1a (in other words, the positive power supply terminal Pi2(+)) and the back gates of the nMOS transistors MN1 to MN3 as the power supply [1a] VD1a on the anode side (the cathode on the back gate side).

[0086] In Figure 9In this case, the power supply [3] VD3 is coupled to the ground power supply potential GND of the battery BAT, particularly via an external resistor such as 100 Ω, to the ground power supply potential GND. The breakdown voltage of the anti-backflow diode Dc in the negative potential detection circuit VNDETa is, for example, 20 V or the like, which is substantially the same as the breakdown voltage of the power transistor QN1(L). As described above, from the viewpoint of protecting the power transistor QN1(L), the breakdown voltage of the anti-backflow diode Dc is ideally set to be equal to or lower than the breakdown voltage of the power transistor QN1(L) (however, higher than the battery power supply potential VB).

[0087] In this configuration, first, it is assumed that the battery BAT is connected in sequence. In this case, since the power supply [1b] VD1b becomes substantially the same potential as the power supply [1a] VD1a through the pMOS transistor MP1, the negative potential discrimination circuit JDGa does not perform a discrimination operation. The negative potential determination circuit JDGa controls the nMOS transistor MN16 in the gate discharge circuit DCG1b to be cut off by controlling the negative potential detection signal [1] S_DET1 to be substantially the power supply potential [1a] VD1a via the resistor R12. The negative potential determination circuit JDGa supplies the power supply potential [1a] VD1a to the back gates of the nMOS transistors MN1 to MN3 in the booster circuit CP1b via the diode D11. As a result, the booster CP1b performs a charging operation and a pumping operation based on a clock signal (not shown) to raise the gate potential of the power transistor QN1(L) to a potential at which the power transistor QN1(L) can operate in a sufficiently linear range.

[0088] Next, it is assumed that the battery BAT is connected reversely. In this case, since the anti-backflow diode Dc does not break down, no potential difference is generated between both ends of the resistor R11. Therefore, the nMOS transistor MN11 is cut off, and the power supply potential [1b] VD1b (i.e., approximately the battery power supply potential VB) is transmitted through the resistor R12, so that the nMOS transistor MN12 is turned on and the pMOS transistor MP11 is cut off. As a result, the negative potential detection signal [1] S_DET 1 becomes the same potential as the power supply [1b] VD1b (substantially the battery power supply potential VB), and the negative potential detection signal [2] S_DET2 becomes the same potential as the power supply [1a] VD1a (i.e., the ground power supply potential GND).

[0089] The nMOS transistor MN16 in the gate discharge circuit DCG1b is turned on in response to the negative potential detection signal [1] S_DET1. In the booster circuit CP1b, Figure 5The parasitic bipolar transistor BT in it conducts in response to the negative potential detection signal [2]S_DET2, and the oscillator circuit does not operate, so the pumping operation is not performed. Therefore, the booster CP1b is deactivated. As a result, the power transistor QN1(L) is cut off to cut off the reverse conduction.

[0090] Next, it is assumed that when the battery BAT is connected in sequence, a negative surge (for example, -60V to -120V) is applied to the power supply [1a]VD1a. Since the potential relationship between the power supply [1a]VD1a and the power supply [3]VD3 is the same as the potential relationship when the battery BAT is reversely connected as described above, the power transistor QN1(L) is cut off by turning on the nMOS transistor MN16, unless the reverse connection of the battery BAT and the application of the negative surge are distinguished.

[0091] However, when a negative surge is applied, it is desired that the power transistor QN1(L) conducts. Here, when Figure 7 the control input signal IN shown is at an effective level, the power transistor QN1(L) conducts initially, so there will be no particular problem even if a negative surge is applied to the control input signal IN. On the other hand, when the control input signal IN is at an invalid level (that is, when the booster circuit CP1b is initially invalid), the control input signal IN needs to be designed to turn on the power transistor QN1(L), which is different from the case when the battery BAT is reversely connected to the booster circuit QN1.

[0092] When a negative surge is applied to the power supply [1a]VD1a, the reverse current prevention diode Dc breaks down via the ESD protection diode De1, and a potential difference is generated between both ends of the resistor R11. The power supply [1b]VD1b becomes lower than the potential of the power supply [3]VD3 and higher than the power supply potential [1a]VD1a through the forward voltage of the ESD protection diode De1. As a result, the nMOS transistor MN11 conducts, and the negative potential detection signal [1]S_DET 1 becomes the same potential as the power supply signal [1a]VD1a. As a result, the nMOS transistor MN16 in the gate discharge circuit DCG1b is cut off.

[0093] In addition, in response to the conduction of the nMOS transistor MN11, the pMOS transistor MP11 conducts and the nMOS transistor MN12 is cut off. As a result, current flows from the pMOS transistor MP11 through the resistor R13 and the diode D11. As a result, the negative potential detection signal [2]S_DET 2 becomes positive with reference to the power supply potential [1a]VD1a through the breakdown voltage (for example, 6V) of the diode (zener diode) D11.

[0094] In the booster CP1b, the parasitic bipolar transistor BT turns on in response to the negative potential detection signal [2]S_DET2 and performs a charging operation. In the boost circuit CP1b, since the pumping operation is not performed due to the invalidation of the control input signal IN, only the charging operation of the boost circuit CP1b is activated. As a result, a conduction voltage determined by the breakdown voltage of the diode (Zener diode) D11 can be applied between the gate and source of the power transistor QN1(L). At this time, the nMOS transistor MN16 is turned off. As a result, when a negative surge is applied, the power transistor QN1(L) can be controlled to turn on. As described above, the breakdown voltage of the diode D11 only needs to be a value at which the power transistor QN1(L) can operate in a sufficiently linear range.

[0095] Here, the base current of the parasitic bipolar transistor ( Figure 5 BT in) in the booster CP1b can be adjusted by the resistor R13, and the conduction speed of the power transistor QN1(L) can be determined by the resistor R13. For example, if quick conduction is desired, the resistor R13 can be set to a small resistance value. Here, the nMOS transistor MN16 is provided in the gate discharge circuit DCG1b. On the other hand, it is not easy to use a pMOS transistor instead of an nMOS transistor. That is, in order to discharge the gate potential of the power transistor QN1(L) to the ground power supply potential GND while the power supply [1a]VD1a is at the ground power supply potential GND when the battery BAT is reversely connected, a negative potential needs to be applied to the gate of the pMOS transistor.

[0096] In order to prevent jitter near the breakdown voltage of the reverse current prevention diode Dc, it is desirable that the negative potential detection signal [1]S_DET1 and the negative potential detection signal [2]S_DET2 be latched in the state when a negative surge is applied. The nMOS transistors MN13 to MN15, the resistors R14 and R15, and the capacitor C11 are provided as elements for latching. When the power supply potential [1a]VD1a returns to the positive electrode, the latch is released because the potential difference between the power supply potential [1a]VD1a and the power supply potential [1b]VD1b becomes smaller.

[0097] As described above, by quickly turning on the power transistor QN1(L) when a negative surge is applied, the loss of the power transistor QN1(L) can be greatly reduced compared to when breakdown occurs, and a low breakdown voltage configuration can be applied to the power transistor QN1(L). In addition, the power transistor QN1(L) can be protected. Specific examples of the loss are shown below.

[0098] Assume that the breakdown voltage of the power transistor QN1(L) is "BV1", the on-resistance is "Ron1", the negative surge potential is "Vsr", and the load resistance is "RL". The loss PL1 in the breakdown case is represented by Equation (1), and the loss PL2 in the on case is represented by Equation (2). For example, when Vsr = -100V, BV1 = 20V, Ron1 = 5mΩ, and RL = 1Ω, PL1 is 1600W, while PL2 is 50W.

[0099] PL1 = BV1 × (|Vsr| - BV1) / RL (1)

[0100] PL2 = Ron × (|Vsr| - RL)2 (2)

[0101] Figure 10 is a circuit diagram showing an example of the configuration when Figure 9 's circuit is formed on a wiring substrate. As Figure 10 shown, Figure 9 's circuit can be implemented by mounting multiple components on the circuit board BD2. In Figure 10 , the charging circuit CU is a circuit corresponding to the parasitic bipolar transistor BT of Figure 5 when applying a negative surge, and the boost circuit CU is mounted in the driver DVb1. Figure 11 is a schematic diagram comparing the Figure 7 relay device and Figure 10 's relay device in terms of a schematic example.

[0102] As Figure 11 shown, in the relay device (printed circuit board BD2) according to Figure 10 , compared with the Figure 7 relay device RLYb, the number of components is greatly increased. Therefore, it is difficult to miniaturize the device. In addition, considering the dump surge, Figure 10 the gate oxide breakdown voltage of the pMOS transistor MPb1 in

[0103] In the second embodiment, when the control input signal IN is made valid while the battery BAT is connected in sequence, both the charging operation and the pumping operation of the boost circuit CP1b are activated. The nMOS transistor MN16 in the gate discharge circuit DCG1b is turned off because its source is coupled to the power supply [1a] VD1a, its gate is coupled to the power supply [1a] VD1a via the pMOS transistor MP1 and the resistor R12, and the boosted potential is applied to the drain. As a result, the power transistor QN1(L) is turned on. On the other hand, when the control input signal IN is made invalid, the nMOS transistor MN16 is turned off during the period when the boosted potential at the drain is maintained, and the power transistor QN1(L) is turned on during this period. However, the power transistor QN2 is turned off.

[0104] When the battery BAT is connected in reverse, the booster CP1b is disabled, and the nMOS transistor MN16 is turned on because its source is coupled to the power supply [1a] VD1a and its gate is coupled to the power supply [3] VD3 via the ESD protection diode De1 and the resistor R12. As a result, the power transistor QN1(L) is turned off. In addition, when the battery BAT is connected in the forward direction, when the control input signal IN is made invalid, and when a negative surge is applied to the control input signal IN, the boost circuit CP1b is activated in the charging operation of the boost circuit CP1B. The nMOS transistor MN16 is turned off because its source is coupled to the power supply [1a] VD1a and its gate is also coupled to the power supply [1a] VD1a via the nMOS transistor MN11. As a result, the power transistor QN1(L) is turned on.

[0105] By using this method, the same effect as in the first embodiment can be obtained. In addition, by configuring the power transistor QN1(L) so that it can be driven when a negative surge is applied, the loss when a negative surge is applied can be reduced, and a structure having a lower withstand voltage than the structure of the power transistor QN2 can be applied to the power transistor QN1(L). As a result, further reduction or miniaturization of the loss of the relay device can be achieved.

[0106] Third Embodiment

[0107] As described above, Figure 9 As a prerequisite for the third embodiment, the gate potential of the nMOS transistor MN16 in the gate discharge circuit DCG1b shown above is controlled by the negative potential detection signal [1] S_DET1. When the battery BAT is connected in the forward direction, the negative potential detection signal [1] S_DET1 becomes substantially the same potential as the power supply signal [1a] VD1a. Therefore, the nMOS transistor MN16 is turned off, and the gate charge of the power transistor QN1(L) is not discharged. That is, the power transistor QN1(L) cannot be controlled to be turned off.

[0108] On the other hand, the power supply of the load LD is controlled by the power transistor QN2, and the power transistor QN2 turns on and off rapidly in response to the control input signal IN. Therefore, by controlling the power transistor QN2 to be off regardless of the state of the power transistor QN1(L), the supply of the forward current to the load LD can be cut off.

[0109] Therefore, although no fatal problem occurs because the power transistor QN1(L) cannot be controlled to be off, problems may occur when using a capacitor load or the like. For example, when using a capacitor load and cranking occurs when the control input signal IN is invalid, since the potential of the capacitor load > the power supply potential [1a]VD1a, the charge of the capacitor load may escape to the power supply [1a]VD1a, and may not be restored thereafter.

[0110] Figure 12 It is a waveform diagram showing an exemplary problem that is a prerequisite for the relay device (semiconductor device) according to the third embodiment. Figure 12 It shows the changes in the potential of the power supply potential [1a]VD1a, the gate potentials of the power transistors QN1(L) and QN2, and the output potential VO when the control input signal IN is invalid at time t1 and cranking occurs between times t2 and t5.

[0111] When the control input signal IN is invalid at time t1, the gate potential of the power transistor QN2 is reduced by the gate discharge circuit DCG2 until the gate potential of the control input signal IN becomes equal to the output potential VO of the load drive terminal Po2(+). On the other hand, since the nMOS transistor MN16 in the gate discharge circuit DCG1b is not turned on, the gate potential of the power transistor QN1(L) is maintained at a potential at which the power transistor QN1(L) can be turned on. Strictly speaking, due to the leakage current of each element coupled to the gate, the gate potential of the power transistor QN1(L) drops to the power supply potential [1a]VD1a in the long term, but in Figure 12 it is assumed that there is no leakage current.

[0112] When cranking occurs at time t2 and the power supply potential [1a]VD1a drops, the charge of the capacitor load coupled to the load drive terminal Po2(+) escapes to the power supply [1a]VD1a via the parasitic diode Dn2 of the power transistor QN2 and the channel of the power transistor QN1(L). During the period from time t4 to time t5, the power supply potential [1a]VD1a returns to the original potential. However, since the power transistor QN2 is off, the potential of the capacitor load (output potential VO) remains at the potential that dropped during the period from time t3 to time t4, without the discharged charge being re-supplied.

[0113] For example, when a unit with a capacitor load as a backup power source exists downstream of the relay device, the capacitor load can be used. In this case, for example, there may be a risk that the downstream unit is cut off by a low voltage. Therefore, it is advantageous to use the relay device (semiconductor device) of the third embodiment described later.

[0114] Figure 13 is a block diagram showing a schematic configuration of the semiconductor device (relay device) according to the third embodiment. Figure 13 The semiconductor device (relay device) RLYc shown is different from the Figure 7 configuration shown in the following four points. The first difference is that the load LD2 is a capacitor load. As the second difference, a delay circuit DLY is added, and as the third difference, a gate discharge circuit DCG3 is added. As the fourth difference, as Figure 14 shown in detail in, the gate potential of the power transistor QN1(L) is input to the negative potential detection circuit VNDET.

[0115] The delay circuit DLY outputs a delay signal S_DLY that is valid for a predetermined period, which is triggered by the transition of the control signal INx output from the input buffer IBF to invalid (i.e., the transition of the control input signal IN to invalid). The gate discharge circuit DCG3 is provided between the gate of the power transistor QN1(L) and the power supply [3]VD3, and receives the delay signal S_DLY from the delay circuit DLY to discharge the charge of the gate of the power transistor QN1(L) toward the power supply [3]VD3.

[0116] Figure 14 is a circuit diagram showing a detailed configuration example of the main part of the Figure 13 semiconductor device (relay device) shown, to show the main part of the relay device (third embodiment). Figure 15 is a circuit diagram showing a detailed configuration example of the delay circuit in Figure 13 . Figure 14 shows Figure 13 an example of the configuration around the negative potential detection circuit VNDET, around the boost circuit CP1b, around the gate discharge circuit DCG1b, and around the gate discharge circuit DCG3 shown.

[0117] Compared with Figure 9Compared with the configuration shown, the negative potential determination circuit JDGc in the negative potential detection circuit VNDETc (VNDET) further includes an nMOS transistor MN21 serially coupled with a resistor R12 and a capacitor C21 provided between the gate of the nMOS transistor MN16 and the power supply [3]VD3. The gate of the nMOS transistor MN21 is coupled to the gate of the power transistor QN1(L). The gate discharge circuit DCG3 includes a resistor R21 and an nMOS transistor MN22 serially coupled between the gate of the nMOS transistor MN21 (and the power transistor QN1(L)) and the power supply [3]VD3. The delayed signal S_DLY is applied to the gate of the nMOS transistor MN22.

[0118] First, an overview of the circuit shown will be described. Figure 14 The cause of the problem described with reference to Figure 12 is that the nMOS transistor MN16 in the gate discharge circuit DCG1b is controlled to conduct when the battery BAT is reversely connected, but remains cut off when the battery BAT is forwardly connected. As a result, even when the control input signal IN is invalid during the forward connection of the battery BAT, the on-state of the power transistor QN1(L) can be maintained, and thus, charge loss occurs during startup.

[0119] Here, the reason why the nMOS transistor MN16 remains cut off is that the gate potential of the nMOS transistor MN16 follows the power supply potential [1a]VD1a. On the other hand, assume that when the power supply potential [1a]VD1a fluctuates due to startup, the gate potential of the nMOS transistor MN16 maintains the gate potential of the power supply potential [1a]VD1a before startup without following the gate potential [1a]VD1a. In this case, the nMOS transistor MN16 automatically conducts because a gate-source voltage is generated according to the change in the power supply potential [1a]VD1a. As a result, the power transistor QN1(L) can be controlled to cut off.

[0120] Therefore, the capacitor C21 is provided, and the capacitor C21 maintains the potential of the negative potential detection signal [1]S_DET1, that is, the gate potential of the nMOS transistor MN16, before startup. Specifically, when the power supply potential [1a]VD1a is applied to the gate (negative potential detection signal [1]S_DET1) during the valid period of the control input signal IN, the nMOS transistor (short-circuit transistor) MN16 is cut off. During the invalid period of the control input signal IN, the capacitor C21 maintains the gate potential of the nMOS transistor MN16 during the valid period of the control input signal IN.

[0121] However, since the changes in the power supply potential [1b] VD1b and the power supply potential [1a] VD1a are interlocked, if the nMOS transistor MN21 is not provided, the potential of the capacitor C21 is interlocked with the power supply potential [1b] VD1b, and the power supply potential [1a] VD1a before startup cannot be maintained. Therefore, the nMOS transistor (control transistor) MN21 is provided. The nMOS transistor MN21 is provided between the power supply [1b] VD1b (and thus the power supply [1a] VD1a (positive power supply terminal Pi2(+))) and the gate of the nMOS transistor MN16. During the inactive period of the control input signal IN, the nMOS transistor MN21 is controlled to be cut off, thereby controlling the gate of the nMOS transistor MN16 to a high impedance state.

[0122] Specifically, the gate of the nMOS transistor MN21 is coupled to the gate of the power transistor QN1(L) and has the same potential as the gate. Therefore, when a change in the power supply potential [1a] VD1a occurs, the power supply potential [1a] VD1a is applied to the gate of the nMOS transistor MN16, and the gate potential of the power transistor QN1(L) is controlled to the power supply potential [1a] VD1a in the changed state after startup. In the nMOS transistor MN21, the source (power supply potential [1b] VD1b) fluctuates together with the fluctuating power supply potential [1a] VD1a, but since the gate also fluctuates in the same way, they remain disconnected. As a result, the gate of the nMOS transistor MN16 remains in a high impedance state, and its gate potential remains at the power supply potential [1a] VD1a before startup by the capacitor C21.

[0123] On the other hand, for example, when the gate of the power transistor QN1(L) maintains a boosted potential before startup, the power transistor QN1(L) conducts, and the nMOS transistor MN21 also conducts. Here, as described above, in order to cut off the nMOS transistor MN21 during the inactive period of the control input signal IN, when the control input signal IN transitions from the active level to the inactive level, it is necessary to initially control the nMOS transistor MN21 to be cut off.

[0124] Otherwise, when the power supply potential [1a] VD1a fluctuates, the negative potential detection signal [1] S_DET1 starts to follow the power supply potential [1a] VD1a in the fluctuating state, so that the nMOS transistor MN16 is turned off, and as a result, the nMOS transistor MN21 can also remain turned on. Therefore, the gate discharge circuit DCG3 is provided. When the control input signal IN changes from the active level to the inactive level, the gate discharge circuit DCG3 sets the gate potentials of the nMOS transistor MN21 and the power transistor QN1(L) to "VD1a - VF" (VF is the forward voltage of the protection diode D2). As a result, the gate discharge circuit DCG3 controls the MOS transistor MN21 to be cut off, and in addition, the gate discharge circuit also controls the power transistor QN1(L) to be cut off.

[0125] Next, the details of the Figure 14 and Figure 15 circuit shown will be described. Figure 15 The delay circuit DLY shown includes nMOS transistors MN31 to MN33, pMOS transistors MP31 to MP34, resistors R31 to R33, capacitors C31 to C33, diode D31, inverter IV31, and current sources IS31 and IS32. The current sources IS31 and IS32 are implemented by a current mirror circuit, a depletion-type transistor with its gate and source shorted, etc. Note that the resistors R31 to R33 can be replaced by a depletion-type transistor with its gate and source shorted, etc.

[0126] The current source IS31, diode D31, and resistor R33 generate a power supply (power supply potential) [6] VD6, which is a reference for the power supply [1b] VD1b. The control signal INx from the input buffer IBF is input to the gates of the nMOS transistor MN31 and the pMOS transistor MP31. The capacitors C32 and C33, resistor R32, nMOS transistor MN33, pMOS transistors MP33 and MP34, and inverter IV31 constitute a timer circuit. The delayed signal S_DLY is output by the inverter IV31. The inverter IV31 also has the function of shifting the signal level between the power supply [1b] VD1b and the power supply [6] VD6 to the signal between the power supply [1b] VD1b and the power supply [3] VD3.

[0127] In such a configuration, in response to the activation of the control signal IN, the control signal INx reaches an active level, which is the VD3 level in this case. As a result, the nMOS transistor MN31 is turned off, and the power supplies [1b] VD1b and [6] VD6 have the same potential. That is, the power supply [6] VD6 is deactivated without generating a predetermined power supply. The pMOS transistor MP31 is turned on, and the node Na has the same potential as the power supply [1b] VD1b.

[0128] When the control input signal IN switches from active to inactive, the control signal INx becomes an inactive level, which is the VD1b level in this case, and the nMOS transistor MN31 is turned on while the pMOS transistor MP31 is turned off. However, at this time, since the pMOS transistor MP32 is turned off, the potential of the node Na changes from the power supply potential [1b] VD1b to the power supply [3] VD3, where the time constant is determined by the capacitor C31 and the resistor R31.

[0129] On the other hand, immediately after the control signal INx switches from the active level (VD3 level) to the inactive level (VD1b level), the potential of the node Na is near the power supply potential [1b] VD1b. Therefore, the nMOS transistor MN32 is turned on, and the power supply [6] VD6 is generated by the diode D31 and the current source IS31. That is, the power supply [6] VD6 is activated. As will be described in detail later, immediately after the power supply [6] VD6 is generated, since the potential of the node Nb is at the power supply potential [6] VD6, the pMOS transistor MP32 is turned on, and the on state of the nMOS transistor MN32 is maintained regardless of the time constant determined by the capacitor C31 and the resistor R31.

[0130] The capacitor C32, the resistor R32, and the nMOS transistor MN33 are provided to initialize the potential of the node Nb, and immediately after the power supply [6] VD6 is generated, the nMOS transistor MN33 is controlled to be turned on to lower the potential of the node Nb to the level of the power supply potential [6] VD6. As a result, the pMOS transistor MP32 is turned on, and as described above, the nMOS transistor MN32 remains on regardless of the time constant of the capacitor C31 and the resistor R31.

[0131] After a predetermined period determined by capacitor C32 and resistor R32 has elapsed, nMOS transistor MN33 is turned off. As a result, capacitor C33 starts to be charged by the current obtained by mirroring current source IS32 by pMOS transistors MP33 and MP34, and the potential of node Nb changes from power supply potential [6]VD6 to power supply potential [1b]VD1b. Delay signal S_DLY becomes active level during the period from the activation time of power supply [6]VD6 to the time when the potential of node Nb reaches the threshold of inverter IV31, and during this period, nMOS transistor MN22 in gate discharge circuit DCG3 is turned on.

[0132] When the potential of node Nb reaches the threshold of inverter IV31, delay signal S_DLY becomes negative gate level, and nMOS transistor MN22 in gate discharge circuit DCG3 is turned off. The length of the active period of delay signal S_DLY is appropriately set together with the resistance value of resistor R21 in gate discharge circuit DCG3 such that the gate charge of power transistor QN1(L) is discharged during the active period of delay signal S_DLY. When the potential of node Nb exceeds the threshold of inverter IV31 and approaches power supply potential [1b]VD1b, pMOS transistor MP32 is turned off.

[0133] As a result, the potential of node Na changes from power supply potential [1b]VD1b to power supply potential [3]VD3 according to the time constant determined by capacitor C31 and resistor R31, and nMOS transistor MN32 is turned off. As a result, the potential of power supply [6]VD6 becomes the same as the potential of power supply [1b]VD1b, and the current consumed by delay circuit DLY becomes zero. When control input signal IN switches from active to inactive, delay circuit DLY can operate only for a predetermined period. Therefore, after a certain period, it is desirable to activate power supply [6]VD6 in this way to eliminate the consumed current.

[0134] Figure 16 is a waveform diagram showing Figure 14 an example of the operation of the circuit shown. When control input signal IN is inactive, delay signal S_DLY is made active for a predetermined period, i.e., from time t1 to t3. The gate charge of power transistor QN1(L) needs to be discharged during the period from t1 to t3, and needs to be discharged more slowly than the gate charge of power transistor QN2. In this case, the gate charge of power transistor QN1(L) is discharged at time t2, and the gate charge of power transistor QN2 is discharged after time t1 and before time t2. With respect to this discharge order, if power transistor QN1(L) is turned off before power transistor QN2, the combined resistance of power transistor QN1(L) and power transistor QN2 may be discontinuous, thus generating switching noise.

[0135] The period from time t4 to time t7 is the period during which the potential of the power supply [1a] VD1a changes due to startup. Since the power transistor QN​​1(L) is turned off at time t2 during the potential change (that is, the gate and source are coupled to the power supply [1a] VD1a), the potential of the capacitor load (output potential VO) is not transferred to the power supply [1a] VD1a, which is different from Figure 12 the case of

[0136] That is, since Figure 14 the nMOS transistor MN11 and the nMOS transistor MN21 in are turned off during the potential change, the negative potential detection signal [1] S_DET1 is held by the capacitor C21 at the level before time t1 (near the power supply potential [1a] VD1a level before the potential change period). As a result, during the potential change period, the nMOS transistor MN16 in the gate discharge circuit DCG1b controls the gate potential of the power transistor QN​​1(L) to be equal to the power supply potential [1a] VD1a after the potential change period.

[0137] Note that even without using this control, the gate potential of the power transistor QN​​1(L) follows the source potential to some extent through the gate-drain capacitance. However, since the balance between the gate-source capacitance of the power transistor QN​​1(L) and the charging operation of the booster CP1b associated with the residual charge of the negative potential detection signal [2] S_DET2 can be considered, it is preferable to perform the above control.

[0138] In the third embodiment, in addition to performing the same operations as in the second embodiment, when the battery BAT is connected in sequence and the control input signal IN is invalid, when the nMOS transistor MN21 is turned off when startup occurs during the invalidation of the control input signal IN, the capacitor C21 also holds the gate potential of the nMOS transistor MN16 before startup. As a result, the nMOS transistor MN16 automatically turns on because the source potential is reduced by startup, and thus the power transistor QN​​1(L) is turned off. When the battery BAT is connected in reverse, the nMOS transistor MN21 can be turned off, but since the parasitic diode Dn21 with the power supply [1b] VD1b as its anode conducts, the operation is the same as that of the second embodiment.

[0139] By using this method, the same effects as in the second embodiment can be obtained. In addition, during the invalidation of the control input signal IN, the power transistor QN​​1(L) can be controlled to be turned off, and even when the power supply potential [1a] VD1a fluctuates due to startup, the power transistor QN​​1(L) can remain turned off. As a result, charge loss in the capacitor load can be prevented. Here, various circuits are added to Figure 9Configuration example, however, a similar circuit can also be added to Figure 4 Configuration example.

[0140] Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from its gist.

Claims

1. A semiconductor device, comprising: A positive power supply terminal and a negative power supply terminal, coupled to a power supply; A first power transistor and a second power transistor connected in series, wherein the breakdown voltage of the first power transistor is less than that of the second power transistor; A load driving terminal, coupled to a load, wherein the source and back gate of the first power transistor are coupled to the positive power supply terminal, and the drain of the first power transistor is coupled to the load driving terminal via the second power transistor, wherein the source and back gate of the second power transistor are coupled to the load driving terminal, and the drain of the second power transistor is coupled to the positive power supply terminal; A first boost circuit for charging the gate of the first power transistor; A first gate discharge circuit for discharging the gate potential of the first power transistor to the source when the potential of the negative power supply terminal is higher than that of the positive power supply terminal; And A negative potential detection circuit for distinguishing a reverse connection of the power supply and the application of a negative surge at the power supply, and providing corresponding outputs to the first gate discharge circuit and the first boost circuit according to the distinguishing result, Wherein the first gate discharge circuit includes an n-channel short-circuit transistor, and the n-channel short-circuit transistor is used to short-circuit the gate of the first power transistor to the source when the potential of the negative power supply terminal is higher than that of the positive power supply terminal.

2. The semiconductor device according to claim 1, Wherein the semiconductor device is formed by a semiconductor package.

3. The semiconductor device according to claim 1, wherein the negative potential detection circuit is configured to determine whether the negative potential applied to the positive power supply terminal is on the positive side or the negative side of a predetermined negative threshold potential with respect to the negative power supply terminal, and is used to control the short-circuit transistor to conduct in a first case on the positive side, and is used to control the short-circuit transistor to cut off in a second case on the negative side.

4. The semiconductor device according to claim 3, wherein the negative potential detection circuit has a first resistor and a first Zener diode provided in series between the positive power supply terminal and the negative power supply terminal, and the negative potential detection circuit determines whether the negative threshold potential is on the positive side or the negative side by detecting whether the first Zener diode breaks down.

5. The semiconductor device according to claim 3, wherein the negative potential detection circuit has a second Zener diode, one end of the second Zener diode is coupled to the positive power supply terminal, and in a second semiconductor device, the potential with respect to the potential of the positive power supply terminal at which the breakdown voltage of the second Zener diode is positive is applied to the gate of the first power transistor via the first boost circuit.

6. The semiconductor device according to claim 3, wherein the first power transistor has a lower stress structure than the second power transistor.

7. The semiconductor device according to claim 4, wherein when the potential of the positive power supply terminal is applied to the gate during the active period of the control input signal, the short-circuit transistor is turned off, and the semiconductor device further includes a capacitor that holds the gate potential of the short-circuit transistor during the active period of the control input signal during the inactive period of the control input signal.

8. The semiconductor device according to claim 7 further comprises: A control transistor having its source and drain provided between the positive power supply terminal and the gate of the short-circuit transistor, wherein the gate of the control transistor is coupled to the gate of the first power transistor, the source of the control transistor is coupled to the first Zener diode, and during the inactive period of the control input signal, the control transistor controls the gate of the short-circuit transistor to be in a high impedance state by being controlled to be turned off.

9. The semiconductor device according to claim 2, wherein the first gate discharge circuit has a second resistor that allows a gate discharge current smaller than the gate charging current generated when the first boost circuit turns on the first power transistor to pass through.

10. The semiconductor device according to claim 2, further comprising: A second boost circuit for charging the gate of the second power transistor when the control input signal is made active; and A second gate discharge circuit for discharging the gate charge of the second power transistor to the source when the control input signal is made inactive.

11. An electronic control device, comprising: A microcontroller, a relay device, a battery, and a load; wherein the relay device includes: A positive power supply terminal and a negative power supply terminal coupled to the battery; A first power transistor and a second power transistor connected in series, wherein the breakdown voltage of the first power transistor is less than that of the second power transistor; A load driving terminal coupled to the load, wherein the source and back gate of the first power transistor are coupled to the positive power supply terminal, and the drain of the first power transistor is coupled to the load driving terminal via the second power transistor, wherein the source and back gate of the second power transistor are coupled to the load driving terminal, and the drain of the second power transistor is coupled to the positive power supply terminal; A first boost circuit for charging the gate of the first power transistor; A first gate discharge circuit for discharging the gate potential of the first power transistor to the source when the potential of the negative power supply terminal is higher than that of the positive power supply terminal; and A negative potential detection circuit for distinguishing a reverse connection of the power supply and the application of a negative surge at the power supply, and providing corresponding outputs to the first gate discharge circuit and the first boost circuit according to the distinguishing result, wherein the first gate discharge circuit includes an n-channel short-circuit transistor that shorts the gate of the first power transistor to the source when the potential of the negative power supply terminal is higher than that of the positive power supply terminal.

12. The electronic control device according to claim 11, wherein the negative potential detection circuit is configured to determine whether the negative potential applied to the positive power supply terminal is on the positive side or the negative side of a predetermined negative threshold potential with respect to the negative power supply terminal, and is configured to control the short-circuit transistor to conduct in a first case on the positive side, and is configured to control the short-circuit transistor to cut off in a second case on the negative side.

13. The electronic control device according to claim 12, wherein the negative potential detection circuit has a first resistor and a first Zener diode provided in series between the positive power supply terminal and the negative power supply terminal, and the negative potential detection circuit determines whether the negative threshold potential is on the positive side or the negative side by detecting the breakdown of the first Zener diode.

14. The electronic control device according to claim 12, wherein the negative potential detection circuit has a second Zener diode, one end of the second Zener diode being coupled to the positive power supply terminal, and wherein in the second case, a potential with respect to the potential of the positive power supply terminal at which the breakdown voltage of the second Zener diode is positive is applied to the gate of the first power transistor via a first boost circuit.

15. The electronic control device according to claim 12, wherein the first power transistor has a lower voltage withstand structure than the second power transistor.

16. The electronic control device according to claim 13, wherein the short-circuit transistor cuts off when the potential of the positive power supply terminal is applied to the gate during the active period of the control input signal, and wherein the relay device further has a capacitor that holds the gate potential of the short-circuit transistor during the active period of the control input signal during the inactive period of the control input signal.

17. The electronic control device according to claim 16, wherein the relay device further has a control transistor provided between the positive power supply terminal and the gate of the short-circuit transistor with its source and drain, wherein the gate of the control transistor is coupled to the gate of the first power transistor, the source of the control transistor is coupled to the first Zener diode, and wherein during the inactive period of the control input signal, the control transistor controls the gate of the short-circuit transistor to be in a high impedance state by being controlled to cut off.

18. The electronic control device according to claim 11, wherein the electronic control device is mounted on a vehicle.

19. A semiconductor device, comprising: a positive power supply terminal and a negative power supply terminal, coupled to a power supply; a first power transistor and a second power transistor connected in series; A load driving terminal is coupled to a load, wherein a source and a back gate of the first power transistor are coupled to the positive power supply terminal, and a drain of the first power transistor is coupled to the load driving terminal via the second power transistor, wherein a source and a back gate of the second power transistor are coupled to the load driving terminal, and a drain of the second power transistor is coupled to the positive power supply terminal; A first boost circuit for charging the gate of the first power transistor; A first gate discharge circuit is coupled between the gate and the source of the first power transistor for discharging the gate potential of the first power transistor to the source when the potential of the negative power supply terminal is higher than the potential of the positive power supply terminal; wherein the first gate discharge circuit is a parallel circuit composed of a first resistor and a diode, and the first resistor is configured to allow a gate discharge current smaller than the gate charging current generated when the first boost circuit turns on the first power transistor to pass through; wherein the first boost circuit includes a pMOS transistor and a second resistor serially coupled between the power supply and the load driving terminal, and a plurality of nMOS transistors and corresponding capacitors serving as a body of the boost circuit.

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