A self-recovery inversion unit structure

Abstract

The present invention relates to a self-recovery inverting unit structure, comprising a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube, realizing the function of outputting an input signal invertedly, and at the same time, if a single particle flip occurs at the output node OUT, due to the feedback characteristics of the first PMOS tube and the third NMOS tube themselves, the value of the output node OUT will be quickly corrected, and the feedback mechanism is only turned on when the output node of the self-recovery inverting unit is disturbed, further reducing the hardware and power consumption overhead of constructing a latch module. The present invention can be widely used in the structure of constructing a latch, and is used to realize the function of anti-single particle flip reinforcement. The present invention is suitable for fields with high requirements on the reliability and comprehensive overhead of the latch.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit anti-single particle upset reinforcement, and in particular to a self-recovery inversion unit structure. Background Art

[0002] With the rapid development of semiconductor technology, digital integrated circuits are increasingly susceptible to single-particle upsets caused by space radiation. Latches are basic sequential circuit units with storage structures, which work in space radiation environments for a long time. Inverters are the basic units that constitute latches. Therefore, it is of great significance to strengthen the inverters against single-particle upsets in order to improve the reliability of integrated circuits.

[0003] The main problems with the current structural design of inverters are: when a single-particle flip occurs at the output node of the inverter, the output node of the inverter will remain at an erroneous logic value and cannot achieve self-recovery from the single-particle flip. Or, although self-recovery from the single-particle flip at the output node can be achieved, there are problems such as large area overhead, high power consumption, transmission delay, and a relatively complex feedback mechanism. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a self-recovering inverting unit structure in view of the defects involved in the background technology.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] A self-recovery inverting unit structure, characterized by comprising a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube;

[0007] The source of the first PMOS tube is connected to an external power supply, the drain is connected to the source of the second PMOS tube, and the gate is respectively connected to the drain of the third PMOS tube, the drain of the first NMOS tube, and the gate of the third NMOS tube;

[0008] The gate of the second PMOS tube is connected to the gate of the first NMOS tube, and the drain is connected to the source of the third PMOS tube;

[0009] The gate of the second NMOS tube is connected to the gate of the third PMOS tube, the drain is connected to the source of the first NMOS tube, and the source is connected to the drain of the third NMOS tube;

[0010] The source of the third NMOS tube is grounded.

[0011] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0012] The output node is reinforced by using the feedback mechanism of the MOS tube. Once a single-particle upset occurs at the output node, its logic value will be quickly corrected, and the feedback mechanism is only turned on when the output node of the self-recovery inverting unit is disturbed, reducing the hardware and power consumption of the latch module. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a structural schematic diagram of the present invention;

[0014] Figure 2 It is the truth table of the present invention. DETAILED DESCRIPTION

[0015] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0016] The present invention can be implemented in many different forms and should not be considered to be limited to the embodiments described herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete, and will fully express the scope of the present invention to those skilled in the art. In the accompanying drawings, components are enlarged for clarity.

[0017] like Figure 1 As shown, the present invention discloses a self-recovery inverting unit structure, comprising a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube;

[0018] The source of the first PMOS tube is connected to an external power supply, the drain is connected to the source of the second PMOS tube, and the gate is respectively connected to the drain of the third PMOS tube, the drain of the first NMOS tube, and the gate of the third NMOS tube;

[0019] The gate of the second PMOS tube is connected to the gate of the first NMOS tube, and the drain is connected to the source of the third PMOS tube;

[0020] The gate of the second NMOS tube is connected to the gate of the third PMOS tube, the drain is connected to the source of the first NMOS tube, and the source is connected to the drain of the third NMOS tube;

[0021] The source of the third NMOS tube is grounded.

[0022] The working principle of the self-recovery inverting unit proposed in the present invention is described below. The specific working principle is as follows:

[0023] When the first signal input terminal I1 and the second signal input terminal I2 of the self-recovering inverting unit input the same logic value, the signal output terminal OUT will have the function of outputting the input signal inverted, that is, when the first signal input terminal I1 and the second signal input terminal I2 simultaneously input logic 0, the signal output terminal OUT will output logic 1; when the first signal input terminal I1 and the second signal input terminal I2 simultaneously input logic 1, the signal output terminal OUT will output logic 0.

[0024] When different logic values ​​are input to the first signal input terminal I1 and the second signal input terminal I2 of the self-recovering inverting unit, the signal output terminal OUT will maintain the current value unchanged, that is, when the first signal input terminal I1 inputs logic 0 and the second signal input terminal I2 inputs logic 1 or the first signal input terminal I1 inputs logic 1 and the second signal input terminal I2 inputs logic 0, the signal output terminal OUT will maintain the current value unchanged.

[0025] When a single-particle upset occurs at the output node OUT of the self-restoring inverting unit, the value of the output node OUT will be quickly corrected due to the feedback characteristics of the first PMOS tube and the third NMOS tube themselves, and the feedback mechanism is only turned on when the output node OUT of the self-restoring inverting unit is disturbed.

[0026] The truth table of the present invention is as follows: Figure 2 shown.

[0027] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0028] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A self-recovering inverting unit structure, characterized in that: It includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube; The source of the first PMOS tube is connected to an external power supply, the drain of the first PMOS tube is connected to the source of the second PMOS tube, and the gate of the first PMOS tube is respectively connected to the drain of the third PMOS tube, the drain of the first NMOS tube, and the gate of the third NMOS tube; The gate of the second PMOS tube is connected to the gate of the first NMOS tube, and the drain of the second PMOS tube is connected to the source of the third PMOS tube; The gate of the second NMOS tube is connected to the gate of the third PMOS tube, the drain of the second NMOS tube is connected to the source of the first NMOS tube, and the source of the second NMOS tube is connected to the drain of the third NMOS tube; The source of the third NMOS tube is grounded.

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