Fin Field-Effect Transistor Device

Abstract

Embodiments of the present invention illustrate the structure and formation method of a fin field-effect transistor device. The fin field-effect transistor device includes: a substrate; a fin located on the substrate; and a gate structure located on the fin. The gate structure includes a work function metal layer on the inner side sidewalls of the gate structure. The topmost surface of the work function metal layer is lower than the upper surface of the gate structure. The gate structure also includes a fill gate metal layer on the topmost surface of the work function metal layer. The upper surface of the fill gate metal layer is substantially coplanar with the upper surface of the gate structure. The gate structure also includes a self-assembled monolayer between the fill gate metal layer and the work function metal layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures, and more particularly to structures and methods for improving gate resistance. Background Art

[0002] Complementary metal oxide semiconductor field effect transistors serve as key components in the semiconductor industry and play important roles in various electronic devices. In semiconductor processes, metals and high-k dielectric materials are used to replace polysilicon and silicon oxide to form gate structures in transistors to meet performance requirements (such as carrier mobility and device speed) as transistor sizes are scaled down. To form a metal gate, a dummy gate may be first formed and then removed to create a space (such as a trench or a reserved position) for the metal gate. Then, a high-k dielectric material and a metal are deposited in the trench to fill the trench and form the metal gate. Summary of the Invention

[0003] A fin field effect transistor device provided by an embodiment of the present invention includes: a substrate; fins located on the substrate; and a gate structure located on the fins. The gate structure includes a work function metal layer located on the inner sidewalls of the gate structure, and the topmost surface of the work function metal layer is lower than the upper surface of the gate structure; a filling gate metal layer located on the topmost surface of the work function metal layer, and the upper surface of the filling gate metal layer is substantially coplanar with the upper surface of the gate structure; and a self-assembled monolayer located between the filling gate metal layer and the work function metal layer.

[0004] A method for forming a semiconductor device provided by an embodiment of the present invention includes: providing a substrate, and the substrate includes a gate structure having a work function metal layer; removing the top of the work function metal layer; forming a self-assembled monolayer on the topmost surface of the work function metal layer exposed by removing the top of the work function metal layer; and depositing a filling gate metal layer into the top from which the work function metal layer has been removed, and the self-assembled monolayer is located between the filling gate metal layer and the work function metal layer.

[0005] A method for forming a semiconductor device provided by an embodiment of the present invention includes: providing a substrate, and the substrate includes a gate structure; selectively removing the top of the gate structure; forming an adhesion layer on the upper surface of the gate structure exposed by removing the top of the gate structure; and selectively depositing a conductive layer into the top of the gate structure where the top has been removed and on the adhesion layer, and the adhesion layer bonds the upper surface of the gate structure exposed by removing the top of the gate structure and the conductive layer. Brief Description of the Drawings

[0006] Figure 1A are drawings of metal oxide semiconductor field effect transistor devices in some embodiments.

[0007] Figure 1B are some embodimentsFigure 1A Top view of the n-type metal oxide semiconductor device in

[0008] Figure 2 In some embodiments, it is a cross-sectional view of the gate.

[0009] Figures 3A to 3C 、 Figures 4A to 4C 、And Figures 5A to 5C In some embodiments, it is a cross-sectional view of the gate.

[0010] Figure 6 In some embodiments, it is a drawing of the manufacturing process in the gate for forming the gate metal back-etching.

[0011] Explanation of reference numerals:

[0012] h1, h2, h3 Vertical depth

[0013] H F Fin height

[0014] H G Gate height

[0015] Lg Gate length

[0016] L S Length

[0017] W Fin width

[0018] 100 Semiconductor structure

[0019] 102 Substrate

[0020] 104 Fin

[0021] 106 Isolation structure

[0022] 108 Gate structure

[0023] 108’, 108’-1, 108’-2, 108’-3 Intermediate gate structure

[0024] 110 D Drain region

[0025] 110 S Source region

[0026] 111 Spacer layer

[0027] 112 Channel region

[0028] 113 Lightly doped drain region

[0029] 114, 128 Upper surface

[0030] 115, 115’, 115” high dielectric constant dielectric layers

[0031] 116, 116’, 116” capping layers

[0032] 117 sacrificial gate structure

[0033] 117’ gate formation trench

[0034] 117A, 117B1, 117B2, 117C1, 117C2 etch-back trenches

[0035] 118, 118’, 118” barrier metal layers

[0036] 119, 119’, 119” work function metal layers

[0037] 120, 120’, 120” self-assembled monolayers

[0038] 121, 121’ filling gate metal layers

[0039] 125 gate dielectric layer

[0040] 128 dashed line

[0041] 131 cross-section line

[0042] 150 transistor region

[0043] 200, 300, 400, 500 structures

[0044] 600 method

[0045] 601, 602, 603, 604 steps Detailed implementation manners

[0046] The different embodiments or examples provided below can implement different structures of the present disclosure. Embodiments of specific components and arrangements are used to simplify the present disclosure rather than limit the present disclosure.

[0047] In addition, spatially relative terms such as “below”, “beneath”, “lower side”, “above”, “upper side” or similar terms can be used to simplify the description of the relative relationship between one element and another element in the drawings. Spatially relative terms can extend to elements used in other directions and are not limited to the directions shown in the drawings. The elements can also be rotated 90° or other angles, so the directional terms are only used to illustrate the directions in the drawings.

[0048] An example of the field effect transistor described herein is a metal oxide semiconductor field effect transistor. For example, the metal oxide semiconductor field effect transistor may be (i) a planar structure formed in or on a flat surface of a substrate such as a semiconductor wafer, or (ii) a vertical structure.

[0049] The term "fin field effect transistor" refers to a field effect transistor formed on a fin, and the fin is vertically oriented relative to the planar surface of the wafer.

[0050] "Source / drain" refers to the source / drain junction formed at both ends of the field effect transistor.

[0051] The term "vertical" described herein refers to being approximately perpendicular to the surface of the substrate.

[0052] The term "epitaxial layer" refers to a layer or structure of a single crystal material. Similarly, the term "epitaxial growth" refers to a layer or structure of a single crystal material. The material grown epitaxially may be doped or undoped.

[0053] The term "nominal" described herein refers to the desired target, characteristic value or parameter for a component or process step, which has been set during the design stage of the product, together with the upper and lower limit ranges of the set desired values. The range of values generally comes from slight variations or tolerances in the process.

[0054] One of the problems in forming a metal gate with a small gate length is how to deposit a sufficient amount of metal into the gate formation trench. For example, when the gate length of the metal gate is 7 nm, its gate resistance is higher than that of a metal gate with a gate length of 20 nm because the amount of metal deposited in the 7 nm metal gate is less. Similarly, the gate resistance of a 7 nm metal gate and a 20 nm metal gate is higher than that of a metal gate with a gate length of 240 nm.

[0055] To reduce the gate resistance, dry etch back and wet etch back can be used to remove part of the work function metal in the metal gate and fill more metal into the metal gate. However, the etch selectivity of the etch back method is low, which may cause metal loss in the etched metal gate. For example, in addition to the work function metal, the gate metal (such as tungsten) and the barrier layer (such as titanium nitride) may also be etched back, resulting in the depression depth in the etch back profile. The above steps may also reduce the gate height. In addition, the by-products formed during these etch back methods may be difficult to remove. These etch back methods do not provide the required etch selectivity between the work function metal and the gate metal. For example, a wet etching method can be used to etch back the gate metal. As a result, as semiconductor devices continue to shrink, it will become increasingly difficult to fabricate metal gates with the required low gate resistance.

[0056] Embodiments of the present invention illustrate selective back etching to remove a portion of the work function metal surrounding the metal in the metal gate. Subsequently, a conductive material with a relatively low or lower resistance is filled into the space formed by removing the work function metal to increase the metal volume in the metal gate. The selective back etching process can form one or more self-assembled monolayers on the etched portion. The self-assembled monolayers can improve the adhesion between the etched portion and the newly deposited filling gate metal. The newly deposited filling gate metal (such as a conductive material) can be deposited by selective deposition, which can include desired and / or different dopant concentrations and / or types to further improve (such as reduce) the gate resistance. The selective back etching and the selective deposition method do not require additional masks or additional manufacturing processes. Therefore, it substantially does not affect (such as reduce) the gate height, and more metal can be deposited into the metal gate. By using the method disclosed in the embodiments of the present invention, the metal gate can have more metal than at the beginning of fabrication, the gate resistance can be reduced, and the electrical properties of the semiconductor device can be improved. In addition, the newly deposited filling gate metal can adhere to the etched portion of the metal gate without voids or with a small number of voids formed therein. The formed gate metal can be more consistent, thus reducing the gate resistance. The method and structure of the embodiments of the present invention can improve device performance.

[0057] Figure 1A , Figure 1B , Figure 2 , Figures 3A to 3C , Figures 4A to 4C and Figures 5A to 5C are metal gates in various semiconductor devices fabricated by a method with improved gate resistance in embodiments of the present invention. The manufacturing process can form a metal gate with an increased amount of gate metal, which can have a lower gate resistance than other gate metal structures. The newly added gate metal according to the embodiments disclosed herein can adhere to the portion in contact with the filling gate metal (without voids or with a small number of voids therein). The term "filling gate metal" refers to the conductive material subsequently deposited into the removed portion of the work function metal layer and can serve as the gate metal of the metal gate structure. Embodiments of the present invention can be used to form metal gates of various metals (such as tungsten, copper, aluminum, any other suitable metal, or a combination thereof). The metal gate can be formed in various semiconductor devices and structures. For example, embodiments of the present invention can be used to form metal gates in planar devices and fin field-effect transistors. The manufacturing processes provided herein are only illustrative, and other processes performed in the embodiments of the present invention are not shown in the subsequent drawings.

[0058] Figure 1AIs an isometric view of a semiconductor structure 100 in some embodiments of the present invention. The semiconductor structure 100 includes fin field-effect transistors. The semiconductor structure 100 includes a substrate 102, a plurality of fins 104, a plurality of isolation structures 106, and a gate structure 108 located on the sidewalls and upper surfaces of each fin 104. The fins 104 and the isolation structures 106 have upper surfaces 114 and 128 respectively. The gate structure 108 includes a gate dielectric layer 125 and a sacrificial gate structure 117. In some embodiments, one or more additional layers or structures may be included in the gate structure 108. Figure 1A Is an isometric view of the structure after patterning the gate dielectric layer and the gate layer to form the gate structure 108. Figure 1A Only shows a single gate structure 108. An integrated circuit may include a plurality of gate structures.

[0059] Figure 1A Each fin 104 shown includes a pair of source / drain terminals. For simplicity of illustration, the first of the pair of source / drain terminals is referred to as the source region 110 S and the second of the pair of source / drain terminals is referred to as the drain region 110 D where the source / drain terminals are formed in, on top of, and / or around the fin 104. The channel region 112 of the fin 104 is located under the gate structure 108. The gate structure 108 has a gate length Lg and a gate width (2H F +W), as Figure 1A shown. In some embodiments, the fin width W is between about 6 nm and about 12 nm. In some embodiments, the fin width W is between about 4 nm and about 6 nm. In some embodiments, the gate structure 108 has a gate height H from the upper surface 114 of the fin to the upper surface of the gate structure 108 G which is between about 50 nm and about 80 nm. In some embodiments, the fin 104 has a fin height H from the upper surface 128 of the isolation structure to the upper surface 114 of the fin F which is between about 25 nm and about 35 nm.

[0060] The substrate 102 may be a silicon substrate. In other embodiments, the substrate 102 may include other semiconductor elements such as germanium, semiconductor compounds (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), semiconductor alloys (including silicon germanium, gallium phosphoarsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, and / or gallium phosphoindium arsenide), or combinations thereof. In some embodiments, the substrate 102 is a semiconductor-on-insulator. In some embodiments, the substrate 102 may be an epitaxial material.

[0061] The isolation structure 106 includes a dielectric material, which may be composed of silicon oxide, spin-on glass, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, a low dielectric constant dielectric material, and / or other suitable insulating materials. The isolation structure 106 may be a shallow trench isolation structure. In some embodiments, the isolation structure 106 is a shallow trench isolation structure, and its forming method is to etch trenches in the substrate 102. Then, an insulating material can be filled into the trenches, followed by chemical mechanical polishing planarization and back etching. In addition, other manufacturing techniques can also be used to form the isolation structure 106 and / or the fin 104. The isolation structure 106 may include a multi-layer structure, such as having one or more liner layers.

[0062] The fin 104 is the active region where one or more transistors are located. The fin 104 may include silicon or another semiconductor element such as germanium, a semiconductor compound (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, and / or gallium arsenide phosphide indium), or a combination of the above. The manufacturing method of the fin 104 can adopt any suitable process, including photolithography and etching processes. The photolithography process may include forming a photoresist layer on the substrate (such as on a silicon layer), exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a photoresist-containing mask unit. Then, the mask unit can be used to protect the area of the substrate during the etching process of forming a depression into the isolation structure 106, and a raised fin is left. The method of etching the depression can adopt reactive ion etching and / or other suitable processes. A variety of other methods can be used to form the fin 104 on the substrate 102. In some embodiments, the fin 104 may include epitaxial material.

[0063] Figure 1A The shown gate structure 108 may be a sacrificial gate structure in a replacement gate process, which can be replaced by a metal gate structure. Before the replacement process, the sacrificial gate structure 117 may include a sacrificial material such as polysilicon. The replacement process can remove the sacrificial material and fill the trenches, spaces, and / or openings formed by removing the sacrificial material with a conductive material (such as a metal) to form a metal gate structure. The spacer layer 111 can be retained during the replacement process and maintain the space for depositing the conductive material. Then, the conductive material can be deposited into the space maintained by the spacer layer 111 to form a metal gate structure. The method of forming the metal gate structure will be described in detail below.

[0064] The semiconductor structure 100 includes fins 104 and a gate structure 108. The semiconductor structure 100 may include various structures of transistors employing the semiconductor structure 100 formed by additional processes, such as lightly doped drain regions and doped source / drain structures. A lightly doped drain region may be formed in the fin 104 by doping, and the term "lightly doped drain region" refers to a lightly doped region between the channel region of a transistor and at least one source / drain region. The doping process may be carried out by ion implantation. Embodiments of the present invention are not limited to ion implantation as the doping process for the lightly doped drain region.

[0065] Figure 1B is a top view of a transistor region 150 of one of the fins 104 having Figure 1A the surface height along the upper surface 128 of the isolation structure 106. The transistor region 150 includes a source region 110 S and a drain region 110 D . The transistor region 150 also includes a channel region 112, which is part of the fin 104, and the gate structure 108 surrounds the fin 104 on three sides, as Figure 1A shown. The channel region 112 under the gate structure 108 has a width (fin width W). The length of the channel region 112 may be slightly different from the gate length Lg, depending on the conditions of the manufacturing process and the device design. For simplicity of illustration, the length of the channel region 112 is labeled as the gate length Lg. The transistor region 150 also includes a gate dielectric layer 125 and a sacrificial gate structure 117. Figure 1B Also shown is a spacer layer 111 formed on the gate structure 108. The lightly doped drain region 113 is formed in the upper surface and sidewalls of the fin 104. Figure 1B The lightly doped drain region 113 shown in S has a width (fin width W) and a length L Figure 1B . The boundary of the lightly doped drain region 113 may or may not be aligned with the spacer layer 111 (along the Figure 1B surface height shown). Figure 1A Another gate structure 108 is also shown in dashed lines. Other gate structures 108 have been described above, which are parallel and similar to the above-described gate structure 108 and are not shown in

[0066] Figure 1BShow the spacer layer 111 between the sacrificial gate structures 117 surrounding the gate structure 108. The method of forming the spacer layer 111 can be any suitable method. For example, a conformal spacer layer is first deposited on the substrate, including on the gate structure 108. Then, a part of the conformal spacer layer can be removed by a re-etching process to expose a part of the source / drain region for ion implantation. Then, a part of the conformal spacer layer on the gate structure 108 is removed. The remaining conformal spacer layer forms the spacer layer 111, which is at least located on the sidewalls of the dummy gate structure 117. The spacer layer 111 can include a dielectric material, such as silicon oxide, silicon oxynitride, silicon carbonitride, silicon nitride, any other suitable material, or any combination of the above. In some embodiments, the deposition process is a plasma-enhanced chemical vapor deposition process, but other feasible deposition processes can also be used. In some embodiments, the thickness of the spacer layer 111 is between about 2 nm and about 14 nm. The thickness of the spacer layer 111 can provide a distance deviated from the lightly doped drain region and prevent dopants from being implanted into the channel region 112.

[0067] Then, using any suitable process, a lightly doped drain region 113 is formed in the fin 104 between adjacent spacer layers 111. For example, an ion implantation process can be used to form the lightly doped drain region 113, which can use any suitable dopant species. Although the lightly doped drain region 113 in the drawings is adjacent to the upper surface of the fin 104, the lightly doped drain region 113 can be adjacent to both the upper surface and the sidewalls of the fin 104. The lightly doped drain implantation can be performed vertically or obliquely toward the sidewalls of the fin. The lightly doped drain region 113 can extend to a depth below the surface of the fin 104, depending on the implantation process. For example, the lightly doped drain region 113 can extend to a depth below the upper surface of the fin 104. In other embodiments, the lightly doped drain region 113 can extend from the sidewall surface of the fin 104 into the interior of the fin 104. The substrate 102 can have p-type and n-type devices. Additional processes, such as a lithography patterning process, can be used to protect the p-type device regions from being affected by dopant ions used in the n-type device regions. After implanting the dopant ions, a thermal annealing can be performed to drive in and activate the dopants. The thermal annealing can be a rapid thermal processing annealing, spike annealing, microsecond annealing, laser annealing, any other suitable annealing process, or any combination of the above. Spike annealing is operated at the spike annealing temperature for a period of time (in seconds). Microsecond annealing is operated at the spike annealing temperature for a period of time (in microseconds). Laser annealing is operated at the spike annealing temperature for a period of time (from nanoseconds to microseconds).

[0068] In addition, any suitable process can be used to form the source region 110 S / drain region 110 DA lightly doped drain region 113 in the fin 104 between adjacent spacer layers 111. For example, any suitable doping species can be used for ion implantation to form the source region 110 S / drain region 110 D . In another example, a portion of the lightly doped drain region 113 between adjacent spacer layers 111 is removed, and an epitaxial process is performed to grow a suitable source / drain material between the adjacent spacer layers 111. In-situ doping with any suitable dopant can be used to make the source region 110 S / drain region 110 D have any suitable doping level. Depending on different applications and / or embodiments, the source region 110 S / drain region 110 D The depth from the upper surface 114 can be greater than or less than the depth of the lightly doped drain region 113. The source region 110 S / drain region 110 D The lateral width of can be less than, equal to, or greater than the lateral width of the lightly doped drain region 113, depending on the application.

[0069] Figures 2 to 5C are different cross-sectional views of various stages of fabricating a fin field-effect transistor in various embodiments of the present invention. The method provided by the embodiments of the present invention can be part of a gate replacement process or after a gate replacement process. In the embodiments of the present invention, the metal gate structure formed by the method disclosed in the embodiments of the present invention can be referred to as an intermediate gate structure 108'. Figure 1A And 1B The gate structure 108 shown can also be referred to as a sacrificial gate structure, and Figure 1A And 1B The sacrificial gate structure 117 shown can also be referred to as a gate structure. The intermediate gate structure 108' can be formed based on the gate structure 108.

[0070] Figures 2 to 5C shows an exemplary fabrication process for forming this metal gate structure. In some embodiments, the substrate 102 includes silicon. In the embodiments of the present invention, structures of different sizes (such as intermediate gate structures 108' with different gate lengths) are arranged in the same drawing for illustrative purposes. The sizes of these structures in the drawings do not represent the actual sizes of the structures. For illustrative purposes, Figures 2 to 5C The structure shown is a cross-sectional view of a semiconductor structure along Figure 1A The section line 131 or a section line along a similar direction. The semiconductor structure can be formed in the same or different integrated circuits. The semiconductor structure can be formed via the same or different fabrication processes.

[0071] Figure 2 In some embodiments, the structure 200 including the exemplary intermediate gate structure 108' alongFigure 1A An accompanying drawing of the cross - hatched line 131 shown. An intermediate gate structure 108' can be formed based on the gate structure 108, which includes a gate - forming trench 117' surrounded by a spacer layer 111. The gate length (Lg) of the subsequently formed metal gate structure is defined as the lateral length of the metal gate subsequently formed between the source and drain regions, as Figure 2 shown. After removing the sacrificial gate structure 117, an intermediate gate structure 108' can be formed from the gate structure 108. After removing the sacrificial gate structure 117, a gate - forming trench 117' can be formed. The method of removing the sacrificial gate structure 117 can include removing the sacrificial gate material (such as polysilicon) from the gate structure 108 to form the gate - forming trench 117'. The spacer layer 111 can be retained on the fin 104 and can be used to retain the space required for depositing other layers in the intermediate gate structure 108' and to protect the subsequently formed metal gate structure. The intermediate gate structure 108' can be used to represent a partially formed gate structure with any suitable gate length Lg.

[0072] Methods for removing the sacrificial gate structure 117 may include any suitable process. For example, a patterning process (such as photolithography) and a subsequent etching process (such as wet etching or dry etching process) may be used to remove the sacrificial material surrounded by the spacer layer 111. During the patterning process and the etching process, one or more hard masks may be formed on the gate structure 108 to expose the sacrificial material and protect the spacer layer 111. The etching process may be a selective etching or a time-controlled etching, so that the sacrificial material can be completely removed. In some embodiments, the selective etching does not require an additional etching mask. For example, the selective etching can be directly directed to the semiconductor structure 100. The details of the removal process and the related masks are not described in detail herein. The channel region 112 may be formed under the gate structure 108 before forming the gate structure 108 or after removing the sacrificial gate structure 117. The dashed line 128 refers to the upper surface height of the isolation structure 106. The gate dielectric layer 125 may be formed as part of the gate structure 108, or the gate dielectric layer 125 may be formed after forming the gate-forming trench 117'. Any suitable process may be used to form the gate dielectric layer 125. For example, the gate dielectric layer may include silicon nitride, silicon oxide, silicon carbonitride, silicon carbon oxynitride, any other suitable material, or any combination of the above. In another example, the gate dielectric layer 125 may also include hafnium oxide, zirconium oxide, lanthanum oxide, and / or other suitable high-k dielectric materials, and the deposition method may be plasma-enhanced chemical vapor deposition, chemical vapor deposition, physical vapor deposition, and / or atomic layer deposition. The gate dielectric layer can reduce the reaction between the substrate material in the fin 104 and the subsequently formed high-k dielectric layer, and maintain the reliability of the semiconductor structure 100 to maintain the carrier mobility in the channel region 112. In some embodiments, after forming the gate-forming trench 117', the gate dielectric layer 125 is formed by plasma-enhanced chemical vapor deposition. In some embodiments, the gate dielectric layer 125 includes silicon oxide, and its thickness is between about to between.

[0073] Figures 3A to 3C Structure 300 in some embodiments includes exemplary intermediate gate structures 108'-1, 108'-2, and 108'-3 with different gate lengths. Figures 3A to 3C Each along Figure 1A the cross-section line 131 shown. Figures 3A to 3C The intermediate gate structure 108' shown can each be formed by Figure 2formed by the gate structure 108 shown. For the purpose of illustrating the methods and structures of embodiments of the present invention, the gate lengths of the intermediate gate structures 108'-1, 108'-2, and 108'-3 are different from each other. In some embodiments, the gate length Lg of the intermediate gate structure 108'-1 < the gate length Lg of the intermediate gate structure 108'-2 < the gate length Lg of the intermediate gate structure 108'-3. For example, the gate length Lg of the intermediate gate structure 108'-1 can be 7 nm, the gate length Lg of the intermediate gate structure 108'-2 can be 20 nm, and the gate length Lg of the intermediate gate structure 108'-3 can be 240 nm.

[0074] In some embodiments, intermediate gate structures (such as Figure 2 the intermediate gate structure 108' shown) with similar structures (such as different sizes and / or different gate lengths) can be used to respectively form Figures 3A to 3C the intermediate gate structures 108'-1, 108'-2, and 108'-3 shown. Multiple layers can be sequentially deposited into the gate formation trench 117' to form Figure 2 the intermediate gate structures 108'-1, 108'-2, and 108'-3 shown from Figures 3A to 3C the intermediate gate structure 108' shown. The subsequently formed metal gate structure can include a barrier layer, a gate dielectric layer, a work function layer, a metal layer, and / or other suitable materials filled in the gate formation trench. In other embodiments, the metal gate structure can further include a capping layer, an etch stop layer, and / or other suitable materials. The spacer layer 111 can include a dielectric material such as silicon nitride, silicon carbonitride, silicon carbonitride, other suitable insulating materials, or any combination of the above. For illustrative purposes, the gate dielectric layer 125 in different drawings of embodiments of the present invention refers to the gate dielectric layer at the bottom of the metal gate structure. However, the gate dielectric layer 125 can include the same or different materials in different structures.

[0075] A high-k dielectric layer can be first formed on the sidewalls of the spacer layer 111 and the gate dielectric layer 125 in the gate formation trench 117'. The high-k dielectric layer can form a barrier between the channel region 112 and the subsequently formed metal gate to avoid leakage current in the channel region 112 and reduce the power consumption of the semiconductor structure 100. In some embodiments, the high-k dielectric layer can include hafnium oxide, zirconium oxide, lanthanum oxide, other suitable materials, or any combination of the above. The method for forming the high-k dielectric layer can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, other suitable deposition methods, or any combination of the above. In some embodiments, the thickness of the high-k dielectric layer is between about 5 nm and about 15 nm. In the embodiments of the present invention, the intermediate gate structures 108'-1, 108'-2, and 108'-3 respectively have high-k dielectric layers 115, 115', and 115".

[0076] A capping layer can be formed on the high-k dielectric layer in the gate formation trench 117'. In one example, the capping layer can include a high-k barrier material, such as titanium nitride and / or TSN. In another example, the capping layer can protect the high-k dielectric layer from the influence of the subsequently formed barrier metal layer and can reduce the interface traps between the gate dielectric layer 125 and the substrate 102. The method for forming the capping layer can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, metalorganic chemical vapor deposition, sputtering, other suitable deposition methods, or any combination of the above. The thickness of the capping layer can be between about 1 nm and about 3 nm. In some embodiments, the capping layer is about 1.5 nm. In the embodiments of the present invention, the intermediate gate structures 108'-1, 108'-2, and 108'-3 respectively have capping layers 116, 116', and 116".

[0077] A barrier metal layer can be further formed on the capping layer in the gate formation trench 117'. The barrier layer can include a barrier metal and / or compound, such as tantalum nitride and / or niobium nitride. The barrier metal layer can improve the adhesion between the capping layer and the subsequently formed work function metal layer. The barrier metal layer can also prevent carrier and / or ion diffusion between the capping layer and the work function metal layer. The method for forming the barrier metal layer can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, metalorganic chemical vapor deposition, sputtering, other suitable deposition methods, or any combination of the above. The thickness of the barrier metal layer can be between about 1 nm and about 3 nm. In some embodiments, the thickness of the barrier metal layer is about 1.5 nm. In the embodiments of the present invention, the intermediate gate structures 108'-1, 108'-2, and 108'-3 respectively have barrier metal layers 118, 118', and 118".

[0078] A work function metal layer may also be formed on the barrier metal layer in the gate formation trench 117'. Exemplary p-type work function metals that may be included in the metal gate structure include titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals that may be included in the metal gate structure include titanium, silver, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable n-type work function materials, or combinations thereof. The work function is related to the material composition of the work function layer, so the material of the first work function layer can be selected to adjust its work function to achieve the critical voltage required for the device to be formed in the individual region. In some embodiments, the work function metal layer may include a work function metal such as titanium nitride, titanium aluminum nitride, titanium aluminum carbide, other suitable work function metals, or any combination thereof. The work function metal layer can change the critical voltage of the intermediate gate structure 108' to the desired value. The method for forming the work function metal layer may be chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, metalorganic chemical vapor deposition, sputtering, other suitable deposition methods, or any combination thereof. In some embodiments, the thickness of the work function metal layer is between about 1 nm and about 3 nm. In the embodiments of the present invention, the intermediate gate structures 108'-1, 108'-2, and 108'-3 each have a work function metal layer 119, 119', and 119".

[0079] A fill gate metal (such as a gate metal layer) may be further formed on the work function metal layer in the gate formation trench 117'. The fill gate metal layer can fill the remaining space in the gate formation trench 117'. The fill gate metal layer may include suitable conductive materials such as copper, aluminum, and / or tungsten. In some embodiments, the fill gate metal layer includes tungsten. The method for forming the fill gate metal layer may be chemical vapor deposition, physical vapor deposition, plasma enhanced chemical vapor deposition, metalorganic chemical vapor deposition, sputtering, other suitable deposition methods, or any combination thereof. In some embodiments, the thickness of the fill gate metal layer is between about 1 nm and 3 nm. In the embodiments of the present invention, the intermediate gate structures 108'-2 and 108'-3 each have a fill gate metal layer 121 and 121'. In some embodiments, the intermediate gate structure 108'-1 has a small amount of gate metal or no gate metal, as Figure 3A shown. The reason for the lack of gate metal in the intermediate gate structure 108'-1 may include a small gate length and a lack of space for depositing the gate metal after forming the work function metal layer 119. As Figure 3AAs shown, the work function metal layer 119 can fill the remaining space in the gate formation trench 117' after the deposition barrier metal layer 118. In addition, since the gate length of the middle gate structure 108'-2 is less than that of the middle gate structure 108'-3, less gate metal is deposited in the middle gate structure 108'-2 than in the middle gate structure 108'-3.

[0080] In some embodiments, after forming the above-mentioned layers, a planarization process such as chemical mechanical polishing can be employed to remove the excess thickness of these layers on the spacer layer 111. The upper surface of the gate formation trench 117' can be planarized. In this way, the upper surfaces of the spacer layer 111, the high-k dielectric layer, the capping layer, the barrier metal layer, the work function metal layer, and the filled gate metal layer can be coplanar with each other. For illustrative purposes, the semiconductor structure formed after the planarization process is referred to as the middle gate structure 108'. In various embodiments, other planarization and / or etching processes can also be employed to form the middle gate structures 108'-1, 108'-2, and 108'-3.

[0081] As Figures 3A to 3C shown, the high-k dielectric layers 115, 115', and 115", the capping layers 116, 116', and 116", and the barrier metal layers 118, 118', and 118" each form a U-shaped structure (such as a view along the section line 131 or the x-y plane) in the gate formation trench 117' of each of the middle gate structures 108'-1, 108'-2, and 108'-3. Due to the gate length difference, the work function metal layers 119' and 119" in the middle gate structures 108'-2 and 108'-3 each form a U-shaped structure in the respective gate formation trench 117', while the work function metal layer 119 in the middle gate structure 108'-1 can form a vertical strip structure (along the y-axis) in the gate formation trench 117'. In summary, for the middle gate structure 108'-1, the topmost side surface of the work function metal layer 119 can be substantially coplanar with the upper surface of the middle gate structure 108'-1. For the middle gate structures 108'-2 and 108'-3, the topmost side surfaces of the work function metal layers 119' and 119" can be substantially coplanar with the upper surfaces of the middle gate structures, respectively.

[0082] As Figures 3A to 3CAs shown, the amount of the filling gate metal layer 121 deposited in the intermediate gate structure with a smaller gate length (such as the intermediate gate structure 108'-2) is less than that deposited in the intermediate gate structure with a larger gate length (such as the intermediate gate structure 108'-3). In particular, for some intermediate gate structures with a small gate length (such as the intermediate gate structure 108'-1), no gate metal can be deposited in the gate formation trench 117'. In this way, as the technology node evolves, it becomes increasingly difficult to deposit sufficient gate metal in the metal gate structure. The gate resistance of the metal gate structure can increase as the amount of the gate metal decreases. Therefore, the gate resistance can increase from the intermediate gate structure 108'-1 to the intermediate gate structure 108'-3. Figures 4A to 5C An embodiment for showing a method of improving the gate resistance of different intermediate gate structures.

[0083] Figures 4A to 4C Show the structure 400 in some embodiments, which includes exemplary intermediate gate structures 108'-1, 108'-2, and 108'-3 with different gate lengths. Figures 4A to 4C Along Figure 1A The cross-section line 131 shown. In some embodiments, the top of the work function metal layer in each of the intermediate gate structures 108'-1, 108'-2, and 108'-3 is back-etched to a desired depth to form a back-etched trench from the topmost side surface of the work function metal layer that is exposed. As Figures 4A to 4C Shown, in the intermediate gate structure 108'-1, the back-etched trench 117A is formed in the work function metal layer 119 and has a vertical depth (or recess depth) h1. In the intermediate gate structure 108'-2, the back-etched trenches 117B1 and 117B2 are formed in the work function metal layer 119' and each has a vertical depth h2 (along the y-axis). In the intermediate gate structure 108'-3, the back-etched trenches 117C1 and 117C2 are formed in the work function metal layer 119'' and each has a vertical depth h3. In some embodiments, the vertical depth of the back-etched trenches in each work function metal layer can vary between about 40 nm and about 50 nm, and the vertical depths h1, h2, and h3 can be the same or different. For illustrative purposes, it is assumed that the back-etched trenches in the same gate formation trench generally have the same depth (such as the vertical depths h1, h2, and h3). In some embodiments, the vertical depths h1, h2, and h3 are less than the vertical length of the individual work function metal layer and can be about 40 nm.

[0084] In some embodiments, the top of the work function metal layer in the intermediate gate structure 108' is removed and a re-etch trench is formed. The above steps may expose the inner surface of the etched portion. For example, for the re-etch trench 117A of the intermediate gate structure 108'-1, the topmost surface of the etched work function metal layer 119 and the sidewall surface of the barrier metal layer 118 may be exposed. For the re-etch trenches 117B1 and 117B2 of the intermediate gate structure 108'-2, the topmost surface of the etched work function metal layer 119', a portion of the sidewall surface of the filled gate metal layer 121, and a portion of the sidewall surface of the barrier metal layer 118' may be exposed. For the re-etch trenches 117C1 and 117C2 of the intermediate gate structure 108'-3, the topmost surface of the etched work function metal layer 119", a portion of the sidewall surface of the filled gate metal layer 121', and a portion of the sidewall surface of the barrier metal layer 118" may be exposed. The exposed surfaces may contact the subsequently deposited filled gate metal (such as the gate metal deposited in a subsequent process to fill the re-etch trench).

[0085] In some embodiments, a suitable etching process may be employed for the re-etch process. In some embodiments, wet etching is performed to selectively etch the top of the individual work function metal layers. In some embodiments, the etchant (such as an etching solution) may selectively etch the work function metal layer on other layers and / or materials in the gate formation trench 117'. For example, the etching selectivity of the etchant on the gate metal (such as the ratio of the etching rates) may be at least about 2, and / or the etching selectivity on the high-k dielectric material may be at least about 2. In some embodiments, the etching selectivity on the gate metal is at least about 3. The etching selectivity on other layers and / or materials may be as high as desired, so that after selective etching, the top of the work function metal layer can be removed while the other layers in the gate formation trench 117' may remain substantially the same thickness, height, and / or shape.

[0086] An etchant can be dispensed onto a wafer or semiconductor structure 100 that needs to be processed under suitable conditions. The etchant can include phosphoric acid, which can be mixed with other etchants and / or additives. In some embodiments, the etchant includes a mixture of hydrogen peroxide, phosphoric acid, and hot deionized water. In some embodiments, the fill gate metal layer contains tungsten and the work function metal layer includes titanium nitride, and the weight ratio of phosphoric acid:hydrogen peroxide:hot deionized water is about 10:1:1.5, and the etch selectivity is about 5 (for example, the etch rate of the work function metal layer is about five times that of the fill gate metal layer). In some embodiments, the weight ratios of hydrogen peroxide, phosphoric acid, and hot deionized water can be varied to adjust the etch selectivity and / or etch rate on the same or different materials. For example, when the fill gate metal layer and / or the work function metal layer contain other materials, the weight ratio of phosphoric acid:hydrogen peroxide:hot deionized water can be varied. In some embodiments, other acidic media or solutions can be mixed into the mixture to obtain different etch selectivities, etch rates, and / or pH control. For example, hydrogen chloride can be added to the mixture to adjust the pH value of the etchant. The etch conditions and / or parameters (such as etch time and etchant temperature) can be controlled to obtain the desired vertical depth of the etched trench. For example, when the etch selectivity is about 5 and a vertical depth of about 40 nm is desired, the etch time of the semiconductor structure 100 can be about 360 seconds, and the etch temperature can be between room temperature and about 80 °C. In some embodiments, increasing the etchant temperature can increase the etch rate and thus reduce the etch time.

[0087] In some embodiments, after the etching process, a wet solution can be used to rinse the semiconductor structure 100 or the wafer. In some embodiments, the rinse solution is a mixture of pure deionized water, deionized water containing carbon dioxide, diluted ammonium hydroxide, any other suitable rinse solution, or any combination of the above. Any suitable method can be used to dry the rinsed semiconductor structure 100 or wafer. In some embodiments, the drying process includes nitrogen spin drying and / or isopropyl alcohol drying. The drying temperature of the drying process can be between room temperature and about 100 °C.

[0088] When the etchant reacts with the work function metal layer and / or other layers of the intermediate gate structure 108' (such as the fill gate metal layer and / or the barrier metal layer), it can be used to form a self-assembled monolayer. In some embodiments, the etchant helps to form a self-assembled monolayer when reacting with the fill gate metal, the work function metal layer, and the barrier metal layer, and the self-assembled monolayer after the etching process can cover the exposed surfaces of these layers. As Figures 4A to 4CAs shown, self-assembled monolayers 120, 120', and 120'' are formed after selective etching. After selective etching, the self-assembled monolayers can cover the topmost exposed surface of the work function metal layer, the upper surface and sidewall surfaces of the filled gate metal layer that are exposed, and the topmost exposed surface of the barrier metal layer. For example, for the middle gate structure 108'-1, the self-assembled monolayer can cover the topmost exposed surface of the etched work function metal layer 119 and the upper surface and sidewall surfaces of the barrier metal layer 118 that are exposed. For the middle gate structure 108'-2, the self-assembled monolayer can cover the topmost exposed surface of the etched work function metal layer 119', the upper surface and sidewall surfaces of the filled gate metal layer 121 that are exposed, and the upper surface and sidewall surfaces of the barrier metal layer 118' that are exposed. For the middle gate structure 108'-3, the self-assembled monolayer can cover the topmost exposed surface of the etched work function metal layer 119'', the upper surface and sidewall surfaces of the filled gate metal layer 121' that are exposed, and the upper surface and sidewall surfaces of the barrier metal layer 118'' that are exposed. The self-assembled monolayer can serve as an adhesion layer, and then can bond and / or adhere to the filled gate metal in the etch trenches (such as etch trenches 117A, 117B1, 117B2, 117C1, and 117C2), and improve the contact and / or adhesion between the filled gate metal and the materials in the etch trenches.

[0089] Specifically, the self-assembled monolayer can be formed between the phosphate and the materials of the middle gate structures 108'-1, 108'-2, and 108'-3 (such as the materials of the work function metal layer, the filled gate metal layer, and / or the barrier metal layer). For example, the phosphate can form a self-assembled monolayer with the metal oxides in these layers. In some embodiments, the metal layer includes tungsten, the work function metal layer includes titanium nitride, and the barrier metal layer includes tantalum nitride. The phosphate can then react with titanium oxide in the work function metal layer to form a self-assembled monolayer of titanium phosphate on the exposed surface of the work function metal layer, react with tantalum oxide in the barrier metal layer to form a self-assembled monolayer of tantalum phosphate on the exposed surface of the barrier metal layer, and react with tungsten oxide in the filled gate metal layer to form a self-assembled monolayer of tungsten phosphate on the exposed surface of the filled gate metal layer. In the embodiments of the present invention, the term "self-assembled monolayer of metal phosphate" is only for convenience of description to distinguish different chemical compounds, rather than indicating the chemical composition or chemical formula of the compound.

[0090] Self-assembled monolayers can cover materials reactive with phosphates. In some embodiments, the etchant composition can be selected to match the material being etched and / or the exposed material, so that the self-assembled monolayer can completely cover the inner surface of the re-etched trench. The self-assembled monolayer can improve the adhesion between the subsequently deposited fill gate metal and the re-etched trench, so that the fill gate metal can fill the re-etched trench with little or no void. In summary, the amount of gate metal in the subsequently formed metal gate structure can be increased, and the gate resistance can be reduced. In some embodiments, the self-assembled monolayer is formed on the work function metal layer to improve the adhesion between the fill gate metal and the work function metal layer. In some embodiments, the self-assembled monolayer is formed on the fill gate metal layer, which can improve the adhesion between the fill metal and the gate metal, so that no voids are formed between the fill metal and the gate metal. In some embodiments, the resistance of the self-assembled monolayer is low enough or negligible, so that the presence of the self-assembled monolayer only has a little or no effect on the conductivity of the fill gate metal layer and the fill gate metal. In various embodiments, other suitable materials can also be used to form the work function metal layer, the fill gate metal layer, and / or the metal barrier layer. The etchant composition can be changed to ensure that the self-assembled monolayer (having an adhesive function to bond the fill gate metal to the work function metal layer) is formed at least on the work function metal layer. The specific selection of the etchant composition is not limited to the embodiments of the present invention.

[0091] In some embodiments, the work function metal layer can be re-etched by other methods. For example, a planarization process can be used to expose the topmost surface of the work function metal layer in the intermediate gate structure 108' and a mask can be used to cover the topmost surfaces of other layers. In summary, the top of the work function metal layer can be removed by a suitable etching (such as a wet and / or dry etching process with controlled time). The mask can be removed after re-etching. Optionally, any suitable method can be used to form an adhesive layer (such as a liner layer or a self-assembled monolayer) on the inner surfaces of the re-etched trenches 117A, 117B1, 117B2, 117C1, and 117C2. For example, the re-etched trenches can be rinsed with a suitable acidic solution (such as a sulfuric acid-based solution) to form the adhesive layer in the re-etched trenches. The adhesive layer can be in any suitable form, such as a monolayer or a thin film. The resistance of the adhesive layer is low enough, so that the presence of the adhesive layer only slightly affects or does not affect the conductivity of the fill gate metal layer and the fill gate metal.

[0092] Figures 5A to 5C Shows the structure 500 in some embodiments, which includes exemplary intermediate gate structures 108'-1, 108'-2, and 108'-3 with different gate lengths. Figures 5A to 5C Along Figure 1A the indicated section line 131. As Figures 5A to 5CAs shown, the fill gate metal (which has the same pattern as the fill gate metal layer in the drawings) can be deposited into the recessed etch trenches to contact the fill gate metal layer. The self-assembled monolayers formed in each of the intermediate gate structures 108'-1, 108'-2, and 108'-3 can improve the adhesion and / or bonding between the fill gate metal and the fill gate metal layer, the adhesion and / or bonding between the fill gate metal and the work function metal layer, and / or the adhesion and / or bonding between the fill gate metal and the barrier metal layer. In some embodiments, the doping level of the fill gate metal is higher than the doping level of the fill gate metal layer. In some embodiments, the fill gate metal is formed via a suitable deposition method such as chemical vapor deposition, atomic layer deposition, or a similar method, and the fill gate metal is doped in-situ, so that the desired doping level and dopant species can be formed in the fill gate metal to further reduce the resistance of the subsequently formed metal gate structure.

[0093] In some embodiments, the fill gate metal is deposited via a selective deposition method and the fill gate metal is doped in-situ during the selective deposition. In some embodiments, the fill gate metal layer includes tungsten, and the fill gate metal includes tungsten. The selective deposition method for forming tungsten can include atomic layer deposition. In some embodiments, tungsten pentachloride gas and hydrogen precursor gas can be used for the atomic layer deposition process. Solid tungsten can be selectively formed in the recessed etch trenches. In some embodiments, the flow rate of tungsten pentachloride is between about 50 sccm and about 100 sccm, and the hydrogen flow rate is between about 1000 sccm and about 2000 sccm. Tungsten pentachloride can be carried by argon and pumped into a reaction chamber with a temperature between about 450°C and 550°C, such that the chamber pressure is about 40 Torr. Hydrogen can be pumped into the reaction chamber such that the chamber pressure is about 60 Torr. In summary, tungsten can be deposited to fill the recessed etch trenches. In some embodiments, tungsten is formed using a selective deposition process without the need for an additional mask to ensure that tungsten is formed in the recessed etch trenches. In some embodiments, after tungsten is formed, chemical mechanical polishing can be performed to planarize the upper surfaces of the intermediate gate structures 108'-1, 108'-2, and 108'-3.

[0094] In some embodiments, other deposition methods (such as selective or non-selective methods) can also be used to fill the recessed etch trenches with the fill gate metal. If a non-selective deposition method is used, recessed etching can be performed to remove the excess gate metal outside the recessed etch trenches. For example, a patterning process can be performed to expose and remove the excess gate metal outside the recessed etch trenches. Then, a chemical mechanical polishing process can be performed to planarize the upper surfaces of the intermediate gate structures 108'-1, 108'-2, and 108'-3.

[0095] In some embodiments, a fill gate metal having a different gate metal (such as a native gate metal material different from the fill gate metal layer) may also be deposited. The fill gate metal may have a relatively low resistance or a lower resistance compared to the fill gate metal layer. In some embodiments, a self-assembled monolayer covering the etch-back trench may improve the adhesion between the fill gate metal (such as a metal and / or conductive material including a native gate metal material different from the fill gate metal layer) and the work function metal layer.

[0096] In some embodiments, a suitable dopant may be formed in the fill gate metal to further reduce the gate resistance. For example, boron may be doped into the fill gate metal to increase the doping level and thus reduce the gate resistance. Boron may be deposited on the fill gate metal (which includes the same or different materials from the native gate metal material of the fill gate metal layer). In some embodiments, in some embodiments, a self-assembled monolayer covering the etch-back trench may improve the adhesion between the doped fill gate metal and at least the work function metal layer. In some embodiments, the self-assembled monolayer bonds the doped fill gate metal to the fill gate metal layer with few or no voids therein.

[0097] After depositing the fill gate metal into the etch-back trenches 117A, 117B1, 117B2, 117C1, and 117C2, a metal gate structure may be formed. Figures 5A to 5C The intermediate gate structures 108'-1, 108'-2, and 108'-3 shown may illustrate cross-sectional views of the metal gate structure having the fill gate metal. Compared to the metal gate structure without the fill gate metal (such as Figures 3A to 3C the intermediate gate structures 108'-1, 108'-2, and 108'-3 shown), the metal gate structure having the fill gate metal may have more gate metal and a lower gate resistance.

[0098] In some embodiments, after forming the metal gate structure, the metal gate structure may be separated, divided, and / or segmented along the x-axis or the direction in which the metal gate structure extends to form a short-channel metal gate structure. For example, a metal gate structure may be located on a fin 104. In some embodiments, the channel length after separation and / or cutting is about 10 nm. An insulating material (such as silicon nitride and / or silicon oxide) may be deposited on the separated metal gate structures as appropriate to electrically insulate the metal gate structures from each other. In some embodiments, chemical mechanical polishing is performed to planarize the upper surface of the insulating material. In some embodiments, the foregoing process is referred to as a "final cut scheme".

[0099] In the embodiments of the present invention, the method of partially replacing the work function metal layer with a conductive material can reduce the gate resistance of the metal gate structure. In some embodiments, other parts and / or layers of the metal gate structure can also be replaced with a conductive material (such as a conductive material with a desired resistance and / or doping level) to further reduce the gate resistance. For example, the top of the barrier metal layer and the top of the work function metal layer can be removed together (or selectively removed) to further increase the amount of gate metal in the metal gate structure. One or more etch-back processes can be performed. In summary, the etchant for removing these parts can be adjusted to form a self-assembled monolayer on the etched surface and improve the adhesion between other layers exposed on the etched surface and the subsequently deposited conductive material. In addition, a suitable conductive material can be formed (or selectively formed) in the etch-back trench to fill the metal gate structure. The specific methods and structures can refer to the embodiments of the present invention and will not be repeated here.

[0100] Compared with other solutions, the metal gate structure formed by using the methods and structures disclosed in the embodiments of the present invention has a lower gate resistance. Selective etching can be performed to remove the top of the work function metal layer and form a self-assembled monolayer on the inner surface of the etched part to improve the adhesion between the subsequently deposited filling gate metal and the work function metal layer. Selective deposition can be performed to fill the etched part with the filling gate metal. The filling gate metal has a relatively low or lower gate resistance compared with the original gate metal material. Before the gate metal filling process, for a metal gate structure with a small amount or no filling gate metal layer on the work function metal layer, after the filling process, the gate metal can be deposited into the gate metal structure and the gate resistance can be reduced. For a metal gate structure that already has sufficient gate metal in the filling gate metal layer before the gate metal filling process, the metal gate structure can contain more gate metal (or a conductive material with a relatively low or lower resistance) to further reduce the gate resistance. In some embodiments, selective etching and selective deposition do not require an additional mask for the process, so no additional manufacturing process needs to be added when forming the semiconductor structure 100. In some embodiments, selective etching has little or no effect on the gate size (such as the gate height). In some embodiments, after a manufacturing process such as an etch-back process, the gate height of the metal gate structure is reduced by at most about 10%.

[0101] Figure 6 is a flowchart of an exemplary method 600 for forming a metal gate structure with a filling gate metal. Other manufacturing processes can also be performed between various steps of the method 600, but related descriptions are omitted here for the sake of simplicity. It can also be performed in a different order Figure 6The manufacturing process shown. Any variation of the described manufacturing steps falls within the scope of the embodiments of the present invention. For ease of explanation, the term "first metal gate structure" refers to the metal gate structure before the disclosed method is performed, and the "second metal gate structure" refers to the metal gate structure formed by using the disclosed method.

[0102] In step 601, a substrate is provided. The substrate may include a first metal gate structure having a work function metal layer. The first metal gate structure may be formed from a gate replacement process and may also include other layers such as a high-k dielectric layer, a capping layer, a barrier layer, or similar layers surrounding the work function metal layer. In some embodiments, the first metal gate structure has a small gate length and may include a small amount of gate metal or no gate metal on the work function metal layer. In some embodiments, the first metal gate structure has insufficient gate metal on the work function metal layer. The substrate may include any suitable semiconductor material. The work function metal layer may include a suitable material having a desired work function, such as titanium nitride. The gate metal may include a suitable conductive material, such as tungsten. Figures 3A to 3C Details of the first metal gate structure may be provided in connection with the description.

[0103] In step 602, the top of the work function metal layer is removed by selective etching. An etchant having a desired etching selectivity may be dispensed onto the wafer and / or substrate for selective etching. In some embodiments, the etchant has a desired higher etching selectivity for the work function metal layer of the first metal gate structure and other materials (such as gate metal). In some embodiments, the time of the selective etching may be controlled to remove a desired amount (such as depth) of the top of the work function metal layer. After the etching process, a re-etch trench may be formed in the work function metal layer, and the topmost side surface of the work function metal layer may be exposed. In some embodiments, the fill gate metal layer includes tungsten and the work function metal layer includes titanium nitride, and the mixture used for selective etching includes phosphoric acid, hydrogen peroxide, and hot deionized water. In some embodiments, the etching selectivity of the etchant for titanium nitride is five times higher than that for tungsten. In some embodiments, the inner surface of the re-etch trench that is exposed also includes other layers surrounding the work function metal layer, such as a fill gate metal layer and / or a barrier metal layer. The etchant may react with the materials exposed in the re-etch trench and form a self-assembled monolayer on the exposed surface of the re-etch trench. The self-assembled monolayer may improve the adhesion between the exposed inner surface of the re-etch trench and the subsequently deposited fill gate metal. In some embodiments, the self-assembled monolayer improves the adhesion between the subsequently formed fill gate metal and the work function metal layer and reduces and / or eliminates voids between the fill gate metal and the fill gate metal layer. Details of the composition of the etchant and the self-assembled monolayer, such as in conjunction with Figures 4A to 4C the above related content described.

[0104] In step 603, a conductive material is deposited into the re-etched trenches in the work function metal layer to form a second metal gate structure. The conductive material may be referred to as fill gate metal. A selective deposition method may be employed to deposit a suitable conductive material, which may be the same as or different from the fill gate metal layer. In-situ doping may be used to increase the doping level of the conductive material, thereby further reducing the gate resistance of the second metal gate structure. In some embodiments, atomic layer deposition is performed to selectively deposit the conductive material into the re-etched trenches. In some embodiments, the fill gate metal layer of the first metal gate structure includes tungsten, the fill gate metal includes tungsten, and boron is doped into the fill gate metal via in-situ doping. Meanwhile, the self-assembled monolayer on the inner surface of the re-etched trenches can improve the adhesion between the fill gate metal and the work function metal layer, and can also improve the adhesion between the fill gate metal and the fill gate metal layer. In some embodiments, tungsten pentachloride gas and a precursor gas of hydrogen may be used for the atomic layer deposition process. Solid tungsten may be selectively formed in the re-etched trenches. In some embodiments, the flow rate of tungsten pentachloride is between about 50 standard cubic centimeters per minute (sccm) and about 100 sccm, and the flow rate of hydrogen gas may be between about 1000 sccm and about 2000 sccm. Tungsten pentachloride may be carried by argon and pumped into a reaction chamber with a temperature between about 450 °C and about 550 °C, and the chamber pressure may be about 40 Torr. Hydrogen gas may be pumped into the reaction chamber, and the chamber pressure may be about 60 Torr. Chemical mechanical polishing may be performed as appropriate to planarize the upper surface of the second metal gate structure. The fill gate metal has been paired with Figures 5A to 5C as detailed above.

[0105] Method 600 may further optionally include step 604. In step 604, the second metal gate structure may be cut and / or separated along the direction of the fin 104 to form a short channel structure. An insulating material (such as silicon nitride) may be used to fill the space between adjacent short channel structures to insulate the short channel structures from each other. In some embodiments, chemical mechanical polishing is performed to planarize the short channel structure.

[0106] Embodiments of the present invention illustrate a selective etch-back process for removing a work function metal around a gate metal in a metal gate. Subsequently, a conductive material with a relatively low resistance or lower resistance is filled into the space created by removing the work function metal to increase the volume of the gate metal in the metal gate. The selective etch-back process forms a self-assembled monolayer on the etched portion. The self-assembled monolayer can improve the adhesion between the etched portion and the newly deposited filled gate metal. The deposition method of the newly deposited filled gate metal (such as a conductive material) can use a selective deposition method and can include desired and / or different dopant concentrations and / or types to further improve (such as reduce) the gate resistance. The selective etch-back and the selective deposition method do not require additional masks or additional manufacturing processes. Therefore, it substantially does not affect (such as reduce) the gate height and more gate metal can be deposited into the metal gate. By using the method disclosed in the embodiments of the present invention, the amount of gate metal in the metal gate can be higher than that of the initially fabricated metal gate, the gate resistance can be reduced, and the electrical properties of the semiconductor device can be improved. In addition, the newly deposited filled gate metal can adhere to the etched portion of the metal gate, and there are few (or no) voids formed in the filled gate metal. The formed gate metal can be more consistent. The gate resistance can be further reduced. Therefore, the method and structure disclosed in the embodiments of the present invention can improve device performance.

[0107] In some embodiments, a fin field-effect transistor device includes: a substrate; a fin located on the substrate; and a gate structure located on the fin. The gate structure includes a work function metal layer located on the inner sidewalls of the gate structure, and the topmost surface of the work function metal layer is lower than the upper surface of the gate structure; a filled gate metal layer located on the topmost surface of the work function metal layer, and the upper surface of the filled gate metal layer is substantially coplanar with the upper surface of the gate structure; and a self-assembled monolayer located between the filled gate metal layer and the work function metal layer.

[0108] In some embodiments, the self-assembled monolayer includes an adhesion layer located between the work function metal layer and the filled gate metal layer.

[0109] In some embodiments, the fin field-effect transistor device further includes other filled gate metal layers surrounded by the work function metal layer, and the upper surfaces of the other filled gate metal layers are substantially coplanar with the upper surface of the gate structure, wherein the self-assembled monolayer is located between the other filled gate metal layers and the filled gate metal layer.

[0110] In some embodiments, the self-assembled monolayer includes: a first portion formed by phosphate and the work function metal layer, located between the work function metal layer and the filled gate metal layer; and a second portion formed by phosphate and the other filled gate metal layers, located between the filled gate metal layer and the other filled gate metal layers.

[0111] In some embodiments, the fin field-effect transistor device further includes a barrier metal layer surrounding the work function metal layer, and an upper surface of the barrier metal layer is substantially coplanar with an upper surface of the gate structure, wherein the self-assembled monolayer further includes a third portion formed by a phosphate and the barrier metal layer, and is located between the barrier metal layer and the fill gate metal layer.

[0112] In some embodiments, the fill gate metal layer and other fill gate metal layers each include a common conductive material.

[0113] In some embodiments, the fill gate metal layer has a first doping level, the other fill gate metal layers have a second doping level, and the first doping level is higher than the second doping level.

[0114] In some embodiments, the work function metal layer includes titanium nitride, titanium aluminum nitride, or titanium aluminum carbide; the barrier metal layer includes tantalum nitride or niobium nitride; the fill gate metal layer and other fill gate metal layers each include one or more of tungsten and aluminum; and the fill gate metal layer includes boron.

[0115] In some embodiments, the first portion of the self-assembled monolayer includes titanium oxide and phosphate, the second portion of the self-assembled monolayer includes tungsten oxide and phosphate, and the third portion of the self-assembled monolayer includes tantalum oxide and phosphate.

[0116] In some embodiments, a method of forming a semiconductor device includes: providing a substrate, and the substrate includes a gate structure having a work function metal layer; removing a top portion of the work function metal layer; forming a self-assembled monolayer on a topmost side surface of the work function metal layer exposed by removing the top portion of the work function metal layer; and depositing a fill gate metal layer into the top portion from which the work function metal layer has been removed, and the self-assembled monolayer is located between the fill gate metal layer and the work function metal layer.

[0117] In some embodiments, the step of removing the top portion of the work function metal layer includes performing a selective etch-back, which etches the work function metal layer at a rate higher than that of etching other materials of the substrate.

[0118] In some embodiments, the work function metal layer includes titanium nitride, titanium aluminum nitride, or titanium aluminum carbide; and the step of performing a selective etch-back includes using a mixture of hydrogen peroxide, phosphoric acid, and hot deionized water to remove the top portion of the work function metal layer at room temperature to 80 °C.

[0119] In some embodiments, the step of performing a selective etch-back further includes forming a self-assembled monolayer on the work function metal layer, and wherein the self-assembled monolayer includes a portion formed by the mixture and the work function metal layer.

[0120] In some embodiments, the step of depositing a fill gate metal layer into the top from which the work function metal layer has been removed includes selectively depositing a gate metal into the top from which the work function metal layer has been removed, and a self-assembled monolayer serves as an adhesion layer between the fill gate metal layer and the work function metal layer.

[0121] In some embodiments, the substrate further includes other fill gate metal layers surrounded by the work function metal layer, and the step of performing selective back etching further includes forming other portions of the self-assembled monolayer on the other fill gate metal layers, the other portions of the self-assembled monolayer being formed by a mixture and the other fill gate metal layers, and the other fill gate metal layers being bonded to the fill gate metal layer via the other portions of the self-assembled monolayer.

[0122] In some embodiments, the step of depositing the fill gate metal layer includes performing atomic layer deposition and in-situ doping processes, and the fill gate metal layer and the other fill gate metal layers include a common conductive material.

[0123] In some embodiments, the common conductive material includes tungsten; and the doping level of the fill gate metal layer is higher than that of the other fill gate metal layers, and the fill gate metal layer includes boron.

[0124] In some embodiments, a method of forming a semiconductor device includes: providing a substrate, and the substrate includes a gate structure; selectively removing the top of the gate structure; forming an adhesion layer on the upper surface of the gate structure exposed by removing the top of the gate structure; and selectively depositing a conductive layer into the top of the gate structure from which the adhesion layer has been removed, and the adhesion layer bonds the upper surface of the gate structure exposed by removing the top of the gate structure and the conductive layer.

[0125] In some embodiments, the doping level of the conductive layer is higher than that of the removed top of the gate structure.

[0126] In some embodiments, the step of selectively removing the top of the gate structure includes a selective etching process, and the step of depositing the conductive layer includes a selective deposition process and an in-situ doping process.

[0127] It can be understood that the paragraphs of the embodiments (not the abstract) can be used to interpret the claims. The abstract may illustrate one or more exemplary embodiments rather than all exemplary embodiments, and thus does not limit the appended claims.

[0128] The features of the above embodiments or examples are conducive to those skilled in the art in the technical field to understand the embodiments of the present invention. Those skilled in the art in the technical field should understand that the embodiments of the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages as those of the above embodiments. Those skilled in the art in the technical field should also understand that these equivalent substitutions do not depart from the concept and scope of the present disclosure, and can be changed, replaced, or varied without departing from the concept and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: Providing a substrate, and the substrate includes a gate structure having a work function metal layer and a barrier metal layer, and the work function metal layer and the barrier metal layer are substantially flush; Removing the top of the work function metal layer to form a lower side portion of the work function metal layer, and a first upper surface of the lower side portion of the work function metal layer is lower than a second upper surface of the barrier metal layer; Forming a self-assembled monolayer on the first upper surface of the lower side portion of the work function metal layer; and Depositing a fill gate metal layer on the self-assembled monolayer.

2. The method for forming a semiconductor structure according to claim 1, wherein the step of removing the top of the work function metal layer includes performing a selective back-etching, and the etching rate of the work function metal layer is higher than the etching rate of the barrier metal layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The work function metal layer includes titanium nitride, titanium aluminum nitride, or titanium aluminum carbide; and The step of performing the selective back-etching includes using a mixture of hydrogen peroxide, phosphoric acid, and hot deionized water to remove the top of the work function metal layer at room temperature to 80 °C.

4. The method for forming a semiconductor structure according to claim 3, wherein the step of performing the selective back-etching further includes simultaneously forming the self-assembled monolayer on the first upper surface of the lower side portion of the work function metal layer.

5. The method for forming a semiconductor structure according to claim 4, wherein the step of depositing the fill gate metal layer on the self-assembled monolayer includes selectively depositing the fill gate metal layer into the top of the removed work function metal layer, and the self-assembled monolayer is an adhesion layer between the fill gate metal layer and the work function metal layer.

6. The method for forming a semiconductor structure according to claim 5, wherein the substrate further includes another fill gate metal layer surrounded by the work function metal layer, and wherein the step of performing the selective back-etching further includes forming another portion of the self-assembled monolayer on the other fill gate metal layer, the other portion of the self-assembled monolayer is formed by a mixture and the other fill gate metal layer, and the other fill gate metal layer is adhered to the fill gate metal layer via the other portion of the self-assembled monolayer.

7. The method for forming a semiconductor structure according to claim 6, wherein the step of depositing the fill gate metal layer includes performing atomic layer deposition and in-situ doping process, and wherein the fill gate metal layer and the other fill gate metal layer include a common conductive material.

8. The method for forming a semiconductor structure according to claim 7, wherein: The common conductive material includes tungsten; and The doping level of the fill gate metal layer is higher than the doping level of the other fill gate metal layer, and the fill gate metal layer includes boron.

9. A method for forming a semiconductor structure, comprising: Providing a substrate, and the substrate includes a gate structure having a first metal layer and a second metal layer, and the second metal layer having a side surface is located on the first metal layer; Removing the top of the gate structure, including selectively removing the top of the first metal layer to expose the side surface of the second metal layer; Form an adhesive layer on the exposed side surface of the second metal layer and a lower side portion of the first metal layer; And Deposit a conductive layer into the top of the removed gate structure on the adhesive layer, and the adhesive layer bonds the upper surface of the gate structure exposed by removing the top of the gate structure to the conductive layer.

10. The method for forming a semiconductor structure according to claim 9, wherein the doping level of the conductive layer is higher than the doping level of the top of the removed gate structure.

11. The method for forming a semiconductor structure according to claim 10, wherein the step of removing the top of the gate structure includes performing a selective etching process to selectively etch the first metal layer rather than the second metal layer, and wherein the step of depositing the conductive layer includes performing a selective deposition process and an in-situ doping process.

12. A method for forming a semiconductor structure, comprising: Form a gate structure on a substrate; Form a recess structure in the gate structure, wherein the lower surface and the side surface of the recess structure include a self-assembled monolayer, wherein the step of forming the recess structure includes exposing a first inner surface and a second inner surface of the gate structure, and wherein the first inner surface and the second inner surface include different conductive materials; and Form a metal material layer on the recess structure.

13. The method for forming a semiconductor structure according to claim 12, wherein the self-assembled monolayer includes phosphorus.

14. The method for forming a semiconductor structure according to claim 12, wherein the step of forming the gate structure includes: Form a filled gate metal layer on the substrate; And Form a work function metal layer to surround the filled gate metal layer.

15. The method for forming a semiconductor structure according to claim 14, wherein the step of forming the recess structure includes removing an upper side portion of the work function metal layer to expose the side surface of the filled gate metal layer, wherein the upper surface of the lower side portion of the work function metal layer includes the first inner surface of the gate structure; and wherein the exposed side surface of the filled gate metal layer includes the second inner surface of the gate structure.

16. The method for forming a semiconductor structure according to claim 12, wherein the step of forming the gate structure includes forming a first layer and a second layer of conductive material on the substrate, wherein the conductive material includes a first metal element and a second metal element, and wherein the self-assembled monolayer includes the first metal element, the second metal element, and phosphate.

17. The method for forming a semiconductor structure according to claim 12, wherein the step of forming the recess structure includes dispensing a wet etchant on the substrate, and wherein the wet etchant includes phosphoric acid.

18. The method for forming a semiconductor structure according to claim 17, wherein the wet etchant further includes hydrogen chloride.

19. The method for forming a semiconductor structure according to claim 12, wherein the step of forming the recess structure includes: Extend the recess structure into the upper surface of the gate structure; And Form the self-assembled monolayer on the upper surface of the gate structure.

20. The method for forming a semiconductor structure as claimed in claim 12, wherein the step of forming the recessed structure further includes respectively forming a first portion and a second portion of the self-assembled monolayer on the first inner side surface and the second inner side surface of the gate structure, and wherein the first portion and the second portion of the self-assembled monolayer comprise different conductive materials.

21. A fin field-effect transistor device, comprising: a substrate; a fin located on the substrate; a gate structure located on the fin, and the gate structure includes: a work function metal layer located on the inner side sidewalls of the gate structure, and the topmost surface of the work function metal layer is lower than the upper surface of the gate structure; a filled gate metal layer located on the topmost surface of the work function metal layer, and the upper surface of the filled gate metal layer is substantially coplanar with the upper surface of the gate structure; and a self-assembled monolayer located between the filled gate metal layer and the work function metal layer.

22. The fin field-effect transistor device as claimed in claim 21, wherein the self-assembled monolayer includes an adhesion layer located between the work function metal layer and the filled gate metal layer.

23. The fin field-effect transistor device as claimed in claim 22, further comprising another filled gate metal layer surrounded by the work function metal layer, and the upper surface of the another filled gate metal layer is substantially coplanar with the upper surface of the gate structure, wherein the self-assembled monolayer is located between the another filled gate metal layer and the filled gate metal layer.

24. The fin field-effect transistor device as claimed in claim 23, wherein the self-assembled monolayer includes: a first portion formed by phosphate and the work function metal layer, located between the work function metal layer and the filled gate metal layer; and a second portion formed by phosphate and the another filled gate metal layer, located between the filled gate metal layer and the another filled gate metal layer.

25. The fin field-effect transistor device as claimed in claim 24, further comprising a barrier metal layer surrounding the work function metal layer, and the upper surface of the barrier metal layer is substantially coplanar with the upper surface of the gate structure, wherein the self-assembled monolayer further includes a third portion formed by phosphate and the barrier metal layer, located between the barrier metal layer and the filled gate metal layer.

26. The fin field-effect transistor device as claimed in claim 23, wherein the filled gate metal layer and the another filled gate metal layer comprise a common conductive material.

27. The fin field-effect transistor device as claimed in claim 23, wherein the filled gate metal layer has a first doping level, the another filled gate metal layer has a second doping level, and the first doping level is higher than the second doping level.

28. The fin field-effect transistor device as claimed in claim 25, wherein: the work function metal layer includes titanium nitride, titanium aluminum nitride, or titanium aluminum carbide; the barrier metal layer includes tantalum nitride or niobium nitride; the filled gate metal layer and the another filled gate metal layer each comprise one or more of tungsten and aluminum; and the filled gate metal layer includes boron.

29. The fin field effect transistor device as claimed in claim 25, wherein the first portion of the self-assembled monolayer comprises titanium oxide and phosphate, the second portion of the self-assembled monolayer comprises tungsten oxide and phosphate, and the third portion of the self-assembled monolayer comprises tantalum oxide and phosphate.

30. A gate structure, comprising: a barrier layer, and an upper surface of the barrier layer is substantially coplanar with an upper surface of the gate structure; a work function metal layer, and an upper surface of the work function metal layer is lower than the upper surface of the gate structure; a first filling metal layer, located on the work function metal layer, wherein an upper surface of the first filling metal layer is substantially coplanar with the upper surface of the gate structure; a second filling metal layer, and an upper surface of the second filling metal layer is substantially coplanar with the upper surface of the gate structure; and a self-assembled monolayer, comprising: a first portion, sandwiched between the barrier layer and the first filling metal layer; a second portion, sandwiched between the work function metal layer and the first filling metal layer; and a third portion, sandwiched between the first filling metal layer and the second filling metal layer.

31. The gate structure as claimed in claim 30, wherein the first portion of the self-assembled monolayer comprises phosphate and the barrier layer, the second portion of the self-assembled monolayer comprises phosphate and the work function metal layer, and the third portion of the self-assembled monolayer comprises phosphate and the second filling metal layer.

32. The gate structure as claimed in claim 31, wherein the first portion, the second portion, and the third portion of the self-assembled monolayer further comprise chloride.

33. The gate structure as claimed in claim 30, wherein: the barrier layer comprises tantalum nitride or niobium nitride; the work function metal layer comprises titanium nitride, titanium aluminum nitride, or titanium aluminum carbide; and each of the first filling metal layer and the second filling metal layer comprises one or more of tungsten and aluminum.

34. The gate structure as claimed in claim 30, wherein the first filling metal layer is doped with boron at a first doping level, the second filling metal layer is doped with boron at a second doping level, and the first doping level is higher than the second doping level.

35. The gate structure as claimed in claim 30, wherein the self-assembled monolayer comprises an adhesion layer.

36. The gate structure as claimed in claim 30, wherein each of the first filling metal layer and the second filling metal layer comprises a common conductive material.

37. A semiconductor structure, comprising: a work function metal layer, surrounding a first filling metal layer, and an upper surface of the work function metal layer is lower than an upper surface of the first filling metal layer; a second filling metal layer, located on the work function metal layer, and an upper surface of the second filling metal layer is substantially coplanar with the upper surface of the first filling metal layer; a first self-assembled monolayer, sandwiched between the first filling metal layer and the second filling metal layer; and a second self-assembled monolayer, sandwiched between the work function metal layer and the second filling metal layer.

38. The semiconductor structure according to claim 37, wherein the first self-assembled monolayer comprises phosphate, the first filling metal layer, and the second filling metal layer, and the second self-assembled monolayer comprises phosphate, the work function metal layer, and the second filling metal layer.

39. The semiconductor structure according to claim 37, further comprising: a barrier layer surrounding the work function metal layer and the second filling metal layer, wherein an upper surface of the barrier layer is substantially coplanar with an upper surface of the first filling metal layer; and a third self-assembled monolayer interposed between the barrier layer and the second filling metal layer, wherein the third self-assembled monolayer comprises phosphate, the barrier layer, and the second filling metal layer.

40. The semiconductor structure according to claim 37, wherein the first filling metal layer is doped with boron at a first doping level, the second filling metal layer is doped with boron at a second doping level, and the first doping level is lower than the second doping level.

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