Fan-out antenna package structure and packaging method

Abstract

The present invention provides a fan-out antenna packaging structure and a packaging method. The packaging structure includes: a redistribution layer; a first metal connection post located on the second surface of the redistribution layer; a first antenna metal layer located on the first metal connection post; a semiconductor chip electrically connected to the redistribution layer; a first packaging layer covering the redistribution layer, the first metal connection post, the first antenna metal layer, and the semiconductor chip and exposing the first antenna metal layer and the adhesive layer; a second metal connection post located on the first antenna metal layer; a second antenna metal layer located on the second metal connection post and electrically connected to the second metal connection post; a second packaging layer covering the second metal connection post and the second antenna metal layer and exposing the second antenna metal layer; and metal bumps located on the first surface of the redistribution layer. The present invention realizes the integration of multiple layers of antenna metal layers, effectively reduces the packaging volume, and has high integration and electrical stability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly to a fan-out antenna packaging structure and a packaging method thereof. Background Art

[0002] Lower cost, more reliable, faster and higher density circuits are the goals pursued by integrated circuit packaging. In the future, integrated circuit packaging will improve the integration density of various electronic components by continuously reducing the minimum feature size. Currently, common packaging methods include: Wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Package (FOWLP), Flip Chip, Package on Package (POP), and so on. Among them, the fan-out wafer level package has become one of the relatively advanced packaging methods at present due to its relatively large number of input / output ports (I / O) and good integration flexibility.

[0003] With the popularization of high-tech electronic products and the increase in people's demands, especially to meet people's mobile needs, currently, most high-tech electronic products have added wireless communication functions.

[0004] Generally speaking, the existing antenna structures usually directly fabricate the antenna on the surface of the circuit board. This approach will cause the antenna to occupy additional circuit board area and have poor integration. For various high-tech electronic products, using a larger circuit board means that the high-tech electronic products occupy a larger volume, which goes against people's demands for miniaturization and portability of high-tech electronic products. Therefore, how to reduce the area of the circuit board occupied by the antenna and reduce the volume of the antenna packaging structure to improve the integration performance of the antenna packaging structure will be the problems that these electronic devices need to overcome.

[0005] In view of this, it is necessary to design a new fan-out antenna packaging structure and a packaging method to solve the above-mentioned technical problems caused by the antenna occupying the area of the circuit board. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a fan-out antenna packaging structure and a packaging method thereof, which are used to solve the problems of large volume and poor integration of the antenna packaging structure caused by the antenna occupying the area of the circuit board in the prior art.

[0007] In view of this, the present invention provides a fan-out antenna packaging structure, including:

[0008] A redistribution layer, the redistribution layer including a first surface and a second surface opposite to each other;

[0009] A first metal connection column, located on the second surface of the re-wiring layer and electrically connected to the re-wiring layer;

[0010] A first antenna metal layer, located on the first metal connection column and electrically connected to the first metal connection column;

[0011] A semiconductor chip, located on the second surface of the re-wiring layer and electrically connected to the re-wiring layer;

[0012] A first encapsulation layer, covering the re-wiring layer, the first metal connection column, the first antenna metal layer and the semiconductor chip, and the first encapsulation layer exposes the first antenna metal layer and an adhesive layer adhered to the semiconductor chip;

[0013] A second metal connection column, located on the first antenna metal layer and electrically connected to the first antenna metal layer;

[0014] A second antenna metal layer, located on the second metal connection column and electrically connected to the second metal connection column;

[0015] A second encapsulation layer, covering the second metal connection column and the second antenna metal layer, and the second encapsulation layer exposes the second antenna metal layer; and

[0016] Metal bumps, located on the first surface of the re-wiring layer.

[0017] Optionally, the semiconductor chip further includes a chip metal part connected to the contact pads of the semiconductor chip, and the chip metal part includes one of a metal column and a metal ball.

[0018] Optionally, the side surface of the chip metal part is covered by the re-wiring layer.

[0019] Optionally, the adhesive layer includes one of an epoxy resin layer and a polymer thin film layer.

[0020] Optionally, a first metal connection block is further included between the first metal connection column and the first antenna metal layer, and the cross-sectional area of the first metal connection block is larger than that of the first metal connection column; a second metal connection block is further included between the second metal connection column and the second antenna metal layer, and the cross-sectional area of the second metal connection block is larger than that of the second metal connection column.

[0021] Optionally, the first encapsulation layer includes one of an epoxy resin layer, a polyimide layer and a silica gel layer; the second encapsulation layer includes one of an epoxy resin layer, a polyimide layer and a silica gel layer.

[0022] Optionally, the rewiring layer includes a patterned dielectric layer and a patterned metal wiring layer stacked in sequence.

[0023] Optionally, the dielectric layer includes one or a combination of two or more of an epoxy resin layer, a silicone layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer, and a fluorine-containing glass layer, and the metal wiring layer includes one or a combination of two or more of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer, and a titanium layer.

[0024] Optionally, the metal bump includes one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump.

[0025] The present invention also provides a fan-out antenna packaging method, including the following steps:

[0026] S1: Provide a support substrate, and form a separation layer on the support substrate;

[0027] S2: Form a second antenna metal layer on the separation layer;

[0028] S3: Form a second metal connection column on the second antenna metal layer;

[0029] S4: Package the second antenna metal layer and the second metal connection column with a second encapsulation layer, and expose the second metal connection column by the second encapsulation layer;

[0030] S5: Form a first antenna metal layer on the second encapsulation layer, and electrically connect the first antenna metal layer to the second metal connection column;

[0031] S6: Form a first metal connection column on the first antenna metal layer;

[0032] S7: Provide a semiconductor chip, and bond the semiconductor chip to the second encapsulation layer, wherein the semiconductor chip further includes a chip metal part connected to a contact pad of the semiconductor chip;

[0033] S8: Package the first antenna metal layer, the first metal connection column, and the semiconductor chip with a first encapsulation layer, and expose the first metal connection column and the chip metal part by the first encapsulation layer;

[0034] S9: Form a rewiring layer on the first encapsulation layer, the rewiring layer includes a second surface in contact with the first encapsulation layer and a first surface opposite thereto, and the rewiring layer is electrically connected to the first metal connection column and the chip metal part;

[0035] S10: Form metal bumps on the rewiring layer; and

[0036] S11: Peel the support substrate based on the separation layer.

[0037] Optionally, the support substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate; the separation layer includes one of a tape and a polymer layer, and the curing method of the polymer layer includes one of ultraviolet curing and thermal curing.

[0038] Optionally, the method for forming the second encapsulation layer in step S4 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating; the method for forming the first encapsulation layer in step S8 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating.

[0039] Optionally, forming the second metal connection column in step S3 includes the following steps:

[0040] S3-1: Form a second metal connection block on the second antenna metal layer, and the second metal connection block is electrically connected to the second antenna metal layer;

[0041] S3-2: Use a wire bonding process to form the second metal connection column on the upper surface of the second metal connection block, and the cross-sectional area of the second metal connection block is larger than that of the second metal connection column.

[0042] Optionally, forming the first metal connection column in step S6 includes the following steps:

[0043] S6-1: Form a first metal connection block on the first antenna metal layer, and the first metal connection block is electrically connected to the first antenna metal layer;

[0044] S6-2: Use a wire bonding process to form the first metal connection column on the upper surface of the first metal connection block, and the cross-sectional area of the first metal connection block is larger than that of the first metal connection column.

[0045] Optionally, forming the redistribution layer in step S9 includes the following steps:

[0046] S9-1: Use a physical vapor deposition process or a chemical vapor deposition process to form a dielectric layer on the first encapsulation layer, and etch the dielectric layer to form a patterned dielectric layer;

[0047] S9-2: Use a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process, or a chemical plating process to form a metal wiring layer on the patterned dielectric layer, and etch the metal wiring layer to form a patterned metal wiring layer.

[0048] Optionally, step S9 further includes N cyclic steps formed by combining step S9-1 and step S9-2, where N≥1.

[0049] The fan-out type antenna packaging structure and packaging method of the present invention have the following beneficial effects:

[0050] 1) The present invention uses a redistribution layer and metal pillars to realize the integration of multiple antenna metal layers, greatly improving the efficiency and performance of the antenna and enhancing the integration of the antenna packaging structure;

[0051] 2) The present invention places the semiconductor chip in the packaging layer, and the antenna metal layer and the adhesive layer adhered to the semiconductor chip are on the same horizontal plane, saving space volume and making the volume of the packaging structure smaller; while packaging the metal pillars and the antenna metal layer, the packaging layer also realizes the packaging of the semiconductor chip, improving the stability of the semiconductor chip and saving costs;

[0052] 3) Before bonding the semiconductor chip, the present invention first forms metal pillars, improving the cleanliness of the bonding surface between the metal pillars and the antenna metal layer and enhancing the stability of the metal pillars;

[0053] 4) The present invention directly forms a redistribution layer on the packaging layer, simultaneously realizing the electrical connection of the metal pillars and the semiconductor chip and reducing the process complexity;

[0054] 5) The antenna metal layers of the present invention are all located within the packaging layer, which can further reduce the volume of the packaging structure. And in the final step, the support substrate is peeled off based on the separation layer, improving the cleanliness and electrical stability of the packaging structure;

[0055] 6) The present invention uses a fan-out type packaging method to package the antenna structure, which can effectively reduce the packaging volume, making the antenna packaging structure have a high integration degree and better packaging performance, and having a wide application prospect in the field of semiconductor packaging. Description of the Drawings

[0056] Figure 1 It shows a schematic flow chart of the fan-out type antenna packaging method in the present invention.

[0057] Figures 2 to 14 It shows a schematic structural diagram presented by each step of the antenna packaging method in the present invention, where Figure 14 It is a schematic structural diagram of the fan-out type antenna packaging structure in the present invention.

[0058] Description of Component Labels

[0059] 101 Support Substrate

[0060] 102 Separation Layer

[0061] 103 Redistribution Layer

[0062] 113 dielectric layer

[0063] 123 metal wiring layer

[0064] 104 first metal connecting post

[0065] 114 first metal connecting block

[0066] 105 semiconductor chip

[0067] 115 chip metal part

[0068] 125 adhesive layer

[0069] 106 first encapsulation layer

[0070] 107 first antenna metal layer

[0071] 108 second metal connecting post

[0072] 118 second metal connecting block

[0073] 109 second encapsulation layer

[0074] 110 second antenna metal layer

[0075] 111 metal bump

[0076] Steps S1 to S11 Detailed implementation manners

[0077] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0078] Please refer to Figures 1 to 14 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0079] Such as Figure 14As shown in the figure, the present invention provides a fan-out antenna packaging structure, and the packaging structure includes: a redistribution layer 103, a first metal connection pillar 104, a semiconductor chip 105, a first packaging layer 106, a first antenna metal layer 107, a second metal connection pillar 108, a second packaging layer 109, a second antenna metal layer 110, and metal bumps 111.

[0080] Specifically, the redistribution layer 103 includes an opposite first surface and a second surface. The first metal connection pillar 104 is located on the second surface of the redistribution layer 103 and is electrically connected to the redistribution layer 103; the first antenna metal layer 107 is located on the first metal connection pillar 104 and is electrically connected to the first metal connection pillar 104; the semiconductor chip 105 is located on the second surface of the redistribution layer 103 and is electrically connected to the redistribution layer 103; the first packaging layer 106 covers the redistribution layer 103, the first metal connection pillar 104, the first antenna metal layer 107, and the semiconductor chip 105, and the first packaging layer 106 exposes the first antenna metal layer 107 and the adhesive layer 125 adhered to the semiconductor chip 105; the second metal connection pillar 108 is located on the first antenna metal layer 107 and is electrically connected to the first antenna metal layer 107; the second antenna metal layer 110 is located on the second metal connection pillar 108 and is electrically connected to the second metal connection pillar 108; the second packaging layer 109 covers the second metal connection pillar 108 and the second antenna metal layer 110, and the second packaging layer 109 exposes the second antenna metal layer 110; the metal bumps 111 are located on the first surface of the redistribution layer 103 and are electrically connected to the redistribution layer 103. In this embodiment, the redistribution layer 103, the first metal connection pillar 104, and the second metal connection pillar 108 are used to realize the integration of the first antenna metal layer 107 and the second antenna metal layer 110, which can improve the efficiency and performance of the antenna and the integration of the antenna packaging structure; the semiconductor chip 105 is placed in the first packaging layer 106, and the first antenna metal layer 107 and the adhesive layer 125 are on the same horizontal plane, further saving space volume and making the volume of the packaging structure further reduced; the first antenna metal layer 107 and the second antenna metal layer 110 are respectively located in the first packaging layer 106 and the second packaging layer 109, which can further reduce the volume of the packaging structure, improve the integration degree of the antenna packaging structure and the packaging performance.

[0081] As a further embodiment of this embodiment, the rewiring layer 103 includes a patterned dielectric layer 113 and a patterned metal wiring layer 123 stacked in sequence. Further, the dielectric layer 113 includes one or a combination of two or more of an epoxy resin layer, a silicone layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer, and a fluorine-containing glass layer, and the metal wiring layer 123 includes one or a combination of two or more of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer, and a titanium layer. The specific number of layers and types of the dielectric layer 113 and the metal wiring layer 123 in the rewiring layer 103 are not overly limited here.

[0082] As a further embodiment of this embodiment, a first metal connection block 114 is further included between the first metal connection post 104 and the first antenna metal layer 107. Preferably, the first metal connection post 104 is located at the symmetric center of the first metal connection block 114, and the cross-sectional area of the first metal connection block 114 is larger than that of the first metal connection post 104, thereby increasing the contact area between the first metal connection block 114 and the first antenna metal layer 107 and improving electrical stability.

[0083] As Figure 14 shown, the first metal connection post 104 is located on the second surface of the rewiring layer 103 and is connected to the first antenna metal layer 107 through the first metal connection block 114. Further, the materials of the first metal connection post 104 and the first metal connection block 114 include one or a combination of Au, Ag, Cu, and Al, which are not overly limited here.

[0084] As a further embodiment of this embodiment, the semiconductor chip 105 further includes a chip metal part 115 connected to a contact pad (not shown) of the semiconductor chip 105. The chip metal part 115 includes one of a metal post and a metal ball, and the electrical connection between the semiconductor chip 105 and the rewiring layer 103 is achieved through the chip metal part 115. The chip metal part 115 serves as the electrical connection end of the semiconductor chip 105, facilitating the process operation and avoiding the wire bonding process on the contact pad of the semiconductor chip 105, thereby improving the stability and yield of the semiconductor chip 105.

[0085] As Figure 14 shown, the chip metal part 115 includes the metal post with a certain height. The height range of the metal post includes 25 μm to 250 μm, and the material of the metal post includes one of copper, nickel, tin, and silver. The number and type of the semiconductor chips 105 are not limited here.

[0086] As a further embodiment of this embodiment, the side surface of the chip metal part 115 is covered by the dielectric layer 113 in the redistribution layer 103. Since the side surface of the chip metal part 115 with a certain height is covered by the dielectric layer 113, the electrical stability between the semiconductor chip 105 and the redistribution layer 103 can be further enhanced.

[0087] As a further embodiment of this embodiment, the adhesive layer 125 bonded to the semiconductor chip 105 is exposed on the first encapsulation layer 106 and joined to the second encapsulation layer 109. The semiconductor chip 105 is fixed on the second encapsulation layer 109 through the adhesive layer 125. The adhesive layer 125 includes one of an epoxy resin layer and a polymer thin film layer, such as a metal DAF film, a metal conductive adhesive, etc.

[0088] As a further embodiment of this embodiment, the first encapsulation layer 106 includes one of an epoxy resin layer, a polyimide layer, and a silicone layer. The surface of the first encapsulation layer 106 in contact with the redistribution layer 103 is a flat surface that has been ground or polished to improve the contact performance between the first metal connection posts 104 and the semiconductor chip 105 and the redistribution layer 103. The material of the first antenna metal layer 107 can be Au, Cu, etc., and the first antenna metal layer 107 can have various different patterns according to performance requirements, which are not limited here. As Figure 14 shown, the first antenna metal layer 107 is formed within the first encapsulation layer 106.

[0089] As a further embodiment of this embodiment, a second metal connection block 118 is further included between the second metal connection post 108 and the second antenna metal layer 110 located on the first antenna metal layer 107, and the cross-sectional area of the second metal connection block 118 is larger than that of the second metal connection post 108. Preferably, the second metal connection post 108 is located at the symmetric center of the second metal connection block 118, so as to increase the contact area between the second metal connection block 118 and the second antenna metal layer 110 and improve the electrical stability. Further, the materials of the second metal connection post 108 and the second metal connection block 118 include one or a combination of Au, Ag, Cu, and Al, which are not overly limited here.

[0090] As a further embodiment of this embodiment, the height of the second metal connection post 108 is less than the height of the first metal connection post 104, thereby further reducing the volume of the encapsulation structure.

[0091] Specifically, the second encapsulation layer 109 includes one of an epoxy resin layer, a polyimide layer, and a silica gel layer. The contact surface between the second encapsulation layer 109 and the first encapsulation layer 106 is a flat surface that has been ground or polished to improve the contact performance between the second metal connection post 108 and the first metal connection layer 107. The material of the second antenna metal layer 110 can be Au, Cu, etc., and the second antenna metal layer 110 can have various different patterns according to performance requirements, which are not limited here. As Figure 14 shown, the second antenna metal layer 110 is formed within the second encapsulation layer 109, which can further reduce the volume of the encapsulation structure and improve the cleanliness and electrical performance stability of the encapsulation structure.

[0092] As a further embodiment of this embodiment, the metal bump 111 includes one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump. The metal bump 111 may further include a columnar metal connected to the metal bump 111, which is not limited here.

[0093] As Figure 14 shown, the semiconductor chip 105 is electrically connected to the first antenna metal layer 107 and the second antenna metal layer 110 through the redistribution layer 103, the first metal connection post 104, and the second metal connection post 108 to realize the function of the antenna. According to this structure, more antenna encapsulation structures with more layers can be realized through more metal connection posts, encapsulation layers, and antenna metal layers, which are not limited here. Thus, the integration of multiple-layer antenna metal layers can be further realized, greatly improving the efficiency and performance of the antenna, further improving the integration of the antenna encapsulation structure, reducing the encapsulation volume, and making the antenna encapsulation structure have a high degree of integration.

[0094] As Figure 1 shown, this embodiment also provides a fan-out antenna encapsulation method, including the following steps:

[0095] S1: Provide a support substrate and form a separation layer on the support substrate;

[0096] S2: Form a second antenna metal layer on the separation layer;

[0097] S3: Form a second metal connection post on the second antenna metal layer;

[0098] S4: Encapsulate the second antenna metal layer and the second metal connection post with a second encapsulation layer and expose the second metal connection post on the second encapsulation layer;

[0099] S5: Form a first antenna metal layer on the second encapsulation layer, and the first antenna metal layer is electrically connected to the second metal connection post;

[0100] S6: Form a first metal connection column on the first antenna metal layer;

[0101] S7: Provide a semiconductor chip, and bond the semiconductor chip to the second encapsulation layer, wherein the semiconductor chip further includes a chip metal part connected to the contact pads of the semiconductor chip;

[0102] S8: Encapsulate the first antenna metal layer, the first metal connection column, and the semiconductor chip with a first encapsulation layer, and expose the first metal connection column and the chip metal part on the first encapsulation layer;

[0103] S9: Form a redistribution layer on the surface of the first encapsulation layer. The redistribution layer includes a second surface in contact with the first encapsulation layer and an opposite first surface. The redistribution layer is electrically connected to the first metal connection column and the chip metal part;

[0104] S10: Form metal bumps on the first surface of the redistribution layer; and

[0105] S11: Peel off the support substrate based on the separation layer.

[0106] Specifically, in this embodiment, when the first encapsulation layer encapsulates the first metal connection column and the first antenna metal layer, it also realizes the encapsulation of the semiconductor chip, improves the stability of the semiconductor chip, and saves costs; before bonding the semiconductor chip, the first metal connection column is formed first, which improves the cleanliness of the bonding surface between the first metal connection column and the first antenna metal layer, and can improve the stability of the first metal connection column; the redistribution layer is directly formed on the first encapsulation layer, which simultaneously realizes the electrical connection of the first metal connection column and the semiconductor chip, and reduces the process complexity; the first antenna metal layer and the second antenna metal layer are respectively located in the first encapsulation layer and the second encapsulation layer, which can further reduce the volume of the encapsulation structure, and in the last step, the support substrate is peeled off based on the separation layer, which improves the cleanliness and electrical stability of the encapsulation structure; the antenna structure is encapsulated by a fan-out packaging method, which can effectively reduce the encapsulation volume, making the antenna encapsulation structure have a high integration degree and better packaging performance. As Figures 2 to 14 shown, it schematically shows the structural schematic diagrams presented by the steps of the antenna packaging method in the present invention.

[0107] As Figure 2 shown, first perform step S1, provide a support substrate 101, and form a separation layer 102 on the support substrate 101.

[0108] As a further embodiment of this embodiment, the support substrate 101 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate. In this embodiment, the support substrate 101 is preferably a glass substrate, which has a low cost, is easy to form the separation layer 102 on its surface, and can reduce the difficulty of the subsequent peeling process.

[0109] As a further embodiment of this embodiment, the separation layer 102 includes one of a tape and a polymer layer. The polymer layer is first coated on the surface of the support substrate 101 by a spin coating process, and then cured and formed by an ultraviolet curing or thermal curing process.

[0110] Specifically, in this embodiment, the separation layer 102 is selected as the polymer layer of the LTHC photothermal conversion layer, so that in the subsequent step S11, the LTHC photothermal conversion layer can be heated based on a laser, so that the support substrate 101 is separated from the LTHC photothermal conversion layer.

[0111] As Figure 3 shown, then step S2 is performed to form a second antenna metal layer 110 on the separation layer 102.

[0112] Specifically, the second antenna metal layer 110 can be first formed on the separation layer 102 by a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process, or an electroless plating process, and then the required patterned second antenna metal layer 110 is formed by an etching process.

[0113] As Figure 4 shown, then step S3 is performed to form a second metal connection column 108 on the second antenna metal layer 110, and the second metal connection column 108 is electrically connected to the second antenna metal layer 110.

[0114] As a further embodiment of this embodiment, forming the second metal connection column 108 in step S3 includes the following steps:

[0115] S3-1: A second metal connection block 118 is formed on the second antenna metal layer 110, and the second metal connection block 118 is electrically connected to the second antenna metal layer 110;

[0116] S3-2: A wire bonding process is used to form the second metal connection column 108 on the upper surface of the second metal connection block 118, and the cross-sectional area of the second metal connection block 118 is larger than that of the second metal connection column 108. Preferably, the second metal connection column 108 is located at the center of symmetry of the second metal connection block 118, so as to increase the contact area between the second metal connection block 118 and the second antenna metal layer 110 and improve the electrical stability.

[0117] Specifically, the wire bonding process includes one of a thermocompression wire bonding process, an ultrasonic wire bonding process, and a thermocompression ultrasonic wire bonding process; the materials of the second metal connection column 108 and the second metal connection block 118 include one or a combination of Au, Ag, Cu, and Al.

[0118] As Figures 5 to 6 shown, then step S4 is carried out, and the second antenna metal layer 110 and the second metal connection column 108 are encapsulated by the second encapsulation layer 109, and the second encapsulation layer 109 exposes the second metal connection column 108.

[0119] As a further embodiment of this embodiment, the method for forming the second encapsulation layer 109 in step S4 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating, and the material of the second encapsulation layer 109 includes one of polyimide, silica gel, and epoxy resin.

[0120] Specifically, after the second encapsulation layer 109 is formed, it further includes applying a grinding or polishing method to the surface of the second encapsulation layer 109 to provide a flat second encapsulation layer 109 and improve the electrical connection between the first antenna metal layer 107 formed subsequently and the second metal connection column 108.

[0121] As Figure 7 shown, then step S5 is carried out, and the first antenna metal layer 107 is formed on the second encapsulation layer 109, and the first antenna metal layer 107 is electrically connected to the second metal connection column 108.

[0122] Specifically, the first antenna metal layer 107 can be first formed on the second encapsulation layer 109 by a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process, or a chemical plating process, and then an etching process is used to form the required patterned first antenna metal layer 107.

[0123] As Figure 8 shown, then step S6 is carried out, and the first metal connection column 104 is formed on the first antenna metal layer 107, and the first metal connection column 104 is electrically connected to the first antenna metal layer 107.

[0124] As a further embodiment of this embodiment, forming the first metal connection column 104 in step S6 includes the following steps:

[0125] S6-1: A first metal connection block 114 is formed on the first antenna metal layer 107, and the first metal connection block 114 is electrically connected to the first antenna metal layer 107;

[0126] S6-2: The first metal connection column 104 is formed on the upper surface of the first metal connection block 114 by using a wire bonding process, and the cross-sectional area of the first metal connection block 114 is larger than that of the first metal connection column 104. Preferably, the first metal connection column 104 is located at the symmetric center of the first metal connection block 114, so as to increase the contact area between the first metal connection block 114 and the first antenna metal layer 107 and improve the electrical stability.

[0127] As Figure 9 shown, then step S7 is carried out. A semiconductor chip 105 is provided and the semiconductor chip 105 is bonded to the second encapsulation layer 109. Among them, the semiconductor chip 105 further includes a chip metal part 115 connected to the contact pads of the semiconductor chip 105.

[0128] Specifically, the chip metal part 115 includes one of a metal column with a certain height and a metal ball. The chip metal part 115 serves as the electrical connection end of the semiconductor chip 105, which is convenient for process operation and avoids the wire bonding process on the contact pads of the semiconductor chip 105, thereby improving the stability and yield of the semiconductor chip 105. The material of the chip metal part 115 includes one of copper, nickel, tin and silver. In this embodiment, the chip metal part 115 adopts the metal column, and the height range of the metal column includes 25μm to 250μm. The number and types of the semiconductor chips 105 are not limited here.

[0129] As a further embodiment of this embodiment, the semiconductor chip 105 is bonded to the surface of the second encapsulation layer 109 through an adhesive layer 125. The adhesive layer 125 includes one of an epoxy resin layer and a polymer film layer, such as a metal DAF film, a metal conductive adhesive, etc.

[0130] As Figures 10 to 11 shown, then step S8 is carried out. The first antenna metal layer 107, the first metal connection column 104 and the semiconductor chip 105 are encapsulated by using a first encapsulation layer 106, and the first encapsulation layer 106 exposes the first metal connection column 104 and the chip metal part 115.

[0131] As a further embodiment of this embodiment, the method for forming the first encapsulation layer 106 in step S8 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating. The material of the first encapsulation layer 106 includes one of polyimide, silica gel and epoxy resin.

[0132] Specifically, after forming the first encapsulation layer 106, it further includes applying a grinding or polishing method to the surface of the first encapsulation layer 106 to provide a flat first encapsulation layer 106, improving the electrical connection between the subsequently formed redistribution layer 103, the first metal connection pillar 104, and the chip metal part 115.

[0133] As Figure 12 shown, then step S9 is performed to form a redistribution layer 103 on the surface of the first encapsulation layer 106. The redistribution layer 103 includes a second surface in contact with the first encapsulation layer 106 and an opposite first surface. The redistribution layer 103 is electrically connected to the first metal connection pillar 104 and the chip metal part 115.

[0134] As a further embodiment of this embodiment, forming the redistribution layer 103 in step S9 includes the following steps:

[0135] S9-1: Form a dielectric layer 113 on the first encapsulation layer 106 by physical vapor deposition process or chemical vapor deposition process, and etch the dielectric layer 113 to form a patterned dielectric layer 113;

[0136] S9-2: Form a metal wiring layer 123 on the patterned dielectric layer 113 by physical vapor deposition process, chemical vapor deposition process, evaporation process, sputtering process, electroplating process or electroless plating process, and etch the metal wiring layer 123 to form a patterned metal wiring layer 123.

[0137] As a further embodiment of this embodiment, step S9 further includes N cyclic steps formed by combining step S9-1 and step S9-2, where N≥1.

[0138] As a further embodiment of this embodiment, the side surface of the chip metal part 115 is covered by the dielectric layer 113 in the redistribution layer 103. Since the side surface of the chip metal part 115 with a certain height is covered by the dielectric layer 113, the electrical stability between the semiconductor chip 105 and the redistribution layer 103 can be further enhanced.

[0139] As Figure 13 shown, then step S10 is performed to form metal bumps 111 on the first surface of the redistribution layer 103.

[0140] Specifically, the metal bump 111 is formed on the metal wiring layer 123 of the encapsulation structure obtained in step S9. The metal bump 111 includes one of solder, silver solder, and gold-tin alloy solder. The metal bump 111 may further include a columnar metal connected to the metal bump 111. The redistribution layer 103 may include multiple layers of the patterned dielectric layer 113 and the patterned metal wiring layer 123, which is not limited herein.

[0141] As Figure 14 shown, finally, step S11 is performed to peel off the support substrate 101 based on the separation layer 102.

[0142] Specifically, the LTHC photothermal conversion layer is heated based on a laser to separate the support substrate 101 from the LTHC photothermal conversion layer.

[0143] In summary, the fan-out antenna encapsulation structure and encapsulation method of the present invention have the following beneficial effects:

[0144] 1) The present invention uses a redistribution layer and metal connection columns to realize the integration of multiple antenna metal layers, greatly improving the efficiency and performance of the antenna and enhancing the integration of the antenna encapsulation structure;

[0145] 2) The present invention places the semiconductor chip in the encapsulation layer, and the bonding layer between the antenna metal layer and the semiconductor chip is on the same horizontal plane, saving space volume and making the volume of the encapsulation structure smaller; while encapsulating the metal connection columns and the antenna metal layer, the encapsulation layer also realizes the encapsulation of the semiconductor chip, improving the stability of the semiconductor chip and saving costs;

[0146] 3) Before bonding the semiconductor chip, the present invention first forms metal connection columns, improving the cleanliness of the bonding surface between the metal connection columns and the antenna metal layer and enhancing the stability of the metal connection columns;

[0147] 4) The present invention directly forms a redistribution layer on the encapsulation layer, simultaneously realizing the electrical connection of the metal connection columns and the semiconductor chip and reducing the process complexity;

[0148] 5) All the antenna metal layers of the present invention are located within the encapsulation layer, which can further reduce the volume of the encapsulation structure. And in the final step, the support substrate is peeled off based on the separation layer, improving the cleanliness and electrical stability of the encapsulation structure;

[0149] 6) The present invention uses a fan-out encapsulation method to encapsulate the antenna structure, which can effectively reduce the encapsulation volume, making the antenna encapsulation structure have a high integration degree and better encapsulation performance, and having a wide application prospect in the field of semiconductor packaging.

[0150] Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value. The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A fan-out antenna package structure, characterized in that, The encapsulation structure includes: A redistribution layer, the redistribution layer including an opposite first surface and a second surface, the redistribution layer including a patterned dielectric layer and a patterned metal wiring layer stacked in sequence; A first metal connection post, located on the second surface of the redistribution layer and electrically connected to the redistribution layer; A first antenna metal layer, located on the first metal connection post and electrically connected to the first metal connection post; A semiconductor chip, located on the second surface of the redistribution layer and electrically connected to the redistribution layer, the semiconductor chip further including a chip metal part connected to a contact pad of the semiconductor chip, and a side surface of the chip metal part being covered by the redistribution layer to enhance electrical stability between the semiconductor chip and the redistribution layer; A first encapsulation layer, covering the redistribution layer, the first metal connection post, the first antenna metal layer, and the semiconductor chip, and the first encapsulation layer exposing the first antenna metal layer and an adhesive layer adhered to the semiconductor chip; A second metal connection post, located on the first antenna metal layer and electrically connected to the first antenna metal layer; A second antenna metal layer, located on the second metal connection post and electrically connected to the second metal connection post, realizing the integration of multiple antenna metal layers, improving the efficiency and performance of the antenna, further improving the integration of the antenna encapsulation structure, reducing the encapsulation volume, and enabling the antenna encapsulation structure to have a high integration degree; A second encapsulation layer, covering the second metal connection post and the second antenna metal layer, and the second encapsulation layer exposing the second antenna metal layer; and Metal bumps, located on the first surface of the redistribution layer, the metal bumps including one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump.

2. The fan-out antenna package structure according to claim 1, wherein: The chip metal part includes one of a metal post and a metal ball.

3. The fan-out type antenna packaging structure according to claim 1, wherein: The adhesive layer includes one of an epoxy resin layer and a polymer thin film layer.

4. The fan-out antenna packaging structure according to claim 1, wherein: A first metal connection block is further included between the first metal connection post and the first antenna metal layer, and a cross-sectional area of the first metal connection block is larger than that of the first metal connection post; a second metal connection block is further included between the second metal connection post and the second antenna metal layer, and a cross-sectional area of the second metal connection block is larger than that of the second metal connection post.

5. The fan-out antenna package structure according to claim 1, wherein: The first encapsulation layer includes one of an epoxy resin layer, a polyimide layer, and a silicone layer; the second encapsulation layer includes one of an epoxy resin layer, a polyimide layer, and a silicone layer.

6. The fan-out type antenna package structure according to claim 1, wherein: The dielectric layer includes one or a combination of two or more of an epoxy resin layer, a silicone layer, a PI layer, a PBO layer, a BCB layer, a silicon oxide layer, a phosphosilicate glass layer, and a fluorine-containing glass layer, and the metal wiring layer includes one or a combination of two or more of a copper layer, an aluminum layer, a nickel layer, a gold layer, a silver layer, and a titanium layer.

7. A fan-out type antenna packaging method, characterized in that, Including the following steps: S1: Provide a support substrate, and form a separation layer on the support substrate; S2: Form a second antenna metal layer on the separation layer; S3: Form a second metal connection post on the second antenna metal layer; S4: Encapsulate the second antenna metal layer and the second metal connection posts with a second encapsulation layer, and expose the second metal connection posts on the second encapsulation layer; S5: Form a first antenna metal layer on the second encapsulation layer, and electrically connect the first antenna metal layer to the second metal connection posts, realizing the integration of multi-layer antenna metal layers, improving the efficiency and performance of the antenna, further enhancing the integration of the antenna encapsulation structure, reducing the encapsulation volume, and enabling the antenna encapsulation structure to have a high degree of integration; S6: Form first metal connection posts on the first antenna metal layer; S7: Provide a semiconductor chip, and bond the semiconductor chip to the second encapsulation layer. Among them, the semiconductor chip further includes a chip metal part connected to the contact pads of the semiconductor chip; S8: Encapsulate the first antenna metal layer, the first metal connection posts and the semiconductor chip with a first encapsulation layer, and expose the first metal connection posts and the chip metal part on the first encapsulation layer; S9: Form a redistribution layer on the first encapsulation layer. The redistribution layer includes a second surface in contact with the first encapsulation layer and an opposite first surface. The redistribution layer is electrically connected to the first metal connection posts and the chip metal part, and the side surface of the chip metal part is covered by the redistribution layer to enhance the electrical stability between the semiconductor chip and the redistribution layer; S10: Form metal bumps on the first surface of the redistribution layer; and S11: Peel off the support substrate based on the separation layer.

8. The fan-out type antenna packaging method according to claim 7, wherein: The support substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate; the separation layer includes one of a tape and a polymer layer, and the curing method of the polymer layer includes one of ultraviolet curing and thermal curing.

9. The fan-out type antenna packaging method according to claim 7, wherein: The method for forming the second encapsulation layer in step S4 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating; the method for forming the first encapsulation layer in step S8 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating.

10. The fan-out type antenna packaging method according to claim 7, characterized in that: The formation of the second metal connection posts in step S3 includes the following steps: S3-1: Form second metal connection blocks on the second antenna metal layer, and electrically connect the second metal connection blocks to the second antenna metal layer; S3-2: Use a wire bonding process to form the second metal connection posts on the upper surface of the second metal connection blocks, and the cross-sectional area of the second metal connection blocks is larger than that of the second metal connection posts.

11. The fan-out type antenna packaging method according to claim 7, characterized in that: The formation of the first metal connection posts in step S6 includes the following steps: S6-1: Form first metal connection blocks on the first antenna metal layer, and electrically connect the first metal connection blocks to the first antenna metal layer; S6-2: Use a wire bonding process to form the first metal connection posts on the upper surface of the first metal connection blocks, and the cross-sectional area of the first metal connection blocks is larger than that of the first metal connection posts.

12. The fan-out antenna packaging method according to claim 7, wherein: The formation of the redistribution layer in step S9 includes the following steps: S9-1: A dielectric layer is formed on the first encapsulation layer by using a physical vapor deposition process or a chemical vapor deposition process, and the dielectric layer is etched to form a patterned dielectric layer; S9-2: A metal wiring layer is formed on the patterned dielectric layer by using a physical vapor deposition process, a chemical vapor deposition process, an evaporation process, a sputtering process, an electroplating process or a chemical plating process, and the metal wiring layer is etched to form a patterned metal wiring layer.

13. The fan-out type antenna packaging method according to claim 12, wherein: Step S9 further includes N cyclic steps formed by combining step S9-1 and step S9-2, where N≥1.

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