A digitally compensated differential signal acquisition system circuit and compensation method

Abstract

The invention relates to the technical field of signal processing, in particular to a digitally compensated differential signal acquisition system circuit and a compensation method, comprising a high-frequency electromagnetic interference filter, a differential amplifier, an analog-to-digital converter, a processor, and a controller. The output end of the high-frequency electromagnetic interference filter is connected to the input end of the differential amplifier, the output end of the differential amplifier is connected to the analog input end of the analog-to-digital converter, the digital output end of the analog-to-digital converter is connected to the digital input end of the processor, the control input end of the analog-to-digital converter is connected to the control output end of the controller, and the timing control output end of the controller is connected to the timing control input end of the analog-to-digital converter. Compared with the prior art, the invention overcomes the technical problems of mismatch between channels and reduced common-mode rejection ratio caused by precision mismatch and drift of analog devices, while reducing device cost, reducing the power and temperature of device operation, and improving the stability of the device.

Description

Technical Field

[0001] The invention relates to the technical field of signal processing, in particular to a digitally compensated differential signal acquisition system circuit and a compensation method. Background Art

[0002] In signal acquisition systems, especially those involving medical diagnostic information, single-ended signals are often converted into differential signals to enhance the anti-interference performance in the signal transmission link. A pair of differential signals can be described by the following formula: ,in, For common mode signals, , The two poles are equal in amplitude and phase; For differential mode signals, , The two poles have equal amplitude and a phase difference of 180°.

[0003] In the electrophysiological system, the single-ended electrical signal from the human body is picked up by electrodes on the body surface and inside the body, and after being processed by single-ended to differential conversion, it enters the differential amplifier for amplification, such as Figure 1 The differential amplifier circuit shown in Figure 1. Under ideal conditions, the output voltage of the amplifier is given by the following formula: .

[0004] Furthermore, when conditions, and will Substitute, It can be further simplified to That is, in an ideal situation, the common mode signal is completely suppressed by the differential amplifier and only the differential mode signal is amplified.

[0005] The above discussion is based on the following conditions: 1) The amplifier is an ideal amplifier, that is, Has the ability to completely suppress; 2) In reality, since the internal circuit of the amplifier cannot be completely symmetrical, it is impossible to achieve Complete inhibition of. The actual resistor values ​​described cannot be completely equal, and the resistor ratio cannot be completely adapted. At the same time, the resistor value will change in an environment with temperature changes. The law of is the resistance at temperature The resistance value when is the resistance at temperature The resistance value when is the resistance change caused by temperature change, is the temperature relative to the temperature The amount of change, usually inside the chassis, The maximum temperature can reach 50-60℃. For the resistor The average rate of change of resistance value with temperature in the range of Generally, it is ±200-400PPM / ℃. Assuming that the resistor is a thick film chip resistor, and the zero power resistance at 25℃ is 1000Ω, then in a chassis with good heat dissipation, its resistance value will change to 1000±6Ω, and the change amount reaches 0.6% of the original resistance value.

[0006] The resistance drift discussed above will cause some Towards Changes in the common-mode signal result in a decrease in the performance of the amplifier based on the analog circuit. In engineering, the ability of the amplifier to suppress common-mode signals is called the common-mode rejection ratio (CMRR). Give its mathematical definition, where It represents the gain of the amplifier for differential mode signal. Represents the amplifier's gain for common-mode signals.

[0007] Below Figure 1 As an example, the influence of external resistor mismatch on the common mode rejection ratio of the amplifier is discussed. Assuming that the resistors are of the same precision, their tolerance is , , then middle, and can be express.

[0008] The common mode rejection ratio caused by the resistor is recorded as , the common-mode rejection ratio caused by the amplifier device is recorded as The overall common mode rejection ratio R of the two is recorded as ,but: , That is, the common-mode rejection ratio caused by the resistor is related to the differential-mode gain and the resistor accuracy. The overall common-mode rejection ratio is given by and The smaller value is determined.

[0009] exist , Based on the assumption that the differential mode gain , , , then we can calculate If other conditions remain unchanged, , then we can calculate If the common-mode rejection ratio of the amplifier is to be fully utilized, the corresponding resistor accuracy , which is obviously unrealistic from a technical and economic perspective.

[0010] Due to the continuous development of semiconductor technology, the common-mode rejection ratio of the amplifier device itself can reach up to 120~140dB, that is, the common-mode signal amplitude at the output of the amplifier can reach a minimum of 10% of the input common-mode signal amplitude. -6 Up to 10 -7 In order to achieve such excellent common-mode rejection performance, the required resistor adaptation requirements will be more stringent. In addition, the slight differences in circuit board wiring and the on-resistance differences between channel switching devices make it almost impossible to achieve in the analog domain.

[0011] Figure 2 It is the overall circuit structure of the existing multi-channel medical electrical signal acquisition and processing system. 1 To BUF N It is an analog buffer amplifier that plays the role of impedance transformation and is used to obtain weak electrical signals from the human body with high signal source internal resistance. 1 To AMP N is a differential amplifier with Figure 1 The circuit structure shown has a general theoretical gain of 20-100V / V. 1 To AAF N It is an anti-aliasing filter network, usually composed of a low-pass RC filter, which is used to filter out signals outside the required spectrum to avoid spectrum aliasing distortion in subsequent processing. MUX is a channel selection network, usually composed of multiple analog switches, whose channel on-impedance is about tens to hundreds of ohms, and the on-impedance consistency between channels is relatively poor, which aggravates the gain mismatch between channels. ADC is an analog-to-digital converter device, generally using at least 14 bits in the medical field and a sampling rate of at least 100kSa / s to meet the needs of collecting weak signals. PROC is a processor, which is directly connected to the analog-to-digital converter device, and is used to receive digitized electrophysiological signals sent from the analog-to-digital converter device, and communicates with the controller CTRL at the same time to control the channel selection network MUX to switch channels. It can be found that in the existing multi-channel medical electrical signal acquisition and processing system, due to the presence of many analog devices, such as resistors and capacitors, according to The discussion will have a great impact on the common-mode rejection ratio of the amplifier. The direct result is that the gains of different channels are different. Therefore, it is impossible to directly differentiate each channel to form a so-called bipolar signal, which greatly reduces the flexibility and reliability of the acquisition system.

[0012] From the above analysis, the current signal processing field, especially the medical electrophysiological signal processing field, needs to design a digitally compensated differential signal acquisition system circuit and compensation method to relax the accuracy requirements of analog devices, reduce system complexity and manufacturing costs, improve system stability, and solve the above-mentioned technical problems caused by analog device accuracy and drift. Summary of the invention

[0013] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a digitally compensated differential signal acquisition system circuit and compensation method, relax the accuracy requirements of analog devices, reduce system complexity and manufacturing costs, and improve system stability.

[0014] In order to achieve the above-mentioned purpose, the present invention is a digitally compensated differential signal acquisition system circuit, comprising a high-frequency electromagnetic interference filter, a differential amplifier, an analog-to-digital converter, a processor, and a controller, characterized in that: the output end of the high-frequency electromagnetic interference filter is connected to the input end of the differential amplifier, the output end of the differential amplifier is connected to the analog input end of the analog-to-digital converter, the digital output end of the analog-to-digital converter is connected to the digital input end of the processor, the control input end of the analog-to-digital converter is connected to the control output end of the controller, the timing control output end of the controller is connected to the timing control input end of the analog-to-digital converter, the differential amplifier comprises a reference voltage source, a reference digital-to-analog converter 1, a reference digital-to-analog converter 2, and an amplifier, the output end of the reference voltage source is connected to the power supply end of the reference digital-to-analog converter 1, the input end of the reference digital-to-analog converter 1 is connected to the digital reference source, the output end of the reference digital-to-analog converter 1 is connected to the in-phase input end of the amplifier, the inverting input end of the amplifier is connected to the output end of the high-frequency electromagnetic interference filter, the input end of the reference digital-to-analog converter 2 is connected to the digital gain signal, the output end of the reference digital-to-analog converter 2 is connected to the gain control input end of the amplifier, and the output end of the amplifier is connected to the analog input end of the analog-to-digital converter.

[0015] The high-frequency electromagnetic interference filter is an LC network composed of inductance and capacitance, and the -3dB frequency of the LC network is less than 20MHz.

[0016] The maximum sampling frequency of the analog-to-digital converter is greater than 500KSa / S, the number of effective conversion bits is greater than or equal to 12, the clock frequency of the processor is greater than 24MHz, and the controller is a 32-bit or 64-bit controller.

[0017] The output initial accuracy of the reference voltage source is less than ±0.2%, the output noise amplitude is less than 100 μVpp, and the effective conversion bit number of the reference digital-to-analog converter 1 and the reference digital-to-analog converter 2 is greater than or equal to 12.

[0018] The amplifier is a variable gain amplifier or a fixed gain amplifier. The gain of the variable gain amplifier can be continuously adjusted within the range of 3dB to 40dB, and the gain range of the fixed gain amplifier is 10-200 V / V.

[0019] A compensation method for a digitally compensated differential signal acquisition system circuit, characterized in that the steps of obtaining a gain amplitude-frequency response curve of a channel are as follows: Step 1, determining a theoretical gain; Step 2, determining a starting frequency , the frequency is , the amplitude is The sine signal is loaded to the input of the amplifier; Step 3, the amplitude of the output sine signal of the amplifier is measured. ; Step 4, calculate the amplifier Gain at frequency ; Step 5, set the amplitude to The frequency of the sinusoidal signal increases to , loaded to the amplifier input; Step 6, measure the output sine signal amplitude of the amplifier ; Step 7, calculate the amplifier Gain at frequency ; Step 8, repeat steps 1 to 7, wherein, The frequency of the sinusoidal signal at the frequency point is , the measured amplitude of the sinusoidal signal is , the calculated gain ; Step 9, set the sampling frequency to , then when When Plotted in sequence in a rectangular coordinate system, it becomes the gain amplitude-frequency response curve of the channel.

[0020] The In the formula, i is a natural number greater than or equal to 1.

[0021] After obtaining the gain amplitude-frequency response curve of the channel, calculate the gain amplitude-frequency response curve for different frequency points. Gain correction factor , ; Calculation for different frequencies The calibrated gain , ; Different frequency points Gain after calibration Saved to the processor for use in digital compensation.

[0022] After obtaining the gain amplitude-frequency response curve of the channel, proceed as follows: Step a, apply the Laplace transform method to establish the mathematical model of the circuit; Step b, according to different frequency points Calculated gain , and infer the actual analog device value ; Step c, in the digital domain, calculate the frequency Theoretical gain The corresponding theoretical value of the analog device ; Step e, calculate for different frequencies Different resistors and capacitors Correction factor , ; Step f, calculate for different frequencies Different resistors and capacitors Application of numerical calibration , Step g, different frequency points Different resistors and capacitors All values ​​are saved in the processor for use in digital compensation.

[0023] Compared with the prior art, the present invention designs a digitally compensated differential signal acquisition system circuit and a compensation method, which overcomes the technical problems of channel mismatch and reduced common mode rejection ratio caused by precision mismatch and drift of analog devices, while reducing device costs, lowering the power and temperature of equipment operation, and improving the stability of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 FIG. 1 is an electrical schematic diagram of a differential amplifier in the prior art.

[0025] Figure 2 The present invention is an overall circuit diagram of a multi-channel medical electrical signal acquisition and processing system in the prior art.

[0026] Figure 3 This is the overall circuit structure of the present invention.

[0027] Figure 4 This is the circuit structure of the differential amplifier in the present invention.

[0028] Figure 5 It is a frequency response diagram of two analog channels without digital compensation in the present invention.

[0029] Figure 6 It is a schematic diagram of the digital compensation method 1 in the present invention.

[0030] Figure 7 It is a schematic diagram of digital compensation method 2 in the present invention. DETAILED DESCRIPTION

[0031] The present invention will now be further described with reference to the accompanying drawings.

[0032] See also Figure 3-4The present invention is a digitally compensated differential signal acquisition system circuit, comprising a high-frequency electromagnetic interference filter, a differential amplifier, an analog-to-digital converter, a processor, and a controller. The output end of the high-frequency electromagnetic interference filter is connected to the input end of the differential amplifier, the output end of the differential amplifier is connected to the analog input end of the analog-to-digital converter, the digital output end of the analog-to-digital converter is connected to the digital input end of the processor, the control input end of the analog-to-digital converter is connected to the control output end of the controller, and the timing control output end of the controller is connected to the timing control input end of the analog-to-digital converter. The differential amplifier comprises a reference voltage source, a reference digital-to-analog converter 1, a reference digital-to-analog converter 2, and an amplifier. The output end of the reference voltage source is connected to the power supply end of the reference digital-to-analog converter 1, the input end of the reference digital-to-analog converter 1 is connected to the digital reference source, the output end of the reference digital-to-analog converter 1 is connected to the in-phase input end of the amplifier, the inverting input end of the amplifier is connected to the output end of the high-frequency electromagnetic interference filter, the input end of the reference digital-to-analog converter 2 is connected to the digital gain signal, the output end of the reference digital-to-analog converter 2 is connected to the gain control input end of the amplifier, and the output end of the amplifier is connected to the analog input end of the analog-to-digital converter.

[0033] In the present invention, the high-frequency electromagnetic interference filter is an LC network composed of inductors and capacitors, the -3dB frequency of the LC network is less than 20MHz, the model is NFW31SP106X1E4K, NFW31SP206X1E4L, or it is composed of an LC network composed of discrete inductors or capacitors, which is less susceptible to temperature and can pass a larger current. The maximum sampling frequency of the analog-to-digital converter is greater than 500KSa / S, and the number of effective conversion bits is greater than or equal to 12, and the models are AD7720, AD9874, ADS1675, ADS1672, etc. The clock frequency of the processor is greater than 24MHz, and the model is TMS320C6748. The controller is a 32-bit or 64-bit controller, and the model is XC6SLX4. The initial output accuracy of the reference voltage source is less than ±0.2%, and the output noise amplitude is less than 100μV pp , models are REF2041, REF6250, LTC6652AHLS8-5, LTC6655BHLS8-4.096, etc. The effective conversion bit number of the reference digital-to-analog converter 1 and the reference digital-to-analog converter 2 is greater than or equal to 12, and the models are DAC80501, DAC8551, DAC8311, etc. The amplifier is a variable gain amplifier of models AD8338, AD8330, AD8336, VCA810, etc. or a fixed gain amplifier of models INA141, INA2141, INA106, LT1101, AD621, etc. The gain of the variable gain amplifier can be continuously adjusted in the range of 3dB to 40dB, and the gain range of the fixed gain amplifier is 10-200 V / V.

[0034] Figure 3 It is the overall circuit structure of the present invention. Among them, EMIF 1 To EMIF N It is a high frequency electromagnetic interference filter. AMP 1 To AMP N It is a differential amplifier, which can be composed of a fixed-gain amplifier or a digitally controlled variable-gain amplifier. The purposes of this level are as follows: 1) to perform impedance transformation and obtain weak electrical signals from the human body with high signal source internal resistance; 2) to amplify weak electrical signals; 3) to drive subsequent analog-to-digital conversion devices, such as converting single-ended signals into differential signals and driving differential input analog-to-digital conversion devices. Among them, the gain of the fixed-gain amplifier is set by the resistors packaged inside the integrated circuit. Since these resistors are trimmed during the manufacturing process of the integrated circuit, the resistor matching degree packaged inside the fixed-gain amplifier is very high, so that the gain error between different fixed-gain amplifiers of the same model is less than 0.3%, avoiding the gain mismatch problem caused by the incompatibility of external gain resistors. Another implementation method is to use a digitally controlled variable-gain amplifier. The gain of this amplifier is driven by a digital signal to drive a digital-to-analog converter, and the absolute accuracy of the controlled gain can reach ±0.25dB. The signal passing through the amplifier is converted to the analog-to-digital converter ADC by the analog-to-digital converter device. 1 To ADC N Acquisition. Among them, the analog-to-digital converter preferably adopts a multi-channel synchronous sampling analog-to-digital converter with Sigma-Delta modulation, because its conversion accuracy can reach 24bit, and the sampling rate can reach 500-600kSa / S, which is much higher than the frequency range of general electrophysiological signals, generally DC-2KHz, so it can greatly relax the design requirements of the anti-aliasing filter network in the existing medical electrical signal acquisition and processing system, and even omit the corresponding analog anti-aliasing filter network, and process it in the digital domain instead; at the same time, because each channel is sampled synchronously, the problem of crosstalk between channels caused by the external channel switching network MUX is avoided, but because the price of this type of device is relatively expensive, in order to save cost considerations, an analog-to-digital converter ADC with an internal channel switching device can be used instead, and an appropriate channel acquisition timing can be used to maintain good channel consistency and reduce crosstalk between channels. The converted digital signal is transmitted to the processor PROC for digital filtering, digital compensation and other operations. The processor PROC communicates with the controller CTRL to control the timing of reading the data collected by the analog-to-digital converter ADC. Figure 3 Single-ended signal of each channel arrive After the above amplification, analog-to-digital conversion and digital compensation, due to the gain error between the channels , any two single-ended signals can be combined in the digital domain to form a corresponding differential signal, greatly improving the performance of the amplifier.

[0035] Figure 4 This is the circuit structure of the differential amplifier of the present invention. In which, DAC 1 , DAC 2 is the reference digital-to-analog converter, REF is the reference voltage source, and is the reference digital-to-analog converter-DAC 1 Provides reference voltage for digital-to-analog conversion. Reference digital-to-analog converter - DAC 1 Output Connect to the in-phase input of the digital control variable gain amplifier VGA, the analog signal Connect to the inverting input of VGA. Reference digital-to-analog converter 2 DAC 2 For digital gain control, the analog voltage output Connected to the gain control input of the variable gain amplifier VGA, the output voltage of the variable gain amplifier VGA can be Given. Among them, is the gain of the variable gain amplifier VGA, is the potential of the non-inverting input terminal of the variable gain amplifier VGA, is the potential of the inverting input terminal of the variable gain amplifier VGA, is the gain control coefficient, which is related to the specific variable gain amplifier VGA device selection. The output voltage of the variable gain amplifier VGA is then converted into a digital signal by the analog-to-digital converter ADC.

[0036] Figure 5 This is the amplitude-frequency response of the two analog channels without digital compensation. The horizontal dotted line at +20dB in the figure is the theoretical gain of channels A and B. The solid line indicated by A is the gain frequency response curve of channel A, and the dotted line indicated by B is the gain frequency response curve of channel B. - Inside the thick solid circle at the frequency point, it can be seen that channels A and B deviate from the theoretical gain at these frequency points; for the same channel at different frequency points, its gain also fluctuates, rather than being a flat horizontal line; and the cutoff frequency of the -3dB passband of channels A and B is Assume that channel A is , i=1,2,…, gain at the frequency point With theoretical gain The difference between , B channel in Gain at frequency With theoretical gain The difference between , then the digital compensation in the processor PROC is to make the frequency band of the electrical signal within a certain range, so that , All tend to 0, thereby improving the gain matching between channels.

[0037] See also Figure 6 , the curve drawn by the solid line is the gain frequency response of a certain channel. The digital compensation involved in this method is as follows: First, obtain the gain frequency response curve of the channel, the steps are as follows: Step 1, determine the theoretical gain; Step 2, determine the starting frequency , the frequency is , the amplitude is The sine signal is loaded to the input of the amplifier; Step 3, the amplitude of the output sine signal of the amplifier is measured. ; Step 4, calculate the amplifier Gain at frequency ; Step 5, set the amplitude to The frequency of the sinusoidal signal increases to , loaded to the amplifier input; Step 6, measure the output sine signal amplitude of the amplifier ; Step 7, calculate the amplifier Gain at frequency ; Step 8, repeat steps 1 to 7, wherein, The frequency of the sinusoidal signal at the frequency point is , the measured amplitude of the sinusoidal signal is , the calculated gain ; Step 9, set the sampling frequency to , then when When Plotted in sequence in a rectangular coordinate system, it is the gain amplitude-frequency response curve of the channel, where i is a natural number greater than or equal to 1.

[0038] After obtaining the gain amplitude-frequency response curve of the channel, calculate the gain amplitude-frequency response curve for different frequency points. Gain correction factor , ; Calculation for different frequencies The calibrated gain , ; Different frequency points Gain after calibration Saved to the processor for use in digital compensation.

[0039] Finally, change to a different channel and repeat the above steps.

[0040] The accuracy of each channel gain after the above digital gain compensation calibration is only determined by the number of bits of floating point numbers stored in the processor PROC. In existing processors PROC, 32 bits are often used to store floating point numbers. After removing one sign bit, the matching degree of the channel gain obtained, that is, the error between the channel gains can reach , which is much greater than the existing analog amplifier channel gain matching. Theoretically, digital equalization filters can also be used to complete the above operations, but due to their bandwidth If it is large, it will have a certain impact on the flatness of the channel gain.

[0041] See also Figure 7 , the curve drawn by the solid line is the gain amplitude-frequency response of a certain channel. The digital compensation involved in this method is as follows: the method for obtaining the gain amplitude-frequency response curve of the channel is the same as the above.

[0042] After obtaining the gain amplitude-frequency response curve of the channel, proceed as follows: Step a, apply the Laplace transform method to establish the mathematical model of the circuit; Step b, according to different frequency points Calculated gain , and infer the actual analog device value ; Step c, in the digital domain, calculate the frequency Theoretical gain The corresponding theoretical value of the analog device ; Step e, calculate for different frequencies Different resistors and capacitors Correction factor , ; Step f, calculate for different frequencies Different resistors and capacitors Application of numerical calibration , Step g, different frequencies Different resistors and capacitors All the values ​​are saved to the processor for digital compensation. Specific digital compensation is used at different frequencies. In the digital domain, a set of data that can make the resistors and capacitors most suitable can be used to compensate the circuit model established in the digital domain.

[0043] Finally, change to a different channel and repeat the above steps.

[0044] The accuracy of each channel gain after the above digital gain compensation calibration is only determined by the number of bits of floating point numbers stored in the processor PROC. In existing processors PROC, 32 bits are often used to store floating point numbers. After removing one sign bit, the matching degree of the channel gain obtained, that is, the error between the channel gains can reach , which is much greater than the existing analog amplifier channel gain matching. Theoretically, digital equalization filters can also be used to complete the above operations, but due to their bandwidth If it is large, it will have a certain impact on the flatness of the channel gain.

[0045] After the above digital resistor and capacitor value compensation, the mismatch degree of the resistor and capacitor values ​​in the digital domain is only determined by the number of bits stored in the floating point number in the processor PROC. If the existing 32-bit floating point processor PROC device is used, the mismatch between the resistor and capacitor can reach ,according to , Calculation, assuming the differential mode gain is , the common mode rejection ratio caused by the resistor It can reach 208.7dB, which is much higher than the common mode rejection ratio CMRR based on current analog amplifiers.

[0046] Apart from Figure 6 , Figure 7 In addition to the digital compensation method described above, the time domain digital signal output by the analog-to-digital converter ADC can be FFT-ed, and then different frequency points can be compensated in the frequency domain. After compensating the gain, IFFT is used to transform the frequency domain signal into the time domain.

Claims

1. A digitally compensated differential signal acquisition system circuit, comprising a high-frequency electromagnetic interference filter, a differential amplifier, an analog-to-digital converter, a processor, and a controller, characterized in that: The output end of the high-frequency electromagnetic interference filter is connected to the input end of the differential amplifier, the output end of the differential amplifier is connected to the analog input end of the analog-to-digital converter, the digital output end of the analog-to-digital converter is connected to the digital input end of the processor, the control input end of the analog-to-digital converter is connected to the control output end of the controller, the timing control output end of the controller is connected to the timing control input end of the analog-to-digital converter, the differential amplifier includes a reference voltage source, a reference digital-to-analog converter 1, a reference digital-to-analog converter 2, and an amplifier, the output end of the reference voltage source is connected to the power supply end of the reference digital-to-analog converter 1, the input end of the reference digital-to-analog converter 1 is connected to the digital reference source, the output end of the reference digital-to-analog converter 1 is connected to the in-phase input end of the amplifier, the inverting input end of the amplifier is connected to the output end of the high-frequency electromagnetic interference filter, the input end of the reference digital-to-analog converter 2 is connected to the digital gain signal, the output end of the reference digital-to-analog converter 2 is connected to the gain control input end of the amplifier, and the output end of the amplifier is connected to the analog input end of the analog-to-digital converter. The steps to obtain the gain-frequency response curve of the channel are as follows: Step 1, determine the theoretical gain; Step 2, determine the starting frequency f1, and load a sinusoidal signal with a frequency of f1 and an amplitude of A to the input of the amplifier; Step 3, measure the output sinusoidal signal amplitude of the amplifier as A′1; Step 4, calculate the gain of the amplifier at the frequency point f1 Step 5, increase the frequency of the sinusoidal signal with amplitude A to f2 = f1 + Δf, and load it to the amplifier input; Step 6, measure the output sinusoidal signal amplitude of the amplifier to be A′2; Step 7, calculate the gain of the amplifier at the frequency point f2 Step 8: Repeat steps 1 to 7, where f n The frequency of the sinusoidal signal at the frequency point is f n =f1+(n-1)Δf, the measured amplitude of the sinusoidal signal is A′ n , the calculated gain Step 9, let the sampling frequency be f s , then when When the ordered pair (f i ,G′ i ) are plotted in sequence in a rectangular coordinate system, which is the gain amplitude-frequency response curve of the channel.

2. The digitally compensated differential signal acquisition system circuit according to claim 1, characterized in that: The high-frequency electromagnetic interference filter is an LC network composed of inductance and capacitance, and the -3dB frequency of the LC network is less than 20MHz.

3. The digitally compensated differential signal acquisition system circuit according to claim 1, characterized in that: The maximum sampling frequency of the analog-to-digital converter is greater than 500KSa / S, the number of effective conversion bits is greater than or equal to 12, the clock frequency of the processor is greater than 24MHz, and the controller is a 32-bit or 64-bit controller.

4. The digitally compensated differential signal acquisition system circuit according to claim 1, characterized in that: The output initial accuracy of the reference voltage source is less than ±0.2%, and the output noise amplitude is less than 100μV. pp The effective conversion bit number of the reference digital-to-analog converter 1 and the reference digital-to-analog converter 2 is greater than or equal to 12.

5. The digitally compensated differential signal acquisition system circuit according to claim 1, characterized in that: The amplifier is a variable gain amplifier or a fixed gain amplifier. The gain of the variable gain amplifier can be continuously adjusted within the range of 3dB to 40dB, and the gain range of the fixed gain amplifier is 10-200V / V.

6. The digitally compensated differential signal acquisition system circuit according to claim 1, characterized in that: The (f i ,G′ i ), i is a natural number greater than or equal to 1.

7. The digitally compensated differential signal acquisition system circuit according to claim 1, characterized in that: After obtaining the gain amplitude-frequency response curve of the channel, calculate the gain amplitude-frequency response curve for different frequency points. i The gain correction factor k i , Calculate the frequency f i The calibrated gain G i,C , G i,C =k i G′ i ; Different frequency points f i The calibrated gain G i，c Save to the processor for digital compensation, G is the frequency point f i Theoretical gain.

8. The digitally compensated differential signal acquisition system circuit according to claim 1, characterized in that: After obtaining the gain amplitude-frequency response curve of the channel, proceed as follows: Step a, apply the Laplace transform method to establish the mathematical model of the circuit; Step b, according to different frequency points f i Calculated gain G′ i , and inversely deduce the value of the actual analog device R′ i , C′ i ; Step c, in the digital domain, calculate the frequency point f i The theoretical value R of the analog device corresponding to the theoretical gain G i , C i ; Step d, calculate for different frequency points f i Different resistors and capacitors R i , C i The correction factor k R，i , k C，i , Step e: Calculate the frequency f at different frequencies. i Different resistors and capacitors R i , C i Application of numerical calibration R i，C , C i，C , R i，C =k R，i R′ i , C i，C =k C，i C′ i ; Step f, different frequency points f i Different resistors and capacitors R i , C i All values ​​are saved in the processor for use in digital compensation.

Images