Method for forming a semiconductor device

Abstract

The present disclosure provides a method for forming a semiconductor device. The present disclosure improves the method of exposing the conductive layer in the silicon through-hole via from the back of the semiconductor substrate in the process of forming a through-hole via, reduces the size of the semiconductor substrate removed by the grinding and thinning process in the existing process, and increases the size of the semiconductor substrate removed by the selective etching process. As a result, it is not necessary to grind the semiconductor substrate and the conductive layer at the same time, which prevents the conductive material ions in the conductive layer from diffusing into the semiconductor substrate, thereby improving the yield of the product.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor device. Background Art

[0002] 3D Integrated Circuit (IC) is defined as a system-level integrated structure that stacks multiple chips in a vertical plane direction to save space. At present, most 3D integrated circuit technologies use through silicon vias (TSV) to allow the circuits of multiple chips to be electrically connected to each other in the vertical direction. According to the different stages of the through silicon via manufacturing process, it can be divided into three process flows: via-first, via-middle and via-last. Among them, via-middle is a through silicon via that is etched on the wafer after manufacturing complementary metal oxide semiconductor (CMOS) but before the back end of line (BEOL). Generally, the via-middle process can be well integrated with other processes and is currently the most commonly used method in the industry.

[0003] In the through-hole process, the process of exposing the silicon via on the back of the wafer generally adopts grinding and chemical mechanical polishing (CMP) and other processes to thin the silicon substrate to expose the copper pillars in the silicon via, and then etch back the silicon substrate to make the copper pillars in the silicon via higher than the surface of the silicon substrate. Taking the process of silicon via with a depth of 110μm as an example, first, grinding and thinning to a semiconductor substrate thickness of 105μm, then chemical mechanical polishing to a semiconductor substrate thickness of 103μm, and then etch back the silicon substrate, generally using a selective etching process to remove part of the semiconductor substrate, so that the thickness of the semiconductor substrate is 98μm, and finally an isolation layer is deposited and the surface is flattened to expose the conductive layer.

[0004] However, since the copper pillars in the through-hole structure are exposed during the process of grinding and thinning the semiconductor substrate, copper ions diffuse outward into the substrate during the chemical mechanical polishing process. As a result, in the subsequent process of etching back the silicon substrate, the silicon substrate around the copper pillars cannot be completely etched because it is covered by copper ions, forming a Figure 1 The silicon shown is residual, and a large amount of copper ions exist on the surface of the residual silicon substrate, which causes leakage of semiconductor devices and reduces the yield of products. Summary of the invention

[0005] In view of this, the present disclosure provides a method for forming a semiconductor device to improve the yield of the semiconductor device.

[0006] The present invention provides a method for forming a semiconductor device, comprising:

[0007] Providing a first semiconductor substrate, a through-hole structure is formed on the front surface of the first semiconductor substrate, the through-hole structure includes a dielectric layer formed on the bottom and sidewall of the through-hole and a conductive layer filled on the dielectric layer;

[0008] connecting the front side of the first semiconductor substrate to the second semiconductor substrate;

[0009] thinning the back side of the first semiconductor substrate using a first planarization process;

[0010] Performing selective etching on the back side of the first semiconductor substrate to remove a portion of the substrate material of the first semiconductor substrate to expose the bottom of the through-hole structure, wherein the material of the first semiconductor substrate has a higher etching selectivity than the material of the dielectric layer;

[0011] Depositing an isolation layer on the back side of the etched first semiconductor substrate;

[0012] A second planarization process is used to thin the isolation layer and remove the dielectric layer at the bottom of the through-hole structure to expose the conductive layer in the through-hole structure.

[0013] Furthermore, the dielectric layer includes an oxide layer and a barrier layer stacked in sequence.

[0014] Furthermore, in the selective etching process, the substrate material is removed while the barrier layer is kept uncovered.

[0015] Further, the process conditions of the selective etching process are set to make the material of the first semiconductor substrate have a higher etching selectivity ratio with respect to the material of the barrier layer.

[0016] Furthermore, the material of the barrier layer is tantalum nitride (TaN) and / or tantalum carbonitride (TaCN).

[0017] Further, the material of the conductive structure is copper;

[0018] The material of the first semiconductor substrate is silicon, and the through-hole structure is a through-silicon via.

[0019] Further, the thickness of the back side of the first semiconductor substrate thinned by the first planarization process is controlled so that the through-hole structure is not exposed.

[0020] Furthermore, the first planarization process includes grinding and thinning and chemical mechanical polishing.

[0021] Furthermore, the method of selectively etching the first semiconductor substrate includes one or more deep reactive ion etchings.

[0022] Furthermore, the method for depositing the isolation layer is to alternately deposit an oxide layer and a nitride layer.

[0023] Furthermore, the second planarization process is chemical mechanical polishing.

[0024] Further, the etching depth of the selective etching is configured such that the height of the first semiconductor substrate after etching is smaller than the height of the conductive layer.

[0025] The disclosed embodiment improves the method of exposing the conductive layer in the through silicon via from the back side of the semiconductor substrate in the process of through silicon via, reduces the size of the semiconductor substrate removed by the grinding and thinning process in the existing process, and increases the size of the semiconductor substrate removed by the selective etching process. As a result, there is no need to grind the semiconductor substrate and the conductive layer at the same time, which prevents the conductive ions in the conductive layer from diffusing into the semiconductor substrate, thereby improving the yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0027] Figure 1 It is a through silicon via formed by existing process;

[0028] Figure 2 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure;

[0029] Figure 3-Figure 9 Schematic cross-sectional view of a structure formed in each step of the method for forming a semiconductor substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0031] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0032] Unless the context clearly requires otherwise, the words "include", "comprises" and the like throughout the specification and claims should be interpreted as inclusive rather than exclusive or exhaustive; that is, as "including but not limited to". In the description of the present invention, unless otherwise specified, "multi-layer" means two or more layers.

[0033] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be an intervening element or layer. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there is no intervening element or layer. For ease of description, spatial relationship terms such as "under, below, below, above, above, and above may be used to describe the relationship between an element or feature and another (or more) element or feature as shown in the accompanying drawings. It should be understood that the spatial relationship terms are intended to summarize the different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, the element described as being "under" or "below" other elements or features will be "above" the other elements or features. Therefore, the exemplary term "under" can cover both the above and below orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0034] Figure 2 is a flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure, with reference to Figure 2 , the forming method of the embodiment of the present disclosure comprises the following steps:

[0035] Step S100, providing a first semiconductor substrate. A through-hole structure is formed on the front surface of the first semiconductor substrate, and the through-hole structure includes a dielectric layer formed on the bottom and sidewall of the through-hole and a conductive layer filled on the dielectric layer.

[0036] Step S200: Connecting the front side of the first semiconductor substrate to the second semiconductor substrate.

[0037] Step S300: thinning the back side of the first semiconductor substrate using a first planarization process.

[0038] Step S400, performing selective etching on the back side of the first semiconductor substrate to remove part of the substrate material of the first semiconductor substrate to expose the bottom of the through-hole structure, wherein the material of the first semiconductor substrate has a higher etching selectivity than the dielectric layer material;

[0039] Step S500: depositing an isolation layer on the back side of the etched first semiconductor substrate.

[0040] Step S600: using a second planarization process to thin the oxide isolation layer and remove the dielectric layer at the bottom of the through-hole structure to expose the conductive layer in the through-hole structure.

[0041] Figure 3-Figure 9 Schematic cross-sectional view of a structure formed in each step of the method for forming a semiconductor substrate according to an embodiment of the present disclosure. Figure 3 is a schematic cross-sectional view of the first semiconductor substrate 100. Figure 3 In step S100, a first semiconductor substrate 100 is provided. The first semiconductor substrate 100 includes a front side 101 and a back side 102, wherein a through hole structure 300 is formed on the front side 101 of the first semiconductor substrate 100, and the through hole structure 300 includes a dielectric layer 310 formed on the bottom and sidewall of the through hole and a conductive layer 320 filled on the dielectric layer 310. In this embodiment, the depth of the through hole is 110 μm.

[0042] The first semiconductor substrate 100 provided in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate or a silicon germanium single crystal substrate. Alternatively, the first semiconductor substrate 100 may also be a silicon on insulator (SOI) substrate, a stacked silicon on insulator (SSOI), a stacked silicon germanium on insulator (S-SiGeOI), a silicon germanium on insulator (SiGeOI), a germanium on insulator (GeOI), a substrate of an epitaxial layer structure on silicon or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium. Preferably, the first semiconductor substrate 100 is a silicon single crystal substrate. Several epitaxial interface layers or strained layers and other structures may also be formed on the surface of the first semiconductor substrate 100 to improve the electrical performance of the semiconductor device. An isolation region is formed in the first semiconductor substrate 100. As an example, the isolation region is a shallow trench isolation (STI) region or a local oxide silicon (LOCOS) isolation region. The isolation region can divide the first semiconductor substrate 100 into several active regions, etc. For simplicity, the isolation region is not shown in the figure.

[0043] The dielectric layer 310 in the through-hole structure 300 includes an oxide layer 311 and a barrier layer 312 stacked in sequence. The oxide layer 311 is located at the bottom of the through-hole structure, and the barrier layer 312 is formed on the oxide layer 311. The oxide layer 311 can protect the conductive layer 320 from being etched in the subsequent etching process of etching the first semiconductor substrate 100. The material of the oxide layer 311 can be an insulating material such as silicon oxide (SiO2). The barrier layer 312 plays a role in blocking the ions in the conductive layer 320 from diffusing into the first semiconductor substrate 100. The material of the barrier layer 312 can include any one of tantalum nitride (TaN) or tantalum carbonitride (TaCN) or a combination thereof. It should be understood that it can also be other materials such as silicon oxynitride (SiON), tantalum (Ta), silicon nitride (SiN) that play a role in blocking the diffusion of conductive ions in the conductive layer 320. The conductive layer 320 makes the first semiconductor substrate 100 and the second semiconductor substrate 200 form an electrical connection with each other in the subsequent process. The conductive layer 320 may be made of a metal material, such as any one of copper (Cu), iron (Fe), aluminum (Al), tungsten (W) and sodium (Na) or a combination thereof, or may be a conductive polymer or metal silicide.

[0044] The through hole structure 300 can be formed by a through silicon via process. Specifically, in an optional implementation, the method for forming the through hole structure 300 in the first semiconductor substrate 100 includes: first, forming a through hole on the front side 101 of the first semiconductor substrate 100, and the through hole can be formed by dry etching, preferably reactive ion etching. As an example, the depth of the through hole is 110 μm, and there is a certain distance between the bottom of the through hole and the back side 102 of the semiconductor substrate 100. Then, a dielectric layer 310 is formed on the sidewall and bottom of the through hole, wherein the dielectric layer 310 includes a barrier layer 312 made of tantalum nitride (TaN) and an oxide layer 311 made of silicon oxide (SiO2). Finally, a conductive layer 320 made of copper (Cu) is filled on the surface of the dielectric layer 310, and the front side 101 of the first semiconductor substrate 100 is chemically mechanically polished to make the front side 101 of the first semiconductor substrate 100 flat.

[0045] It should be understood that, as an example, the drawings of the present disclosure only show one through-hole structure 300 in the first semiconductor substrate 100 . In practice, a plurality of through-hole structures 300 may be formed in the first semiconductor substrate 100 .

[0046] refer to Figure 4In step S200, the front side 101 of the first semiconductor substrate 100 is connected to the second semiconductor substrate 200. Specifically, the method for connecting the front side 101 of the first semiconductor substrate 100 to the second semiconductor substrate 200 includes: providing a second semiconductor substrate 200, in which active devices, micro-electromechanical systems (MEMS) devices, inertial sensors, interconnect structures and other devices may be formed, or CMOS image sensors and the like may also be formed. In this embodiment, the second semiconductor substrate 200 is a MEMS device. A first bonding layer and a second bonding layer (not shown in the figure) are formed on the front side 101 of the first semiconductor substrate 100 and the front side of the second semiconductor substrate, respectively, and then the first bonding layer and the second bonding layer are bonded into one by thermal compression bonding (TCB) or van der Waals eutectic bonding.

[0047] refer to Figure 5 In step S300, a first planarization process is used to thin the back side 102 of the first semiconductor substrate 100. In an optional implementation, a grinding process is first used to thin the back side 102 of the first semiconductor substrate 100 so that the thickness of the first semiconductor substrate 100 is 115 μm, and then a chemical mechanical polishing (CMP) is used to thin the back side 102 of the first semiconductor substrate 100 so that the thickness of the first semiconductor substrate 100 is 113 μm.

[0048] Unlike the prior art process in which the conductive layer is exposed during the grinding and thinning process, the embodiment of the present disclosure reduces the size of the back side 102 of the semiconductor substrate removed by grinding and thinning, thereby ensuring that the conductive layer 320 is wrapped by the dielectric layer 310 and that conductive ions do not diffuse into the first semiconductor substrate 100 during the first planarization process.

[0049] refer to Figure 6 and Figure 7 In step S400, selective etching is performed on the back side 102 of the first semiconductor substrate 100. Part of the substrate material of the first semiconductor substrate 100 is removed to expose the bottom of the through-hole structure 300, and the height of the first semiconductor substrate 100 is less than the height of the conductive layer 320. In the selective etching process, the material of the first semiconductor substrate 100 has a higher etching selectivity than the dielectric layer material.

[0050] Preferably, in this step, a deep reactive ion etching (DRIE) method is used to remove part of the substrate material of the first semiconductor substrate 100, while leaving the dielectric layer 310 in the through-hole structure 300 substantially unetched or only a small part etched, so that the barrier layer 312 wrapped by the oxide layer 311 will not be exposed. Reactive ion etching is a device that uses active groups generated by high-frequency glow discharge to chemically react with the corroded material to form volatile products to cause atoms on the sample surface to fall off from the lattice, thereby realizing the preparation of fine patterns on the sample surface. The use of deep reactive ion etching can maintain a very high etching selectivity. In an optional implementation, the back side 102 of the first semiconductor substrate 100 is etched to a thickness of 10 μm. Due to the high selectivity of deep reactive ion etching, the first semiconductor substrate 100 made of silicon is etched, but the oxide layer 311 at the bottom of the through-hole structure 300 is not affected by the etching and the through-hole structure 300 is retained, so that the height of the conductive layer 320 is greater than the thickness of the first semiconductor substrate 100 after etching, thereby ensuring that the chemical mechanical polishing can first expose the conductive layer 320 after the subsequent deposition of the isolation layer 400, while the back side 102 of the first semiconductor substrate 100 is still covered by the isolation layer 400. Due to the inconsistency and variability of the etching rate, it is easy to cause the surface of the first semiconductor substrate 100 after etching to be uneven, and the greater the etching depth, the worse the uniformity. Preferably, etching can be performed in multiple times to improve the uniformity of the surface of the first semiconductor substrate 100. Considering the etching efficiency, two deep reactive ion etchings can be used to remove part of the substrate material of the first semiconductor substrate 100, and the depth of each etching is 5 μm.

[0051] In an optional implementation, two deep reactive ion etchings are performed to remove part of the substrate material of the first semiconductor substrate 100, and the depth of each etching is 5 μm. The process conditions of the deep reactive ion etching are: silicon hexafluoride (SF6) gas is selected as the process gas, and a radio frequency power supply is applied to make the silicon hexafluoride reaction gas form a high ionization. In the etching step, the working pressure is controlled to be 20mTorr~8Torr, the power is 2000W, the frequency is 13.5MHz, and the DC bias can be continuously controlled within -500V~1000V to ensure the needs of anisotropic etching. The deep reactive ion etching system can select commonly used equipment and is not limited to a certain model.

[0052] Compared with the prior art, the through-hole structure 300 is still in the first semiconductor substrate 100 after the grinding and thinning process, which prevents the conductive ions in the conductive layer 320 from diffusing into the first semiconductor substrate 100 during the process. In the process of selectively etching the first semiconductor substrate 100, the embodiment of the present disclosure selectively etches and removes the thickness of the first semiconductor substrate 100, and uses deep reactive ion etching with a high etching selectivity ratio to ensure that the through-hole structure 300 is not etched, and the conductive layer 320 is wrapped by the dielectric layer 310, so that the conductive ions in the conductive layer 320 will not diffuse into the first semiconductor substrate 100. At the same time, the first semiconductor substrate 100 is etched by multiple deep reactive ion etching methods to ensure the uniformity of etching.

[0053] refer to Figure 8 In step S500, an isolation layer 400 is deposited on the back side 102 of the etched first semiconductor substrate 100. The isolation layer 400 covers the back side 102 of the first semiconductor substrate 100 and the upper surface and sidewall of the portion of the through-hole structure 300 that is higher than the first semiconductor substrate 100, and the lower surface of the isolation layer 400 is lower than the bottom of the conductive layer 320 in the through-hole structure 300. The material of the isolation layer can be one or more of silicon oxide (SiO2) or silicon nitride (SiN) and other materials. Preferably, the isolation layer 400 is an ONO isolation layer, i.e., a plurality of alternately stacked silicon oxide (SiO2) layers and silicon nitride (SiN) layers. The ONO isolation layer can be formed by alternately depositing oxide layers and nitride layers for multiple times. The deposition method of the deposited isolation layer 400 can be any existing technology known to those skilled in the art, preferably chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), etc.

[0054] refer to Fig. 9In step S600, the isolation layer 400 is thinned by a second planarization process and the dielectric layer 310 at the bottom of the through-hole structure 300 is removed to expose the conductive layer 320 in the through-hole structure. The second planarization process may be a process well known to those skilled in the art, preferably chemical mechanical polishing is used to planarize the surface of the isolation layer 400 and remove the dielectric layer 310 at the bottom of the through-hole structure 300. The formed isolation layer 400 covers the back side 102 of the first semiconductor substrate 100 and exposes the conductive layer 320 of the through-hole structure 300 and the dielectric layer 310 outside the conductive layer 320.

[0055] Unlike the prior art in which the conductive layer 320 is exposed simultaneously during the process of chemically mechanically polishing the first semiconductor substrate 100, in the embodiment of the present disclosure, after forming the isolation layer 400, the conductive layer 320 is exposed simultaneously during the chemically mechanical polishing of the isolation layer 400. Since the isolation layer 400 can prevent the conductive ions in the conductive layer 320 from diffusing compared with the first semiconductor substrate 100, the situation in the prior art in which the conductive ions in the conductive layer 320 diffuse into the first semiconductor substrate 100 during the chemically mechanical polishing of the first semiconductor substrate 100, thereby improving the yield of the product.

[0056] In subsequent processes, a dielectric material layer will be deposited on the isolation layer 400 , the dielectric material layer will be patterned, and a conductive material will be deposited in the patterned dielectric material layer to form an interconnect structure, so that the first semiconductor substrate 100 and the second semiconductor substrate 200 are circuit-connected.

[0057] The disclosed embodiment improves the method of exposing the conductive layer in the through silicon via from the back side of the semiconductor substrate in the process of forming a through silicon via, reduces the size of the semiconductor substrate removed by the grinding and thinning process in the existing process, and increases the size of the semiconductor substrate removed by the selective etching process. As a result, there is no need to grind the semiconductor substrate and the conductive layer at the same time, which prevents the conductive ions in the conductive layer from diffusing into the semiconductor substrate, thereby improving the yield of the product.

[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a first semiconductor substrate, a through-hole structure is formed on the front surface of the first semiconductor substrate, the through-hole structure comprises a dielectric layer formed at the bottom and sidewall of the through-hole and a conductive layer filled on the dielectric layer, the dielectric layer comprises an oxide layer located at the bottom of the through-hole structure and a barrier layer covering the oxide layer, and the conductive layer comprises a conductive polymer; connecting the front side of the first semiconductor substrate to the second semiconductor substrate; thinning the back side of the first semiconductor substrate using a first planarization process; Performing selective etching on the back side of the first semiconductor substrate to remove part of the substrate material of the first semiconductor substrate to expose the bottom of the through-hole structure, wherein the material of the first semiconductor substrate has a higher etching selectivity than the dielectric layer material, and in the selective etching process, while removing the substrate material, the barrier layer is kept from being exposed, and the oxide layer is used to protect the barrier layer from being etched in the selective etching process; Depositing an isolation layer on the back side of the etched first semiconductor substrate, wherein the isolation layer is a plurality of alternately stacked silicon oxide layers and silicon nitride layers; A second planarization process is used to thin the isolation layer and remove the dielectric layer at the bottom of the through-hole structure to expose the conductive layer in the through-hole structure, wherein the isolation layer has a stronger ability to prevent the diffusion of conductive ions in the conductive layer than the first semiconductor substrate; Wherein, the method for selectively etching the first semiconductor substrate includes multiple etchings, and the second planarization process is chemical mechanical polishing.

2. The method according to claim 1, characterized in that The process conditions of the selective etching process are set so that the material of the first semiconductor substrate has a higher etching selectivity with respect to the material of the barrier layer.

3. The method according to claim 1, characterized in that The material of the barrier layer is tantalum nitride (TaN) and / or tantalum carbonitride (TaCN).

4. The method according to claim 1, characterized in that: The material of the first semiconductor substrate is silicon; and the through-hole structure is a through-silicon via.

5. The method according to claim 1, characterized in that The thickness of the back side of the first semiconductor substrate thinned by the first planarization process is controlled so that the through-hole structure is not exposed.

6. The method according to claim 1, characterized in that The first planarization process includes grinding and thinning and chemical mechanical polishing.

7. The method according to claim 1, characterized in that The method of selectively etching the first semiconductor substrate includes one or more deep reactive ion etchings.

8. The method according to claim 1, characterized in that The method for depositing the isolation layer is to alternately deposit silicon oxide layers and silicon nitride layers.

9. The method according to claim 1, characterized in that: The etching depth of the selective etching is configured such that the height of the first semiconductor substrate after etching is smaller than the height of the conductive layer.

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