A signal-in-place detection circuit

Abstract

The present invention discloses a in-place signal detection circuit, including a metal tube and a limit block. It is characterized in that: the detection circuit further includes a PIN terminal, whose first pin is electrically connected to the metal tube and the third capacitor C3 respectively, and the first pin is grounded. Wherein the third capacitor C3 is electrically connected to the third pin of the PIN terminal through the twelfth resistor R12, and the twelfth resistor R12 is also electrically connected to the seventh resistor R7, and the VCC power supply is electrically connected to the third pin of the PIN terminal through the seventh resistor R7; After filtering the signal for jitter and poor contact conditions, the present invention eliminates the jitter influence by comparing the levels, and can select whether to extend the output time of the trigger signal through a function switch, thereby greatly improving the accuracy and stability of the in-place signal detection.

Description

Technical Field

[0001] The present invention relates to a detection circuit for in-place signals. Background Art

[0002] In the industry of pipe cutting machines, the fixed-length in-place signal of steel pipes does not use sensors. Most of the electrical processes are to apply 0V power to the entire equipment. With the steel pipe as a conductor, it hits a metal limit block. The limit block is connected to the input terminal of a sinking-type PLC to provide an input signal, so as to judge whether the steel pipe is in place.

[0003] In the pipe cutting machine industry, the signal detection scheme for feeding the pipe material to the cutting position needs to be accurate and stable, and it cannot affect the pipe cutting accuracy. The consistency and repeatability of the sensor need to have good performance parameter indicators.

[0004] Since the contact reliability of the pipe material is not always good at the moment when it reaches the fixed limit block, due to inertia, there will be multiple rebounds, and finally the pipe material and the block do not contact, resulting in the PLC not receiving the signal. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a detection circuit for in-place signals.

[0006] To solve the above technical problem, the present invention provides the following technical solutions:

[0007] An in-place signal detection circuit of the present invention includes a metal tube and a limit block, and is characterized in that: the detection circuit further includes a PIN terminal, and its first pin is electrically connected to the metal tube and the third capacitor C3 respectively, and the first pin is grounded. Among them, the third capacitor C3 is electrically connected to the third pin of the PIN terminal through the twelfth resistor R12, and the twelfth resistor R12 is also electrically connected to the seventh resistor R7, and the VCC power supply is electrically connected to the third pin of the PIN terminal through the seventh resistor R7; the third pin of the PIN terminal is also electrically connected to the limit block, one end of the ninth resistor R9, and one end of the second voltage regulator diode D2 respectively. Among them, the other end of the second voltage regulator diode D2 is electrically connected to the third pin of the timer chip and one end of the voltage stabilizing diode respectively, and the other end of the voltage stabilizing diode is grounded. Among them, the other end of the ninth resistor R9 is electrically connected to one end of the second capacitor C2 and the non-inverting input terminal of the operational amplifier respectively. Among them, the other end of the second capacitor C2 is grounded. Among them, the inverting input terminal of the operational amplifier is electrically connected to one end of the second resistor R2 and one end of the sixth resistor R6 respectively. Among them, the other end of the second resistor R2 is connected to the VCC power supply, and the other end of the sixth resistor R6 is grounded. The eighth terminal of the operational amplifier is connected to the VCC power supply, the fourth terminal of the operational amplifier is grounded, and the output terminal of the operational amplifier is electrically connected to the second pin of the timer chip and one end of the fifth resistor R5 respectively. Among them, the other end of the fifth resistor R5 is connected to the VCC power supply.

[0008] Preferably, the detection circuit further includes an opto-solid state relay chip, whose first pin is electrically connected to the second pin of the toggle switch chip through the eleventh resistor R11, whose second pin is electrically connected to the fifth pin of the toggle switch chip through a light-emitting diode, whose third pin is electrically connected to the fourth pin of the cable socket chip, and whose fourth pin is electrically connected to the third pin of the cable socket chip; the first pin of the toggle switch chip is connected to the VCC power supply, the third pin of the toggle switch chip is electrically connected to the third pin of the timer chip, the fourth pin of the toggle switch chip is grounded, and the sixth pin of the toggle switch chip is electrically connected to the second pin of the timer chip.

[0009] Preferably, the first pin of the timer chip is electrically connected to one end of the fourth capacitor C4 and one end of the fifth capacitor C5 respectively, and is grounded. Among them, the other end of the fourth capacitor C4 is electrically connected to one end of the eighteenth resistor R18, the sixth pin and the seventh pin of the timer chip respectively. Among them, the other end of the fifth capacitor C5 is electrically connected to the fifth pin of the timer chip; the other end of the eighteenth resistor R18 is electrically connected to the fourth pin and the eighth pin of the timer chip respectively, and is connected to the VCC power supply.

[0010] Preferably, the first pins of the flexible cable socket chip are respectively electrically connected to the positive pole of the 24V power supply and one end of the first fuse FU1. The other end of the first fuse FU1 is electrically connected to one end of the first diode D1. The other end of the first diode D1 is respectively electrically connected to one end of the third voltage stabilizing diode D3, one end of the first varistor RV1, and one end of the first inductor L1. The other end of the first inductor L1 is respectively electrically connected to one end of the first polarized capacitor CE1 and the first pin of the first linear power supply chip U1. The second pin of the first linear power supply chip U1, the other end of the first polarized capacitor CE1, the other end of the third voltage stabilizing diode D3, and the other end of the first varistor RV1 are all electrically connected to the second pin of the flexible cable socket chip. The second pin of the flexible cable socket chip is also connected to the negative pole of the 24V power supply.

[0011] Preferably, the third pin of the first linear power supply chip U1 is respectively electrically connected to one end of the second polarized capacitor CE2 and the first end of the common mode inductor. The other end of the second polarized capacitor CE2 is respectively electrically connected to the second pin of the flexible cable socket chip and the second end of the common mode inductor.

[0012] Preferably, the third end of the common mode inductor is respectively electrically connected to one end of the sixth polarized capacitor CE6, the second pin of the second linear power supply chip U2, one end of the third polarized capacitor CE3, and the second pin of the isolated power supply chip. The fourth end of the common mode inductor is respectively electrically connected to the other end of the sixth polarized capacitor CE6 and the first pin of the second linear power supply chip U2. The third pin of the second linear power supply chip U2 is respectively electrically connected to the other end of the third polarized capacitor CE3 and the first pin of the isolated power supply chip.

[0013] Preferably, the third pin of the isolated power supply chip is respectively electrically connected to one end of the fourth polarized capacitor CE4, one end of the fifth polarized capacitor CE5, and one end of the first capacitor C1, and is grounded; the fourth pin of the isolated power supply chip is respectively electrically connected to the other end of the fourth polarized capacitor CE4, the other end of the fifth polarized capacitor CE5, and the other end of the first capacitor C1 through the second inductor L2, and is connected to the VCC power supply.

[0014] The beneficial effects achieved by the present invention are:

[0015] After the present invention filters the signal for the situations of jitter and poor contact, eliminates the jitter influence by comparing the levels, and can select whether to extend the output time of the trigger signal through the function switch, thereby greatly improving the accuracy and stability of the in-place signal detection. Description of the Drawings

[0016] The accompanying drawings are used to provide a further understanding of the present invention and form a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the accompanying drawings:

[0017] Figure 1 It is a partial circuit diagram of the present invention;

[0018] Figure 2 It is a partial circuit diagram of the present invention;

[0019] Figure 3 It is a partial circuit diagram of the present invention;

[0020] Figure 4 It is a partial circuit diagram of the present invention;

[0021] Figure 5 It is a diagram of the actual measurement data of the present invention;

[0022] Figure 6 It is a diagram of the actual measurement data of the present invention; Detailed implementation manners

[0023] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to explain and illustrate the present invention and are not used to limit the present invention.

[0024] Embodiment

[0025] In this embodiment Figures 1 to 4 constitute the complete circuit diagram of the present invention, as shown in Figures 1 to 4As shown, a in-place signal detection circuit includes a metal tube and a limit block. The detection circuit further includes a PIN terminal, whose first pin is electrically connected to the metal tube and the third capacitor C3 respectively, and the first pin is grounded. The third capacitor C3 is electrically connected to the third pin of the PIN terminal through the twelfth resistor R12, and the twelfth resistor R12 is also electrically connected to the seventh resistor R7. And the VCC power supply is electrically connected to the third pin of the PIN terminal through the seventh resistor R7; the third pin of the PIN terminal is also electrically connected to the limit block, one end of the ninth resistor R9, and one end of the second zener diode D2 respectively. One end of the second zener diode D2 is electrically connected to the third pin of the timer chip and one end of the voltage stabilizing diode respectively, and the other end of the voltage stabilizing diode is grounded. One end of the ninth resistor R9 is electrically connected to one end of the second polar capacitor C2 and the non-inverting input terminal of the operational amplifier respectively. The other end of the second polar capacitor C2 is grounded. The inverting input terminal of the operational amplifier is electrically connected to one end of the second resistor R2 and one end of the sixth resistor R6 respectively. The other end of the second resistor R2 is connected to the VCC power supply. The other end of the sixth resistor R6 is grounded. The eighth terminal of the operational amplifier is connected to the VCC power supply. The fourth terminal of the operational amplifier is grounded. The output terminal of the operational amplifier is electrically connected to the second pin of the timer chip and one end of the fifth resistor R5 respectively. The other end of the fifth resistor R5 is connected to the VCC power supply; the detection circuit further includes an opto-solid state relay chip, whose first pin is electrically connected to the second pin of the toggle switch chip through the eleventh resistor R11, its second pin is electrically connected to the fifth pin of the toggle switch chip through a light-emitting diode, its third pin is electrically connected to the fourth pin of the cable socket chip, and its fourth pin is electrically connected to the third pin of the cable socket chip; the first pin of the toggle switch chip is connected to the VCC power supply, the third pin of the toggle switch chip is electrically connected to the third pin of the timer chip, the fourth pin of the toggle switch chip is grounded, and the sixth pin of the toggle switch chip is electrically connected to the second pin of the timer chip; the first pin of the timer chip is electrically connected to one end of the fourth capacitor C4 and one end of the fifth capacitor C5 respectively, and is grounded. The other end of the fourth capacitor C4 is electrically connected to one end of the eighteenth resistor R18, the sixth pin and the seventh pin of the timer chip respectively. The other end of the fifth capacitor C5 is electrically connected to the fifth pin of the timer chip; the other end of the eighteenth resistor R18 is electrically connected to the fourth pin and the eighth pin of the timer chip respectively, and is connected to the VCC power supply;The first pin of the flexible cable socket chip is electrically connected to the positive electrode of the 24V power supply and one end of the first fuse FU1. The other end of the first fuse FU1 is electrically connected to one end of the first diode D1. The other end of the first diode D1 is electrically connected to one end of the third voltage regulator diode D3, one end of the first varistor RV1, and one end of the first inductor L1. The other end of the first inductor L1 is electrically connected to one end of the first polarized capacitor CE1 and the first pin of the first linear power supply chip U1. The second pin of the first linear power supply chip U1, the other end of the first polarized capacitor CE1, the other end of the third voltage regulator diode D3, and the other end of the first varistor RV1 are all electrically connected to the second pin of the flexible cable socket chip. The second pin of the flexible cable socket chip is also connected to the negative electrode of the 24V power supply. The third pin of the first linear power supply chip U1 is electrically connected to one end of the second polarized capacitor CE2 and the first end of the common mode inductor. The other end of the second polarized capacitor CE2 is electrically connected to the second pin of the flexible cable socket chip and the second end of the common mode inductor. The third end of the common mode inductor is electrically connected to one end of the sixth polarized capacitor CE6, the second pin of the second linear power supply chip U2, one end of the third polarized capacitor CE3, and the second pin of the isolated power supply chip. The fourth end of the common mode inductor is electrically connected to the other end of the sixth polarized capacitor CE6 and the first pin of the second linear power supply chip U2. The third pin of the second linear power supply chip U2 is electrically connected to the other end of the third polarized capacitor CE3 and the first pin of the isolated power supply chip. The third pin of the isolated power supply chip is electrically connected to one end of the fourth polarized capacitor CE4, one end of the fifth polarized capacitor CE5, and one end of the first capacitor C1, and is grounded. The fourth pin of the isolated power supply chip is electrically connected to the other end of the fourth polarized capacitor CE4, the other end of the fifth polarized capacitor CE5, and the other end of the first capacitor C1 through the second inductor L2, and is connected to the VCC power supply.

[0026] In this embodiment, the detection circuit further includes a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, and a seventeenth resistor R17. The thirteenth resistor R13, the fourteenth resistor R14, and the fifteenth resistor R15 are all grounded. The sixteenth resistor R16 and the seventeenth resistor R17 are both connected to the VCC power supply. The above resistors are used for the flying wires in the present invention, and also to reduce the number of traces on the front side, making the present invention more beautiful. At the same time, it also prevents the LOGO of Morikawa from being full of traces and vias.

[0027] Such as Figure 5As shown, when the original signal has a situation of poor contact after impact (CH1 waveform), a reliable and stable long-term output is obtained after being processed by the in-place signal processing module, effectively avoiding the problem of slave computer response. (0 - 1S can be set).

[0028] As Figure 6 shown, when there are poor contacts such as jitter and intermittency during the process of the original signal hitting the limit block (CH1), the output remains stable after processing.

[0029] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements on some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A signal-in-place detection circuit, comprising a metal tube and a limit block, characterized in that: The detection circuit further includes a PIN terminal, the first pin of which is electrically connected to the metal tube and the third capacitor C3 respectively, and the first pin is grounded. The third capacitor C3 is electrically connected to the third pin of the PIN terminal through the twelfth resistor R12, and the twelfth resistor R12 is also electrically connected to the seventh resistor R7. And the VCC power supply is electrically connected to the third pin of the PIN terminal through the seventh resistor R7; the third pin of the PIN terminal is also electrically connected to the limit block, one end of the ninth resistor R9, and one end of the second zener diode D2 respectively. The other end of the second zener diode D2 is electrically connected to the third pin of the timer chip and one end of the voltage stabilizing diode respectively, and the other end of the voltage stabilizing diode is grounded. The other end of the ninth resistor R9 is electrically connected to one end of the second capacitor C2 and the non-inverting input terminal of the operational amplifier respectively. The other end of the second capacitor C2 is grounded. The inverting input terminal of the operational amplifier is electrically connected to one end of the second resistor R2 and one end of the sixth resistor R6 respectively. The other end of the second resistor R2 is connected to the VCC power supply. The other end of the sixth resistor R6 is grounded. The eighth terminal of the operational amplifier is connected to the VCC power supply. The fourth terminal of the operational amplifier is grounded. The output terminal of the operational amplifier is electrically connected to the second pin of the timer chip and one end of the fifth resistor R5 respectively. The other end of the fifth resistor R5 is connected to the VCC power supply; The detection circuit further includes a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, and a seventeenth resistor R17. The thirteenth resistor R13, the fourteenth resistor R14, and the fifteenth resistor R15 are all grounded. The sixteenth resistor R16 and the seventeenth resistor R17 are both connected to the VCC power supply.

2. The in-place signal detection circuit according to claim 1, wherein: The detection circuit further includes an optical solid-state relay chip, the first pin of which is electrically connected to the second pin of the toggle switch chip through the eleventh resistor R11, the second pin of which is electrically connected to the fifth pin of the toggle switch chip through a light-emitting diode, the third pin of which is electrically connected to the fourth pin of the cable socket chip, and the fourth pin of which is electrically connected to the third pin of the cable socket chip; the first pin of the toggle switch chip is connected to the VCC power supply, the third pin of the toggle switch chip is electrically connected to the third pin of the timer chip, the fourth pin of the toggle switch chip is grounded, and the sixth pin of the toggle switch chip is electrically connected to the second pin of the timer chip.

3. The in-place signal detection circuit according to claim 2, wherein: The first pin of the timer chip is electrically connected to one end of the fourth capacitor C4 and one end of the fifth capacitor C5 respectively, and is grounded. The other end of the fourth capacitor C4 is electrically connected to one end of the eighteenth resistor R18, the sixth pin and the seventh pin of the timer chip respectively. The other end of the fifth capacitor C5 is electrically connected to the fifth pin of the timer chip. The other end of the eighteenth resistor R18 is electrically connected to the fourth pin and the eighth pin of the timer chip respectively, and is connected to the VCC power supply.

4. The in-place signal detection circuit according to claim 3, wherein: The first pin of the flexible cable socket chip is electrically connected to the positive pole of the 24V power supply and one end of the first fuse FU1 respectively. The other end of the first fuse FU1 is electrically connected to one end of the first diode D1. The other end of the first diode D1 is electrically connected to one end of the third voltage regulator diode D3, one end of the first varistor RV1 and one end of the first inductor L1 respectively. The other end of the first inductor L1 is electrically connected to one end of the first polarized capacitor CE1 and the first pin of the first linear power supply chip U1 respectively. The second pin of the first linear power supply chip U1, the other end of the first polarized capacitor CE1, the other end of the third voltage regulator diode D3 and the other end of the first varistor RV1 are all electrically connected to the second pin of the flexible cable socket chip. The second pin of the flexible cable socket chip is also connected to the negative pole of the 24V power supply.

5. The in-place signal detection circuit according to claim 4, wherein: The third pin of the first linear power supply chip U1 is electrically connected to one end of the second polarized capacitor CE2 and the first end of the common mode inductor respectively. The other end of the second polarized capacitor CE2 is electrically connected to the second pin of the flexible cable socket chip and the second end of the common mode inductor respectively.

6. The in-place signal detection circuit according to claim 5, characterized in that: The third end of the common mode inductor is electrically connected to one end of the sixth polarized capacitor CE6, the second pin of the second linear power supply chip U2, one end of the third polarized capacitor CE3 and the second pin of the isolated power supply chip respectively. The fourth end of the common mode inductor is electrically connected to the other end of the sixth polarized capacitor CE6 and the first pin of the second linear power supply chip U2 respectively. The third pin of the second linear power supply chip U2 is electrically connected to the other end of the third polarized capacitor CE3 and the first pin of the isolated power supply chip respectively.

7. The in-place signal detection circuit according to claim 6, wherein: The third pin of the isolated power supply chip is electrically connected to one end of the fourth polarized capacitor CE4, one end of the fifth polarized capacitor CE5 and one end of the first capacitor C1 respectively, and is grounded. The fourth pin of the isolated power supply chip is electrically connected to the other end of the fourth polarized capacitor CE4, the other end of the fifth polarized capacitor CE5 and the other end of the first capacitor C1 respectively through the second inductor L2, and is connected to the VCC power supply.

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