A video test signal synthesis device for air defense missile simulator

Abstract

The invention discloses a video test signal synthesis device for an air defense missile simulator, which is composed of a video signal generation module for generating a video signal and inputting the signal into a video input terminal of a display so as to detect whether the display is good or bad, and a power supply module for supplying power to the video signal generation module; the video signal generation module comprises two single-chip microcomputers, and an adder electrically connected to the video signal output terminals of the two single-chip microcomputers respectively, and a reverse amplifier electrically connected to the adder; the two single-chip microcomputers are composed of a first single-chip microcomputer for generating a synchronization signal and a square image signal, and a second single-chip microcomputer for receiving the synchronization signal output by the first single-chip microcomputer, keeping synchronization with the synchronization signal, and outputting a circle signal for highlighting display at the same time; the video test signal synthesis device for an air defense missile simulator of the invention has a simple structure, is easy to power, has good stability, is easy to carry, and is suitable for use under field conditions.

Description

Technical Field

[0001] The invention relates to a video signal generator, in particular to a video test signal synthesis device for an air defense missile simulator, and belongs to the technical field of video signal synthesis. Background Art

[0002] The portable air defense missile simulator system is a new type of air defense missile weapon simulation system independently developed by my country. Maintaining its good combat simulation performance is an important aspect to ensure that our army's air defense missile combat effectiveness is fully exerted. The display part of the portable air defense missile simulator system consists of a shooter monitor and three projections. A unified standard calibration signal is required for simulation training. At the same time, a standard video calibration signal is also required to inspect and splice the three projection videos. By inputting a standard video signal and observing the display of the monitor, the imaging performance, splicing effect, and simulation performance of the monitor can be judged.

[0003] The display part of the portable air defense missile simulator system is an indispensable visual tool for the shooter to shoot, and it is also an important channel for the shooter to exchange information with the training judges; maintaining the normal coordination of each display is an important guarantee for the performance of the portable air defense missile simulator system. However, at present, there are several problems in the detection, maintenance and adjustment of the display system: (1) The display test method is too simple, and only uses methods such as power off, indicator light, contrast adjustment, brightness adjustment, etc. to detect, which cannot correctly reflect the fault; (2) The display test equipment is relatively large and not convenient for use in field conditions; (3) Under field conditions, it is difficult to find a standard video signal to perform functional detection on the display; (4) The display cannot be coordinated and adjusted. Therefore, in order to solve the above problems, the present invention uses a single-chip microcomputer to design a standard video signal generator, thereby realizing the adjustment, detection and maintenance of the shooter display and three projection displays of the portable air defense missile simulator; compared with the previous old-fashioned adjustment, inspection and maintenance methods, this design overcomes the previous method of only using power off, watching indicator lights, adjusting contrast and brightness, and manually comparing video signals to detect and adjust the display, making the adjustment and detection faster and more accurate, the performance is better, and the work efficiency and simulation accuracy are greatly improved; at the same time, it has a small size, low power supply, and is easy to use, which is more suitable for simulation training requirements under field conditions. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes a video test signal synthesis device for an air defense missile simulator, which has a simple structure, is easy to power, has good stability, is easy to carry, and is suitable for use under field conditions.

[0005] The video test signal synthesis device of the air defense missile simulator of the present invention is composed of a video signal generating module for generating a video signal and inputting the signal to a video input terminal of a monitor so as to detect whether the monitor is good or bad, and a power supply module for supplying power to the video signal generating module, and the video signal generating module is electrically connected to the power supply module;

[0006] The video signal generating module comprises two single-chip microcomputers, and an adder electrically connected to the video signal output terminals of the two single-chip microcomputers, and a reverse amplifier electrically connected to the adder. The video signals output by the first single-chip microcomputer and the second single-chip microcomputer are synthesized by the adder, and then reversely amplified once to form a final full video signal; the output terminal of the reverse amplifier is electrically connected to the video input terminal of the monitor; the two single-chip microcomputers are composed of a first single-chip microcomputer for generating a synchronization signal and a square image signal, and a second single-chip microcomputer for receiving the synchronization signal output by the first single-chip microcomputer and keeping synchronization therewith, and outputting a highlighted circle signal at the same time. The video signal generating module is used to display a highlighted circle with a black and white square as the base on the monitor; wherein, the square The grid image signal is generated by the grid signal output terminal of the first single-chip microcomputer outputting a periodically changing level, and superimposing it on the synchronization signal to realize the display of the grid; the circle graphic signal is generated by the first single-chip microcomputer outputting a signal to set a time base for the second single-chip microcomputer. The second single-chip microcomputer outputs a high level in a specified time period through timing, and superimposes it on the grid signal, thereby superimposing a highlighted circle on the grid; a different high level is added to each row to form a circle, and the high level output of each row is slightly changed to form a rough circle, and by calculating when and how long a circular high level is generated for each row of signals, the edge of the circle is made as smooth as possible, thereby solving the problem of jagged edges at the edge of the circle.

[0007] Furthermore, the power supply module includes a DC / DC module for converting a +12V voltage into a -12V voltage, and a first step-down module and a second step-down module for changing the +12V and -12V voltages into +5V and -5V voltages, respectively; the first step-down module and the second step-down module are electrically connected to the DC / DC module, respectively, and the +12V voltage is converted into a -12V voltage by the DC / DC module, and the +12V and -12V voltages are changed into +5V and -5V voltages by using voltage regulator chips 7805 and 7905, respectively; the functions of each voltage are: the +12V and -12V voltages are used as power supplies for the LF347N amplifier; the +5V voltage is used as a power supply for the first microcontroller and the second microcontroller; the present application requires the generation of a full television signal with a positive polarity, and the voltage of the synchronization pulse is -0.3V, and the -5V voltage is designed to synthesize this negative voltage.

[0008] Furthermore, the first step-down module includes a 7805 voltage regulator chip and its peripheral circuits.

[0009] Furthermore, the second step-down module includes a 7905 voltage regulator chip and its peripheral circuits.

[0010] Furthermore, the first unit machine and the second single-chip microcomputer are both composed of an AT89C2051 single-chip microcomputer chip and its minimum system.

[0011] Furthermore, the fifteenth pin, the sixteenth pin and the nineteenth pin of the first single-chip microcomputer are electrically connected to the twelfth pin, the sixteenth pin and the nineteenth pin of the second single-chip microcomputer respectively.

[0012] Further, the adder is composed of a first series group, a second series group, a third series group and a fourth series group; the first series group is composed of a first resistor and a seventeenth resistor connected in series, and the other end of the first resistor is electrically connected to the eighteenth pin of the first single-chip microcomputer; the second series group is composed of a second resistor and a sixteenth resistor connected in series, and the other end of the second resistor is electrically connected to the fourteenth pin of the first single-chip microcomputer; the third series group is composed of a third resistor and a fifteenth resistor connected in series, and the other end of the third resistor is electrically connected to the fourteenth pin of the second single-chip microcomputer; the fourth series group is composed of a fourth resistor and a fourteenth resistor connected in series, and the other end of the fourth resistor is electrically connected to the output end of the second step-down module; the other ends of the fifteenth to seventeenth resistors are electrically connected to the other end of the fourteenth resistor and then electrically connected to the input end of the reverse amplifier.

[0013] Furthermore, the reverse amplifier is composed of a LF347N amplifier and its peripheral circuits.

[0014] Compared with the prior art, the video test signal synthesis device of the air defense missile simulator of the present invention synthesizes the video signals output by the first single-chip microcomputer and the second single-chip microcomputer through an adder, and then reversely amplifies them once to form a final full video signal, which is input to the video input end of the monitor for playback and calibration; the adjustment and detection are faster and more accurate, the performance is more excellent, and the work efficiency and simulation accuracy are greatly improved; at the same time, the device has a small size, low power supply, and is easy to use, and is more suitable for simulation training requirements under field conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic block diagram of the video signal generation principle of the present invention.

[0016] Figure 2 It is a schematic diagram of the overall circuit structure of the present invention.

[0017] Figure 3 It is a schematic diagram of the voltage amplitude of the synchronization signal of the present invention.

[0018] Figure 4It is a schematic diagram of video test signals of an air defense missile simulator of the present invention.

[0019] Figure 5 It is a schematic diagram of the circle generation principle of the present invention.

[0020] Figure 6 It is a flow chart of the generation of synchronization signals and square signals of the present invention.

[0021] Figure 7 It is a flow chart of the circle signal generation of the present invention.

[0022] The components in the accompanying drawings are marked as: 1-display, 2-video signal generating module, 21-single-chip microcomputer, 22-adder, 23-reverse amplifier, 3-power supply module, U1-first single-chip microcomputer, U2-second single-chip microcomputer, U3-LF347N amplifier, U4-7805 voltage regulator chip, U5-7905 voltage regulator chip, P1.0-the twelfth pin of the second single-chip microcomputer, P1.2-the fourteenth pin of the first single-chip microcomputer / the second single-chip microcomputer, P1.3-the fifteenth pin of the first single-chip microcomputer, P1.4-the sixteenth pin of the first single-chip microcomputer / the second single-chip microcomputer, P1.6-the eighteenth pin of the first single-chip microcomputer, P1.7-the nineteenth pin of the first single-chip microcomputer / the second single-chip microcomputer. DETAILED DESCRIPTION

[0023] like Figure 1 and Figure 2 The video test signal synthesis device for an air defense missile simulator shown in the figure is composed of a video signal generating module 2 for generating a video signal and inputting the signal to a video input terminal of a monitor 1, thereby detecting whether the monitor 1 is good or bad, and a power supply module 3 for supplying power to the video signal generating module 2, and the video signal generating module 2 is electrically connected to the power supply module 3;

[0024] The video signal generating module 2 comprises two single-chip microcomputers 21, an adder 22 electrically connected to the video signal output ends of the two single-chip microcomputers 21 respectively, and a reverse amplifier 23 electrically connected to the adder 22; the output end of the reverse amplifier 23 is electrically connected to the video input end of the display 1; the two single-chip microcomputers 21 are composed of a first single-chip microcomputer U1 for generating a synchronization signal and a grid image signal, and a second single-chip microcomputer U2 for receiving the synchronization signal output by the first single-chip microcomputer U1, keeping synchronization therewith, and outputting a highlighted circle signal.

[0025] The power module 3 includes a DC / DC module for converting a +12V voltage into a -12V voltage, and a first step-down module and a second step-down module for changing the +12V and -12V voltages into +5V and -5V voltages respectively; the first step-down module and the second step-down module are electrically connected to the DC / DC module respectively.

[0026] The first step-down module includes a 7805 voltage regulator chip U4 and its peripheral circuits.

[0027] The second step-down module includes a 7905 voltage regulator chip U5 and its peripheral circuits.

[0028] The first unit machine U1 and the second single-chip machine U2 are both composed of an AT89C2051 single-chip machine chip and its minimum system.

[0029] The fifteenth pin P1.3, the sixteenth pin P1.4 and the nineteenth pin P1.7 of the first single-chip microcomputer U1 are electrically connected to the twelfth pin P1.0, the sixteenth pin P1.4 and the nineteenth pin P1.7 of the second single-chip microcomputer U2 respectively.

[0030] The adder 22 is composed of a first series group, a second series group, a third series group and a fourth series group; the first series group is formed by a first resistor R1 and a seventeenth resistor R17 connected in series, and the other end of the first resistor R1 is electrically connected to the eighteenth pin P1.6 of the first single-chip microcomputer U1; the second series group is formed by a second resistor R2 and a sixteenth resistor R16 connected in series, and the other end of the second resistor R2 is electrically connected to the fourteenth pin P1.2 of the first single-chip microcomputer U1; the third series group is formed by a third resistor R3 and a fifteenth resistor R15 connected in series, and the other end of the third resistor R3 is electrically connected to the fourteenth pin P1.2 of the second single-chip microcomputer U2; the fourth series group is formed by a fourth resistor R4 and a fourteenth resistor R14 connected in series, and the other end of the fourth resistor R4 is electrically connected to the output end of the second step-down module; the other ends of the fifteenth to seventeenth resistors R15 to R17 are electrically connected to the other end of the fourteenth resistor R14 and then electrically connected to the input end of the reverse amplifier 23.

[0031] The reverse amplifier 23 is composed of a LF347N amplifier U3 and its peripheral circuits.

[0032] The video test signal synthesis device for an air defense missile simulator of the present invention synthesizes the video signals output by the first single-chip microcomputer and the second single-chip microcomputer through an adder, and then performs reverse amplification once to form a final full video signal; Figure 4As shown, the video signal generating module is used to display a bright circle with black and white squares as the background on the monitor; specifically, the square image signal is generated by the square signal output terminal of the first single-chip microcomputer outputting a periodically high and low changing level, and superimposing it on the synchronization signal to realize the display of the square; the circle graphic signal is generated by the first single-chip microcomputer outputting a signal to set a time base for the second single-chip microcomputer, and the second single-chip microcomputer outputs a high level in a specified time period through timing, and superimposes it on the square signal, thereby superimposing a bright circle on the square; wherein the fourteenth pin (P1.2) of the first single-chip microcomputer is used to output The black and white checkered signal belongs to the image signal. As described above, it only exists in the positive period of the line, and does not exist in the line blanking period and the field blanking period. The fifteenth pin (P1.3) is used as the odd-even field mark signal. Since the equalization pulses of the odd field and the even field are different, the odd-even field mark needs to be transmitted between the first microcontroller and the second microcontroller to maintain their synchronization. The eighteenth pin (P1.6) is used as the video synchronization signal. The signal includes the field synchronization signal, the line synchronization signal, the front equalization pulse, the rear equalization pulse and the slot pulse, which can be said to be a combination of video auxiliary signals. Since the image can be strictly controlled in this application The timing of signal generation, so there is no need for line blanking pulse and field blanking pulse, so the pin signal does not include these two signals; the nineteenth pin (P1.7) transmits the synchronization signal to the second single-chip microcomputer. After each line synchronization of the first single-chip microcomputer, a pulse is sent to the second single-chip microcomputer, so that the second single-chip microcomputer uses this pulse as a timing reference to accurately generate a circular signal; the sixteenth pin (P1.4) is used as a field reset signal, that is, a pulse signal is output at the end of each field. This pulse signal causes the second single-chip microcomputer to cycle to the beginning of the process and execute, so that the second single-chip microcomputer completes one synchronization per field; the twelfth pin (P1.0 ) is used to connect to the fifteenth pin (P1.3) of the first single-chip microcomputer to receive the odd and even field mark signal; the fourteenth pin (P1.2) is used as a circle image signal, and the signal output by this pin is superimposed on the display screen to generate a highlighted circle; the sixteenth pin (P1.4) is used to connect to the sixteenth pin (P1.4) of the first single-chip microcomputer to receive the field reset signal, so that the single-chip microcomputer jumps to the beginning of the process to execute; the nineteenth pin (P1.7) is connected to the nineteenth pin (P1.7) of the first single-chip microcomputer to receive the synchronization signal sent by the first single-chip microcomputer, to create a timing reference for the single-chip microcomputer, so that it can accurately generate a circle signal; Figure 5As shown, a different high level is added to each row to form a circle, and the high level outputted by each row is slightly changed to form a rough circle, and by calculating when and how long a circular high level should be generated for each row of signals, the edge of the circle is made as smooth as possible, thereby solving the problem of sawtooth generation at the edge of the circle; the power supply module uses a DC / DC module to convert the +12V voltage into a -12V voltage, and uses voltage regulator chips 7805 and 7905 to change the +12V and -12V voltages into +5V and -5V voltages respectively; the functions of each voltage are: +12V and -12V voltages are used as power supplies for the LF347N amplifier; +5V voltage is used as a power supply for the first microcontroller and the second microcontroller; this application needs to generate a full television signal with a positive polarity, and the voltage of the synchronization pulse is -0.3V, and the -5V voltage is designed to synthesize this negative voltage.

[0033] like Figure 3 As shown, here, the line blanking and field blanking are omitted; it can be seen from the figure that the synchronization signal is -0.3V, 0V voltage represents a black screen, and 0.7V voltage represents a white screen; the resistance values ​​of the first to fourth resistors in the circuit diagram are calculated based on this signal;

[0034] In practice, the output of the microcontroller is about 4V, and the output of the 7905 voltage regulator chip is -5V. In practice, in order to make the synchronization signal more stable, the synchronization low level is reduced to -0.7V. In order to make the highlighted circle clear, the superimposed signal of the circle is set to 0.5V. First, the second-stage magnification is given as Its reciprocal is -3, so let N = 3; the synchronization signal after the first stage amplification is 0.7NV, the white signal is -0.7NV, the black signal is still 0V, and the superimposed circular signal is -0.5NV; then the following formula can be listed from the circuit diagram (the following synchronization, square, and circle represent the synchronization signal, square signal, and circular signal output by the microcontroller respectively):

[0035] The following resistance units are all KΩ, and the voltage units are all V. Let R18 = R = 20,

[0036] Synchronous = 0, square = 0, circle = 0, then

[0037] but

[0038]

[0039] Synchronization = 4, square = 0, circle = 0, then

[0040] Simplified

[0041]

[0042] Synchronous = 4, square = 4, circle = 0, then

[0043] Simplified

[0044]

[0045] Synchronous = 4, square = 0, circle = 4, then

[0046] Simplified

[0047]

[0048] The process of generating synchronization signals, square signals and circle signals through programming is as follows:

[0049] (1) Generate synchronization signals through programming and use loop sub-processes to achieve delay, that is, each instruction has a certain execution time, and the purpose of accurate delay is achieved by calculating its execution time;

[0050] Specifically,

[0051] First, in order to make the MCU work stably, there is a delay of about 20 microseconds at the beginning of the process execution. The purpose is to wait for the MCU to stabilize before executing the whole process; the next step is to reset the values ​​of each pin and flag, including the odd and even field flag, to prevent the second MCU from resetting and triggering the assignment; as mentioned above, if Figure 6 As shown, the present application starts processing from odd field synchronization, so the odd field flag is assigned to 1 (1 represents odd field); the next step is the generation of field synchronization and post-equalization signals; in the entire process, a delay module is generally used to implement redundant time delay, and register Rn is used to count the number of high levels;

[0052] It can be seen from the waveform diagram of the synchronization signal that the distance between the last high level of the post-equalization and the first line synchronization is different in the odd field and the even field, so when processing, odd field and even field control modules are established to control the odd field and the even field differently; the next is the processing of blanking line synchronization, where a slight change is made to the synchronization signal, and the post-blanking of the odd field is ended 32 microseconds (i.e., half a line period) in advance, which enables the odd field and the even field to share the same processing flow here; it generates a line synchronization signal and a grid signal by establishing a line synchronization process, and outputs a line synchronization trigger signal to the second single-chip microcomputer, which is completed by adjusting the line synchronization process time; according to the synchronization waveform diagram, the next should be the pre-equalization signal, because the time between the last line synchronization pulse of the odd field and the even field and the first pre-equalization pulse is different, so it is consistent with the above-mentioned blanking line synchronization processing; the odd field front blanking time is increased by one line synchronization period, and the even field front blanking time is increased by half a line synchronization period;

[0053] Then, after the pre-equalization pulse jumps back to CTB to generate the next field synchronization signal; of course, there are two things to do before the jump: first, the odd and even field flags must be changed, and second, a reset signal must be sent to the second microcontroller so that each field of the second microcontroller is synchronized with the synchronization signal, which is achieved here through pin P1.7;

[0054] (ii) Generate a grid signal through programming,

[0055] First, let's analyze the relationship between the grid signal and time: this application uses a 5:4 monitor, so the number of grids is set to 10*8, that is, 10 grids horizontally and 8 grids vertically. The display effect is as follows: Figure 5 As shown;

[0056] First analyze the horizontal time. The line synchronization cycle is 64us. Excluding the 12us retrace time, the display time is only 52us. Divide it into ten parts, each part is 5us, that is, each square gap can execute 10 single-cycle instructions; then do a vertical analysis. Each field can display 287 lines, which should be divided into 8 parts, each part has 36 lines, which means that the first square signal level after every 36 lines of line synchronization should be flipped; so far, the settings are made according to the above analysis; the details are as follows:

[0057] First, set the black and white judgment flag 09H, the total number of row synchronizations and the number of columns of the squares; because there are 288 row synchronizations in total, and the register is 8 bits, two registers are used to count the total number of rows; delay to the appropriate time, generate the falling edge of the synchronization signal, and at the same time generate the falling edge of the synchronization signal transmitted to the second single-chip microcomputer. At this time, the time interval to the rising edge of the synchronization signal is 5us. During this 5us time, the total number of row synchronizations must be counted and judged; then generate the rising edge of the synchronization signal and transmit it to the second single-chip microcomputer; next, it is necessary to determine whether a row of squares is over, and select different process branches according to the judgment result, and correctly output the high and low level timing of the square signal; no matter which process branch it chooses, it requires the same starting time for the square signal output, so there are several jumps in this process section to achieve this function; then the single-chip square signal output port outputs 10 equally spaced high and low level signals; this is to complete the output of a row of signals, and the loop is executed until the front equalization pulse;

[0058] (iii) Generate circular signals through programming,

[0059] The circular signal is generated by the second single-chip microcomputer, and the starting position and width of each row of circular signals are different. In order to realize this function, a data table is stored in the second single-chip microcomputer; the first column of the table is the starting time of the circular signal (microseconds), and the second column is the width of the circular signal; Figure 7The figure shows the flow chart of circle signal generation. Because the second single chip starts execution from field synchronization, there is a certain delay at the beginning of the process to wait for the arrival of line synchronization. The diameter of the circle selected by this application is 3 / 5 of the width of the display. Then, it can be calculated that each vertical field occupies 230 lines, and there are 28 lines without circles on the circle. The values ​​of each data in the data table can be calculated by these standards. In the process, the data register pointer DPTR must first be assigned the starting address of the data table, and the Rn register is used to count the lines without circles and the lines with circles. After the line with circles appears, the value pointed to by DPTR is read, and DPTR is incremented. Then, the pin P1.2 is set and reset according to the time specified by the data to output the desired circle signal.

[0060] The above is a brief analysis of the entire process. The core is to generate the required video signal by setting or resetting the microcontroller pin at the appropriate time.

[0061] The above embodiments are only preferred implementations of the present invention, so all equivalent changes or modifications made according to the structures, features and principles described in the scope of the patent application of the present invention are included in the scope of the patent application of the present invention.

Claims

1. An air defense missile simulator video test signal synthesis device, characterized in that: The video signal generating module is composed of a video signal generating module and a power supply module for supplying power to the video signal generating module, and the video signal generating module is used to generate a video signal and input the signal to the video input terminal of the monitor, so as to detect the quality of the monitor; the video signal generating module is electrically connected to the power supply module; The video signal generating module comprises two single-chip microcomputers, an adder electrically connected to the video signal output terminals of the two single-chip microcomputers, and an inverting amplifier electrically connected to the adder; the output terminal of the inverting amplifier is electrically connected to the video input terminal of the monitor; the two single-chip microcomputers are composed of a first single-chip microcomputer for generating a synchronization signal and a square image signal, and a second single-chip microcomputer for receiving the synchronization signal output by the first single-chip microcomputer and keeping synchronization with it, and outputting a circle signal for highlighting display; The power supply module includes a DC / DC module for converting a +12V voltage into a -12V voltage, and a first step-down module and a second step-down module for changing the +12V and -12V voltages into +5V and -5V voltages, respectively; the first step-down module and the second step-down module are electrically connected to the DC / DC module, respectively; The first step-down module includes a 7805 voltage regulator chip and its peripheral circuits; The second step-down module includes a 7905 voltage regulator chip and its peripheral circuits; The first single-chip microcomputer and the second single-chip microcomputer are both composed of a minimum system of AT89C2051 single-chip microcomputers; The reverse amplifier is composed of a LF347N amplifier and its peripheral circuits.

2. The air defense missile simulator video test signal synthesis device according to claim 1, characterized in that: The fifteenth pin, the sixteenth pin and the nineteenth pin of the first single-chip microcomputer are electrically connected to the twelfth pin, the sixteenth pin and the nineteenth pin of the second single-chip microcomputer respectively.

3. The air defense missile simulator video test signal synthesis device according to claim 1, characterized in that: The adder is composed of a first series group, a second series group, a third series group and a fourth series group; the first series group is composed of a first resistor and a seventeenth resistor connected in series, and the other end of the first resistor is electrically connected to the eighteenth pin of the first single-chip microcomputer; the second series group is composed of a second resistor and a sixteenth resistor connected in series, and the other end of the second resistor is electrically connected to the fourteenth pin of the first single-chip microcomputer; the third series group is composed of a third resistor and a fifteenth resistor connected in series, and the other end of the third resistor is electrically connected to the fourteenth pin of the second single-chip microcomputer; the fourth series group is composed of a fourth resistor and a fourteenth resistor connected in series, and the other end of the fourth resistor is electrically connected to the output end of the second step-down module; the other ends of the fifteenth to seventeenth resistors are electrically connected to the other end of the fourteenth resistor and then electrically connected to the input end of the reverse amplifier.

Images