Semiconductor package with improved heat dissipation and electromagnetic shielding properties

Abstract

A semiconductor package may include: a first semiconductor chip located on and electrically connected to a wiring substrate; an intermediate layer located on the first semiconductor chip and covering the entire surface of the first semiconductor chip; a second semiconductor chip located on the intermediate layer and electrically connected to the wiring substrate; a molding layer located on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the molding layer including one or more inner surfaces defining molded vias that expose a portion of the surface of the intermediate layer; an electromagnetic shielding layer located on the one or more inner surfaces of the molding layer and also on one or more outer surfaces of the molding layer; and a heat dissipation layer located on the electromagnetic shielding layer in the molded vias, such that the heat dissipation layer fills the molded vias.

Description

[0001] Cross-reference of related applications

[0002] This application claims the rights of Korean Patent Application No. 10-2018-0104781, filed on September 3, 2018, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to semiconductor packaging, and more specifically, to semiconductor packaging with improved heat dissipation and electromagnetic shielding properties. Background Technology

[0004] As the speed and performance of electronic devices increase, the heat dissipation characteristics of the semiconductor packages included in these devices can be improved to enhance operational reliability. In some cases, semiconductor packages may be susceptible to damage or interference from electromagnetic waves, which can lead to reduced operational reliability of electronic devices containing semiconductor packages. Summary of the Invention

[0005] The present invention provides a semiconductor package with improved heat dissipation and electromagnetic shielding characteristics, which improves the resistance of the semiconductor package to damage or obstruction caused by electromagnetic waves, thereby enabling electronic devices including the semiconductor package to have improved operational reliability based on the improved heat dissipation and electromagnetic shielding characteristics of the semiconductor package.

[0006] According to some exemplary embodiments, a semiconductor package may include: a first semiconductor chip on a wiring substrate; an intermediate layer on the first semiconductor chip; a second semiconductor chip on the intermediate layer; a molding layer on the wiring substrate, the molding layer covering the first semiconductor chip and the second semiconductor chip; an electromagnetic shielding layer on one or more inner surfaces of the molding layer; and a heat dissipation layer. The intermediate layer may cover the entire surface of the first semiconductor chip. The second semiconductor chip may be electrically connected to the wiring substrate. The molding layer may include one or more inner surfaces defining molded vias that expose a portion of the surface of the intermediate layer. The electromagnetic shielding layer may be located on the one or more inner surfaces of the molding layer. The electromagnetic shielding layer may also be located on one or more outer surfaces of the molding layer. The heat dissipation layer may be located on the electromagnetic shielding layer in the molded vias, such that the heat dissipation layer fills the molded vias.

[0007] According to some exemplary embodiments, a semiconductor package may include: a first semiconductor chip located on a wiring substrate; an intermediate layer located on the first semiconductor chip; a second semiconductor chip located on the intermediate layer; a third semiconductor chip located on the intermediate layer; a molding layer located on the wiring substrate; an electromagnetic shielding layer located on one or more inner surfaces of the molding layer, the electromagnetic shielding layer also located on one or more outer surfaces of the molding layer; and a heat dissipation layer located on the electromagnetic shielding layer in a molded via, such that the heat dissipation layer fills the molded via. The first semiconductor chip may be electrically connected to the wiring substrate. The first semiconductor chip may include a logic chip. The intermediate layer may cover the entire surface of the first semiconductor chip. The second semiconductor chip may be electrically connected to the wiring substrate. The second semiconductor chip may include a memory chip. The third semiconductor chip may be isolated from the second semiconductor chip and not in direct contact. The third semiconductor chip may be electrically connected to the wiring substrate. The third semiconductor chip may include a separate memory chip. The molding layer may cover the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip. The molded layer may include one or more inner surfaces that at least partially define molded through-holes that expose a portion of the surface of the intermediate layer.

[0008] According to some exemplary embodiments, a semiconductor package may include: a first semiconductor chip on a wiring substrate; an intermediate layer on the first semiconductor chip; a second semiconductor chip on the intermediate layer; a third semiconductor chip on the intermediate layer; a molding layer on the wiring substrate; an electromagnetic shielding layer; and a heat dissipation layer. The first semiconductor chip is electrically connected to the wiring substrate. The first semiconductor chip may include a logic chip, and the logic chip may include a heat source. The intermediate layer may cover the entire surface of the first semiconductor chip. The second semiconductor chip is electrically connected to the wiring substrate. The second semiconductor chip may include a memory chip. The third semiconductor chip may be isolated from the second semiconductor chip and not in direct contact. The third semiconductor chip is electrically connected to the wiring substrate. The third semiconductor chip may include a separate memory chip. The molding layer may cover the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip. The molding layer may include a plurality of inner surfaces that at least partially define a plurality of molded vias, the plurality of molded vias exposing a portion of the surface of the intermediate layer in both a central region between the second semiconductor chip and the third semiconductor chip and an edge portion of the intermediate layer. The electromagnetic shielding layer may be located on the plurality of inner surfaces of the molded layer. The electromagnetic shielding layer may also be located on one or more outer surfaces of the molded layer. The heat dissipation layer may be located on the electromagnetic shielding layer in each of the plurality of molded through-holes, such that the heat dissipation layer fills the plurality of molded through-holes. Attached Figure Description

[0009] Exemplary embodiments of the present invention will become clearer by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a plan view of a semiconductor package according to some exemplary embodiments of the present invention.

[0011] Figure 2 These are some exemplary embodiments of the present invention, truncated along line of sight II-II'. Figure 1 The diagram shows a cross-sectional view of the main parts of a semiconductor package.

[0012] Figure 3A , Figure 3B and Figure 3C Each of these are exemplary embodiments of the concept according to the present invention, shown Figure 1 and Figure 2 The diagram shows a plan view of the various configurations of the heat source, molded vias, electromagnetic shielding layer, and heat dissipation layer in the semiconductor package.

[0013] Figure 4These are exemplary embodiments of the present invention, conformally formed in Figure 1 and Figure 2 A cross-sectional view of the main portion of the electromagnetic shielding layer on the inner wall of the molded through-hole of the semiconductor package 10 shown.

[0014] Figure 5 This is a cross-sectional view of the main parts of a semiconductor package according to some exemplary embodiments of the present invention.

[0015] Figure 6 This is a cross-sectional view of the main parts of a semiconductor package according to some exemplary embodiments of the present invention.

[0016] Figure 7 This is a cross-sectional view of the main parts of a semiconductor package according to some exemplary embodiments of the present invention.

[0017] Figure 8 This is a plan view of a semiconductor package according to some exemplary embodiments of the present invention.

[0018] Figure 9 These are exemplary embodiments of the present invention, truncated along line of sight IX-IX'. Figure 8 The diagram shows a cross-sectional view of the main parts of a semiconductor package.

[0019] Figure 10 This is a cross-sectional view of a semiconductor package according to some exemplary embodiments of the present invention.

[0020] Figure 11 , Figure 12 , Figure 13 and Figure 14 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package, based on some exemplary embodiments of the concept of the present invention.

[0021] Figure 15 , Figure 16 and Figure 17 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package, based on some exemplary embodiments of the concept of the present invention.

[0022] Figure 18 This is a block diagram of an electronic system including some exemplary embodiments of a semiconductor package according to the concept of the present invention. Detailed Implementation

[0023] Exemplary embodiments of the inventive concept can be implemented through one or more embodiments or combinations of embodiments. Therefore, the spirit of the inventive concept is not to be interpreted solely by one exemplary embodiment. The drawings are not necessarily shown to scale. In some embodiments, the scale of at least a portion of the structures shown in the drawings may be exaggerated to clearly illustrate the characteristics of the embodiments.

[0024] Figure 1 This is a plan view of a semiconductor package 10 according to some exemplary embodiments of the present invention.

[0025] Figure 2 It is intercepted along line of sight II-II' Figure 1 A cross-sectional view of the main parts of the semiconductor package 10 shown.

[0026] Specifically Figure 2 It is along Figure 1 The image shows a cross-sectional view of the main portion taken from line II-II'. Semiconductor package 10 can be a system-in-package (SIP) or a multi-stacked package. Semiconductor package 10 can be an electronic system comprising multiple semiconductor chips. Semiconductor package 10 can be a processor, application processor, modem, etc.

[0027] The semiconductor package 10 may include a wiring substrate 102, an intermediate layer 114, a first semiconductor chip CH1, a second semiconductor chip CG2, a third semiconductor chip CG3 located on the wiring substrate 102, molding layers 116a and 116b, electromagnetic shielding layers 120a and 120b, and heat dissipation layers 122a, 122b, and 122c. Figure 1 In the reference designation, electromagnetic shielding layers 120a and 120b are both represented by 120.

[0028] For convenience, some exemplary embodiments of the semiconductor package 10 are shown as including a second semiconductor chip CG2 and a third semiconductor chip CG3. However, the semiconductor package 10 may include only one of the second semiconductor chip CG2 and the third semiconductor chip CG3.

[0029] The wiring substrate 102 may be a printed circuit board (PCB) with a circuit pattern. The wiring substrate 102 may have a certain length in the X direction and a certain length in the Y direction perpendicular to the X direction. The external terminal 104 may be located on the lower surface of the wiring substrate 102 with a certain area. The external terminal 104 may contain conductive material and may have the shape of a solder ball. The external terminal 104 can electrically connect the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 to an external electrical device (not shown in the figure).

[0030] A first semiconductor chip CH1 may be attached to and located on a wiring substrate 102. The first semiconductor chip CH1 may be electrically connected to the wiring substrate 102. The first semiconductor chip CH1 may be attached to the wiring substrate 102 in the Z direction perpendicular to the XY plane. The first semiconductor chip CH1 may be a logic chip (LC) and / or include a logic chip (LC). The first semiconductor chip CH1 may include a central processing unit (CPU). The first semiconductor chip CH1 may include an integrated circuit, such as a memory circuit, a logic circuit, or a combination thereof. The first semiconductor chip CH1 may include heat sources 110a, 110b, and 110c that generate heat. In some exemplary embodiments, the first semiconductor chip CH1 may include an individual heat source among heat sources 110a, 110b, and 110c. In some exemplary embodiments, the heat source of the first semiconductor chip CH1 may be a heat source included in the logic chip LC included in the first semiconductor chip CH1.

[0031] Heat sources 110a, 110b, and 110c may be blocks within the integrated circuit whose functions are necessary for configuration by hardware or software implementation. For example, heat sources 110a, 110b, and 110c may be a central processing unit or its circuitry. Heat sources 110a, 110b, and 110c may be determined by the circuit design of the first semiconductor chip CH1. In a plan view, heat sources 110a, 110b, and 110c may be arranged spaced apart from each other at the edge portions of the first semiconductor chip CH1, such as in... Figure 1 As shown in the image.

[0032] A connection bump 108 may be located below the first semiconductor chip CH1. The connection bump 108 may be located between the wiring substrate 102 and the first semiconductor chip CH1. The first semiconductor chip CH1 may be electrically connected to the wiring substrate 102 via the connection bump 108. The connection bump 108 may be a connection terminal for electrically connecting the first semiconductor chip CH1 to the wiring substrate 102. The connection bump 108 may contain a conductive material.

[0033] Intermediate layer 114 can be attached to the first semiconductor chip CH1 using adhesive layer 112. Intermediate layer 114 can serve as an intermediate layer for transferring heat generated in the first semiconductor chip CH1. For example, in... Figure 2 As shown, the intermediate layer 114 may cover the entire upper surface CH1T of the first semiconductor chip CH1. The intermediate layer 114 may be a heat sink HS. The heat sink HS may disperse the heat generated in the first semiconductor chip CH1. The heat sink HS may contain a material with high thermal conductivity, such as a metal, a metal alloy, or a carbon material.

[0034] The second semiconductor chip CG2 and the third semiconductor chip CG3 can each be attached to the intermediate layer 114. The positions of the second semiconductor chip CG2 and the third semiconductor chip CG3 can be spaced apart from each other on the intermediate layer 114. To put it another way, and as in... Figure 2 As shown, the third semiconductor chip CG3 can be isolated from the second semiconductor chip CG2 and not in direct contact, although both the second semiconductor chip CG2 and the third semiconductor chip CG3 can be directly located on the intermediate layer 114. The second semiconductor chip CG2 and the third semiconductor chip CG3 can be chips of a different type from the first semiconductor chip CH1. The second semiconductor chip CG2 and the third semiconductor chip CG3 can each be electrically connected to the wiring substrate 102.

[0035] The second semiconductor chip CG2 and the third semiconductor chip CG3 may be and / or include one or more memory chips (MCs) containing one or more memory circuits, such as DRAM chips. The second semiconductor chip CG2 and the third semiconductor chip CG3 may each have a smaller size than the first semiconductor chip CH1.

[0036] The second semiconductor chip CG2 and the third semiconductor chip CG3 can be electrically connected to the wiring substrate 102. The second semiconductor chip CG2 and the third semiconductor chip CG3 can be electrically connected to the wiring substrate 102 via (“through”) separate corresponding bonding lines 115a and 115b.

[0037] As in Figure 2 As shown, the second semiconductor chip CG2 may be and / or include a multi-layer chip, the multi-layer chip including a plurality of sub-chips CH2a and CH2b sequentially stacked on the intermediate layer 114. The third semiconductor chip CG3 may be a multi-layer chip including a plurality of sub-chips CH3a and CH3b sequentially stacked on the intermediate layer 114. Therefore, in the case of including Figure 2 In some exemplary embodiments of the illustrated embodiments, each of the second semiconductor chip CG2 and the third semiconductor chip CG3 may include an independent multilayer chip, and each independent multilayer chip includes a plurality of independent sub-chips sequentially stacked on an intermediate layer 114. The sub-chips CH2a and CH2b constituting the second semiconductor chip CG2, and the sub-chips CH3a and CH3b constituting the third semiconductor chip CG3, may be electrically connected to the wiring substrate 102 via bonding wires 115a and 115b, respectively.

[0038] Molding layers 116a and 116b can be formed on wiring substrate 102 to cover the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3. For example, in Figure 2As shown, molding layers 116a and 116b can jointly form a molding layer 116 located on the wiring substrate 102 and covering at least the first semiconductor chip CH1 and the second semiconductor chip CG2. This molding layer 116 can cover the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3. Molding layer 116a can be formed on the wiring substrate 102 and located below the intermediate layer 114. Molding layer 116b can be formed on the top and sidewalls of the intermediate layer 114. Molding layers 116a and 116b can contain an insulating polymer, such as an epoxy molding compound.

[0039] Molded through-holes 118a, 118b, and 118c can be formed in the molding layer 116b on the intermediate layer 114. Therefore, and as in at least Figure 2 As shown, molded through-holes 118a, 118b, and 118c may each be at least partially defined by one or more inner surfaces 116S of the molded layer 116. In some exemplary embodiments, the molded layer 116b may include one or more inner surfaces 116S that at least partially define a single individual molded through-hole among the molded through-holes 118a, 118b, and 118c. The molded through-holes 118a, 118b, and 118c may expose a portion of the surface 114S of the intermediate layer 114. Figure 1 As shown, the molded through-holes 118a, 118b, and 118c can be one or more molded through-hole patterns, each having a planar constant area on the intermediate layer 114. The molded through-holes 118a, 118b, and 118c can be molded through-hole patterns extending in the Y direction. (As shown in...) Figure 2 As shown, the molded through-hole 118b can be located on the intermediate layer 114 and can be located between the second semiconductor chip CG2 and the third semiconductor chip CG3. For example, in Figure 2 As further shown, the molded through-hole 118b can be isolated from the second semiconductor chip CG2 or the third semiconductor chip CG3 without direct contact with the second semiconductor chip CG2 or the third semiconductor chip CG3. For example, in Figure 2 As further shown, the molded through-hole 118a is located on the edge portion 114E1 of the intermediate layer 114, closer to the second semiconductor chip CG2 than the third semiconductor chip CG3, and can be isolated from the second semiconductor chip CG2 without direct contact. For example, in Figure 2 As further shown, the molded through-hole 118c is located on the edge portion 114E2 of the intermediate layer 114, closer to the third semiconductor chip CG3 than the second semiconductor chip CG2, and can be isolated from the third semiconductor chip CG3 without direct contact. For example, in Figure 2As further shown, the molded through-hole 118b exposes a portion of the surface 114S of the intermediate layer 114 in the central region 114C between the second semiconductor chip CG2 and the third semiconductor chip CG3.

[0040] Figure 2 Examples are shown in which the upper diameter of molded through holes 118a, 118b, and 118c is equal to its lower diameter, and therefore the inner walls of the molded through holes 118a, 118b, and 118c are vertical. However, the upper diameter may be larger or smaller than the lower diameter, and therefore the inner walls may not be vertical. The molded through holes 118a, 118b, and 118c may be referred to as molded grooves. The molded through holes 118a, 118b, and 118c may be referred to as molded through holes.

[0041] Electromagnetic shielding layers 120a and 120b may be formed inside molded vias 118a, 118b, and 118c and located on molded layers 116a and 116b. Alternatively, electromagnetic shielding layers 120a and 120b may each be located on one or more inner surfaces 116S of molded layer 116 and may further be located on one or more outer surfaces 116T of molded layer 116, wherein the inner surfaces 116S at least partially define the one or more molded vias 118a, 118b, and 118c. Electromagnetic shielding layers 120a and 120b may collectively form electromagnetic shielding layer 120. Electromagnetic shielding layers 120a and 120b may surround the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3.

[0042] The electromagnetic shielding layer 120a may be formed to conformally extend (with a constant thickness) within the molded through-holes 118a, 118b, and 118c (i.e., on the bottom and inner walls of the molded through-holes 118a, 118b, and 118c, for example, on one or more inner surfaces 116S)). Figure 2 As shown, electromagnetic shielding layer 120a extends conformally on one or more inner surfaces 116S defining the bottom of molded through-holes 118a, 118b, and / or 118c and the inner walls of the molded through-holes 118a, 118b, and / or 118c. Electromagnetic shielding layer 120b may be conformally formed on one or more outer surfaces 116T of molded layers 116a and 116b and two (“opposite”) sidewalls 116W (e.g., opposite sidewalls 116W of molded layer 116). Electromagnetic shielding layers 120a and 120b may comprise materials including conductors and magnetic materials. Electromagnetic shielding layers 120a and 120b may be formed by dispersing magnetic material in a metallic material.

[0043] Electromagnetic shielding layers 120a and 120b can surround the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3, and can be grounded to the metal wiring of the wiring substrate 102 (not shown in the figure). Therefore, electromagnetic waves transmitted from the outside of the semiconductor package 10 can be shielded by electromagnetic shielding layers 120a and 120b.

[0044] Electromagnetic waves generated by the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 in the semiconductor package 10 can be grounded and removed through the electromagnetic shielding layers 120a and 120b and the metal wiring (not shown) of the wiring substrate 102. Therefore, the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 can be protected from damage or obstruction by electromagnetic waves due to the presence of the electromagnetic shielding layers 120a and 120b.

[0045] Heat dissipation layers 122a, 122b, and 122c may fill the respective molded through-holes 118a, 118b, and 118c on the electromagnetic shielding layer 120a. Alternatively, each heat dissipation layer 122a, 122b, and 122c may be located on the electromagnetic shielding layer 120a in a given molded through-hole 118a, 118b, and 118c, at least partially defined by one or more inner surfaces 116S of the molded layer 116, such that the given heat dissipation layers 122a, 122b, and 122c fill the given molded through-holes 118a, 118b, and 118c. The molded through-holes 118a, 118b, and 118c, and the heat dissipation layers 122a, 122b, and 122c, can correspond to the heat sources 110a, 110b, and 110c of the first semiconductor chip CH1. For example, in... Figure 1 and Figure 2 As shown, the molded through-hole 118b can be formed on the intermediate layer 114 between the second semiconductor chip CG2 and the third semiconductor chip CG3.

[0046] Molded through-holes 118a and 118c can be formed respectively in the edge portion of the intermediate layer 114 separated from one side of the second semiconductor chip CG2 and the edge portion of the intermediate layer 114 separated from one side of the third semiconductor chip CG3. Heat generated in the heat sources 110a, 110b, and 110c of the first semiconductor chip CH1 can be easily discharged to the outside through the intermediate layer 114, the electromagnetic shielding layers 120a and 120b, and the heat dissipation layers 122a, 122b, and 122c, such as by… Figure 2As indicated by the arrows in the diagram. As described herein, a given molded via and heat dissipation layer can "correspond" to a given heat source, wherein the semiconductor package is configured to dissipate heat generated in said heat source to the outside of the semiconductor package 10 through the given molded via and heat dissipation layer. For example, in Figure 2 In this context, the molded through-hole 118b and the heat dissipation layer 122b will be understood as each "corresponding" to the heat source 110b, because the semiconductor package 10 is configured to dissipate heat generated in the heat source 110b to the outside relative to other molded through-holes and heat dissipation layers of the semiconductor package 10 through at least the molded through-hole 118b and the heat dissipation layer 122b, as in... Figure 2 The arrow extending from heat source 110b is shown in the middle. Similarly, for similar reasons and as indicated by... Figure 2 As shown by the arrow patterns extending from the corresponding heat sources 110a and 110c, the molded through-hole 118a and the heat dissipation layer 122a will be understood to correspond to heat source 110a, and the molded through-hole 118c and the heat dissipation layer 122c will be understood to correspond to heat source 110c.

[0047] As in Figure 2 As shown, the upper layer of the semiconductor package 10, including the second semiconductor chip CG2 and the third semiconductor chip CG3, may have a region A including molding regions M1 and M4, chip regions M2 and M3, and heat dissipation regions V1, V2, and V3. In chip regions M2 and M3, the first semiconductor chip CH1 may overlap with the second semiconductor chip CG2 and the third semiconductor chip CG3. Therefore, region A of the semiconductor package 10 may include chip region M2 and heat dissipation regions (e.g., V1, V2, and / or V3), in which the first semiconductor chip CH1 and the second semiconductor chip CG2 extend in a vertical direction perpendicular to the upper surface 102T of the wiring substrate 102 (e.g., as shown in...). Figure 2 The first semiconductor chip CH1 and the second semiconductor chip CG2 overlap in the Z direction (as shown in the diagram), and in the heat dissipation area, the first semiconductor chip CH1 and the second semiconductor chip CG2 do not overlap in the vertical direction.

[0048] In heat dissipation regions V1, V2, and V3, the first semiconductor chip CH1 may not overlap with the second semiconductor chip CG2 and the third semiconductor chip CG3. The second semiconductor chip CG2 and the third semiconductor chip CG3 may be respectively disposed in chip regions M2 and M3. Heat dissipation layers 122a, 122b, and 122c may be respectively disposed in heat dissipation regions V1, V2, and V3, and can easily dissipate heat to the outside because the first semiconductor chip CH1 does not overlap with the second semiconductor chip CG2 and the third semiconductor chip CG3 in heat dissipation regions V1, V2, and V3. Alternatively, heat dissipation regions V1, V2, and / or V3 may include molded through-holes and heat dissipation layers, such as in... Figure 2As shown in the image.

[0049] Heat dissipation layers 122a, 122b, and 122c may comprise a material with high thermal conductivity. Heat dissipation layers 122a, 122b, and 122c may comprise a material with a thermal conductivity higher than that of molding layers 116a and 116b. Heat dissipation layers 122a, 122b, and 122c may be referred to as heat conduction layers or heat channel layers. Heat dissipation layers 122a, 122b, and 122c may comprise a conductive material, such as a metal.

[0050] Heat dissipation layers 122a, 122b, and 122c may contain any material selected from aluminum (Al), tin (Sn), copper (Cu), silver (Ag), nickel (Ni), alumina (Al₂O₃), zinc oxide (ZnO), silicon carbide (SiC), aluminum nitride (AlN), boron nitride (BN), diamond, and combinations thereof. Heat dissipation layers 122a, 122b, and 122c may have a higher thermal conductivity than molded layers 116a and 116b. Heat dissipation layer 122b may overlap with heat source 110b. Heat dissipation layers 122a and 122c may not overlap with heat sources 110a and 110c.

[0051] Since the first semiconductor chip CH1 can be easily dissipated through the intermediate layer 114, the electromagnetic shielding layers 120a and 120b, and the heat dissipation layers 122a, 122b, and 122c, the operational reliability of the first semiconductor chip CH1 can be improved. Furthermore, since the heat generated in the first semiconductor chip CH1 can be easily dissipated through the intermediate layer 114, the electromagnetic shielding layers 120a and 120b, and the heat dissipation layers 122a, 122b, and 122c, the heat will not affect the second semiconductor chip CG2 and the third semiconductor chip CG3, and thus the operational reliability of the second semiconductor chip CG2 and the third semiconductor chip CG3 can be improved.

[0052] Furthermore, since the heat generated in the second semiconductor chip CG2 and the third semiconductor chip CG3 can be easily dissipated to the outside through the intermediate layer 114, the electromagnetic shielding layers 120a and 120b, and the heat dissipation layers 122a, 122b and 122c, the operational reliability of the second semiconductor chip CG2 and the third semiconductor chip CG3 can be improved.

[0053] As described above, the semiconductor package 10 may include electromagnetic shielding layers 120a and 120b, and therefore the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 are unaffected by electromagnetic waves. In other words, the semiconductor package 10 may include electromagnetic shielding layers 120a and 120b, and therefore may have good electromagnetic shielding characteristics.

[0054] Furthermore, since the semiconductor package 10 includes an intermediate layer 114, molded through-holes 118a, 118b, and 118c, and heat dissipation layers 122a, 122b, and 122c for easy heat dissipation, the operational reliability of the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 can be improved. In other words, the semiconductor package 10 may include an intermediate layer 114, molded through-holes 118a, 118b, and 118c, and heat dissipation layers 122a, 122b, and 122c, and therefore can have excellent heat dissipation characteristics.

[0055] Figure 3A , Figure 3B and Figure 3C Each shows Figure 1 and Figure 2 The diagram shows a plan view of the various configurations of the heat source, molded vias, electromagnetic shielding layer, and heat dissipation layer in the semiconductor package 10.

[0056] Specifically, in Figure 1 and Figure 2 In the semiconductor package 10 shown, molded through-holes (see...) Figure 1 The molded through-holes 118a, 118b and 118c are formed on the intermediate layer 114 as a molded through-hole pattern extending in one direction (i.e., the Y direction), as shown above. Figure 1 As shown in the floor plan. Furthermore, as in Figures 3A to 3C As shown, the molded through holes 118-1, 118-2 and 118-3 can be arranged in various ways.

[0057] As in Figure 3A As shown, the molded through-holes 118-1 are arranged as a plurality of molded through-hole patterns 300A (i.e., four molded through-hole patterns 300A) extending in the Y direction and spaced apart from each other ("isolated from each other and not in direct contact"). An electromagnetic shielding layer 120-1 and a heat dissipation layer 122-1 are located within the molded through-holes 118-1. The location of the heat source 110-1 may overlap with the molded through-holes 118-1.

[0058] As in Figure 3B As shown, the molded through-holes 118-2 are arranged as a plurality of molded through-hole patterns 300B extending in the Y direction and spaced apart from each other (i.e., two molded through-hole patterns 300B). An electromagnetic shielding layer 120-2 and a heat dissipation layer 122-2 are located within the molded through-holes 118-2. The location of the heat source 110-2 may overlap with the molded through-holes 118-2.

[0059] As in Figure 3CAs shown, the molded through-holes 118-3 are arranged as a plurality of molded through-hole patterns 300C extending in the Y direction and spaced apart from each other (i.e., two molded through-hole patterns 300C). An electromagnetic shielding layer 120-3 and a heat dissipation layer 122-3 are located within the molded through-holes 118-3. The position of the heat source 110-3 can be configured not to overlap with the molded through-holes 118-3.

[0060] Figure 4 It is formed conformally in Figure 1 and Figure 2 A cross-sectional view of the main portion of the electromagnetic shielding layer on the inner wall of the molded through-hole of the semiconductor package 10 shown.

[0061] Specifically, electromagnetic shielding layers 120a and 120b can be conformally formed on the inner wall of the molded through-hole 118 and on the surface of the molded layer 116 on the intermediate layer 114, such as in Figure 4 As shown in the diagram. Electromagnetic shielding layer 120a may be formed on the inner wall of the molded through-hole 118. Electromagnetic shielding layer 120b may be formed on the surface of the molded layer 116. Electromagnetic shielding layers 120a and 120b can protect the semiconductor chip (i.e., Figure 1 and Figure 2 The first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 are protected from electromagnetic waves.

[0062] Figure 5 This is a cross-sectional view of the main parts of a semiconductor package 20 according to some exemplary embodiments of the present invention.

[0063] Specifically, in addition to forming molded through-holes 118a-1, 118b-1, and 118c-1 with recesses 124a, 124b, and 124c respectively in the semiconductor package 20, the semiconductor package 20 can be connected with... Figure 1 and Figure 2 The semiconductor package 10 shown is the same. Therefore, a simplified explanation or omission of the above references is unnecessary. Figure 1 and Figure 2 The same description applies to the subject.

[0064] Semiconductor package 20 may include an intermediate layer 114 attached to a first semiconductor chip CH1. The intermediate layer 114 may be a heat sink HS. Semiconductor package 20 may include molded through-holes 118a-1, 118b-1, and 118c-1, respectively having recesses 124a, 124b, and 124c (“defined at least partially by said recesses 124a, 124b, and 124c”) that are recessed from the surface of the intermediate layer 114 into the interior of the intermediate layer 114, as shown in... Figure 5 As shown (see) Figure 1 and Figure 2 ).

[0065] In the semiconductor package 20, an electromagnetic shielding layer 120a can be formed in the molded through-holes 118a-1, 118b-1 and 118c-1 in which recesses 124a, 124b and 124c are formed, and thus can effectively protect the second semiconductor chip CG2 and the third semiconductor chip CG3 from electromagnetic wave damage.

[0066] In the semiconductor package 20, heat dissipation layers 122a, 122b, and 122c can be formed in molded through-holes 118a-1, 118b-1, and 118c-1, respectively, which have recesses 124a, 124b, and 124c. The semiconductor package 20 can reduce the heat dissipation path from the first semiconductor chip CH1 to the heat dissipation layers 122a, 122b, and 122c, and thus the heat generated in the first semiconductor chip CH1 can be easily discharged through the heat dissipation layers 122a, 122b, and 122c.

[0067] Figure 6 This is a cross-sectional view of the main portions of a semiconductor package 30 according to some exemplary embodiments of the present invention. (See also...) Figure 6 As shown, region A of semiconductor package 30 includes chip regions M2 and M3, molding regions M5 and M6, and heat dissipation region V2.

[0068] Specifically, in addition to forming a molded through-hole 118b and a heat dissipation layer 122b on the intermediate layer 114 between the second semiconductor chip CG2 and the third semiconductor chip CG3, the semiconductor package 30 can be connected with... Figure 1 and Figure 2 The semiconductor package 10 shown is the same. Therefore, a simplified explanation or omission of the above references is unnecessary. Figure 1 and Figure 2 The same description applies to the subject.

[0069] A molded via 118b may be formed in a molding layer 116b on an intermediate layer 114 in a semiconductor package 30. The molded via 118b may expose a portion of the surface of the intermediate layer 114. The molded via 118b may be located on the intermediate layer 114 between a second semiconductor chip CG2 and a third semiconductor chip CG3. An electromagnetic shielding layer 120a may be formed in the molded via 118b. The electromagnetic shielding layer 120b may be formed on the surfaces of molding layers 116a and 116b. A heat dissipation layer 122b may be formed on the electromagnetic shielding layer 120a in the molded via 118b.

[0070] The semiconductor package 30 can protect the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 from electromagnetic wave damage through electromagnetic shielding layers 120a and 120b. When a heat source 110b is present in the central part of the first semiconductor chip CH1, the semiconductor package 30 can easily dissipate heat to the outside through the intermediate layer 114 above the heat source 110b, the electromagnetic shielding layer 120a, and the heat dissipation layer 122b.

[0071] Figure 7 This is a cross-sectional view of the main parts of a semiconductor package 40 according to some exemplary embodiments of the present invention. (See also...) Figure 7 As shown, region A of semiconductor package 30 includes molding regions M1 and M4, chip region M7, and heat dissipation regions V1 and V3.

[0072] Specifically, in addition to forming molded through-holes 118a and 118c and heat dissipation layers 122a and 122c in the edge portion of the intermediate layer 114, the semiconductor package 40 can be connected with... Figure 1 and Figure 2 The semiconductor package 10 shown is the same. Therefore, a simplified explanation or omission of the above references is unnecessary. Figure 1 and Figure 2 The same description applies to the subject.

[0073] Semiconductor package 40 may have molded vias 118a and 118c formed in molding layer 116b on intermediate layer 114. Molded vias 118a and 118c may expose a portion of the surface of intermediate layer 114. Molded via 118a may be formed in an edge portion of intermediate layer 114 spaced apart from one side of second semiconductor chip CG2. Molded via 118c may be formed in an edge portion of intermediate layer 114 separated from one side of third semiconductor chip CG3.

[0074] An electromagnetic shielding layer 120a may be formed inside the molded through-holes 118a and 118c. An electromagnetic shielding layer 120b may be formed on the surfaces of molded layers 116a and 116b. A heat dissipation layer 122a may be formed on the electromagnetic shielding layer 120a within the molded through-hole 118a. A heat dissipation layer 122c may be formed on the electromagnetic shielding layer 120a within the molded through-hole 118c.

[0075] The semiconductor package 40 can protect the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 from electromagnetic wave damage through electromagnetic shielding layers 120a and 120b. When heat sources 110a and 110c are present in the edge portion of the first semiconductor chip CH1, the semiconductor package 40 can easily dissipate heat to the outside through the intermediate layer 114 above the heat sources 110a and 110c, the electromagnetic shielding layers 120a and 120b, and the heat dissipation layers 122a and 122c.

[0076] Figure 8 This is a plan view of a semiconductor package 50 according to some exemplary embodiments of the present invention, and Figure 9 It is intercepted along the line of sight IX-IX'. Figure 8 A cross-sectional view of the main parts of the semiconductor package 50 shown.

[0077] Specifically Figure 9 It is along Figure 8 The cross-sectional view of the main portion cut off by line IX-IX' in the image. Except that the intermediate layer 114 in semiconductor package 50 includes an interposer chip IP, and the electrical connection between the second semiconductor chip CG2 and the third semiconductor chip CG3 in semiconductor package 50 and the wiring substrate 102 differs from the electrical connection between the second semiconductor chip CG2 and the third semiconductor chip CG3 and the wiring substrate 102 in semiconductor package 10, semiconductor package 50 can be... Figure 1 and Figure 2 The semiconductor package 10 shown is the same. Therefore, a simplified explanation or omission of the above references is unnecessary. Figure 1 and Figure 2 The same description applies to the subject.

[0078] In semiconductor package 50, a first semiconductor chip CH1 can be attached to a wiring substrate 102. An intermediate layer 114 can be mounted on the first semiconductor chip CH1. The intermediate layer 114 can cover the entire surface of the first semiconductor chip CH1. The intermediate layer 114 can be an interposer chip IP. The interposer chip IP can dissipate the heat generated in the first semiconductor chip CH1.

[0079] The interposer chip IP may include a silicon substrate. The interposer chip IP does not include active components (e.g., transistors) and may only include internal wiring layers located on and within the surface of the silicon substrate. Connector pads 128 may be located on the surface of the intermediate layer 114 that includes the interposer chip IP.

[0080] The second semiconductor chip CG2 can be a multilayer chip, in which multiple sub-chips CH2a and CH2b are sequentially stacked on an intermediate layer 114 including an interposer chip IP. Sub-chip CH2b can be electrically connected to a wiring substrate 102 via bonding wire 115a. Sub-chip CH2a can be electrically connected to the wiring substrate 102 via bonding wire 115c through a connection pad 128 on the intermediate layer 114.

[0081] The third semiconductor chip CG3 can be a multilayer chip, in which multiple sub-chips CH3a and CH3b are stacked sequentially on an intermediate layer 114. Sub-chip CH3b can be electrically connected to the wiring substrate 102 via bonding wire 115b. Sub-chip CH3a can be electrically connected to the wiring substrate 102 via bonding wire 115d through the connection pad 128 on the intermediate layer 114.

[0082] Therefore, as in Figures 8 to 9 As shown, each of the second semiconductor chip CG2 and the third semiconductor chip CG3 can be electrically connected to the wiring substrate 102 through the interposer chip IP of the intermediate layer 114.

[0083] The semiconductor package 50 may include electromagnetic shielding layers 120a and 120b to protect the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 from electromagnetic damage. The semiconductor package 50 may include heat dissipation layers 122a, 122b, and 122c in molded through-holes 118a, 118b, and 118c to dissipate heat generated in the first semiconductor chip CH1 to the outside without transferring the heat to the second semiconductor chip CG2 and the third semiconductor chip CG3.

[0084] Furthermore, since the intermediate layer 114 in the semiconductor package 50 includes an interposer chip IP, the second semiconductor chip CG2 and the third semiconductor chip CG3 can be easily connected to the wiring substrate 102. In the semiconductor package 50, the circuitry associated with the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 can be freely designed on the wiring substrate 102.

[0085] Figure 10 This is a cross-sectional view of a semiconductor package 60 according to some exemplary embodiments of the present invention.

[0086] Specifically, except that the intermediate layer 114 in semiconductor package 60 includes an interposer chip IP and the electrical connection between the second semiconductor chip CG2 and the third semiconductor chip CG3 in semiconductor package 60 and the wiring substrate 102 is different from the electrical connection between the second semiconductor chip CG2 and the third semiconductor chip CG3 and the wiring substrate 102 in semiconductor package 10, semiconductor package 60 can be with Figure 1 and Figure 2 The semiconductor package 10 shown is the same.

[0087] Except that the electrical connection between the second semiconductor chip CG2 and the third semiconductor chip CG3 in semiconductor package 60 and the wiring substrate 102 differs from the electrical connection between the second semiconductor chip CG2 and the third semiconductor chip CG3 and the wiring substrate 102 in semiconductor package 50, semiconductor package 60 can be connected with... Figure 8 and Figure 9 The semiconductor package 50 shown is the same. Therefore, a simplified explanation or omission of the above references is unnecessary. Figure 1 , Figure 2 , Figure 8 and Figure 9 The same description applies to the subject.

[0088] In semiconductor package 60, a first semiconductor chip CH1 may be attached to a wiring substrate 102. An intermediate layer 114 may be mounted on the first semiconductor chip CH1. The intermediate layer 114 may be an interposer chip IP. The interposer chip IP may include a silicon substrate and may include internal wiring layers located on and within the surface of the silicon substrate. Connector pads 128 may be located on the surface of the intermediate layer 114 including the interposer chip IP.

[0089] The second semiconductor chip CG2 can be a multilayer chip, in which multiple sub-chips CH2a and CH2b are sequentially stacked on an intermediate layer 114 including an interposer chip IP. The sub-chips CH2a and CH2b can be positioned such that their active surfaces face each other, and chip pads 130a connecting the sub-chips CH2a and CH2b to each other can be formed between the sub-chips CH2a and CH2b.

[0090] Sub-chip CH2b can be electrically connected to the connection pad 128 through a through-hole 129a formed in sub-chip CH2a. Therefore, the plurality of sub-chips CH2a and CH2b of the second semiconductor chip CG2 are electrically connected to each other through one or more through-holes 129a. Sub-chip CH2a can be electrically connected to the wiring substrate 102 through a bonding line 115e connected to the connection pad 128 on the intermediate layer 114.

[0091] The third semiconductor chip CG3 can be a multilayer chip, in which multiple sub-chips CH3a and CH3b are stacked sequentially on an intermediate layer 114. The sub-chips CH3a and CH3b can be positioned such that their active surfaces face each other, and chip pads 130b connecting the sub-chips CH3a and CH3b to each other can be formed between the sub-chips CH3a and CH3b.

[0092] Sub-chip CH3b can be electrically connected to the connection pad 128 through a through-hole 129b formed in sub-chip CH3a. Therefore, the plurality of sub-chips CH3a and CH3b of the third semiconductor chip CG3 are electrically connected to each other through one or more through-holes 129b. Sub-chip CH3a can be electrically connected to the wiring substrate 102 through a bonding line 115f connected to the connection pad 128 on the intermediate layer 114.

[0093] Therefore, as in Figure 10 As shown, each of the second semiconductor chip CG2 and the third semiconductor chip CG3 can be electrically connected to the wiring substrate 102 via an interposer chip IP of the intermediate layer 114 through an independent bonding line.

[0094] In the semiconductor package 60, sub-chips CH2a and CH3a can be directly connected to sub-chips CH2b and CH3b respectively via chip pads 130a and 130b, and the chip pads 130a and 130b on the interposer chip IP forming the intermediate layer 114 can be easily connected to the wiring substrate 102 using bonding wires. Therefore, in the semiconductor package 60, the circuits related to the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 can be freely designed on the wiring substrate 102.

[0095] Figure 11 , Figure 12 , Figure 13 and Figure 14 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package, based on some exemplary embodiments of the concept of the present invention.

[0096] Specifically, providing Figures 11 to 14 In order to explain a kind of manufacturing Figure 1 and Figure 2 The method of semiconductor package 10 shown. Figures 11 to 14 In, and in Figure 1 and Figure 2 The same reference number indicated by the one shown is the same as Figure 1 and Figure 2 The same components are shown, and therefore are simply explained or omitted from the reference. Figure 1 and Figure 2 The same description applies to the subject.

[0097] Reference Figure 11 A first semiconductor chip CH1 is attached to a wiring substrate 102, and an external terminal 104 is formed on the lower surface of the wiring substrate 102. Connecting bumps 108 electrically connect the wiring substrate 102 and the first semiconductor chip CH1 to each other. Multiple first semiconductor chips CH1 can be attached to the wiring substrate 102. For convenience, in... Figure 11Only two first semiconductor chips CH1 are shown. The positions of the first semiconductor chips CH1 are spaced apart from each other.

[0098] Each of the first semiconductor chips CH1 may be a logic chip. The first semiconductor chip CH1 may include heat sources 110a, 110b, and 110c. In a cross-sectional view, heat sources 110a, 110b, and 110c may be located in both the edge and center portions of the first semiconductor chip CH1. Heat sources 110a, 110b, and 110c may be formed at various locations depending on the chip design.

[0099] Intermediate layers 114 are attached to the first semiconductor chip CH1 using adhesive layer 112. In other words, intermediate layers 114 are attached to the first semiconductor chip CH1 using adhesive layer 112. Each of the intermediate layers 114 can be a heat sink HS. The intermediate layers 114 are spaced apart from each other.

[0100] The second semiconductor chip CG2 and the third semiconductor chip CG3 are attached to each of the intermediate layers 114. On the intermediate layer 114, the second semiconductor chip CG2 and the third semiconductor chip CG3 are spaced apart from each other. The second semiconductor chip CG2 and the third semiconductor chip CG3 can be memory chips.

[0101] The second semiconductor chip CG2 may include a multilayer chip in which multiple sub-chips CH2a and CH2b are sequentially stacked. The third semiconductor chip CG3 includes a multilayer chip in which multiple sub-chips CH3a and CH3b are sequentially stacked. The second semiconductor chip CG2 and the third semiconductor chip CG3 may be chips of a different type from the first semiconductor chip CH1.

[0102] The second semiconductor chip CG2 and the third semiconductor chip CG3 are electrically connected to the wiring substrate 102 using bonding wires 115a and 115b, respectively.

[0103] Molding layers 116a and 116b are formed on wiring substrate 102 to fully cover the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3. Molding layer 116a is formed on wiring substrate 102 and below intermediate layer 114. Molding layer 116b is formed on the top and sidewalls of intermediate layer 114. Molding layers 116a and 116b may contain an insulating polymer, such as an epoxy molding compound.

[0104] Reference Figure 12 The molded layer 116b located on the intermediate layer 114 is laser-machined to form molded through holes 118a, 118b and 118c that expose the surface of the intermediate layer 114. The molded through holes 118a, 118b and 118c may be spaced apart from each other on the intermediate layer 114.

[0105] Molded vias 118a and 118c are formed in the edge portions of the intermediate layer 114 spaced apart from one side of the second semiconductor chip CG2 and from one side of the third semiconductor chip CG3. Molded vias 118a and 118c correspond to heat sources 110a and 110c and are formed in regions adjacent to heat sources 110a and 110c. Molded via 118b is formed on the intermediate layer 114 between the second semiconductor chip CG2 and the third semiconductor chip CG3. Molded via 118b corresponds to heat source 110b and is formed to overlap with heat source 110b.

[0106] During or after the formation of molded vias 118a, 118b, and 118c, the molded layers 116a and 116b between the intermediate layers 114 are laser-machined to form molded separation vias 118d that expose the wiring substrate 102. The molded separation vias 118d separate the intermediate layers 114 from each other.

[0107] Reference Figure 13 Electromagnetic shielding layers 120a and 120b are conformally formed (with a constant thickness) on the inner walls of the molded through holes 118a, 118b, and 118c and the molded separate through hole 118d, and on the surface and sidewalls of the molded layers 116a and 116b. Electromagnetic shielding layer 120a may be conformally formed (with a constant thickness) inside the molded through holes 118a, 118b, and 118c and the molded separate through hole 118d, i.e., conformally formed on the bottom and inner walls of the molded through holes 118a, 118b, and 118c and the molded separate through hole 118d.

[0108] The electromagnetic shielding layer 120b may be conformally formed on the surface or two sidewalls of the molding layers 116a and 116b. The electromagnetic shielding layers 120a and 120b may be formed to protect the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3 from damage or obstruction by electromagnetic waves.

[0109] Electromagnetic shielding layers 120a and 120b may comprise materials including conductors and magnetic materials. Electromagnetic shielding layers 120a and 120b may be formed by dispersing magnetic materials in a metallic material. Electromagnetic shielding layers 120a and 120b may be formed by compressing or spraying a layer of electromagnetic shielding material onto molding layers 116a and 116b.

[0110] Reference Figure 14Heat dissipation layers 122a, 122b, and 122c are formed to fill the molded through-holes 118a, 118b, and 118c on the electromagnetic shielding layer 120a within the molded through-holes 118a, 118b, and 118c. Heat dissipation layers 122a, 122b, and 122c comprise a material with high thermal conductivity.

[0111] The heat dissipation layers 122a, 122b, and 122c comprise a conductive material, such as a metal. The heat dissipation layers 122a, 122b, and 122c can be formed by embedding a conductive material (e.g., metal paste or metal powder) into molded through-holes 118a, 118b, and 118c and then sintering the conductive material.

[0112] Subsequently, the electromagnetic shielding layer 120b and the wiring substrate 102, formed between the intermediate layers 114 and located at the bottom of the molded separation via 118d, are cut along the cutting line CUL to complete the process. Figure 2 The semiconductor package 10 shown is illustrated.

[0113] Figure 15 , Figure 16 and Figure 17 This is a cross-sectional view illustrating a method for manufacturing a semiconductor package, based on some exemplary embodiments of the concept of the present invention.

[0114] Specifically, providing Figures 15 to 17 In order to explain a kind of manufacturing Figure 5 The method of semiconductor package 20 shown. Figures 15 to 17 In, and in Figures 11 to 14 The same reference number indicated by the one shown is the same as Figures 11 to 14 The same components are shown, and therefore are simply explained or omitted from the reference. Figures 11 to 14 The same description applies to the subject.

[0115] First, execute the reference. Figure 11 The process described above. Therefore, a first semiconductor chip CH1, electrically connected to a wiring substrate 102 on which external terminals 104 are formed, is attached to the wiring substrate 102. An intermediate layer 114 is attached to the first semiconductor chip CH1 using an adhesive layer 112.

[0116] The second semiconductor chip CG2 and the third semiconductor chip CG3 are attached to each of the intermediate layers 114. The second semiconductor chip CG2 and the third semiconductor chip CG3 are electrically connected to the wiring substrate 102 using bonding wires 115a and 115b, respectively. Molding layers 116a and 116b are formed on the wiring substrate 102 to fully cover the first semiconductor chip CH1, the second semiconductor chip CG2, and the third semiconductor chip CG3.

[0117] Reference Figure 15The molded layer 116b located on the intermediate layer 114 is blade-cut to form molded through holes 118a-1, 118b-1, and 118c-1 that expose the surface of the intermediate layer 114. Recesses 124a, 124b, and 124c that recess from the surface of the intermediate layer 114 can be formed at the bottom of the molded through holes 118a-1, 118b-1, and 118c-1.

[0118] Molded vias 118a-1, 118b-1, and 118c-1 may be spaced apart from each other on the intermediate layer 114. Molded vias 118a-1 and 118c-1 correspond to heat sources 110a and 110c and are formed in regions adjacent to heat sources 110a and 110c. Molded via 118b-1 is formed on the intermediate layer 114 between the second semiconductor chip CG2 and the third semiconductor chip CG3. Molded via 118b-1 corresponds to heat source 110b and is formed to overlap with heat source 110b.

[0119] During or after the formation of molded vias 118a-1, 118b-1, and 118c-1, the molded layers 116a and 116b between the intermediate layers 114 are machined with a cutting tool to form molded separation vias 118d-1 that expose the wiring substrate 102. The molded separation vias 118d-1 separate the intermediate layers 114 from each other.

[0120] Reference Figure 16 Electromagnetic shielding layers 120a and 120b are conformally formed (with constant thickness) on the inner walls of the molded through holes 118a-1, 118b-1 and 118c-1, the inner wall of the molded separation through hole 118d-1, and the surface and sidewalls of the molded layers 116a and 116b.

[0121] The electromagnetic shielding layer 120a is conformally formed (with a constant thickness) inside the molded through holes 118a-1, 118b-1 and 118c-1 and the molded separate through hole 118d-1, that is, conformally formed on the bottom and inner wall of the molded through holes 118a-1, 118b-1 and 118c-1 and the molded separate through hole 118d-1.

[0122] The electromagnetic shielding layer 120b may be conformally formed on the surface or two sidewalls of the molding layers 116a and 116b. The electromagnetic shielding layers 120a and 120b may be formed by compressing or spraying a layer of electromagnetic shielding material onto the molding layers 116a and 116b.

[0123] Reference Figure 17Heat dissipation layers 122a, 122b, and 122c are formed to fill the molded through-holes 118a-1, 118b-1, and 118c-1 in the molded through-holes 118a-1, 118b-1, and 118c-1, which have recesses 124a, 124b, and 124c, respectively. The heat dissipation layers 122a, 122b, and 122c contain a material with high thermal conductivity. Subsequently, the electromagnetic shielding layer 120b and the wiring substrate 102, formed between the intermediate layers 114 and located at the bottom of the molded separated through-holes 118d-1, are cut along the cut line CUL to complete the process. Figure 5 The semiconductor package 20 shown is shown.

[0124] Figure 18 This is a block diagram of an electronic system 200 comprising a semiconductor package according to some exemplary embodiments of the present invention.

[0125] Specifically, the electronic system 200 can be implemented as a mobile system, a personal computer, an industrial computer, or a logical system performing various functions. For example, the mobile system can be a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a cordless phone, a laptop, a memory card, a digital music system, or an information transmission / reception system.

[0126] Electronic system 200 may include various devices, namely processor 230, random access memory (RAM) 240, user interface 250, modem 220, and memory device 210, which communicate with each other via a common bus 260. Each of the devices transmits signals to and receives signals from memory device 210 via the common bus 260. Processor 230 may include at least one of a microprocessor, digital signal processor, microcontroller, and logic element capable of performing the same function as a microprocessor, digital signal processor, or microcontroller.

[0127] Memory device 210 may include flash memory 211 and memory controller 212. Flash memory 211 may store data and may have non-volatile characteristics to retain the stored data even when the power supply is interrupted. Memory device 210, modem 220, and processor 230 may include at least one of the semiconductor packages 10 to 60 described above.

[0128] Although the concept of the invention has been specifically shown and illustrated with reference to embodiments thereof, it should be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the foregoing claims.

Claims

1. A semiconductor package, comprising: A first semiconductor chip is located on a wiring substrate and is electrically connected to the wiring substrate. An intermediate layer is located on the first semiconductor chip, and the intermediate layer covers the entire surface of the first semiconductor chip; A second semiconductor chip is located on the intermediate layer and is electrically connected to the wiring substrate. A molding layer is located on the wiring substrate, the molding layer covers the first semiconductor chip and the second semiconductor chip, the molding layer includes one or more inner surfaces, the one or more inner surfaces at least partially defining molded via holes, the molded via holes exposing a portion of the surface of the intermediate layer; An electromagnetic shielding layer is located on one or more inner surfaces of the molded layer, and the electromagnetic shielding layer is also located on one or more outer surfaces of the molded layer; as well as A heat dissipation layer is located on the electromagnetic shielding layer within the molded through-hole, such that the heat dissipation layer fills the molded through-hole. At least a portion of the heat dissipation layer overlaps with at least a portion of the first semiconductor chip in a direction perpendicular to the upper surface of the first semiconductor chip. The molded through-hole includes multiple molded through-hole patterns that extend in one direction on the intermediate layer and are spaced apart from each other without direct contact. The molding layer is in direct contact with at least a portion of the side surface and the bottom surface of the first semiconductor chip.

2. The semiconductor package according to claim 1, wherein The first semiconductor chip includes a heat source. The molded vias and the heat dissipation layer correspond to the heat source, such that the semiconductor package is configured to discharge heat generated in the heat source to the outside of the semiconductor package through at least the molded vias and the heat dissipation layer.

3. The semiconductor package according to claim 1, wherein The first semiconductor chip includes a logic chip, and The second semiconductor chip includes a memory chip.

4. The semiconductor package according to claim 1, wherein The first semiconductor chip is electrically connected to the wiring substrate via connection bumps, and The second semiconductor chip is electrically connected to the wiring substrate via bonding wires.

5. The semiconductor package according to claim 1, wherein the second semiconductor chip comprises a multilayer chip, the multilayer chip comprising a plurality of sub-chips, the plurality of sub-chips being stacked sequentially on the intermediate layer.

6. The semiconductor package of claim 1, wherein the intermediate layer is a heat sink or an interposer chip.

7. The semiconductor package of claim 1, wherein the molded via is at least partially defined by a recess that recesses from the surface of the intermediate layer into the interior of the intermediate layer.

8. The semiconductor package of claim 1, wherein the plurality of molded via patterns have a planar constant area on the intermediate layer.

9. The semiconductor package of claim 1, wherein the electromagnetic shielding layer extends conformally on the surface defining the bottom of the molded via, on one or more inner surfaces defining the inner wall of the molded via, and on one or more outer surfaces of the molded layer and on opposing sidewalls.

10. The semiconductor package of claim 1, wherein The semiconductor package includes a chip region and a heat dissipation region. In the chip region, the first semiconductor chip and the second semiconductor chip overlap each other in a vertical direction extending perpendicular to the upper surface of the wiring substrate. In the heat dissipation region, the first semiconductor chip and the second semiconductor chip do not overlap each other in the vertical direction. The heat dissipation area includes the molded through-hole and the heat dissipation layer.

11. A semiconductor package, comprising: A first semiconductor chip is located on a wiring substrate and is electrically connected to the wiring substrate. The first semiconductor chip includes a logic chip. An intermediate layer is located on the first semiconductor chip, and the intermediate layer covers the entire surface of the first semiconductor chip; A second semiconductor chip is located on the intermediate layer and is electrically connected to the wiring substrate. The second semiconductor chip includes a memory chip. A third semiconductor chip is located on the intermediate layer. The third semiconductor chip is isolated from the second semiconductor chip and does not directly contact it. The third semiconductor chip is electrically connected to the wiring substrate. The third semiconductor chip includes an independent memory chip. A molding layer is located on the wiring substrate, the molding layer covers the first semiconductor chip, the second semiconductor chip and the third semiconductor chip, the molding layer includes one or more inner surfaces, the one or more inner surfaces at least partially defining molded vias, the molded vias exposing a portion of the surface of the intermediate layer; An electromagnetic shielding layer is located on one or more inner surfaces of the molded layer, and the electromagnetic shielding layer is also located on one or more outer surfaces of the molded layer; as well as A heat dissipation layer is located on the electromagnetic shielding layer within the molded through-hole, such that the heat dissipation layer fills the molded through-hole. At least a portion of the heat dissipation layer overlaps with at least a portion of the first semiconductor chip in a direction perpendicular to the upper surface of the first semiconductor chip. The molded through-hole includes multiple molded through-hole patterns that extend in one direction on the intermediate layer and are spaced apart from each other without direct contact. The molding layer is in direct contact with at least a portion of the side surface and the bottom surface of the first semiconductor chip.

12. The semiconductor package of claim 11, wherein the molded through-hole is located on the intermediate layer and between the second semiconductor chip and the third semiconductor chip.

13. The semiconductor package of claim 11, wherein the molded through-hole is located on an edge portion of the intermediate layer, and Compared to the third semiconductor chip, it is closer to the second semiconductor chip, but isolated from the second semiconductor chip and does not directly contact it, or It is closer to the third semiconductor chip than the second semiconductor chip, and is isolated from the third semiconductor chip and does not directly contact it.

14. The semiconductor package of claim 11, wherein each of the second semiconductor chip and the third semiconductor chip comprises an independent multilayer chip, each independent multilayer chip comprising an independent plurality of sub-chips, the independent plurality of sub-chips being stacked sequentially on the intermediate layer.

15. The semiconductor package of claim 11, wherein... The intermediate layer includes heat sinks. The first semiconductor chip is electrically connected to the wiring substrate via connection bumps, and The second semiconductor chip and the third semiconductor chip are each electrically connected to the wiring substrate via independent bonding lines.

16. The semiconductor package of claim 11, wherein... The intermediate layer includes an intermediary chip. Each of the second and third semiconductor chips comprises an independent multilayer chip, and each independent multilayer chip comprises a plurality of sub-chips stacked sequentially. Each of the second semiconductor chip and the third semiconductor chip is electrically connected to the wiring substrate through the interposer chip.

17. A semiconductor package, comprising: A first semiconductor chip is located on a wiring substrate and is electrically connected to the wiring substrate. The first semiconductor chip includes a logic chip, and the logic chip includes a heat source. An intermediate layer is located on the first semiconductor chip, and the intermediate layer covers the entire surface of the first semiconductor chip; A second semiconductor chip is located on the intermediate layer and is electrically connected to the wiring substrate. The second semiconductor chip includes a memory chip. A third semiconductor chip is located on the intermediate layer. The third semiconductor chip is isolated from the second semiconductor chip and does not directly contact it. The third semiconductor chip is electrically connected to the wiring substrate. The third semiconductor chip includes an independent memory chip. A molding layer is located on the wiring substrate, the molding layer covers the first semiconductor chip, the second semiconductor chip and the third semiconductor chip, the molding layer includes a plurality of inner surfaces, the plurality of inner surfaces at least partially defining a plurality of molded vias, the plurality of molded vias exposing a portion of the surface of the intermediate layer in both the central region between the second semiconductor chip and the third semiconductor chip and the edge portion of the intermediate layer; An electromagnetic shielding layer is located on the plurality of inner surfaces of the molded layer, and the electromagnetic shielding layer is also located on one or more outer surfaces of the molded layer; as well as A heat dissipation layer is located on the electromagnetic shielding layer in each of the plurality of molded through-holes, such that the heat dissipation layer fills the plurality of molded through-holes. At least a portion of the heat dissipation layer overlaps with at least a portion of the first semiconductor chip in a direction perpendicular to the upper surface of the first semiconductor chip. Each of the plurality of molded through-holes comprises a plurality of molded through-hole patterns, which extend in one direction on the intermediate layer and are spaced apart from each other without direct contact. The molding layer is in direct contact with at least a portion of the side surface and the bottom surface of the first semiconductor chip.

18. The semiconductor package of claim 17, wherein The intermediate layer includes heat sinks. The first semiconductor chip is electrically connected to the wiring substrate via connection bumps, and The second semiconductor chip and the third semiconductor chip are each electrically connected to the wiring substrate via independent bonding lines.

19. The semiconductor package of claim 17, wherein The intermediate layer includes an intermediary chip. The first semiconductor chip is electrically connected to the wiring substrate via connection bumps. Each of the second and third semiconductor chips comprises an independent multilayer chip, and each independent multilayer chip comprises an independent plurality of sequentially stacked sub-chips. The independent plurality of sub-chips are electrically connected to each other through one or more through-holes. The second semiconductor chip and the third semiconductor chip are each electrically connected to the wiring substrate through the interposer chip via independent bonding lines.

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